From c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 Mon Sep 17 00:00:00 2001
From: Curtis Dunham <Curtis.Dunham@arm.com>
Date: Thu, 13 Oct 2016 23:21:40 +0100
Subject: [PATCH] stats: update references

---
 .../ref/alpha/linux/tsunami-minor/config.ini  |   48 +-
 .../ref/alpha/linux/tsunami-minor/simout      |    8 +-
 .../ref/alpha/linux/tsunami-minor/stats.txt   | 1739 ++---
 .../alpha/linux/tsunami-minor/system.terminal |    2 +-
 .../alpha/linux/tsunami-o3-dual/config.ini    |   41 +-
 .../ref/alpha/linux/tsunami-o3-dual/simout    |   10 +-
 .../ref/alpha/linux/tsunami-o3-dual/stats.txt | 3965 +++++-----
 .../linux/tsunami-o3-dual/system.terminal     |    2 +-
 .../ref/alpha/linux/tsunami-o3/config.ini     |   48 +-
 .../ref/alpha/linux/tsunami-o3/simout         |    8 +-
 .../ref/alpha/linux/tsunami-o3/stats.txt      | 2234 +++---
 .../alpha/linux/tsunami-o3/system.terminal    |    2 +-
 .../arm/linux/realview-minor-dual/config.ini  |   57 +-
 .../ref/arm/linux/realview-minor-dual/simout  |    8 +-
 .../arm/linux/realview-minor-dual/stats.txt   | 5064 ++++++-------
 .../ref/arm/linux/realview-minor/config.ini   |   58 +-
 .../ref/arm/linux/realview-minor/simout       |    8 +-
 .../ref/arm/linux/realview-minor/stats.txt    | 2143 +++---
 .../ref/arm/linux/realview-o3-dual/config.ini |   53 +-
 .../ref/arm/linux/realview-o3-dual/simerr     |    2 +-
 .../ref/arm/linux/realview-o3-dual/simout     |    8 +-
 .../ref/arm/linux/realview-o3-dual/stats.txt  | 6151 +++++++--------
 .../linux/realview-o3-dual/system.terminal    |    2 +-
 .../ref/arm/linux/realview-o3/config.ini      |   56 +-
 .../ref/arm/linux/realview-o3/simout          |    8 +-
 .../ref/arm/linux/realview-o3/stats.txt       | 2722 +++----
 .../linux/realview64-minor-dual/config.ini    |   59 +-
 .../arm/linux/realview64-minor-dual/simout    |    8 +-
 .../arm/linux/realview64-minor-dual/stats.txt | 5661 +++++++-------
 .../realview64-minor-dual/system.terminal     |  251 +-
 .../ref/arm/linux/realview64-minor/config.ini |   60 +-
 .../ref/arm/linux/realview64-minor/simout     |    8 +-
 .../ref/arm/linux/realview64-minor/stats.txt  | 2398 +++---
 .../linux/realview64-minor/system.terminal    |  246 +-
 .../arm/linux/realview64-o3-dual/config.ini   |   55 +-
 .../ref/arm/linux/realview64-o3-dual/simerr   |    2 +-
 .../ref/arm/linux/realview64-o3-dual/simout   |    8 +-
 .../arm/linux/realview64-o3-dual/stats.txt    | 6740 ++++++++---------
 .../linux/realview64-o3-dual/system.terminal  |  248 +-
 .../ref/arm/linux/realview64-o3/config.ini    |   58 +-
 .../ref/arm/linux/realview64-o3/simout        |    8 +-
 .../ref/arm/linux/realview64-o3/stats.txt     | 2906 +++----
 .../arm/linux/realview64-o3/system.terminal   |  256 +-
 .../realview64-simple-timing-dual/config.ini  |   59 +-
 .../realview64-simple-timing-dual/simout      |    8 +-
 .../realview64-simple-timing-dual/stats.txt   | 5594 +++++++-------
 .../system.terminal                           |  254 +-
 .../linux/realview64-simple-timing/config.ini |   60 +-
 .../arm/linux/realview64-simple-timing/simout |    8 +-
 .../linux/realview64-simple-timing/stats.txt  | 2429 +++---
 .../realview64-simple-timing/system.terminal  |  254 +-
 .../ref/arm/linux/minor-timing/config.ini     |   43 +-
 .../10.mcf/ref/arm/linux/minor-timing/simout  |    8 +-
 .../ref/arm/linux/minor-timing/stats.txt      |  560 +-
 .../10.mcf/ref/arm/linux/o3-timing/config.ini |   41 +-
 .../se/10.mcf/ref/arm/linux/o3-timing/simout  |    8 +-
 .../10.mcf/ref/arm/linux/o3-timing/stats.txt  | 1480 ++--
 .../10.mcf/ref/x86/linux/o3-timing/config.ini |   41 +-
 .../se/10.mcf/ref/x86/linux/o3-timing/simout  |   10 +-
 .../10.mcf/ref/x86/linux/o3-timing/stats.txt  | 1562 ++--
 .../ref/alpha/tru64/minor-timing/config.ini   |   41 +-
 .../ref/alpha/tru64/minor-timing/simout       |    8 +-
 .../ref/alpha/tru64/minor-timing/stats.txt    |  915 +--
 .../ref/arm/linux/minor-timing/config.ini     |   43 +-
 .../ref/arm/linux/minor-timing/simout         |    8 +-
 .../ref/arm/linux/minor-timing/stats.txt      |  874 +--
 .../ref/arm/linux/o3-timing/config.ini        |   41 +-
 .../20.parser/ref/arm/linux/o3-timing/simout  |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1792 ++---
 .../ref/x86/linux/o3-timing/config.ini        |   41 +-
 .../20.parser/ref/x86/linux/o3-timing/simout  |   19 +-
 .../ref/x86/linux/o3-timing/stats.txt         | 1617 ++--
 .../ref/alpha/tru64/minor-timing/config.ini   |   41 +-
 .../ref/alpha/tru64/minor-timing/simout       |    8 +-
 .../ref/alpha/tru64/minor-timing/stats.txt    |  662 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |   41 +-
 .../30.eon/ref/alpha/tru64/o3-timing/simout   |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1274 ++--
 .../ref/arm/linux/minor-timing/config.ini     |   43 +-
 .../30.eon/ref/arm/linux/minor-timing/simout  |    8 +-
 .../ref/arm/linux/minor-timing/stats.txt      |  550 +-
 .../30.eon/ref/arm/linux/o3-timing/config.ini |   41 +-
 .../se/30.eon/ref/arm/linux/o3-timing/simout  |   10 +-
 .../30.eon/ref/arm/linux/o3-timing/stats.txt  | 1387 ++--
 .../ref/alpha/tru64/minor-timing/config.ini   |   41 +-
 .../ref/alpha/tru64/minor-timing/simout       |    8 +-
 .../ref/alpha/tru64/minor-timing/stats.txt    |  935 +--
 .../ref/alpha/tru64/o3-timing/config.ini      |   41 +-
 .../ref/alpha/tru64/o3-timing/simout          |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1402 ++--
 .../ref/arm/linux/minor-timing/config.ini     |   43 +-
 .../ref/arm/linux/minor-timing/simout         |    8 +-
 .../ref/arm/linux/minor-timing/stats.txt      |  638 +-
 .../ref/arm/linux/o3-timing/config.ini        |   41 +-
 .../40.perlbmk/ref/arm/linux/o3-timing/simout |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1669 ++--
 .../ref/alpha/tru64/minor-timing/config.ini   |   41 +-
 .../ref/alpha/tru64/minor-timing/simout       |    8 +-
 .../ref/alpha/tru64/minor-timing/stats.txt    | 1090 +--
 .../ref/alpha/tru64/o3-timing/config.ini      |   41 +-
 .../ref/alpha/tru64/o3-timing/simout          |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1563 ++--
 .../ref/arm/linux/minor-timing/config.ini     |   43 +-
 .../ref/arm/linux/minor-timing/simout         |    8 +-
 .../ref/arm/linux/minor-timing/stats.txt      |  813 +-
 .../ref/arm/linux/o3-timing/config.ini        |   41 +-
 .../50.vortex/ref/arm/linux/o3-timing/simout  |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1717 ++---
 .../ref/alpha/tru64/minor-timing/config.ini   |   41 +-
 .../ref/alpha/tru64/minor-timing/simout       |    8 +-
 .../ref/alpha/tru64/minor-timing/stats.txt    | 1100 +--
 .../ref/alpha/tru64/o3-timing/config.ini      |   41 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/simout |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1760 ++---
 .../ref/arm/linux/minor-timing/config.ini     |   43 +-
 .../ref/arm/linux/minor-timing/simout         |    8 +-
 .../ref/arm/linux/minor-timing/stats.txt      |  981 +--
 .../ref/arm/linux/o3-timing/config.ini        |   41 +-
 .../60.bzip2/ref/arm/linux/o3-timing/simout   |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1760 ++---
 .../ref/alpha/tru64/minor-timing/config.ini   |   41 +-
 .../ref/alpha/tru64/minor-timing/simout       |   10 +-
 .../ref/alpha/tru64/minor-timing/stats.txt    |  558 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |   41 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/simout |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1244 +--
 .../ref/arm/linux/minor-timing/config.ini     |   43 +-
 .../ref/arm/linux/minor-timing/simout         |    8 +-
 .../ref/arm/linux/minor-timing/stats.txt      |  554 +-
 .../ref/arm/linux/o3-timing/config.ini        |   41 +-
 .../70.twolf/ref/arm/linux/o3-timing/simout   |   10 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1445 ++--
 .../ref/x86/linux/o3-timing/config.ini        |   41 +-
 .../70.twolf/ref/x86/linux/o3-timing/simout   |   12 +-
 .../ref/x86/linux/o3-timing/stats.txt         | 1472 ++--
 .../tsunami-simple-timing-dual/config.ini     |   41 +-
 .../linux/tsunami-simple-timing-dual/simout   |   10 +-
 .../tsunami-simple-timing-dual/stats.txt      | 2979 ++++----
 .../system.terminal                           |    2 +-
 .../linux/tsunami-simple-timing/config.ini    |   48 +-
 .../alpha/linux/tsunami-simple-timing/simout  |    8 +-
 .../linux/tsunami-simple-timing/stats.txt     | 1641 ++--
 .../tsunami-simple-timing/system.terminal     |    2 +-
 .../realview-simple-timing-dual/config.ini    |   53 +-
 .../linux/realview-simple-timing-dual/simout  |    8 +-
 .../realview-simple-timing-dual/stats.txt     | 4762 ++++++------
 .../linux/realview-simple-timing/config.ini   |   56 +-
 .../arm/linux/realview-simple-timing/simout   |    8 +-
 .../linux/realview-simple-timing/stats.txt    | 2069 ++---
 .../ref/alpha/linux/minor-timing/config.ini   |   41 +-
 .../ref/alpha/linux/minor-timing/simout       |    8 +-
 .../ref/alpha/linux/minor-timing/stats.txt    |  458 +-
 .../ref/alpha/linux/o3-timing/config.ini      |   41 +-
 .../00.hello/ref/alpha/linux/o3-timing/simout |    8 +-
 .../ref/alpha/linux/o3-timing/stats.txt       |  979 +--
 .../config.ini                                |  291 +-
 .../simple-timing-ruby-MESI_Two_Level/simerr  |    3 +-
 .../simple-timing-ruby-MESI_Two_Level/simout  |   10 +-
 .../stats.txt                                 |  371 +-
 .../config.ini                                |  291 +-
 .../simerr                                    |    3 +-
 .../simout                                    |   10 +-
 .../stats.txt                                 |  351 +-
 .../config.ini                                |  417 +-
 .../simple-timing-ruby-MOESI_CMP_token/simerr |    3 +-
 .../simple-timing-ruby-MOESI_CMP_token/simout |   10 +-
 .../stats.txt                                 |  499 +-
 .../config.ini                                |  304 +-
 .../simple-timing-ruby-MOESI_hammer/simerr    |    3 +-
 .../simple-timing-ruby-MOESI_hammer/simout    |   10 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt |  359 +-
 .../alpha/linux/simple-timing-ruby/config.ini |  276 +-
 .../ref/alpha/linux/simple-timing-ruby/simerr |    3 +-
 .../ref/alpha/linux/simple-timing-ruby/simout |   10 +-
 .../alpha/linux/simple-timing-ruby/stats.txt  |  406 +-
 .../ref/alpha/tru64/minor-timing/config.ini   |   41 +-
 .../ref/alpha/tru64/minor-timing/simout       |    8 +-
 .../ref/alpha/tru64/minor-timing/stats.txt    |  492 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |   41 +-
 .../00.hello/ref/alpha/tru64/o3-timing/simout |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  950 +--
 .../config.ini                                |  291 +-
 .../simple-timing-ruby-MESI_Two_Level/simerr  |    3 +-
 .../simple-timing-ruby-MESI_Two_Level/simout  |   12 +-
 .../stats.txt                                 |  290 +-
 .../config.ini                                |  291 +-
 .../simerr                                    |    3 +-
 .../simout                                    |   12 +-
 .../stats.txt                                 |  296 +-
 .../config.ini                                |  417 +-
 .../simple-timing-ruby-MOESI_CMP_token/simerr |    3 +-
 .../simple-timing-ruby-MOESI_CMP_token/simout |   12 +-
 .../stats.txt                                 |  353 +-
 .../config.ini                                |  304 +-
 .../simple-timing-ruby-MOESI_hammer/simerr    |    3 +-
 .../simple-timing-ruby-MOESI_hammer/simout    |   12 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt |  316 +-
 .../alpha/tru64/simple-timing-ruby/config.ini |  276 +-
 .../ref/alpha/tru64/simple-timing-ruby/simerr |    3 +-
 .../ref/alpha/tru64/simple-timing-ruby/simout |   12 +-
 .../alpha/tru64/simple-timing-ruby/stats.txt  |  441 +-
 .../ref/arm/linux/minor-timing/config.ini     |   43 +-
 .../ref/arm/linux/minor-timing/simout         |    8 +-
 .../ref/arm/linux/minor-timing/stats.txt      |  518 +-
 .../arm/linux/o3-timing-checker/config.ini    |   41 +-
 .../ref/arm/linux/o3-timing-checker/simout    |    8 +-
 .../ref/arm/linux/o3-timing-checker/stats.txt |  976 +--
 .../ref/arm/linux/o3-timing/config.ini        |   41 +-
 .../00.hello/ref/arm/linux/o3-timing/simout   |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1024 +--
 .../ref/mips/linux/o3-timing/config.ini       |   41 +-
 .../00.hello/ref/mips/linux/o3-timing/simout  |    8 +-
 .../ref/mips/linux/o3-timing/stats.txt        |  915 +--
 .../mips/linux/simple-timing-ruby/config.ini  |  276 +-
 .../ref/mips/linux/simple-timing-ruby/simerr  |    3 +-
 .../ref/mips/linux/simple-timing-ruby/simout  |   10 +-
 .../mips/linux/simple-timing-ruby/stats.txt   |  433 +-
 .../ref/power/linux/o3-timing/config.ini      |   41 +-
 .../00.hello/ref/power/linux/o3-timing/simout |    8 +-
 .../ref/power/linux/o3-timing/stats.txt       |  945 +--
 .../sparc/linux/simple-timing-ruby/config.ini |  276 +-
 .../ref/sparc/linux/simple-timing-ruby/simerr |    3 +-
 .../ref/sparc/linux/simple-timing-ruby/simout |   12 +-
 .../sparc/linux/simple-timing-ruby/stats.txt  |  440 +-
 .../ref/x86/linux/o3-timing/config.ini        |   41 +-
 .../00.hello/ref/x86/linux/o3-timing/simout   |    8 +-
 .../ref/x86/linux/o3-timing/stats.txt         | 1274 ++--
 .../x86/linux/simple-timing-ruby/config.ini   |  291 +-
 .../ref/x86/linux/simple-timing-ruby/simerr   |    3 +-
 .../ref/x86/linux/simple-timing-ruby/simout   |   12 +-
 .../x86/linux/simple-timing-ruby/stats.txt    |  442 +-
 .../ref/alpha/linux/o3-timing-mt/config.ini   |   41 +-
 .../ref/alpha/linux/o3-timing-mt/simout       |    8 +-
 .../ref/alpha/linux/o3-timing-mt/stats.txt    | 1446 ++--
 .../ref/sparc/linux/o3-timing/config.ini      |   41 +-
 .../ref/sparc/linux/o3-timing/simout          |    8 +-
 .../ref/sparc/linux/o3-timing/stats.txt       | 1177 +--
 .../linux/learning-gem5-p1-simple/config.ini  |   37 +-
 .../linux/learning-gem5-p1-simple/simout      |    8 +-
 .../linux/learning-gem5-p1-simple/stats.txt   |  242 +-
 .../learning-gem5-p1-two-level/config.ini     |   43 +-
 .../linux/learning-gem5-p1-two-level/simout   |    8 +-
 .../learning-gem5-p1-two-level/stats.txt      |  406 +-
 .../linux/learning-gem5-p1-simple/config.ini  |   39 +-
 .../arm/linux/learning-gem5-p1-simple/simout  |    8 +-
 .../linux/learning-gem5-p1-simple/stats.txt   |  188 +-
 .../learning-gem5-p1-two-level/config.ini     |   45 +-
 .../linux/learning-gem5-p1-two-level/simout   |    8 +-
 .../learning-gem5-p1-two-level/stats.txt      |  416 +-
 .../linux/learning-gem5-p1-simple/config.ini  |   37 +-
 .../mips/linux/learning-gem5-p1-simple/simout |    8 +-
 .../linux/learning-gem5-p1-simple/stats.txt   |  224 +-
 .../learning-gem5-p1-two-level/config.ini     |   43 +-
 .../linux/learning-gem5-p1-two-level/simout   |    8 +-
 .../learning-gem5-p1-two-level/stats.txt      |  417 +-
 .../linux/learning-gem5-p1-simple/config.ini  |   37 +-
 .../linux/learning-gem5-p1-simple/simout      |    8 +-
 .../linux/learning-gem5-p1-simple/stats.txt   |  210 +-
 .../learning-gem5-p1-two-level/config.ini     |   43 +-
 .../linux/learning-gem5-p1-two-level/simout   |    8 +-
 .../learning-gem5-p1-two-level/stats.txt      |  420 +-
 .../linux/learning-gem5-p1-simple/config.ini  |   37 +-
 .../x86/linux/learning-gem5-p1-simple/simout  |    8 +-
 .../linux/learning-gem5-p1-simple/stats.txt   |  269 +-
 .../learning-gem5-p1-two-level/config.ini     |   43 +-
 .../linux/learning-gem5-p1-two-level/simout   |    8 +-
 .../learning-gem5-p1-two-level/stats.txt      |  409 +-
 .../ref/x86/linux/gpu-ruby-GPU_RfO/config.ini |  695 +-
 .../ref/x86/linux/gpu-ruby-GPU_RfO/simerr     |    1 +
 .../ref/x86/linux/gpu-ruby-GPU_RfO/simout     |   14 +-
 .../ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt  |  689 +-
 .../ref/sparc/linux/o3-timing-mp/config.ini   |   43 +-
 .../ref/sparc/linux/o3-timing-mp/simout       |   78 +-
 .../ref/sparc/linux/o3-timing-mp/stats.txt    | 4528 +++++------
 .../gpu-randomtest-ruby-GPU_RfO/config.ini    |  607 +-
 .../linux/gpu-randomtest-ruby-GPU_RfO/simerr  |    2 -
 .../linux/gpu-randomtest-ruby-GPU_RfO/simout  |   12 +-
 .../gpu-randomtest-ruby-GPU_RfO/stats.txt     | 1464 ++--
 .../rubytest-ruby-MESI_Two_Level/config.ini   |  289 +-
 .../linux/rubytest-ruby-MESI_Two_Level/simerr |    2 -
 .../linux/rubytest-ruby-MESI_Two_Level/simout |   12 +-
 .../rubytest-ruby-MESI_Two_Level/stats.txt    |  982 +--
 .../config.ini                                |  289 +-
 .../rubytest-ruby-MOESI_CMP_directory/simerr  |    2 -
 .../rubytest-ruby-MOESI_CMP_directory/simout  |   12 +-
 .../stats.txt                                 |  950 +--
 .../rubytest-ruby-MOESI_CMP_token/config.ini  |  415 +-
 .../rubytest-ruby-MOESI_CMP_token/simerr      |    2 -
 .../rubytest-ruby-MOESI_CMP_token/simout      |   12 +-
 .../rubytest-ruby-MOESI_CMP_token/stats.txt   | 1038 ++-
 .../rubytest-ruby-MOESI_hammer/config.ini     |  302 +-
 .../linux/rubytest-ruby-MOESI_hammer/simerr   |    2 -
 .../linux/rubytest-ruby-MOESI_hammer/simout   |   12 +-
 .../rubytest-ruby-MOESI_hammer/stats.txt      |  977 +--
 .../ref/alpha/linux/rubytest-ruby/config.ini  |  274 +-
 .../ref/alpha/linux/rubytest-ruby/simerr      |    2 -
 .../ref/alpha/linux/rubytest-ruby/simout      |   12 +-
 .../ref/alpha/linux/rubytest-ruby/stats.txt   |  709 +-
 .../ref/null/none/tgen-dram-ctrl/config.ini   |   53 +-
 .../ref/null/none/tgen-dram-ctrl/simout       |   10 +-
 .../ref/null/none/tgen-dram-ctrl/stats.txt    |  398 +-
 301 files changed, 72670 insertions(+), 65384 deletions(-)

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
index 2b85e262c..961681a43 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
@@ -25,7 +25,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:134217727
+mem_ranges=0:134217727:0:0:0:0
 memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
@@ -60,7 +60,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=8796093022208:18446744073709551615
+ranges=8796093022208:18446744073709551615:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -170,7 +170,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -604,7 +604,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -664,7 +664,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -827,7 +827,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=0:134217727
+addr_ranges=0:134217727:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -872,7 +872,7 @@ size=1024
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -884,7 +884,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -916,29 +916,36 @@ update_data=false
 warn_access=
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -958,6 +965,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -967,7 +975,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -989,9 +997,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout
index 7ccffc14c..98915ba59 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:23
-gem5 executing on e108600-lin, pid 39539
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:46
+gem5 executing on e108600-lin, pid 28076
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-minor
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1909061460000 because m5_exit instruction encountered
+Exiting @ tick 1893220881500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
index e646f5b40..3b8894174 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
@@ -1,110 +1,110 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.889223                       # Number of seconds simulated
-sim_ticks                                1889223246000                       # Number of ticks simulated
-final_tick                               1889223246000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.893221                       # Number of seconds simulated
+sim_ticks                                1893220881500                       # Number of ticks simulated
+final_tick                               1893220881500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  22780                       # Simulator instruction rate (inst/s)
-host_op_rate                                    22780                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              766551699                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 396616                       # Number of bytes of host memory used
-host_seconds                                  2464.57                       # Real time elapsed on the host
-sim_insts                                    56141873                       # Number of instructions simulated
-sim_ops                                      56141873                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  15759                       # Simulator instruction rate (inst/s)
+host_op_rate                                    15759                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              531367557                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 390932                       # Number of bytes of host memory used
+host_seconds                                  3562.92                       # Real time elapsed on the host
+sim_insts                                    56147815                       # Number of instructions simulated
+sim_ops                                      56147815                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst           1047552                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24859008                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst           1046208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24860800                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25907520                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1047552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1047552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7566528                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7566528                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              16368                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388422                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25907968                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1046208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1046208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7566592                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7566592                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              16347                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388450                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                404805                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          118227                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               118227                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               554488                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13158322                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               508                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13713318                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          554488                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             554488                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4005100                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4005100                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4005100                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              554488                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13158322                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              508                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17718418                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        404805                       # Number of read requests accepted
-system.physmem.writeReqs                       118227                       # Number of write requests accepted
-system.physmem.readBursts                      404805                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     118227                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25900800                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6720                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7565120                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25907520                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7566528                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      105                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                404812                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          118228                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               118228                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               552607                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13131484                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               507                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13684599                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          552607                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             552607                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3996677                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3996677                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3996677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              552607                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13131484                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              507                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17681276                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        404812                       # Number of read requests accepted
+system.physmem.writeReqs                       118228                       # Number of write requests accepted
+system.physmem.readBursts                      404812                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     118228                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25900544                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7424                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7565312                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25907968                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7566592                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      116                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25470                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25713                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25812                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25774                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25230                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24950                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24793                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24569                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25113                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25266                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25525                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24857                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24533                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25560                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25804                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25731                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7815                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7678                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8068                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7736                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7326                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6953                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6780                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6420                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7238                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6883                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7397                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6875                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7088                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8006                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7993                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7949                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               25483                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25705                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25813                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25775                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25223                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24955                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24789                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24583                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25108                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25258                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25518                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24875                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24528                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25564                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25798                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25721                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7829                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7671                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8071                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7745                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7318                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6944                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6788                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6427                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7237                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6873                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7386                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6888                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7081                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8010                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7995                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7945                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1889214280000                       # Total gap between requests
+system.physmem.numWrRetry                          68                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1893211891000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  404805                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  404812                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 118227                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    402482                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2156                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        50                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 118228                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    402391                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2236                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        57                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -149,193 +149,206 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2724                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5709                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5854                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6640                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7088                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7791                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7557                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6981                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5712                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5654                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5555                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       48                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        63746                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      524.988548                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     319.641335                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     414.335221                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14725     23.10%     23.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10901     17.10%     40.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5357      8.40%     48.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3110      4.88%     53.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2601      4.08%     57.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1701      2.67%     60.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1560      2.45%     62.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1439      2.26%     64.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22352     35.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          63746                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5298                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        76.386372                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2900.765356                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5295     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1346                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2487                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5523                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6747                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7723                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7340                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6854                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6034                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5819                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5678                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      418                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      332                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      341                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      273                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      313                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      369                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      324                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      295                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      215                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      192                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      329                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      250                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      399                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      169                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        63319                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      528.527867                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     322.547536                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     413.556682                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14397     22.74%     22.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11107     17.54%     40.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4705      7.43%     47.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3113      4.92%     52.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2233      3.53%     56.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2328      3.68%     59.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1953      3.08%     62.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1598      2.52%     65.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        21885     34.56%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          63319                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5233                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        77.334798                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2918.735904                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5230     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5298                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5298                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.311250                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.880356                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       22.145944                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4698     88.67%     88.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              33      0.62%     89.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             235      4.44%     93.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              22      0.42%     94.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55              12      0.23%     94.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              14      0.26%     94.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              10      0.19%     94.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               4      0.08%     94.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              30      0.57%     95.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95              15      0.28%     95.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            179      3.38%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             1      0.02%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             1      0.02%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             1      0.02%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             6      0.11%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             2      0.04%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             4      0.08%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            12      0.23%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             2      0.04%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             4      0.08%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             2      0.04%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             8      0.15%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5298                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2164522000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9752647000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2023500000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5348.46                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5233                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5233                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.588955                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.741886                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       24.816216                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4718     90.16%     90.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              33      0.63%     90.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             174      3.33%     94.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47               5      0.10%     94.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55               3      0.06%     94.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              12      0.23%     94.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71               8      0.15%     94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               1      0.02%     94.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              32      0.61%     95.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               4      0.08%     95.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            151      2.89%     98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            15      0.29%     98.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            10      0.19%     98.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             2      0.04%     98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             6      0.11%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             3      0.06%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             3      0.06%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             1      0.02%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            10      0.19%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             6      0.11%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            12      0.23%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             9      0.17%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             5      0.10%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             4      0.08%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             3      0.06%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5233                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5895300250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               13483350250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2023480000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       14567.23                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24098.46                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.71                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  33317.23                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.68                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.71                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.01                       # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.68                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.88                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     363251                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95908                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.76                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.12                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3612043.39                       # Average gap between requests
-system.physmem.pageHitRate                      87.81                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  234556560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  127982250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1578025800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                380868480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           123394455600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            60772181625                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1080221277750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1266709348065                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.494357                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1796832063750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     63085100000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     29299865000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  247363200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  134970000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1578634200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                385099920                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           123394455600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            61856765370                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1079269896750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1266867185040                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.577899                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1795248089750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     63085100000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30883852750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                15253451                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          13119801                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            515637                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12113296                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 4570787                       # Number of BTB hits
+system.physmem.avgWrQLen                        24.81                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     363810                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95775                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.90                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  81.01                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3619631.18                       # Average gap between requests
+system.physmem.pageHitRate                      87.89                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  221882640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  117933420                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1444607640                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                306899460                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           4693391040.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             4737017490                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              303974400                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       10896307530                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        5550083520                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       443242644240                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             471515616450                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              249.054730                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           1881921702000                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      481983250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1993748000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   1843690402750                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  14453321750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      8706248250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  23895177500                       # Time in different power states
+system.physmem_1.actEnergy                  230215020                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  122362185                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1444921800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                310146300                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           4816933680.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             4925461770                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              303573120                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       11119407240                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        5660238720                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       442986687510                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             471921610125                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              249.269176                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           1881622925500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      484393500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2046440000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   1842500290250                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  14740166500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      9065047000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  24384544250                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                15264339                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          13122374                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            525708                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             12102111                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 4571092                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             37.733636                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  859438                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              30658                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         6570706                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits             545483                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses          6025223                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       218035                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             37.771030                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  863726                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              33596                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         6525159                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             541190                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          5983969                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       222121                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9316925                       # DTB read hits
-system.cpu.dtb.read_misses                      17695                       # DTB read misses
+system.cpu.dtb.read_hits                      9321681                       # DTB read hits
+system.cpu.dtb.read_misses                      17691                       # DTB read misses
 system.cpu.dtb.read_acv                           211                       # DTB read access violations
-system.cpu.dtb.read_accesses                   764827                       # DTB read accesses
-system.cpu.dtb.write_hits                     6393212                       # DTB write hits
+system.cpu.dtb.read_accesses                   764795                       # DTB read accesses
+system.cpu.dtb.write_hits                     6394158                       # DTB write hits
 system.cpu.dtb.write_misses                      2442                       # DTB write misses
-system.cpu.dtb.write_acv                          158                       # DTB write access violations
-system.cpu.dtb.write_accesses                  298820                       # DTB write accesses
-system.cpu.dtb.data_hits                     15710137                       # DTB hits
-system.cpu.dtb.data_misses                      20137                       # DTB misses
-system.cpu.dtb.data_acv                           369                       # DTB access violations
-system.cpu.dtb.data_accesses                  1063647                       # DTB accesses
-system.cpu.itb.fetch_hits                     4018824                       # ITB hits
-system.cpu.itb.fetch_misses                      6310                       # ITB misses
-system.cpu.itb.fetch_acv                          701                       # ITB acv
-system.cpu.itb.fetch_accesses                 4025134                       # ITB accesses
+system.cpu.dtb.write_acv                          159                       # DTB write access violations
+system.cpu.dtb.write_accesses                  298776                       # DTB write accesses
+system.cpu.dtb.data_hits                     15715839                       # DTB hits
+system.cpu.dtb.data_misses                      20133                       # DTB misses
+system.cpu.dtb.data_acv                           370                       # DTB access violations
+system.cpu.dtb.data_accesses                  1063571                       # DTB accesses
+system.cpu.itb.fetch_hits                     4020046                       # ITB hits
+system.cpu.itb.fetch_misses                      6280                       # ITB misses
+system.cpu.itb.fetch_acv                          699                       # ITB acv
+system.cpu.itb.fetch_accesses                 4026326                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -350,27 +363,27 @@ system.cpu.itb.data_acv                             0                       # DT
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.numPwrStateTransitions               12752                       # Number of power state transitions
 system.cpu.pwrStateClkGateDist::samples          6376                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     281746974.905897                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    439847984.325030                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     281786440.323087                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    439974345.162947                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1000-5e+10         6376    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value        19000                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value       369000                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::total            6376                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON     92804534000                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 1796418712000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        185630526                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     96550538000                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 1796670343500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        193121889                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56141873                       # Number of instructions committed
-system.cpu.committedOps                      56141873                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2958149                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts                    56147815                       # Number of instructions committed
+system.cpu.committedOps                      56147815                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2978612                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                      6376                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   3592815966                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               3.306454                       # CPI: cycles per instruction
-system.cpu.ipc                               0.302439                       # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass             3199005      5.70%      5.70% # Class of committed instruction
-system.cpu.op_class_0::IntAlu                36197195     64.47%     70.17% # Class of committed instruction
-system.cpu.op_class_0::IntMult                  60822      0.11%     70.28% # Class of committed instruction
+system.cpu.quiesceCycles                   3593319874                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               3.439526                       # CPI: cycles per instruction
+system.cpu.ipc                               0.290738                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass             3199269      5.70%      5.70% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                36201024     64.47%     70.17% # Class of committed instruction
+system.cpu.op_class_0::IntMult                  60831      0.11%     70.28% # Class of committed instruction
 system.cpu.op_class_0::IntDiv                       0      0.00%     70.28% # Class of committed instruction
 system.cpu.op_class_0::FloatAdd                 38079      0.07%     70.35% # Class of committed instruction
 system.cpu.op_class_0::FloatCmp                     0      0.00%     70.35% # Class of committed instruction
@@ -398,34 +411,34 @@ system.cpu.op_class_0::SimdFloatMisc                0      0.00%     70.36% # Cl
 system.cpu.op_class_0::SimdFloatMult                0      0.00%     70.36% # Class of committed instruction
 system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     70.36% # Class of committed instruction
 system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     70.36% # Class of committed instruction
-system.cpu.op_class_0::MemRead                9319321     16.60%     86.95% # Class of committed instruction
-system.cpu.op_class_0::MemWrite               6372729     11.35%     98.31% # Class of committed instruction
-system.cpu.op_class_0::IprAccess               951086      1.69%    100.00% # Class of committed instruction
+system.cpu.op_class_0::MemRead                9320403     16.60%     86.95% # Class of committed instruction
+system.cpu.op_class_0::MemWrite               6373341     11.35%     98.31% # Class of committed instruction
+system.cpu.op_class_0::IprAccess               951232      1.69%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::total                 56141873                       # Class of committed instruction
+system.cpu.op_class_0::total                 56147815                       # Class of committed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6376                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211498                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74792     40.94%     40.94% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     131      0.07%     41.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1903      1.04%     42.05% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105883     57.95%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182709                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73425     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.inst.hwrei                     211531                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74800     40.93%     40.93% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     131      0.07%     41.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1905      1.04%     42.05% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105905     57.95%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182741                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73433     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1903      1.28%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73425     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148884                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1835945903000     97.18%     97.18% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                85568000      0.00%     97.18% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               710063500      0.04%     97.22% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             52480708000      2.78%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1889222242500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981723                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1905      1.28%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73433     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148902                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1837683771000     97.07%     97.07% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                86162500      0.00%     97.07% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               712688000      0.04%     97.11% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             54737244500      2.89%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1893219866000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981725                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.693454                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814870                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.693386                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814825                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -464,514 +477,514 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4173      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175546     91.22%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6807      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175574     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6808      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5128      2.66%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5130      2.67%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192434                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5876                       # number of protection mode switches
+system.cpu.kern.callpal::total                 192465                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5875                       # number of protection mode switches
 system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2091                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
 system.cpu.kern.mode_good::kernel                1905                      
 system.cpu.kern.mode_good::user                  1737                      
 system.cpu.kern.mode_good::idle                   168                      
-system.cpu.kern.mode_switch_good::kernel     0.324200                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.324255                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080344                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.392622                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        36856948000      1.95%      1.95% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           4192339500      0.22%      2.17% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1848172945000     97.83%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.080229                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.392541                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        37297482500      1.97%      1.97% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           4311459500      0.23%      2.20% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1851610914000     97.80%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4174                       # number of times the context was actually changed
-system.cpu.tickCycles                        85233988                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       100396538                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           1394263                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.980931                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            13942036                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1394775                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              9.995903                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          94238500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.980931                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999963                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999963                       # Average percentage of cache occupancy
+system.cpu.tickCycles                        85352026                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       107769863                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           1394246                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.980074                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            13946627                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1394758                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              9.999317                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          99338500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.980074                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999961                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999961                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          225                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          219                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63909041                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63909041                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data      7981560                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7981560                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5577988                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5577988                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183448                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183448                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199007                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199007                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13559548                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13559548                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13559548                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13559548                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1096304                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1096304                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       573678                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       573678                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        16581                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        16581                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1669982                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1669982                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1669982                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1669982                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  31558344500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  31558344500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  22538815500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  22538815500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    222577500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    222577500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  54097160000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  54097160000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  54097160000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  54097160000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9077864                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9077864                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6151666                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6151666                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200029                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200029                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199007                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199007                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15229530                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15229530                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15229530                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15229530                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120767                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120767                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093256                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.093256                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.082893                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.082893                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.109654                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.109654                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.109654                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.109654                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28786.125472                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28786.125472                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39288.268855                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39288.268855                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.647548                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13423.647548                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32393.858137                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32393.858137                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32393.858137                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32393.858137                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          63927104                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63927104                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data      7985415                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7985415                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5578562                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5578562                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183593                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183593                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199022                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199022                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13563977                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13563977                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13563977                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13563977                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1096352                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1096352                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       573692                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       573692                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        16450                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        16450                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1670044                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1670044                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1670044                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1670044                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  33571810000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  33571810000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  25337965000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  25337965000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    222587500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    222587500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  58909775000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  58909775000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  58909775000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  58909775000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9081767                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9081767                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6152254                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6152254                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200043                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200043                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199022                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199022                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15234021                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15234021                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15234021                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15234021                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120720                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120720                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093249                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.093249                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.082232                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.082232                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.109626                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.109626                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.109626                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.109626                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30621.378900                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 30621.378900                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44166.495262                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 44166.495262                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13531.155015                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13531.155015                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 35274.384986                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 35274.384986                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35274.384986                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35274.384986                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       837697                       # number of writebacks
-system.cpu.dcache.writebacks::total            837697                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21981                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        21981                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       269759                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       269759                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       837664                       # number of writebacks
+system.cpu.dcache.writebacks::total            837664                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21993                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        21993                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       269693                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       269693                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       291740                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       291740                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       291740                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       291740                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074323                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1074323                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       303919                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       303919                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16578                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        16578                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1378242                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1378242                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1378242                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1378242                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data       291686                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       291686                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       291686                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       291686                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074359                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1074359                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       303999                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       303999                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16447                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        16447                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1378358                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1378358                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1378358                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1378358                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9621                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9621                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16551                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16551                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30011433500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  30011433500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11481403000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11481403000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    205832000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    205832000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  41492836500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  41492836500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  41492836500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  41492836500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1534160500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1534160500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1534160500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   1534160500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.118345                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.118345                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049404                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049404                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.082878                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.082878                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090498                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090498                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090498                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090498                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27935.205241                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27935.205241                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37777.838832                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37777.838832                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12415.972976                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12415.972976                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30105.624774                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30105.624774                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30105.624774                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30105.624774                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.581530                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.581530                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92692.918857                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92692.918857                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           1476241                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.437018                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            19208652                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1476752                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             13.007365                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       33938325500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.437018                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994994                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994994                       # Average percentage of cache occupancy
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9623                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total         9623                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16553                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        16553                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  32011150000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  32011150000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12927980000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12927980000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    205437000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    205437000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  44939130000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  44939130000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  44939130000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  44939130000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1534184500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1534184500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1534184500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   1534184500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.118298                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.118298                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049413                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049413                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.082217                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.082217                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090479                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090479                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090479                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090479                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29795.580434                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29795.580434                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42526.389889                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42526.389889                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12490.849395                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12490.849395                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32603.380254                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 32603.380254                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32603.380254                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 32603.380254                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221383.044733                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221383.044733                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92683.169214                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92683.169214                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements           1477105                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.256263                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            19233040                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1477616                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             13.016264                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       36168250500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.256263                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.994641                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.994641                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          401                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          400                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          22162507                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         22162507                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     19208655                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        19208655                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      19208655                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         19208655                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     19208655                       # number of overall hits
-system.cpu.icache.overall_hits::total        19208655                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1476926                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1476926                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1476926                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1476926                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1476926                       # number of overall misses
-system.cpu.icache.overall_misses::total       1476926                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  20401531500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  20401531500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  20401531500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  20401531500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  20401531500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  20401531500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     20685581                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     20685581                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     20685581                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     20685581                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     20685581                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     20685581                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071399                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.071399                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.071399                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.071399                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.071399                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.071399                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13813.509614                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13813.509614                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13813.509614                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13813.509614                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13813.509614                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13813.509614                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          22188623                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         22188623                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     19233043                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        19233043                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      19233043                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         19233043                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     19233043                       # number of overall hits
+system.cpu.icache.overall_hits::total        19233043                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1477790                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1477790                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1477790                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1477790                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1477790                       # number of overall misses
+system.cpu.icache.overall_misses::total       1477790                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  20696583500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  20696583500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  20696583500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  20696583500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  20696583500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  20696583500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     20710833                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     20710833                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     20710833                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     20710833                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     20710833                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     20710833                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071353                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.071353                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.071353                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.071353                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.071353                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.071353                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14005.091048                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14005.091048                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14005.091048                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14005.091048                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14005.091048                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14005.091048                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      1476241                       # number of writebacks
-system.cpu.icache.writebacks::total           1476241                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1476926                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1476926                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1476926                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1476926                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1476926                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1476926                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  18924605500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  18924605500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  18924605500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  18924605500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  18924605500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  18924605500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071399                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071399                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071399                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.071399                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071399                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.071399                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12813.509614                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12813.509614                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12813.509614                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12813.509614                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12813.509614                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12813.509614                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           339622                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65416.328180                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5334629                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           405144                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            13.167242                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       6356009000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   267.504634                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5791.332200                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 59357.491346                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.004082                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088369                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.905723                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.998174                       # Average percentage of cache occupancy
+system.cpu.icache.writebacks::writebacks      1477105                       # number of writebacks
+system.cpu.icache.writebacks::total           1477105                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1477790                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1477790                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1477790                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1477790                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1477790                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1477790                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19218793500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  19218793500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19218793500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  19218793500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19218793500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  19218793500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071353                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071353                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071353                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.071353                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071353                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.071353                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13005.091048                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13005.091048                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13005.091048                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13005.091048                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13005.091048                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13005.091048                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           339628                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65408.612363                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5336325                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           405150                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            13.171233                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       6812996000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   268.308875                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5785.000603                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 59355.302886                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.004094                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088272                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.905690                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.998056                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          631                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          402                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5153                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        59330                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          578                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          457                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5137                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        59344                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         46327377                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        46327377                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       837697                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       837697                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1475656                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1475656                       # number of WritebackClean hits
+system.cpu.l2cache.tags.tag_accesses         46341016                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        46341016                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks       837664                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       837664                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1476525                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1476525                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           15                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           15                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187300                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187300                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1460502                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1460502                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       818651                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       818651                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1460502                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1005951                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2466453                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1460502                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1005951                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2466453                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       116630                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       116630                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16369                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        16369                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       272219                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       272219                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        16369                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       388849                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        405218                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        16369                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       388849                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       405218                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       249500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       249500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9053314500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9053314500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1334237500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1334237500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  19962557500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  19962557500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1334237500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  29015872000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  30350109500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1334237500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  29015872000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  30350109500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       837697                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       837697                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1475656                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1475656                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           20                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           20                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       303930                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       303930                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1476871                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1476871                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1090870                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1090870                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1476871                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1394800                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2871671                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1476871                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1394800                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2871671                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.250000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383740                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383740                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011084                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011084                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.249543                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.249543                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.011084                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.278785                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.141109                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011084                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.278785                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.141109                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        49900                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        49900                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77624.234759                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77624.234759                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81510.018938                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81510.018938                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73332.711897                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73332.711897                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81510.018938                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74619.896155                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74898.226387                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81510.018938                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74619.896155                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74898.226387                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_hits::cpu.data       187358                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187358                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1461386                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1461386                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       818548                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       818548                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      1461386                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1005906                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2467292                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      1461386                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1005906                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2467292                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       116652                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       116652                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16348                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        16348                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       272226                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       272226                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        16348                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       388878                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        405226                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        16348                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       388878                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       405226                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       331000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       331000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10499091500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  10499091500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1618484000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1618484000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  21963269500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  21963269500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1618484000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  32462361000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  34080845000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1618484000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  32462361000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  34080845000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       837664                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       837664                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1476525                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1476525                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           21                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           21                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       304010                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304010                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1477734                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1477734                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1090774                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1090774                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      1477734                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1394784                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2872518                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1477734                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1394784                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2872518                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.285714                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.285714                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383711                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.383711                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011063                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011063                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.249571                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.249571                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.011063                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.278809                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.141070                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011063                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.278809                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.141070                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55166.666667                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55166.666667                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90003.527586                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90003.527586                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 99001.957426                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 99001.957426                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80680.278519                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80680.278519                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 99001.957426                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83476.979927                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 84103.302848                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 99001.957426                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83476.979927                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 84103.302848                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        76715                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76715                       # number of writebacks
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116630                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116630                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16369                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16369                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       272219                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       272219                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16369                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       388849                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       405218                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16369                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       388849                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       405218                       # number of overall MSHR misses
+system.cpu.l2cache.writebacks::writebacks        76716                       # number of writebacks
+system.cpu.l2cache.writebacks::total            76716                       # number of writebacks
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116652                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       116652                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16348                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16348                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       272226                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       272226                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        16348                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       388878                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       405226                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16348                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       388878                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       405226                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9621                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9621                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16551                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16551                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       199500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       199500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7887014500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7887014500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1170547500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1170547500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  17243377000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  17243377000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1170547500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  25130391500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  26300939000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1170547500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  25130391500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  26300939000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1447515000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1447515000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1447515000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1447515000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383740                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383740                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.011084                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011084                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.249543                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249543                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.011084                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278785                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.141109                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011084                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278785                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.141109                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        39900                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        39900                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67624.234759                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67624.234759                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71510.018938                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71510.018938                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63343.767334                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63343.767334                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71510.018938                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64627.635663                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64905.653253                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71510.018938                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64627.635663                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64905.653253                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87457.857531                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87457.857531                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      5742250                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2870700                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1972                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          998                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          998                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9623                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9623                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16553                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16553                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       271000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       271000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9332571500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9332571500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1455004000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1455004000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  19244147500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  19244147500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1455004000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  28576719000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  30031723000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1455004000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  28576719000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  30031723000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1447540500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1447540500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1447540500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1447540500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.285714                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.285714                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383711                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383711                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.011063                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011063                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.249571                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249571                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.011063                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278809                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.141070                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011063                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278809                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.141070                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45166.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45166.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80003.527586                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80003.527586                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 89001.957426                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 89001.957426                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70691.805706                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70691.805706                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 89001.957426                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73485.049296                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74111.046675                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 89001.957426                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73485.049296                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74111.046675                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208880.303030                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208880.303030                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.831028                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.831028                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      5743946                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2871549                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1963                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          999                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          999                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2574859                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9621                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9621                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       914412                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1476241                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       819473                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           20                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           20                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       303930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       303930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1476926                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091030                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           23                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq          241                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4430038                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4217161                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8647199                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    188999168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142932652                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          331931820                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      340234                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               4923264                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      3228320                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000974                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.031197                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       2575626                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9623                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9623                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       914380                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1477105                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       819494                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           21                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           21                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       304010                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304010                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1477790                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1090934                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           24                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq          242                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4432629                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4217118                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8649747                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    189109696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142929468                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          332039164                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      340242                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               4923392                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      3229178                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000972                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.031158                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3225175     99.90%     99.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3145      0.10%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3226040     99.90%     99.90% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               3138      0.10%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3228320                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5198149000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3229178                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5199830000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       291883                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2215530716                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2216814740                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2103938977                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2103909988                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -985,12 +998,12 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51173                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51173                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5098                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51175                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51175                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -999,11 +1012,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        1812
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33102                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33106                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116552                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20392                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116556                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20408                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1012,50 +1025,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44332                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44348                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705940                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              5405000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2705956                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              5417000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               800000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               803500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              182000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              180500                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            14495500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            15637500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             2305500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5973000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             6005000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               90500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           216181312                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           216245035                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23481000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23483000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.301361                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.299106                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1731952426000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.301361                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.081335                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.081335                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1735874546000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.299106                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.081194                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.081194                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
@@ -1064,14 +1077,14 @@ system.iocache.demand_misses::tsunami.ide        41725                       # n
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21934383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21934383                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4859195929                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4859195929                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   4881130312                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4881130312                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   4881130312                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4881130312                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     22024383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     22024383                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4948308652                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4948308652                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   4970333035                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4970333035                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   4970333035                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4970333035                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1088,19 +1101,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126788.341040                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126788.341040                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116942.528133                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 116942.528133                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 116983.350797                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 116983.350797                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 116983.350797                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 116983.350797                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            18                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127308.572254                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 127308.572254                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119087.135445                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 119087.135445                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 119121.223128                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 119121.223128                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 119121.223128                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 119121.223128                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs          1402                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    4                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   13                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     4.500000                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs   107.846154                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
@@ -1112,14 +1125,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41725
 system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13284383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13284383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2779181979                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2779181979                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   2792466362                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2792466362                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   2792466362                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2792466362                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13374383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13374383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2868251757                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2868251757                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   2881626140                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2881626140                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   2881626140                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2881626140                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1128,75 +1141,75 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76788.341040                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76788.341040                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66884.433457                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66884.433457                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66925.496992                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 66925.496992                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66925.496992                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 66925.496992                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests        827436                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       381422                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          409                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77308.572254                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 77308.572254                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69028.007244                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69028.007244                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69062.340084                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 69062.340084                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69062.340084                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 69062.340084                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests        827498                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       381477                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          410                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295668                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9621                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9621                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       118227                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262241                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              137                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116498                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116498                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        288761                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           23                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295653                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9623                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9623                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       118228                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262245                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              138                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116520                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116520                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        288747                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           24                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33102                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148773                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           46                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181921                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33106                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148793                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           48                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181947                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1265346                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44332                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30816320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30860652                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1265372                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44348                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30816832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30861180                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33518380                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              433                       # Total snoops (count)
+system.membus.pkt_size::total                33518908                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              434                       # Total snoops (count)
 system.membus.snoopTraffic                      27584                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            463499                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001458                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.038162                       # Request fanout histogram
+system.membus.snoop_fanout::samples            463510                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.001463                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.038218                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  462823     99.85%     99.85% # Request fanout histogram
-system.membus.snoop_fanout::1                     676      0.15%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  462832     99.85%     99.85% # Request fanout histogram
+system.membus.snoop_fanout::1                     678      0.15%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              463499                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            29272500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              463510                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            30461000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1319341290                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1319556082                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               31000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               30000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2160301000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2160064000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy             943117                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1228,28 +1241,28 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893220881500                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
index 2c979b67f..b49f55c8a 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles
+
4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index ac0bee128..7fa651550 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -25,7 +25,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:134217727
+mem_ranges=0:134217727:0:0:0:0
 memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
@@ -60,7 +60,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=8796093022208:18446744073709551615
+ranges=8796093022208:18446744073709551615:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -194,7 +194,7 @@ useIndirect=true
 [system.cpu0.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -552,7 +552,7 @@ pipelined=false
 [system.cpu0.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -733,7 +733,7 @@ useIndirect=true
 [system.cpu1.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1091,7 +1091,7 @@ pipelined=false
 [system.cpu1.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1239,7 +1239,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=0:134217727
+addr_ranges=0:134217727:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -1285,7 +1285,7 @@ size=1024
 [system.l2c]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1383,27 +1383,27 @@ system=system
 
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -1423,6 +1423,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -1432,7 +1433,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1454,9 +1455,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index b3e079503..1abbf975c 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -3,14 +3,14 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:23
-gem5 executing on e108600-lin, pid 39569
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:46
+gem5 executing on e108600-lin, pid 28085
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 127844500
-Exiting @ tick 1907672102500 because m5_exit instruction encountered
+info: Launching CPU 1 @ 133768500
+Exiting @ tick 1907549438500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index dfe837c06..2752814bd 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,125 +1,125 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.906534                       # Number of seconds simulated
-sim_ticks                                1906533530000                       # Number of ticks simulated
-final_tick                               1906533530000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.907549                       # Number of seconds simulated
+sim_ticks                                1907549438500                       # Number of ticks simulated
+final_tick                               1907549438500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 134861                       # Simulator instruction rate (inst/s)
-host_op_rate                                   134861                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4533949866                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 343876                       # Number of bytes of host memory used
-host_seconds                                   420.50                       # Real time elapsed on the host
-sim_insts                                    56709432                       # Number of instructions simulated
-sim_ops                                      56709432                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 120882                       # Simulator instruction rate (inst/s)
+host_op_rate                                   120882                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4068519298                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 339992                       # Number of bytes of host memory used
+host_seconds                                   468.86                       # Real time elapsed on the host
+sim_insts                                    56676315                       # Number of instructions simulated
+sim_ops                                      56676315                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.inst           896192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24492096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            81664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           812544                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.inst           857728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24440448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           121088                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           888256                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26283456                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       896192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        81664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          977856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7904832                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7904832                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             14003                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            382689                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1276                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             12696                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             26308480                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       857728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       121088                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          978816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7911424                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7911424                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             13402                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            381882                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1892                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             13879                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                410679                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          123513                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               123513                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              470064                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12846402                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               42834                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              426189                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               504                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13785992                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         470064                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          42834                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             512897                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4146180                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4146180                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4146180                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             470064                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12846402                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              42834                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             426189                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              504                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17932172                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        410679                       # Number of read requests accepted
-system.physmem.writeReqs                       123513                       # Number of write requests accepted
-system.physmem.readBursts                      410679                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     123513                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26276352                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7903488                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26283456                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7904832                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                411070                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          123616                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               123616                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              449649                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12812485                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               63478                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              465653                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               503                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13791768                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         449649                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          63478                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             513127                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4147428                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4147428                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4147428                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             449649                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12812485                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              63478                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             465653                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              503                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17939196                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        411070                       # Number of read requests accepted
+system.physmem.writeReqs                       123616                       # Number of write requests accepted
+system.physmem.readBursts                      411070                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     123616                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26300288                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8192                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7909696                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26308480                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7911424                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      128                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               26110                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26073                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25765                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25777                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25805                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25558                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25453                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25268                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25514                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25670                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25901                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25385                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              25810                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25833                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25046                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25600                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8438                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8395                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7934                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7573                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7567                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7501                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7444                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7061                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7349                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7703                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7693                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7415                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7960                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8226                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7426                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7807                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               26240                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25986                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25958                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25690                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25582                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25570                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25628                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25343                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25590                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25698                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25929                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25525                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              26076                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25420                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25099                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25608                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8587                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8090                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7940                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7436                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7275                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7415                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7544                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7156                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7532                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7639                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7820                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7739                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8260                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7848                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7518                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7790                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          24                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1906529083500                       # Total gap between requests
+system.physmem.numWrRetry                          73                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1907545081500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  410679                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  411070                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 123513                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    317651                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     38167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     29690                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     24938                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        89                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         5                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 123616                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    316681                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     38865                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     30168                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     25023                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       157                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
@@ -159,130 +159,117 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1595                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2892                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3447                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4536                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6970                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     8000                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     9213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7568                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7850                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6391                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6719                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      301                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       57                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64501                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      529.911784                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     323.379229                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     416.310744                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14472     22.44%     22.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11319     17.55%     39.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5673      8.80%     48.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2735      4.24%     53.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2521      3.91%     56.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1561      2.42%     59.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1592      2.47%     61.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1422      2.20%     64.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        23206     35.98%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64501                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5582                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        73.544966                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2807.309852                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5579     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1506                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2688                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4408                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5702                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7521                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7738                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7919                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7524                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6449                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6711                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      778                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      552                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      317                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      295                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      306                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      300                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      340                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      374                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      376                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      412                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      297                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      243                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      360                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      442                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      187                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64388                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      531.308940                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     323.701196                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     416.289256                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14473     22.48%     22.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11513     17.88%     40.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5038      7.82%     48.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2819      4.38%     52.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2271      3.53%     56.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1853      2.88%     58.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1969      3.06%     62.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1608      2.50%     64.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22844     35.48%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64388                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5502                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        74.686478                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2827.616380                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5499     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5582                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5582                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.123253                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.862531                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       21.587113                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4829     86.51%     86.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             142      2.54%     89.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              15      0.27%     89.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              29      0.52%     89.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             220      3.94%     93.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              21      0.38%     94.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              13      0.23%     94.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               6      0.11%     94.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               3      0.05%     94.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               8      0.14%     94.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               8      0.14%     94.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               7      0.13%     94.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               7      0.13%     95.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.05%     95.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               1      0.02%     95.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               1      0.02%     95.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              21      0.38%     95.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.04%     95.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91              16      0.29%     95.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     95.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             179      3.21%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.04%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             3      0.05%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.04%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             5      0.09%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.02%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.04%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             6      0.11%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             3      0.05%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.02%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             2      0.04%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             2      0.04%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.02%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             1      0.02%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227            13      0.23%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5582                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4047296750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11745446750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2052840000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9857.80                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5502                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5502                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.462559                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.761271                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       24.372868                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4982     90.55%     90.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              39      0.71%     91.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             171      3.11%     94.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47               6      0.11%     94.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55               5      0.09%     94.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              13      0.24%     94.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71               3      0.05%     94.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               6      0.11%     94.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              29      0.53%     95.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               6      0.11%     95.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            149      2.71%     98.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             8      0.15%     98.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            14      0.25%     98.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             3      0.05%     98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            12      0.22%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             2      0.04%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             1      0.02%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             1      0.02%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             2      0.04%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            11      0.20%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             6      0.11%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199            14      0.25%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             3      0.05%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             8      0.15%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             5      0.09%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5502                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8174654750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               15879817250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2054710000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19892.48                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28607.80                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.78                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  38642.48                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.79                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.15                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.79                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        4.15                       # Average system write bandwidth in MiByte/s
@@ -290,78 +277,88 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.26                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.95                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     369870                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     99689                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.09                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.71                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3568995.95                       # Average gap between requests
-system.physmem.pageHitRate                      87.92                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  245828520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  134132625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1605310200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                401196240                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           124525493040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            58054066515                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1092995561250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1277961588390                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.306343                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1818124535500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     63663080000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     24745773250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  241799040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  131934000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1597120200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                399031920                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           124525493040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            57215830500                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1093730864250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1277842072950                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.243651                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1819353589250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     63663080000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     23516733250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.cpu0.branchPred.lookups               16961800                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         14485891                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           473040                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            10754552                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                4802971                       # Number of BTB hits
+system.physmem.avgRdQLen                         2.34                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.44                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     370634                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     99508                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.19                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.50                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3567598.71                       # Average gap between requests
+system.physmem.pageHitRate                      87.95                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  229108320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  121773960                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1470818580                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                320732460                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3850104960.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             4304249550                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              244489440                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy        8392475940                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        4645539360                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       448697608680                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             472278008880                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              247.583627                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           1897458465500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      385946750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1635552000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   1866968885000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  12097849250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      8056520750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  18404684750                       # Time in different power states
+system.physmem_1.actEnergy                  230629140                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  122578500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1463307300                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                324402120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3763440720.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             4252821870                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              240122400                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy        8356841250                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        4387202880                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       448891199505                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             472033988085                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              247.455703                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           1897589722250                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      380622500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1598754000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   1867843123750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  11424948500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      7975953750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  18326036000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.cpu0.branchPred.lookups               16746871                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         14324468                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           462281                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            10727156                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                4756454                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            44.659889                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 946597                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             35405                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        5065158                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits            501808                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses         4563350                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted       210940                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            44.340308                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 926491                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             34071                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        5119287                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits            497756                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         4621531                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       206577                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     9542415                       # DTB read hits
-system.cpu0.dtb.read_misses                     34570                       # DTB read misses
-system.cpu0.dtb.read_acv                          614                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  570502                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5776455                       # DTB write hits
-system.cpu0.dtb.write_misses                     8473                       # DTB write misses
-system.cpu0.dtb.write_acv                         390                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 186760                       # DTB write accesses
-system.cpu0.dtb.data_hits                    15318870                       # DTB hits
-system.cpu0.dtb.data_misses                     43043                       # DTB misses
-system.cpu0.dtb.data_acv                         1004                       # DTB access violations
-system.cpu0.dtb.data_accesses                  757262                       # DTB accesses
-system.cpu0.itb.fetch_hits                    1323023                       # ITB hits
-system.cpu0.itb.fetch_misses                     7096                       # ITB misses
-system.cpu0.itb.fetch_acv                         610                       # ITB acv
-system.cpu0.itb.fetch_accesses                1330119                       # ITB accesses
+system.cpu0.dtb.read_hits                     9412979                       # DTB read hits
+system.cpu0.dtb.read_misses                     34328                       # DTB read misses
+system.cpu0.dtb.read_acv                          621                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  567042                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5709982                       # DTB write hits
+system.cpu0.dtb.write_misses                     8326                       # DTB write misses
+system.cpu0.dtb.write_acv                         453                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 184750                       # DTB write accesses
+system.cpu0.dtb.data_hits                    15122961                       # DTB hits
+system.cpu0.dtb.data_misses                     42654                       # DTB misses
+system.cpu0.dtb.data_acv                         1074                       # DTB access violations
+system.cpu0.dtb.data_accesses                  751792                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1307701                       # ITB hits
+system.cpu0.itb.fetch_misses                     6903                       # ITB misses
+system.cpu0.itb.fetch_acv                         605                       # ITB acv
+system.cpu0.itb.fetch_accesses                1314604                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -374,606 +371,604 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numPwrStateTransitions              13007                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         6504                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    284289977.091175                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   440390387.503353                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows            1      0.02%      0.02% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         6503     99.98%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
+system.cpu0.numPwrStateTransitions              12949                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         6475                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    285376318.378378                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   440714536.369915                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10         6475    100.00%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value        79500                       # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           6504                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON    57511518999                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849022011001                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       115029541                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::total           6475                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON    59737777000                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847811661500                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       119482029                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          26105514                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      74391279                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   16961800                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           6251376                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     82220028                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1360432                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                        20                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               28534                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       140847                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       424678                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          286                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  8564382                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               320281                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         109600123                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.678752                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.000671                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          25760123                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      73391497                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   16746871                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           6180701                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     86881424                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1333696                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                         1                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               31404                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       137910                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       424032                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          391                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  8451225                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               316387                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples         113902133                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.644338                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.954525                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                95795479     87.40%     87.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  897061      0.82%     88.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1880834      1.72%     89.94% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  785387      0.72%     90.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2637004      2.41%     93.06% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  588358      0.54%     93.60% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  697546      0.64%     94.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  846325      0.77%     95.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 5472129      4.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               100270966     88.03%     88.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  886228      0.78%     88.81% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1867927      1.64%     90.45% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  772028      0.68%     91.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2612142      2.29%     93.42% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  579506      0.51%     93.93% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  682297      0.60%     94.53% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  834861      0.73%     95.26% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 5396178      4.74%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           109600123                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.147456                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.646715                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                20981522                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             77286866                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  8861450                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1818601                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                651683                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              621495                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                29133                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              64563390                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts                88112                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles                651683                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                21851256                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               51776932                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      17156942                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  9742291                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              8421017                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              62086646                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents               197170                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2004328                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                218757                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               4545100                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           41879351                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             74952395                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        74819888                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           123702                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             34134806                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 7744545                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1440211                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        234687                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 12404512                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             9945616                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            6151141                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1474462                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          959878                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  54892526                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1879962                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 53219239                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            73531                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        9606336                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      4159079                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1308684                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    109600123                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.485576                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.229164                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           113902133                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.140162                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.614247                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                20705856                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             82013409                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  8738075                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1805880                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                638912                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              611998                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                28528                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              63750944                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts                85334                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                638912                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                21566893                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               55682864                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      17571842                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  9616135                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              8825485                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              61313705                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents               198555                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2000786                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                244905                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               4945993                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           41348673                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             74029068                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        73897769                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           122571                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             33810397                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 7538276                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1420468                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        230583                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 12282803                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             9801073                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6065767                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1438850                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          936003                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  54214575                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1853218                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 52616152                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            74253                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        9353064                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      4027640                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1289091                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    113902133                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.461942                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.202978                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           87964311     80.26%     80.26% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            9240201      8.43%     88.69% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3866881      3.53%     92.22% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2775272      2.53%     94.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2892547      2.64%     97.39% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1421694      1.30%     98.69% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             953270      0.87%     99.56% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             366394      0.33%     99.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             119553      0.11%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           92500805     81.21%     81.21% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            9147500      8.03%     89.24% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3821730      3.36%     92.60% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2743420      2.41%     95.01% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2859412      2.51%     97.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1408857      1.24%     98.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             945269      0.83%     99.58% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             359735      0.32%     99.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             115405      0.10%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      109600123                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      113902133                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 170160     16.71%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     1      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     16.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                520319     51.11%     67.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               327644     32.18%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 168885     16.84%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     16.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                512937     51.15%     67.99% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               321005     32.01%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             2537      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             36500931     68.59%     68.59% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               56437      0.11%     68.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              25510      0.05%     68.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1267      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             9976302     18.75%     87.49% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5867670     11.03%     98.52% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            788585      1.48%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             36110587     68.63%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               55774      0.11%     68.74% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.74% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              25398      0.05%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1267      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9844131     18.71%     87.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5797742     11.02%     98.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            778716      1.48%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              53219239                       # Type of FU issued
-system.cpu0.iq.rate                          0.462657                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1018124                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.019131                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         216556534                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         66119650                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     51474452                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             573722                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            277081                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       260310                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              53925009                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 309817                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          608784                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              52616152                       # Type of FU issued
+system.cpu0.iq.rate                          0.440369                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1002827                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.019059                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         219643662                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         65164078                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     50897823                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             567855                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            274599                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       257683                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              53309936                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 306506                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          606515                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1996070                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         4265                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        18313                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       688901                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1936563                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         4258                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        18275                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       663361                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18448                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       363376                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        18355                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       359900                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                651683                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               48679015                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               759858                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           60350483                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           162315                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              9945616                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             6151141                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1664805                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 40490                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               518912                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         18313                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        186521                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       513145                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              699666                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             52530190                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              9602772                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           689049                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                638912                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               52175649                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              1047801                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           59607584                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           159494                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              9801073                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6065767                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1641866                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 39898                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               807337                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         18275                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        179860                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       504304                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              684164                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             51934418                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              9472740                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           681734                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3577995                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    15404618                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 8349417                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5801846                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.456667                       # Inst execution rate
-system.cpu0.iew.wb_sent                      51922146                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     51734762                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 26504573                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 36648490                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.449752                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.723211                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       10116425                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         571278                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           623596                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    107842796                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.464314                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.394503                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                      3539791                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    15207952                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 8258466                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5735212                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.434663                       # Inst execution rate
+system.cpu0.iew.wb_sent                      51337506                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     51155506                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 26224773                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 36250862                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.428144                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.723425                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts        9849450                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         564127                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           611071                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    112190301                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.442089                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.364280                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     90117032     83.56%     83.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7061240      6.55%     90.11% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      3809100      3.53%     93.64% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2021336      1.87%     95.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1578999      1.46%     96.98% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       575276      0.53%     97.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       421394      0.39%     97.91% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       458654      0.43%     98.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1799765      1.67%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     94635636     84.35%     84.35% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      6985533      6.23%     90.58% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      3776917      3.37%     93.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2005568      1.79%     95.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1565673      1.40%     97.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       565948      0.50%     97.63% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       418764      0.37%     98.01% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       453132      0.40%     98.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1783130      1.59%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    107842796                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            50072886                       # Number of instructions committed
-system.cpu0.commit.committedOps              50072886                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    112190301                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            49598051                       # Number of instructions committed
+system.cpu0.commit.committedOps              49598051                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      13411786                       # Number of memory references committed
-system.cpu0.commit.loads                      7949546                       # Number of loads committed
-system.cpu0.commit.membars                     194670                       # Number of memory barriers committed
-system.cpu0.commit.branches                   7579863                       # Number of branches committed
-system.cpu0.commit.fp_insts                    251347                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 46348996                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              640938                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass      2909270      5.81%      5.81% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        32681197     65.27%     71.08% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          55117      0.11%     71.19% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     71.19% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd         25038      0.05%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv          1267      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead        8144216     16.26%     87.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite       5468196     10.92%     98.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess       788585      1.57%    100.00% # Class of committed instruction
+system.cpu0.commit.refs                      13266916                       # Number of memory references committed
+system.cpu0.commit.loads                      7864510                       # Number of loads committed
+system.cpu0.commit.membars                     192309                       # Number of memory barriers committed
+system.cpu0.commit.branches                   7509354                       # Number of branches committed
+system.cpu0.commit.fp_insts                    248727                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 45907115                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              632192                       # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass      2885858      5.82%      5.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        32387672     65.30%     71.12% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          54445      0.11%     71.23% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     71.23% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd         24929      0.05%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv          1267      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        8056819     16.24%     87.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       5408346     10.90%     98.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess       778715      1.57%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         50072886                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1799765                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   166055766                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  122136916                       # The number of ROB writes
-system.cpu0.timesIdled                         488999                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        5429418                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3697477415                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   47166151                       # Number of Instructions Simulated
-system.cpu0.committedOps                     47166151                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              2.438816                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.438816                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.410035                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.410035                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                68768616                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               37693548                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   122704                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  131478                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1676808                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                792469                       # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          1260860                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          506.428743                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           10814422                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1261290                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             8.574096                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         26822500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.428743                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.989119                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.989119                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          430                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          412                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.839844                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         57625075                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        57625075                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6881291                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6881291                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3568585                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3568585                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       177059                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       177059                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       182551                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       182551                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10449876                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10449876                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10449876                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10449876                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1562512                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1562512                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1693924                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1693924                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20209                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        20209                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2828                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         2828                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3256436                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3256436                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3256436                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3256436                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  38980676000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  38980676000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  74553561151                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  74553561151                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    291267500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    291267500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     15945500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     15945500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 113534237151                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 113534237151                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 113534237151                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 113534237151                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      8443803                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8443803                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5262509                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5262509                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       197268                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       197268                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       185379                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       185379                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     13706312                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     13706312                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     13706312                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     13706312                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.185048                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.185048                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.321885                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.321885                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.102444                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.102444                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.015255                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.015255                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.237587                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.237587                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.237587                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.237587                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24947.441044                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 24947.441044                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44012.341257                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44012.341257                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14412.761641                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14412.761641                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5638.437058                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5638.437058                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34864.568857                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 34864.568857                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34864.568857                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 34864.568857                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      4192146                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         2471                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           109181                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             83                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    38.396296                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    29.771084                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       743371                       # number of writebacks
-system.cpu0.dcache.writebacks::total           743371                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       555767                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       555767                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1440437                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1440437                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5460                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5460                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1996204                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1996204                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1996204                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1996204                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1006745                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      1006745                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       253487                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       253487                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14749                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14749                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2828                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         2828                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1260232                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1260232                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1260232                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1260232                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7013                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7013                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10003                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10003                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17016                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17016                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  29619600000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  29619600000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11703772725                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11703772725                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    170858500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    170858500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     13117500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     13117500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  41323372725                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  41323372725                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  41323372725                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  41323372725                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1563340000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1563340000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1563340000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1563340000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.119229                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.119229                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048168                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048168                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.074766                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.074766                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.015255                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.015255                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.091945                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.091945                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.091945                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.091945                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29421.154314                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29421.154314                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46171.096447                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46171.096447                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11584.412503                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11584.412503                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4638.437058                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4638.437058                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32790.289982                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32790.289982                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32790.289982                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32790.289982                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222920.290888                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222920.290888                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91874.706159                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91874.706159                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements           908505                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.512047                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            7601055                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           909016                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             8.361850                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      28452405500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.512047                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995141                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.995141                       # Average percentage of cache occupancy
+system.cpu0.commit.op_class_0::total         49598051                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1783130                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   169680194                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  120607262                       # The number of ROB writes
+system.cpu0.timesIdled                         481372                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        5579896                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3694980588                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   46714728                       # Number of Instructions Simulated
+system.cpu0.committedOps                     46714728                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              2.557695                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.557695                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.390977                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.390977                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                68002622                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               37262146                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   121389                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  130195                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1657828                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                782201                       # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements          1253317                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          506.016530                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           10648438                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1253753                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             8.493250                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         28164500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.016530                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988314                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.988314                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          436                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          414                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3           22                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.851562                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         56881554                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        56881554                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6768789                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6768789                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3521179                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3521179                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       174329                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       174329                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       179913                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       179913                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10289968                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10289968                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10289968                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10289968                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1553170                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1553170                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1684058                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1684058                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20354                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        20354                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         3039                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         3039                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3237228                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3237228                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3237228                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3237228                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41477053500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  41477053500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  85173031211                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  85173031211                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    394024000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    394024000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     17098500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     17098500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 126650084711                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 126650084711                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 126650084711                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 126650084711                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8321959                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8321959                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5205237                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5205237                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       194683                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       194683                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       182952                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       182952                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13527196                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     13527196                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13527196                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     13527196                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.186635                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.186635                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.323531                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.323531                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.104549                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.104549                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.016611                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.016611                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.239313                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.239313                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.239313                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.239313                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26704.773785                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 26704.773785                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50576.067577                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 50576.067577                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19358.553601                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19358.553601                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5626.357354                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5626.357354                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39123.004222                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 39123.004222                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39123.004222                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 39123.004222                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      4484825                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         6096                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           108156                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            130                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    41.466262                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    46.892308                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks       737739                       # number of writebacks
+system.cpu0.dcache.writebacks::total           737739                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       551343                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       551343                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1432280                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1432280                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5686                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5686                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1983623                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1983623                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1983623                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1983623                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1001827                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      1001827                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       251778                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       251778                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14668                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14668                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         3039                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         3039                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1253605                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1253605                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1253605                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1253605                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         6977                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total         6977                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data         9906                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total         9906                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        16883                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        16883                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  31605979000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  31605979000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  13230681248                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  13230681248                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    170838000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    170838000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     14059500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     14059500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  44836660248                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  44836660248                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  44836660248                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  44836660248                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1556905500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1556905500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1556905500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1556905500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.120384                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.120384                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048370                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048370                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.075343                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.075343                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.016611                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.016611                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092673                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.092673                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092673                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.092673                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31548.340182                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31548.340182                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52548.996529                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52548.996529                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11646.986638                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11646.986638                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4626.357354                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4626.357354                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35766.178539                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35766.178539                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35766.178539                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35766.178539                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223148.272897                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223148.272897                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92217.348812                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92217.348812                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements           894430                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          509.352767                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            7502081                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           894941                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             8.382766                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      30333693500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.352767                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994830                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.994830                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          498                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          501                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          9473645                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         9473645                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst      7601055                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        7601055                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      7601055                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         7601055                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      7601055                       # number of overall hits
-system.cpu0.icache.overall_hits::total        7601055                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       963326                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       963326                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       963326                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        963326                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       963326                       # number of overall misses
-system.cpu0.icache.overall_misses::total       963326                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13819823495                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  13819823495                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  13819823495                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  13819823495                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  13819823495                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  13819823495                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      8564381                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      8564381                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      8564381                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      8564381                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      8564381                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      8564381                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.112481                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.112481                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.112481                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.112481                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.112481                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.112481                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14345.946746                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14345.946746                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14345.946746                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14345.946746                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14345.946746                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14345.946746                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         6257                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses          9346457                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         9346457                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst      7502081                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        7502081                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      7502081                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         7502081                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      7502081                       # number of overall hits
+system.cpu0.icache.overall_hits::total        7502081                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       949140                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       949140                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       949140                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        949140                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       949140                       # number of overall misses
+system.cpu0.icache.overall_misses::total       949140                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13882658989                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13882658989                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13882658989                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13882658989                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13882658989                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13882658989                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      8451221                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      8451221                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      8451221                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      8451221                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      8451221                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      8451221                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.112308                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.112308                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.112308                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.112308                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.112308                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.112308                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14626.566143                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14626.566143                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14626.566143                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14626.566143                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14626.566143                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14626.566143                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         6715                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              203                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              267                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    30.822660                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.149813                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks       908505                       # number of writebacks
-system.cpu0.icache.writebacks::total           908505                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        54062                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        54062                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        54062                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        54062                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        54062                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        54062                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       909264                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       909264                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       909264                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       909264                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       909264                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       909264                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12278033496                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  12278033496                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12278033496                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  12278033496                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12278033496                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  12278033496                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.106168                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.106168                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.106168                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.106168                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.106168                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.106168                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13503.265824                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13503.265824                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13503.265824                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13503.265824                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13503.265824                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13503.265824                       # average overall mshr miss latency
-system.cpu1.branchPred.lookups                4250134                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          3659200                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           108723                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2354380                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                 849662                       # Number of BTB hits
+system.cpu0.icache.writebacks::writebacks       894430                       # number of writebacks
+system.cpu0.icache.writebacks::total           894430                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        53904                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        53904                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        53904                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        53904                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        53904                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        53904                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       895236                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       895236                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       895236                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       895236                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       895236                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       895236                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12277660991                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  12277660991                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12277660991                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  12277660991                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12277660991                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  12277660991                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.105930                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.105930                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.105930                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.105930                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.105930                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.105930                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13714.440651                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13714.440651                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13714.440651                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13714.440651                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13714.440651                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13714.440651                       # average overall mshr miss latency
+system.cpu1.branchPred.lookups                4438770                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          3818546                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           113828                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2325021                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                 880835                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            36.088567                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 217108                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              8204                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        1308734                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits            157441                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses         1151293                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted        37897                       # Number of mispredicted indirect branches.
+system.cpu1.branchPred.BTBHitPct            37.885034                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 228893                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              8586                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        1265295                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits            163281                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         1102014                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted        40695                       # Number of mispredicted indirect branches.
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2331871                       # DTB read hits
-system.cpu1.dtb.read_misses                     15400                       # DTB read misses
-system.cpu1.dtb.read_acv                           73                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  429786                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1381774                       # DTB write hits
-system.cpu1.dtb.write_misses                     3743                       # DTB write misses
-system.cpu1.dtb.write_acv                          71                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 161427                       # DTB write accesses
-system.cpu1.dtb.data_hits                     3713645                       # DTB hits
-system.cpu1.dtb.data_misses                     19143                       # DTB misses
-system.cpu1.dtb.data_acv                          144                       # DTB access violations
-system.cpu1.dtb.data_accesses                  591213                       # DTB accesses
-system.cpu1.itb.fetch_hits                     662529                       # ITB hits
-system.cpu1.itb.fetch_misses                     3380                       # ITB misses
-system.cpu1.itb.fetch_acv                         133                       # ITB acv
-system.cpu1.itb.fetch_accesses                 665909                       # ITB accesses
+system.cpu1.dtb.read_hits                     2431495                       # DTB read hits
+system.cpu1.dtb.read_misses                     15697                       # DTB read misses
+system.cpu1.dtb.read_acv                          126                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  432376                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1439190                       # DTB write hits
+system.cpu1.dtb.write_misses                     3913                       # DTB write misses
+system.cpu1.dtb.write_acv                          68                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 163232                       # DTB write accesses
+system.cpu1.dtb.data_hits                     3870685                       # DTB hits
+system.cpu1.dtb.data_misses                     19610                       # DTB misses
+system.cpu1.dtb.data_acv                          194                       # DTB access violations
+system.cpu1.dtb.data_accesses                  595608                       # DTB accesses
+system.cpu1.itb.fetch_hits                     677547                       # ITB hits
+system.cpu1.itb.fetch_misses                     3477                       # ITB misses
+system.cpu1.itb.fetch_acv                         144                       # ITB acv
+system.cpu1.itb.fetch_accesses                 681024                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -986,572 +981,572 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numPwrStateTransitions               4980                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         2490                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    762354971.285141                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   386526411.344669                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         2490    100.00%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.numPwrStateTransitions               5082                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         2541                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    747256549.980323                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   396382548.008070                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10         2541    100.00%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value       400000                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value    975501000                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           2490                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON     8269651500                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898263878500                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                        16541794                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value    975495000                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           2541                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON     8770545000                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898778893500                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                        17543632                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           6749073                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      16895090                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    4250134                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           1224211                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      8698208                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 363130                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.MiscStallCycles               26231                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        65753                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        47571                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           39                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  1900929                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                80768                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          15768440                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.071450                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.476995                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           7091057                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      17620667                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    4438770                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           1273009                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      9220507                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 378986                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.MiscStallCycles               26066                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        68380                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        52547                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           66                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1980567                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                84330                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          16648116                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.058418                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.465473                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                12797159     81.16%     81.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  186632      1.18%     82.34% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  321640      2.04%     84.38% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  225512      1.43%     85.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  384419      2.44%     88.25% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  144313      0.92%     89.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  169042      1.07%     90.24% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  202635      1.29%     91.52% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 1337088      8.48%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                13552832     81.41%     81.41% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  195919      1.18%     82.58% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  328483      1.97%     84.56% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  235159      1.41%     85.97% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  403136      2.42%     88.39% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  149696      0.90%     89.29% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  175199      1.05%     90.34% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  211449      1.27%     91.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 1396243      8.39%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            15768440                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.256933                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.021358                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 5523877                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              7693314                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  2103455                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               273251                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                174542                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              146034                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                 7171                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              13792543                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                22640                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                174542                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 5705734                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 782365                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       5725411                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  2195690                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              1184696                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              13060888                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 4153                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                107025                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 30497                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents                586772                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands            8670673                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             15585724                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        15521516                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            57730                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              6788049                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1882616                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            491915                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         50500                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2201368                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             2434805                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1482534                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           303562                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          164759                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  11452007                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             560044                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 10991859                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            27120                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        2468765                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      1174488                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        414117                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     15768440                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.697080                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.421678                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            16648116                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.253013                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.004391                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 5799032                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              8189176                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  2194913                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               283013                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                181981                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              153262                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                 7666                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              14395116                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                24052                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                181981                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 5988192                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                 920488                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       6008083                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  2289928                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              1259442                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              13629732                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 4042                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                109065                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 36629                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents                635484                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands            9050413                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             16252880                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        16186853                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            59441                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              7085651                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1964754                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            511413                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         53676                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2285701                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             2541438                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1543271                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           322798                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          171550                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  11950332                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             586300                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 11472464                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            27528                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        2575040                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      1218372                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        432674                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     16648116                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.689115                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.415855                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           11265469     71.44%     71.44% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            1937394     12.29%     83.73% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2             827410      5.25%     88.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             596936      3.79%     92.76% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             547934      3.47%     96.24% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             289502      1.84%     98.07% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             188780      1.20%     99.27% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              83209      0.53%     99.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              31806      0.20%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           11949949     71.78%     71.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            2021085     12.14%     83.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2             863131      5.18%     89.10% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             621327      3.73%     92.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             572760      3.44%     96.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             302852      1.82%     98.10% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             196760      1.18%     99.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              86740      0.52%     99.80% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              33512      0.20%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       15768440                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       16648116                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  32091     10.27%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     10.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                173932     55.66%     65.93% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               106485     34.07%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  33628     10.30%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     10.30% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                182347     55.85%     66.15% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               110540     33.85%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass             4751      0.04%      0.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              6803980     61.90%     61.94% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               16523      0.15%     62.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd              13867      0.13%     62.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               2375      0.02%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             2450394     22.29%     84.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            1410696     12.83%     97.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            289273      2.63%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              7109835     61.97%     62.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               17232      0.15%     62.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              14002      0.12%     62.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               2375      0.02%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             2555661     22.28%     84.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1468866     12.80%     97.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            299742      2.61%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              10991859                       # Type of FU issued
-system.cpu1.iq.rate                          0.664490                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     312508                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.028431                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          37874505                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         14381418                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     10489971                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             217280                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            104295                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       101356                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              11183979                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 115637                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          113432                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              11472464                       # Type of FU issued
+system.cpu1.iq.rate                          0.653939                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     326515                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.028461                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          39721820                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         15008897                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     10951678                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             225266                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            107813                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       104885                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              11674098                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 120130                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          118360                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       527848                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         1066                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         5067                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       174171                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       553503                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         1124                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         5247                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       178223                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads          475                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        99025                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads          530                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked       100466                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                174542                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 497039                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               226226                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           12632900                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            57966                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              2434805                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             1482534                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            508876                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  6584                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               218362                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          5067                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         44763                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       141821                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              186584                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             10809707                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              2356029                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           182151                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                181981                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 560519                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               287887                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           13187033                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            58459                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              2541438                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1543271                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            532420                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  6842                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               279702                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          5247                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         45694                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       148663                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              194357                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             11283035                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              2456415                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           189428                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       620849                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     3747857                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 1612675                       # Number of branches executed
-system.cpu1.iew.exec_stores                   1391828                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.653479                       # Inst execution rate
-system.cpu1.iew.wb_sent                      10644010                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     10591327                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  5073681                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  7144079                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.640277                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.710194                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts        2479122                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         145927                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           162123                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     15327061                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.652859                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.628724                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       650401                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     3906085                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 1687752                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1449670                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.643141                       # Inst execution rate
+system.cpu1.iew.wb_sent                      11111703                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     11056563                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  5287384                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  7447136                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.630232                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.709989                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts        2591726                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         153626                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           169211                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     16186649                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.645421                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.620431                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     11704556     76.37%     76.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      1675096     10.93%     87.29% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       596024      3.89%     91.18% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       370132      2.41%     93.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       281840      1.84%     95.44% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       119415      0.78%     96.22% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       109784      0.72%     96.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       115974      0.76%     97.69% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       354240      2.31%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     12404611     76.63%     76.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      1746252     10.79%     87.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       623750      3.85%     91.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       386653      2.39%     93.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       297145      1.84%     95.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       125489      0.78%     96.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       112472      0.69%     96.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       119580      0.74%     97.71% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       370697      2.29%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     15327061                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            10006417                       # Number of instructions committed
-system.cpu1.commit.committedOps              10006417                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     16186649                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            10447204                       # Number of instructions committed
+system.cpu1.commit.committedOps              10447204                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       3215320                       # Number of memory references committed
-system.cpu1.commit.loads                      1906957                       # Number of loads committed
-system.cpu1.commit.membars                      46297                       # Number of memory barriers committed
-system.cpu1.commit.branches                   1432968                       # Number of branches committed
-system.cpu1.commit.fp_insts                     99355                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                  9296453                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              155642                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass       467886      4.68%      4.68% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu         5954632     59.51%     64.18% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          16225      0.16%     64.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd         13860      0.14%     64.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv          2375      0.02%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        1953254     19.52%     84.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       1308912     13.08%     97.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess       289273      2.89%    100.00% # Class of committed instruction
+system.cpu1.commit.refs                       3352983                       # Number of memory references committed
+system.cpu1.commit.loads                      1987935                       # Number of loads committed
+system.cpu1.commit.membars                      48912                       # Number of memory barriers committed
+system.cpu1.commit.branches                   1499265                       # Number of branches committed
+system.cpu1.commit.fp_insts                    102779                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                  9704534                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              163857                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass       490367      4.69%      4.69% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu         6221313     59.55%     64.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          16935      0.16%     64.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd         13993      0.13%     64.54% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.54% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.54% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.54% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv          2375      0.02%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        2036847     19.50%     84.06% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       1365632     13.07%     97.13% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess       299742      2.87%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         10006417                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               354240                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                    27350454                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   25410376                       # The number of ROB writes
-system.cpu1.timesIdled                         127916                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         773354                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3796525267                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                    9543281                       # Number of Instructions Simulated
-system.cpu1.committedOps                      9543281                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.733345                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.733345                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.576919                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.576919                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                13915898                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                7574327                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    57027                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   56084                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 548336                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                233992                       # number of misc regfile writes
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements           125899                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          488.643443                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            2930828                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           126411                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            23.184913                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      47496090500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   488.643443                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.954382                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.954382                       # Average percentage of cache occupancy
+system.cpu1.commit.op_class_0::total         10447204                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               370697                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                    28744557                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   26537349                       # The number of ROB writes
+system.cpu1.timesIdled                         134728                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         895516                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3797555246                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                    9961587                       # Number of Instructions Simulated
+system.cpu1.committedOps                      9961587                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.761128                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.761128                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.567818                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.567818                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                14521823                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                7909607                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    58779                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   57835                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 571518                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                244969                       # number of misc regfile writes
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements           130966                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          487.964655                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            3061418                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           131478                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            23.284641                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      49531315500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   487.964655                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.953056                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.953056                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          239                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          223                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         13906652                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        13906652                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1865609                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1865609                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data       981966                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        981966                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        38120                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        38120                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        34857                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        34857                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      2847575                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         2847575                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      2847575                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        2847575                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       231819                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       231819                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       282423                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       282423                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5078                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         5078                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2912                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         2912                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       514242                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        514242                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       514242                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       514242                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3027811000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   3027811000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  10676531998                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  10676531998                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     51207500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     51207500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     16199500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     16199500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  13704342998                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  13704342998                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  13704342998                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  13704342998                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2097428                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2097428                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1264389                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1264389                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        43198                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        43198                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        37769                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        37769                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      3361817                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3361817                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      3361817                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3361817                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.110525                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.110525                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.223367                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.223367                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.117552                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.117552                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.077100                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.077100                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.152965                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.152965                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.152965                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.152965                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13061.099392                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13061.099392                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37803.337540                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 37803.337540                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10084.186688                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10084.186688                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5563.015110                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5563.015110                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26649.598823                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 26649.598823                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26649.598823                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 26649.598823                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs       625764                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets          300                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs            24254                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets             19                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    25.800445                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    15.789474                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks        81179                       # number of writebacks
-system.cpu1.dcache.writebacks::total            81179                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       142547                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       142547                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       235954                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       235954                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          779                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total          779                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       378501                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       378501                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       378501                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       378501                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        89272                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total        89272                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        46469                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        46469                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4299                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4299                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2912                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         2912                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       135741                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       135741                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       135741                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       135741                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          182                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total          182                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3016                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3016                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3198                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3198                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1142608000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1142608000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1700967690                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1700967690                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     38610000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     38610000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     13287500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     13287500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2843575690                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   2843575690                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2843575690                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   2843575690                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     35749500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     35749500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data     35749500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total     35749500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.042563                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042563                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036752                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036752                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.099518                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.099518                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.077100                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.077100                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.040377                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.040377                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.040377                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.040377                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12799.175553                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12799.175553                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36604.353225                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36604.353225                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8981.158409                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8981.158409                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  4563.015110                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  4563.015110                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20948.539424                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20948.539424                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20948.539424                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20948.539424                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196425.824176                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196425.824176                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11178.705441                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11178.705441                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements           243897                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          471.203096                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            1645008                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           244406                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             6.730637                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1879506005500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   471.203096                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.920319                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.920319                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          420                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          2145410                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         2145410                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst      1645008                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1645008                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      1645008                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1645008                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      1645008                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1645008                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       255921                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       255921                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       255921                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        255921                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       255921                       # number of overall misses
-system.cpu1.icache.overall_misses::total       255921                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3476894499                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   3476894499                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   3476894499                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   3476894499                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   3476894499                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   3476894499                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      1900929                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1900929                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      1900929                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1900929                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      1900929                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1900929                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.134629                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.134629                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.134629                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.134629                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.134629                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.134629                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13585.811633                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13585.811633                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13585.811633                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13585.811633                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13585.811633                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13585.811633                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs          470                       # number of cycles access was blocked
+system.cpu1.dcache.tags.tag_accesses         14512669                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        14512669                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1946433                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1946433                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1026063                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1026063                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        40785                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        40785                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        37242                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        37242                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      2972496                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         2972496                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      2972496                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        2972496                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       241711                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       241711                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       292248                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       292248                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5308                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         5308                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         3094                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         3094                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       533959                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        533959                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       533959                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       533959                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3394927000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3394927000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  12114051455                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  12114051455                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     54394000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     54394000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     17165000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     17165000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  15508978455                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  15508978455                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  15508978455                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  15508978455                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2188144                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2188144                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1318311                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1318311                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        46093                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        46093                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        40336                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        40336                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      3506455                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      3506455                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      3506455                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      3506455                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.110464                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.110464                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.221684                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.221684                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.115158                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.115158                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.076706                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.076706                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.152279                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.152279                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.152279                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.152279                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14045.397189                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14045.397189                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41451.272395                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 41451.272395                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10247.550867                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10247.550867                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5547.834518                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5547.834518                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29045.260881                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 29045.260881                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29045.260881                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 29045.260881                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs       715753                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets          884                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs            24925                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets             13                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    28.716269                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets           68                       # average number of cycles each access was blocked
+system.cpu1.dcache.writebacks::writebacks        84601                       # number of writebacks
+system.cpu1.dcache.writebacks::total            84601                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       148639                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       148639                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       243827                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       243827                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          846                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total          846                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       392466                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       392466                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       392466                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       392466                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        93072                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total        93072                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        48421                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        48421                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4462                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4462                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         3093                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         3093                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       141493                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       141493                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       141493                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       141493                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          218                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total          218                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3153                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3153                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3371                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3371                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1262526500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1262526500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1947214752                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1947214752                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     40086500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     40086500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     14072000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     14072000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3209741252                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   3209741252                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3209741252                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   3209741252                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     41866500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     41866500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data     41866500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total     41866500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.042535                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042535                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036730                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036730                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.096804                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.096804                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.076681                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.076681                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.040352                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.040352                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.040352                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.040352                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13565.051788                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13565.051788                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40214.261416                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40214.261416                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8983.975796                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8983.975796                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  4549.628193                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  4549.628193                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22684.805976                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22684.805976                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22684.805976                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22684.805976                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192048.165138                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192048.165138                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12419.608425                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12419.608425                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements           256896                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          470.782709                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            1710963                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           257408                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             6.646891                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1882016787500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   470.782709                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.919497                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.919497                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          424                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses          2238053                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         2238053                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst      1710963                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1710963                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      1710963                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         1710963                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      1710963                       # number of overall hits
+system.cpu1.icache.overall_hits::total        1710963                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       269604                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       269604                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       269604                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        269604                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       269604                       # number of overall misses
+system.cpu1.icache.overall_misses::total       269604                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3754413998                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   3754413998                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   3754413998                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   3754413998                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   3754413998                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   3754413998                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1980567                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1980567                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      1980567                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1980567                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1980567                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1980567                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.136125                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.136125                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.136125                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.136125                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.136125                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.136125                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13925.661333                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13925.661333                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13925.661333                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13925.661333                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13925.661333                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13925.661333                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs          473                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               38                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               42                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.368421                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    11.261905                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks       243897                       # number of writebacks
-system.cpu1.icache.writebacks::total           243897                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        11440                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        11440                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        11440                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        11440                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        11440                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        11440                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       244481                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       244481                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       244481                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       244481                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       244481                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       244481                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3131245499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3131245499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3131245499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3131245499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3131245499                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3131245499                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.128611                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.128611                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.128611                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.128611                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.128611                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.128611                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12807.725341                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12807.725341                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12807.725341                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 12807.725341                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12807.725341                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 12807.725341                       # average overall mshr miss latency
+system.cpu1.icache.writebacks::writebacks       256896                       # number of writebacks
+system.cpu1.icache.writebacks::total           256896                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        12118                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        12118                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        12118                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        12118                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        12118                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        12118                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       257486                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       257486                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       257486                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       257486                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       257486                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       257486                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3368066498                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   3368066498                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3368066498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   3368066498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3368066498                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   3368066498                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.130006                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.130006                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.130006                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.130006                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.130006                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.130006                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13080.581072                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13080.581072                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13080.581072                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13080.581072                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13080.581072                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13080.581072                       # average overall mshr miss latency
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1564,12 +1559,12 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                 7374                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7374                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               54571                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              54571                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11828                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               54611                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              54611                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11908                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1010                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1578,11 +1573,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        1814
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        40428                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        40508                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83462                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83462                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  123890                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47312                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  123970                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47632                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2733                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1591,50 +1586,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        73538                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        73858                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661656                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661656                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2735194                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             12271500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2735514                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             12353502                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               818000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               824500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              178500                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              180500                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            14105000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            13988000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             2828000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy             2829000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6057000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             6060500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               90500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           216200796                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           216282007                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            27409000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            27449000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41958000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                41699                       # number of replacements
-system.iocache.tags.tagsinuse                0.499134                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.490946                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41715                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1712299837000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.499134                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.031196                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.031196                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1714262123000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.490946                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.030684                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.030684                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375579                       # Number of tag accesses
 system.iocache.tags.data_accesses              375579                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::tsunami.ide          179                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              179                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
@@ -1643,14 +1638,14 @@ system.iocache.demand_misses::tsunami.ide        41731                       # n
 system.iocache.demand_misses::total             41731                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41731                       # number of overall misses
 system.iocache.overall_misses::total            41731                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     22562883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     22562883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4858746913                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4858746913                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   4881309796                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4881309796                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   4881309796                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4881309796                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     22774383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     22774383                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4918988624                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4918988624                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   4941763007                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4941763007                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   4941763007                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4941763007                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          179                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            179                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1667,19 +1662,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126049.625698                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126049.625698                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116931.722011                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 116931.722011                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 116970.832139                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 116970.832139                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 116970.832139                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 116970.832139                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            10                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127231.189944                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 127231.189944                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118381.512899                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118381.512899                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 118419.472502                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 118419.472502                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 118419.472502                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 118419.472502                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs          1165                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    8                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            5                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs   145.625000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
 system.iocache.writebacks::total                41520                       # number of writebacks
@@ -1691,14 +1686,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41731
 system.iocache.demand_mshr_misses::total        41731                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41731                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41731                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13612883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13612883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2778734565                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2778734565                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   2792347448                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2792347448                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   2792347448                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2792347448                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13824383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13824383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2838948426                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2838948426                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   2852772809                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2852772809                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   2852772809                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2852772809                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1707,200 +1702,200 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76049.625698                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76049.625698                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66873.665889                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66873.665889                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66913.025041                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 66913.025041                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66913.025041                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 66913.025041                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   345621                       # number of replacements
-system.l2c.tags.tagsinuse                65429.949099                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4347999                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   411104                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    10.576397                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               5987439000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     292.894251                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5335.962916                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    58874.943819                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      203.860157                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      722.287955                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.004469                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.081420                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.898360                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.003111                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.011021                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.998382                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65483                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         1723                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1817                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5637                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        56151                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.999191                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 38487323                       # Number of tag accesses
-system.l2c.tags.data_accesses                38487323                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks       824550                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          824550                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       880861                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          880861                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            2842                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1401                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                4243                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           470                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           444                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               914                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           147625                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            30184                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               177809                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        895088                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        243149                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1138237                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       727494                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        80955                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           808449                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              895088                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              875119                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              243149                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              111139                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2124495                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             895088                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             875119                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             243149                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             111139                       # number of overall hits
-system.l2c.overall_hits::total                2124495                       # number of overall hits
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77231.189944                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 77231.189944                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68322.786533                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68322.786533                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68360.998035                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68360.998035                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68360.998035                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68360.998035                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                   345941                       # number of replacements
+system.l2c.tags.tagsinuse                65423.095027                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4335515                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   411463                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    10.536828                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               6416575000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks     293.307825                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5315.079150                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    58827.069962                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      210.319847                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      777.318243                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.004476                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.081102                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.897630                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.003209                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.011861                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.998277                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         1694                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1843                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5673                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        56180                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 38390429                       # Number of tag accesses
+system.l2c.tags.data_accesses                38390429                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks       822340                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          822340                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks       875169                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total          875169                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data            2863                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            1494                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                4357                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           501                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           467                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               968                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           145988                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            30963                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               176951                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        881644                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        255533                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total           1137177                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       722233                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data        84048                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           806281                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.inst              881644                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              868221                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              255533                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              115011                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2120409                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             881644                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             868221                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             255533                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             115011                       # number of overall hits
+system.l2c.overall_hits::total                2120409                       # number of overall hits
 system.l2c.UpgradeReq_misses::cpu0.data             6                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data             3                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                 9                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data             5                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                11                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         110021                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          11230                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             121251                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        14005                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         1293                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           15298                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       272996                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         1575                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         274571                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst             14005                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            383017                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1293                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             12805                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                411120                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            14005                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           383017                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1293                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            12805                       # number of overall misses
-system.l2c.overall_misses::total               411120                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data       334500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data        59000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       393500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   9803404500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1283749500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  11087154000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1179329500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    110888000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   1290217500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  20156491500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    149319000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  20305810500                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1179329500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  29959896000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    110888000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1433068500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     32683182000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1179329500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  29959896000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    110888000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1433068500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    32683182000                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       824550                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       824550                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks       880861                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total       880861                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         2848                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         1404                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            4252                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          470                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          445                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           915                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       257646                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        41414                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           299060                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       909093                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       244442                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total       1153535                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data      1000490                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data        82530                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      1083020                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          909093                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1258136                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          244442                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          123944                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2535615                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         909093                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1258136                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         244442                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         123944                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2535615                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.002107                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.002137                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.002117                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.002247                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.001093                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.427024                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.271164                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.405440                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.015405                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005290                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.013262                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.272862                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.019084                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.253523                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.015405                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.304432                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005290                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.103313                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.162138                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.015405                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.304432                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005290                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.103313                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.162138                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data        55750                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19666.666667                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 43722.222222                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89104.848165                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 114314.292075                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 91439.691219                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84207.747233                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 85760.247486                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 84338.965878                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73834.384020                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 94805.714286                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 73954.680210                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 84207.747233                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 78220.799599                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 85760.247486                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 111914.759859                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 79497.913018                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 84207.747233                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 78220.799599                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 85760.247486                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 111914.759859                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 79497.913018                       # average overall miss latency
+system.l2c.ReadExReq_misses::cpu0.data         109595                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          12065                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             121660                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        13405                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst         1909                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total           15314                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       272577                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data         1964                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         274541                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.inst             13405                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            382172                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1909                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             14029                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                411515                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            13405                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           382172                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1909                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            14029                       # number of overall misses
+system.l2c.overall_misses::total               411515                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data       332000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data       117000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       449000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  11349867000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1517430000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  12867297000                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1343054000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst    191509000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total   1534563000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  22206710000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data    230127000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  22436837000                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   1343054000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  33556577000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    191509000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   1747557000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     36838697000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   1343054000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  33556577000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    191509000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1747557000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    36838697000                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks       822340                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       822340                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks       875169                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total       875169                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         2869                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         1499                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            4368                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          501                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          468                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total           969                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       255583                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        43028                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           298611                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       895049                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       257442                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total       1152491                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       994810                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        86012                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      1080822                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          895049                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1250393                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          257442                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          129040                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2531924                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         895049                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1250393                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         257442                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         129040                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2531924                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.002091                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.003336                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.002518                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.002137                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.001032                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.428804                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.280399                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.407420                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.014977                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.007415                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.013288                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.273999                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.022834                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.254011                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014977                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.305642                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.007415                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.108718                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.162531                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014977                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.305642                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.007415                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.108718                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.162531                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 55333.333333                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data        23400                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 40818.181818                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103561.905196                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 125771.239121                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 105764.400789                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100190.525923                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 100319.015191                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 100206.543033                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81469.493024                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 117172.606925                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 81724.904477                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 100190.525923                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 87804.907215                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 100319.015191                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 124567.467389                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 89519.694300                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 100190.525923                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 87804.907215                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 100319.015191                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 124567.467389                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 89519.694300                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks               81993                       # number of writebacks
-system.l2c.writebacks::total                    81993                       # number of writebacks
+system.l2c.writebacks::writebacks               82096                       # number of writebacks
+system.l2c.writebacks::total                    82096                       # number of writebacks
 system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           17                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total           18                       # number of ReadCleanReq MSHR hits
@@ -1910,249 +1905,249 @@ system.l2c.demand_mshr_hits::total                 18                       # nu
 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst            17                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks           10                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total           10                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::writebacks           11                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total           11                       # number of CleanEvict MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu0.data            6                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data            3                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total            9                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data            5                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           11                       # number of UpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       110021                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        11230                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        121251                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        14004                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1276                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        15280                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       272996                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1575                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       274571                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        14004                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       383017                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         1276                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        12805                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           411102                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        14004                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       383017                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         1276                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        12805                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          411102                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7013                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data          182                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadExReq_mshr_misses::cpu0.data       109595                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        12065                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        121660                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        13404                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1892                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total        15296                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       272577                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1964                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       274541                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        13404                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       382172                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         1892                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        14029                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           411497                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        13404                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       382172                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         1892                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        14029                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          411497                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data         6977                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data          218                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::total         7195                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10003                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3016                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        13019                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17016                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3198                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        20214                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       274500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data        57500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       332000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data         9906                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3153                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        13059                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        16883                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3371                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        20254                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       272000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data        95500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       367500                       # number of UpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        18500                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::total        18500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   8703194500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1171449500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   9874644000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1039194500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst     96887500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   1136082000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17432939000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    133569000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  17566508000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1039194500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  26136133500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     96887500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1305018500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  28577234000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1039194500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  26136133500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     96887500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1305018500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  28577234000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1475661000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     33474500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1509135500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1475661000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data     33474500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1509135500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  10253916501                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1396780000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  11650696501                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1208926000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    171260500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   1380186500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  19486691503                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    210487000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  19697178503                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1208926000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  29740608004                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    171260500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1607267000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  32728061504                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1208926000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  29740608004                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    171260500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1607267000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  32728061504                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1469664500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     39141500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1508806000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1469664500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data     39141500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1508806000                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.002107                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.002137                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.002117                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.002247                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.001093                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.427024                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.271164                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.405440                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.015404                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005220                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013246                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.272862                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.019084                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.253523                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015404                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.304432                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005220                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.103313                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.162131                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015404                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.304432                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005220                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.103313                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.162131                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        45750                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19166.666667                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 36888.888889                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.002091                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.003336                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.002518                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.002137                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.001032                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.428804                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.280399                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.407420                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.014976                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007349                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013272                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.273999                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.022834                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.254011                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014976                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.305642                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007349                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.108718                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.162523                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014976                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.305642                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007349                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.108718                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.162523                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 45333.333333                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        19100                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 33409.090909                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        18500                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        18500                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79104.848165                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 104314.292075                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 81439.691219                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74206.976578                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75930.642633                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74350.916230                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63857.855060                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 84805.714286                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63978.016615                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74206.976578                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68237.528621                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75930.642633                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 101914.759859                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 69513.731385                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74206.976578                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68237.528621                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75930.642633                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 101914.759859                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 69513.731385                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210417.938115                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183925.824176                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209747.810980                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86721.967560                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10467.323327                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 74657.935094                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        850516                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       398567                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          435                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93561.900643                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 115771.239121                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 95764.396687                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90191.435392                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 90518.234672                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90231.858002                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71490.593495                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107172.606925                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71745.854000                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90191.435392                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77819.955423                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90518.234672                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 114567.467389                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 79534.143637                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90191.435392                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77819.955423                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90518.234672                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 114567.467389                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 79534.143637                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210644.188046                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179548.165138                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209702.015288                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87049.961500                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11611.242955                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 74494.223363                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests        852108                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       399805                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          437                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                7195                       # Transaction distribution
-system.membus.trans_dist::ReadResp             297176                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13019                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13019                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       123513                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262911                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             6111                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           4826                       # Transaction distribution
+system.membus.trans_dist::ReadResp             297167                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13059                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13059                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       123616                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           263125                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             6609                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           5164                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            121549                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           121146                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        290030                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           49                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            121953                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           121548                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        290016                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           44                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40428                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1177677                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           98                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1218203                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40508                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1179616                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           88                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1220212                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83445                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        83445                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1301648                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        73538                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31530048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31603586                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1303657                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        73858                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31561664                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     31635522                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                34261826                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            11676                       # Total snoops (count)
-system.membus.snoopTraffic                      28672                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            484282                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001355                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.036780                       # Request fanout histogram
+system.membus.pkt_size::total                34293762                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            12507                       # Total snoops (count)
+system.membus.snoopTraffic                      28800                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            485548                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.001427                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.037752                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  483626     99.86%     99.86% # Request fanout histogram
-system.membus.snoop_fanout::1                     656      0.14%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  484855     99.86%     99.86% # Request fanout histogram
+system.membus.snoop_fanout::1                     693      0.14%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              484282                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            36370000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              485548                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            36350498                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1352579532                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1353965073                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               62000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               55000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2178718000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2179761000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy             960113                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy             960863                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      5113699                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2556514                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       337557                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1071                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1003                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests      5108724                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2554049                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       343728                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           1075                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         1007                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops           68                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
 system.toL2Bus.trans_dist::ReadReq               7195                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2265500                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13019                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13019                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       906543                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1152402                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          825837                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           10249                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          5740                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          15989                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           300358                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          300358                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1153745                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1104612                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           49                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq          203                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2726862                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3834313                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       732820                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       401077                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7695072                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    116326272                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    128153608                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     31253696                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     13151546                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              288885122                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          379909                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                   6725760                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          2940742                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.121053                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.326514                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadResp           2263429                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13059                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13059                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       904436                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1151326                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          825788                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           10854                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          6132                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          16986                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           300014                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          300014                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1152722                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1103559                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError           44                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq          238                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2684715                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3812301                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       771824                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       417816                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7686656                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    114526656                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    127297140                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     32917632                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     13697806                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              288439234                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          382362                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                   6813696                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples          2939714                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.123574                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.329478                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                2585068     87.91%     87.91% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 355364     12.08%     99.99% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    309      0.01%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      1      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                2576793     87.65%     87.65% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 362587     12.33%     99.99% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    316      0.01%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                     18      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            2940742                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4550461413                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            2939714                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4544765338                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           301885                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1365446887                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1344393906                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1921756875                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1911305093                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         368286347                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         387758410                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         208891088                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         217734513                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -2184,194 +2179,194 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907549438500                       # Cumulative time (in ticks) in various power states
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6504                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    179089                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   63660     40.34%     40.34% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.08%     40.42% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1926      1.22%     41.64% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    175      0.11%     41.75% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  91921     58.25%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              157813                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    62631     49.19%     49.19% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.10%     49.30% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1926      1.51%     50.81% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     175      0.14%     50.95% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   62456     49.05%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               127319                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1863112245000     97.74%     97.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               65536000      0.00%     97.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              577434000      0.03%     97.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30               84972500      0.00%     97.78% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            42413276000      2.22%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1906253463500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.983836                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6475                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    176726                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   62785     40.28%     40.28% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.08%     40.36% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1925      1.23%     41.60% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    181      0.12%     41.71% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  90860     58.29%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              155882                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    61770     49.18%     49.18% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     131      0.10%     49.29% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1925      1.53%     50.82% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     181      0.14%     50.96% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   61589     49.04%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               125596                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1862335551000     97.65%     97.65% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               64321000      0.00%     97.65% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              576343500      0.03%     97.68% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30               87551500      0.00%     97.68% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            44167527000      2.32%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1907231294000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.983834                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.679453                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.806771                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         7      3.93%      3.93% # number of syscalls executed
-system.cpu0.kern.syscall::3                        15      8.43%     12.36% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      2.25%     14.61% # number of syscalls executed
-system.cpu0.kern.syscall::6                        26     14.61%     29.21% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.56%     29.78% # number of syscalls executed
-system.cpu0.kern.syscall::17                        6      3.37%     33.15% # number of syscalls executed
-system.cpu0.kern.syscall::19                        7      3.93%     37.08% # number of syscalls executed
-system.cpu0.kern.syscall::20                        4      2.25%     39.33% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.56%     39.89% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.69%     41.57% # number of syscalls executed
-system.cpu0.kern.syscall::33                        6      3.37%     44.94% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      1.12%     46.07% # number of syscalls executed
-system.cpu0.kern.syscall::45                       29     16.29%     62.36% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.69%     64.04% # number of syscalls executed
-system.cpu0.kern.syscall::48                        8      4.49%     68.54% # number of syscalls executed
-system.cpu0.kern.syscall::54                        8      4.49%     73.03% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      3.37%     76.40% # number of syscalls executed
-system.cpu0.kern.syscall::71                       17      9.55%     85.96% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.69%     87.64% # number of syscalls executed
-system.cpu0.kern.syscall::74                        4      2.25%     89.89% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.56%     90.45% # number of syscalls executed
-system.cpu0.kern.syscall::90                        2      1.12%     91.57% # number of syscalls executed
-system.cpu0.kern.syscall::92                        7      3.93%     95.51% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      1.12%     96.63% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      1.12%     97.75% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.56%     98.31% # number of syscalls executed
-system.cpu0.kern.syscall::144                       1      0.56%     98.88% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      1.12%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   178                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.677845                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.805712                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         7      4.14%      4.14% # number of syscalls executed
+system.cpu0.kern.syscall::3                        14      8.28%     12.43% # number of syscalls executed
+system.cpu0.kern.syscall::4                         4      2.37%     14.79% # number of syscalls executed
+system.cpu0.kern.syscall::6                        26     15.38%     30.18% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.59%     30.77% # number of syscalls executed
+system.cpu0.kern.syscall::17                        5      2.96%     33.73% # number of syscalls executed
+system.cpu0.kern.syscall::19                        7      4.14%     37.87% # number of syscalls executed
+system.cpu0.kern.syscall::20                        4      2.37%     40.24% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.59%     40.83% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.78%     42.60% # number of syscalls executed
+system.cpu0.kern.syscall::33                        5      2.96%     45.56% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      1.18%     46.75% # number of syscalls executed
+system.cpu0.kern.syscall::45                       26     15.38%     62.13% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.78%     63.91% # number of syscalls executed
+system.cpu0.kern.syscall::48                        8      4.73%     68.64% # number of syscalls executed
+system.cpu0.kern.syscall::54                        8      4.73%     73.37% # number of syscalls executed
+system.cpu0.kern.syscall::59                        6      3.55%     76.92% # number of syscalls executed
+system.cpu0.kern.syscall::71                       15      8.88%     85.80% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.78%     87.57% # number of syscalls executed
+system.cpu0.kern.syscall::74                        3      1.78%     89.35% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.59%     89.94% # number of syscalls executed
+system.cpu0.kern.syscall::90                        2      1.18%     91.12% # number of syscalls executed
+system.cpu0.kern.syscall::92                        7      4.14%     95.27% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      1.18%     96.45% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      1.18%     97.63% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.59%     98.22% # number of syscalls executed
+system.cpu0.kern.syscall::144                       1      0.59%     98.82% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      1.18%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   169                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  278      0.17%      0.17% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.17% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.17% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.17% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3399      2.05%      2.22% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      48      0.03%      2.25% # number of callpals executed
+system.cpu0.kern.callpal::wripir                  293      0.18%      0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.18% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3349      2.05%      2.23% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      48      0.03%      2.26% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.26% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               151231     91.28%     93.54% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   5900      3.56%     97.10% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.10% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     2      0.00%     97.10% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               149333     91.35%     93.61% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   5683      3.48%     97.09% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.09% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     1      0.00%     97.09% # number of callpals executed
 system.cpu0.kern.callpal::rdusp                     8      0.00%     97.10% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     97.11% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4349      2.63%     99.73% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 315      0.19%     99.92% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     97.10% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4311      2.64%     99.73% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 303      0.19%     99.92% # number of callpals executed
 system.cpu0.kern.callpal::imb                     132      0.08%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                165676                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6738                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1097                       # number of protection mode switches
+system.cpu0.kern.callpal::total                163475                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             6664                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1070                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1097                      
-system.cpu0.kern.mode_good::user                 1097                      
+system.cpu0.kern.mode_good::kernel               1070                      
+system.cpu0.kern.mode_good::user                 1070                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.162808                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.160564                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.280026                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1904214078500     99.91%     99.91% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1672761500      0.09%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.276700                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1905216688000     99.91%     99.91% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1682440000      0.09%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3400                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3350                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2490                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     60423                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   18641     37.27%     37.27% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1925      3.85%     41.12% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    278      0.56%     41.67% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  29176     58.33%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               50020                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    18293     47.50%     47.50% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1925      5.00%     52.50% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     278      0.72%     53.22% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   18016     46.78%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                38512                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1873859043000     98.29%     98.29% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              564907000      0.03%     98.32% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              133677500      0.01%     98.32% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            31975089500      1.68%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1906532717000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.981331                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2541                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     62895                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   19560     37.60%     37.60% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1924      3.70%     41.30% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    293      0.56%     41.86% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  30244     58.14%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               52021                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    19198     47.61%     47.61% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1924      4.77%     52.38% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     293      0.73%     53.11% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   18906     46.89%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                40321                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1872948111000     98.19%     98.19% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              564456500      0.03%     98.22% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              141435000      0.01%     98.22% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            33894599000      1.78%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1907548601500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.981493                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.617494                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.769932                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2                         1      0.68%      0.68% # number of syscalls executed
-system.cpu1.kern.syscall::3                        15     10.14%     10.81% # number of syscalls executed
-system.cpu1.kern.syscall::6                        16     10.81%     21.62% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      0.68%     22.30% # number of syscalls executed
-system.cpu1.kern.syscall::17                        9      6.08%     28.38% # number of syscalls executed
-system.cpu1.kern.syscall::19                        3      2.03%     30.41% # number of syscalls executed
-system.cpu1.kern.syscall::20                        2      1.35%     31.76% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      2.03%     33.78% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      2.03%     35.81% # number of syscalls executed
-system.cpu1.kern.syscall::33                        5      3.38%     39.19% # number of syscalls executed
-system.cpu1.kern.syscall::45                       25     16.89%     56.08% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      2.03%     58.11% # number of syscalls executed
-system.cpu1.kern.syscall::48                        2      1.35%     59.46% # number of syscalls executed
-system.cpu1.kern.syscall::54                        2      1.35%     60.81% # number of syscalls executed
-system.cpu1.kern.syscall::58                        1      0.68%     61.49% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      0.68%     62.16% # number of syscalls executed
-system.cpu1.kern.syscall::71                       37     25.00%     87.16% # number of syscalls executed
-system.cpu1.kern.syscall::74                       12      8.11%     95.27% # number of syscalls executed
-system.cpu1.kern.syscall::90                        1      0.68%     95.95% # number of syscalls executed
-system.cpu1.kern.syscall::92                        2      1.35%     97.30% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      2.03%     99.32% # number of syscalls executed
-system.cpu1.kern.syscall::144                       1      0.68%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   148                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.625116                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.775091                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2                         1      0.64%      0.64% # number of syscalls executed
+system.cpu1.kern.syscall::3                        16     10.19%     10.83% # number of syscalls executed
+system.cpu1.kern.syscall::6                        16     10.19%     21.02% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      0.64%     21.66% # number of syscalls executed
+system.cpu1.kern.syscall::17                       10      6.37%     28.03% # number of syscalls executed
+system.cpu1.kern.syscall::19                        3      1.91%     29.94% # number of syscalls executed
+system.cpu1.kern.syscall::20                        2      1.27%     31.21% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      1.91%     33.12% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      1.91%     35.03% # number of syscalls executed
+system.cpu1.kern.syscall::33                        6      3.82%     38.85% # number of syscalls executed
+system.cpu1.kern.syscall::45                       28     17.83%     56.69% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      1.91%     58.60% # number of syscalls executed
+system.cpu1.kern.syscall::48                        2      1.27%     59.87% # number of syscalls executed
+system.cpu1.kern.syscall::54                        2      1.27%     61.15% # number of syscalls executed
+system.cpu1.kern.syscall::58                        1      0.64%     61.78% # number of syscalls executed
+system.cpu1.kern.syscall::59                        1      0.64%     62.42% # number of syscalls executed
+system.cpu1.kern.syscall::71                       39     24.84%     87.26% # number of syscalls executed
+system.cpu1.kern.syscall::74                       13      8.28%     95.54% # number of syscalls executed
+system.cpu1.kern.syscall::90                        1      0.64%     96.18% # number of syscalls executed
+system.cpu1.kern.syscall::92                        2      1.27%     97.45% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      1.91%     99.36% # number of syscalls executed
+system.cpu1.kern.syscall::144                       1      0.64%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   157                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  175      0.33%      0.34% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  181      0.33%      0.33% # number of callpals executed
 system.cpu1.kern.callpal::wrmces                    1      0.00%      0.34% # number of callpals executed
 system.cpu1.kern.callpal::wrfen                     1      0.00%      0.34% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1166      2.23%      2.57% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       5      0.01%      2.58% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      2.59% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                44628     85.35%     87.94% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2858      5.47%     93.41% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.41% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     5      0.01%     93.42% # number of callpals executed
-system.cpu1.kern.callpal::rdusp                     1      0.00%     93.42% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     93.43% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3189      6.10%     99.52% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 200      0.38%     99.91% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1228      2.25%      2.59% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       5      0.01%      2.60% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      2.61% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                46558     85.31%     87.92% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   3077      5.64%     93.55% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.56% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     6      0.01%     93.57% # number of callpals executed
+system.cpu1.kern.callpal::rdusp                     1      0.00%     93.57% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     93.57% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3246      5.95%     99.52% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 212      0.39%     99.91% # number of callpals executed
 system.cpu1.kern.callpal::imb                      48      0.09%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 52290                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1624                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                640                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2399                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                844                      
-system.cpu1.kern.mode_good::user                  640                      
-system.cpu1.kern.mode_good::idle                  204                      
-system.cpu1.kern.mode_switch_good::kernel     0.519704                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 54577                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1699                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                669                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2429                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                888                      
+system.cpu1.kern.mode_good::user                  669                      
+system.cpu1.kern.mode_good::idle                  219                      
+system.cpu1.kern.mode_switch_good::kernel     0.522660                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.085035                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.361999                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        4862135000      0.26%      0.26% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1013458000      0.05%      0.31% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1900657116000     99.69%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1167                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.090161                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.370231                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        5315508000      0.28%      0.28% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1058693000      0.06%      0.33% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1901174392500     99.67%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1229                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
index 7e0283697..a10880583 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
@@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 30 cycles, load miss latency 154 cycles
+
4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles
 
SMP: 2 CPUs probed -- cpu_present_mask = 3
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 42d27bf88..311af1e02 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -25,7 +25,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:134217727
+mem_ranges=0:134217727:0:0:0:0
 memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
@@ -60,7 +60,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=8796093022208:18446744073709551615
+ranges=8796093022208:18446744073709551615:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -194,7 +194,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -552,7 +552,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -612,7 +612,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -775,7 +775,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=0:134217727
+addr_ranges=0:134217727:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -820,7 +820,7 @@ size=1024
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -832,7 +832,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -864,29 +864,36 @@ update_data=false
 warn_access=
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -906,6 +913,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -915,7 +923,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -937,9 +945,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index 04946a155..dd81d337e 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:28
-gem5 executing on e108600-lin, pid 39623
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:44
+gem5 executing on e108600-lin, pid 28053
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1876794488000 because m5_exit instruction encountered
+Exiting @ tick 1865011607500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index f5019500b..b9078b8f1 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,113 +1,113 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.862042                       # Number of seconds simulated
-sim_ticks                                1862042063000                       # Number of ticks simulated
-final_tick                               1862042063000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.865012                       # Number of seconds simulated
+sim_ticks                                1865011607500                       # Number of ticks simulated
+final_tick                               1865011607500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 137297                       # Simulator instruction rate (inst/s)
-host_op_rate                                   137297                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4825772422                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 338492                       # Number of bytes of host memory used
-host_seconds                                   385.85                       # Real time elapsed on the host
-sim_insts                                    52976505                       # Number of instructions simulated
-sim_ops                                      52976505                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 117207                       # Simulator instruction rate (inst/s)
+host_op_rate                                   117207                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4126745503                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 335896                       # Number of bytes of host memory used
+host_seconds                                   451.93                       # Real time elapsed on the host
+sim_insts                                    52969539                       # Number of instructions simulated
+sim_ops                                      52969539                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            963392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24881792                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            962688                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24879872                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25846144                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       963392                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          963392                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7528832                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7528832                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15053                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388778                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25843520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       962688                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          962688                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7514368                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7514368                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15042                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388748                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                403846                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117638                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117638                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               517385                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13362637                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               516                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13880537                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          517385                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             517385                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4043320                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4043320                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4043320                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              517385                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13362637                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              516                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17923857                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        403846                       # Number of read requests accepted
-system.physmem.writeReqs                       117638                       # Number of write requests accepted
-system.physmem.readBursts                      403846                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     117638                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25839232                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6912                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7527104                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25846144                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7528832                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      108                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                403805                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117412                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117412                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               516183                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13340331                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               515                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13857029                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          516183                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             516183                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4029127                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4029127                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4029127                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              516183                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13340331                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              515                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17886156                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        403805                       # Number of read requests accepted
+system.physmem.writeReqs                       117412                       # Number of write requests accepted
+system.physmem.readBursts                      403805                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     117412                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25836672                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6848                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7513280                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25843520                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7514368                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      107                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25618                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25426                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25537                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25512                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25419                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24740                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24937                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25096                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               24930                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25035                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25569                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24892                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24450                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25273                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25713                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25591                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7930                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7514                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7945                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7523                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7351                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6673                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6769                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6726                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7138                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6708                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7428                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6991                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7147                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7895                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8063                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7810                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               25445                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25617                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25496                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25620                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25117                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25178                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24740                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24558                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25032                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25302                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25290                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25006                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24377                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25425                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25800                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25695                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7802                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7592                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7774                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7602                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7239                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7182                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6741                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6416                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7149                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6926                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7200                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7003                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6957                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7880                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8017                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7915                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1862036687500                       # Total gap between requests
+system.physmem.numWrRetry                          50                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1865006319500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  403846                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  403805                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117638                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    315267                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     36112                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     28338                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     23939                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        68                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117412                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    314207                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     36490                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     28744                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     24151                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        88                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         9                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
@@ -149,195 +149,207 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1560                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2800                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3376                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6646                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     9037                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7269                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7983                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8709                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7918                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7621                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5960                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       32                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        61611                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      541.558358                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     333.246769                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     417.180517                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13396     21.74%     21.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10505     17.05%     38.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5359      8.70%     47.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2621      4.25%     51.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2461      3.99%     55.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1425      2.31%     58.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1507      2.45%     60.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1351      2.19%     62.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22986     37.31%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          61611                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5236                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        77.104660                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2917.579007                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5233     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1450                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2607                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5585                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6297                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8264                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6799                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7310                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7943                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7596                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6918                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6963                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6888                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7091                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5971                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6192                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      746                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      325                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      301                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      308                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      376                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      341                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      276                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      305                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      305                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      103                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        61234                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      544.625012                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     334.721385                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     417.137572                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13321     21.75%     21.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10685     17.45%     39.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4509      7.36%     46.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2718      4.44%     51.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2169      3.54%     54.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1832      2.99%     57.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1887      3.08%     60.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1551      2.53%     63.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22562     36.85%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61234                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5157                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        78.280396                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2939.585639                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5154     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5236                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5236                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.461994                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.033018                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       22.013556                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4631     88.45%     88.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              42      0.80%     89.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             243      4.64%     93.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              21      0.40%     94.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55               6      0.11%     94.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              10      0.19%     94.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71               6      0.11%     94.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               2      0.04%     94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              20      0.38%     95.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95              23      0.44%     95.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            185      3.53%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             2      0.04%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             3      0.06%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             1      0.02%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             7      0.13%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             1      0.02%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             1      0.02%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             3      0.06%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             2      0.04%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            11      0.21%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             1      0.02%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             1      0.02%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             2      0.04%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             3      0.06%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             7      0.13%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5236                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3726058000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11296145500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2018690000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9228.90                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5157                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5157                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.764204                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.942160                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       24.363230                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4631     89.80%     89.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              32      0.62%     90.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             183      3.55%     93.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47               6      0.12%     94.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55               4      0.08%     94.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63               9      0.17%     94.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71               9      0.17%     94.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               4      0.08%     94.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              32      0.62%     95.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               5      0.10%     95.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            155      3.01%     98.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            14      0.27%     98.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             9      0.17%     98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             2      0.04%     98.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             9      0.17%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             4      0.08%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             1      0.02%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             2      0.04%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             8      0.16%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             6      0.12%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            10      0.19%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199            10      0.19%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             1      0.02%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             4      0.08%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             2      0.04%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             2      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5157                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     7801574500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               15370912000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2018490000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19325.27                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27978.90                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.88                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.04                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.88                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.04                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  38075.27                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.85                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.03                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.86                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.03                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.98                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.95                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     364089                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95648                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.18                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.31                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3570649.70                       # Average gap between requests
-system.physmem.pageHitRate                      88.18                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  230882400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  125977500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1577823000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                378632880                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           121619072640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            56327619735                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1067810937000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1248070945155                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.272471                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1776230272500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     62177440000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     23627517500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  234896760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  128167875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1571286600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                383486400                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           121619072640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            56258103960                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1067871924000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1248066938235                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.270314                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1776335363750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     62177440000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     23523591750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                19539848                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16614646                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            591620                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12579114                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5416634                       # Number of BTB hits
+system.physmem.avgRdQLen                         1.96                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.64                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     364428                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95430                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.27                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  81.28                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3578176.31                       # Average gap between requests
+system.physmem.pageHitRate                      88.25                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  214821180                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  114180165                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1440644940                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                304576560                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3637439520.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             4203799590                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              238276320                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy        7970182890                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        4260887040                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       438967517640                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             461353182075                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              247.372821                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           1855132089750                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      377139000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1545232000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   1826595828250                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  11096155750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      7918821750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  17478430750                       # Time in different power states
+system.physmem_1.actEnergy                  222396720                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  118202865                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1441758780                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                308225340                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3641127360.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             4165097730                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              227687040                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy        8135120370                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        4246672320                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       438904577085                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             461412058890                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              247.404390                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           1855277049250                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      349511250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1546624000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   1826382821500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  11059060000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      7833171250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  17840419500                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                19540652                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16609155                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            593501                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             12781935                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5419166                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             43.060537                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1121926                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              41569                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         6087322                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits             563395                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses          5523927                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       264320                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             42.397071                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1123794                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              42287                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         6265125                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             563559                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          5701566                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       264926                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     11126873                       # DTB read hits
-system.cpu.dtb.read_misses                      49288                       # DTB read misses
-system.cpu.dtb.read_acv                           612                       # DTB read access violations
-system.cpu.dtb.read_accesses                   995471                       # DTB read accesses
-system.cpu.dtb.write_hits                     6773971                       # DTB write hits
-system.cpu.dtb.write_misses                     12183                       # DTB write misses
-system.cpu.dtb.write_acv                          423                       # DTB write access violations
-system.cpu.dtb.write_accesses                  345274                       # DTB write accesses
-system.cpu.dtb.data_hits                     17900844                       # DTB hits
-system.cpu.dtb.data_misses                      61471                       # DTB misses
-system.cpu.dtb.data_acv                          1035                       # DTB access violations
-system.cpu.dtb.data_accesses                  1340745                       # DTB accesses
-system.cpu.itb.fetch_hits                     1815480                       # ITB hits
-system.cpu.itb.fetch_misses                     10441                       # ITB misses
-system.cpu.itb.fetch_acv                          750                       # ITB acv
-system.cpu.itb.fetch_accesses                 1825921                       # ITB accesses
+system.cpu.dtb.read_hits                     11133148                       # DTB read hits
+system.cpu.dtb.read_misses                      49550                       # DTB read misses
+system.cpu.dtb.read_acv                           604                       # DTB read access violations
+system.cpu.dtb.read_accesses                   995639                       # DTB read accesses
+system.cpu.dtb.write_hits                     6779390                       # DTB write hits
+system.cpu.dtb.write_misses                     12217                       # DTB write misses
+system.cpu.dtb.write_acv                          419                       # DTB write access violations
+system.cpu.dtb.write_accesses                  345330                       # DTB write accesses
+system.cpu.dtb.data_hits                     17912538                       # DTB hits
+system.cpu.dtb.data_misses                      61767                       # DTB misses
+system.cpu.dtb.data_acv                          1023                       # DTB access violations
+system.cpu.dtb.data_accesses                  1340969                       # DTB accesses
+system.cpu.itb.fetch_hits                     1814760                       # ITB hits
+system.cpu.itb.fetch_misses                     10379                       # ITB misses
+system.cpu.itb.fetch_acv                          753                       # ITB acv
+system.cpu.itb.fetch_accesses                 1825139                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -352,146 +364,146 @@ system.cpu.itb.data_acv                             0                       # DT
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.numPwrStateTransitions               12878                       # Number of power state transitions
 system.cpu.pwrStateClkGateDist::samples          6439                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     279534848.967231                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    439378966.267034                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     279577818.217114                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    438970116.286468                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1000-5e+10         6439    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value        96000                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value        62000                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::total            6439                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON     62117170500                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 1799924892500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        124240781                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     64810036000                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 1800201571500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        129626512                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           30188704                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       85612379                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    19539848                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            7101955                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      86725868                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1678156                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles           30190363                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       85695972                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    19540652                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            7106519                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      91835709                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1682318                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.TlbCycles                         61                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                31498                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        207275                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       432547                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          339                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9909625                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                405389                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.MiscStallCycles                29737                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        207098                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       428060                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          576                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9928105                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                408572                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          118425370                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.722923                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.060283                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples          123532763                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.693710                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.023135                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                102607090     86.64%     86.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1029926      0.87%     87.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2106958      1.78%     89.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   967243      0.82%     90.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2899427      2.45%     92.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   665654      0.56%     93.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   809857      0.68%     93.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1032032      0.87%     94.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  6307183      5.33%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                107696719     87.18%     87.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1032377      0.84%     88.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2107068      1.71%     89.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   968796      0.78%     90.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2908740      2.35%     92.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   664008      0.54%     93.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   809572      0.66%     94.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1033225      0.84%     94.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  6312258      5.11%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            118425370                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.157274                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.689084                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 24239485                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              81100635                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  10246732                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2034421                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 804096                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               734883                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 35786                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               73972445                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                113808                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 804096                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 25248689                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                52456334                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       19565246                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  11202200                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               9148803                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               70966243                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                196842                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2117370                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 228092                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4881037                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            47806174                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              85505184                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         85324382                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            168350                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38176913                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  9629253                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1728484                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         276268                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13926032                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             11656323                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             7221031                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1724354                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1093863                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   62666856                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2206869                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  60507866                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             96262                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        11897215                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      5284366                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1545682                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     118425370                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.510937                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.257755                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            123532763                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.150746                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.661099                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 24222797                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              86210181                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  10254650                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2038697                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 806437                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               738100                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 35530                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               74041720                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                113425                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 806437                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25231796                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                56630169                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       20045874                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  11215615                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               9602870                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               71021126                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                199714                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2114917                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 266619                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                5298821                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            47846131                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              85558708                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         85377795                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            168460                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38170817                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  9675306                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1730146                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         277278                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13907871                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             11664536                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             7226725                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1727084                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1123210                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   62712842                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2208202                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  60540114                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             93631                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        11951500                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      5299174                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1546957                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     123532763                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.490073                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.235792                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            93896241     79.29%     79.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10410761      8.79%     88.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             4424184      3.74%     91.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3178503      2.68%     94.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             3240709      2.74%     97.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1606797      1.36%     98.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1097474      0.93%     99.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              434045      0.37%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              136656      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            98992964     80.13%     80.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10407106      8.42%     88.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             4428528      3.58%     92.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3186499      2.58%     94.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             3245157      2.63%     97.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1605158      1.30%     98.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1098083      0.89%     99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              432605      0.35%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              136663      0.11%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       118425370                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       123532763                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  206587     16.63%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 638209     51.38%     68.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                397270     31.98%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  207032     16.67%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      1      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 637905     51.36%     68.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                397118     31.97%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass              7277      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              40893641     67.58%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                62155      0.10%     67.70% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass              7276      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              40915146     67.58%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                62152      0.10%     67.70% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               38558      0.06%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               38560      0.06%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.76% # Type of FU issued
@@ -517,95 +529,95 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.77% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.77% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.77% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.77% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             11671611     19.29%     87.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6881999     11.37%     98.43% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             948989      1.57%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             11677570     19.29%     87.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6886648     11.38%     98.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             949126      1.57%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               60507866                       # Type of FU issued
-system.cpu.iq.rate                           0.487021                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1242066                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.020527                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          240042364                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          76433076                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     58286910                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              737065                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             359346                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       336745                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               61347086                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  395569                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           690461                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               60540114                       # Type of FU issued
+system.cpu.iq.rate                           0.467035                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1242056                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.020516                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          245211443                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          76534751                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     58316055                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              737234                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             359442                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       336937                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               61379174                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  395720                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           691177                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2564224                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         3975                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        22069                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       843181                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2573780                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         3893                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        22128                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       849514                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        17987                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        463704                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        18020                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        462679                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 804096                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                49123510                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                920451                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            68850753                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            204809                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              11656323                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              7221031                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1958834                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  45972                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                671584                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          22069                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         229357                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       628132                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               857489                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              59656852                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              11208773                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            851013                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 806437                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                52697038                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1357053                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            68903527                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            198807                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              11664536                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              7226725                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1959166                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  45872                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               1108146                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          22128                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         230653                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       630212                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               860865                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              59685899                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              11215511                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            854214                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3977028                       # number of nop insts executed
-system.cpu.iew.exec_refs                     18015122                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  9379233                       # Number of branches executed
-system.cpu.iew.exec_stores                    6806349                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.480171                       # Inst execution rate
-system.cpu.iew.wb_sent                       58867691                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      58623655                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  29756177                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  41250197                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.471855                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.721358                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        12492004                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          661187                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            767634                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    116265516                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.483093                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.421972                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                       3982483                       # number of nop insts executed
+system.cpu.iew.exec_refs                     18027322                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  9384105                       # Number of branches executed
+system.cpu.iew.exec_stores                    6811811                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.460445                       # Inst execution rate
+system.cpu.iew.wb_sent                       58897557                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      58652992                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  29769052                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  41264413                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.452477                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.721422                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        12552458                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          661245                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            769809                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    121361631                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.462746                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.395074                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     96403146     82.92%     82.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7978599      6.86%     89.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4192375      3.61%     93.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2264506      1.95%     95.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1757271      1.51%     96.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       632678      0.54%     97.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       482043      0.41%     97.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       513720      0.44%     98.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2041178      1.76%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    101505032     83.64%     83.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7973925      6.57%     90.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4190958      3.45%     93.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2263923      1.87%     95.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1758393      1.45%     96.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       630847      0.52%     97.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       481222      0.40%     97.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       521755      0.43%     98.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2035576      1.68%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    116265516                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56167063                       # Number of instructions committed
-system.cpu.commit.committedOps               56167063                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    121361631                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56159642                       # Number of instructions committed
+system.cpu.commit.committedOps               56159642                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15469949                       # Number of memory references committed
-system.cpu.commit.loads                       9092099                       # Number of loads committed
-system.cpu.commit.membars                      226348                       # Number of memory barriers committed
-system.cpu.commit.branches                    8440307                       # Number of branches committed
+system.cpu.commit.refs                       15467967                       # Number of memory references committed
+system.cpu.commit.loads                       9090756                       # Number of loads committed
+system.cpu.commit.membars                      226364                       # Number of memory barriers committed
+system.cpu.commit.branches                    8439956                       # Number of branches committed
 system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52016709                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               740521                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass      3197831      5.69%      5.69% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         36215597     64.48%     70.17% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           60674      0.11%     70.28% # Class of committed instruction
+system.cpu.commit.int_insts                  52009640                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               740476                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass      3197376      5.69%      5.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         36210459     64.48%     70.17% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           60672      0.11%     70.28% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.28% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd          38085      0.07%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.35% # Class of committed instruction
@@ -633,544 +645,544 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.35% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead         9318447     16.59%     86.94% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        6383804     11.37%     98.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess        948989      1.69%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead         9317120     16.59%     86.94% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        6383168     11.37%     98.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess        949126      1.69%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          56167063                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               2041178                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    182633884                       # The number of ROB reads
-system.cpu.rob.rob_writes                   139481914                       # The number of ROB writes
-system.cpu.timesIdled                          555871                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         5815411                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3599843346                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    52976505                       # Number of Instructions Simulated
-system.cpu.committedOps                      52976505                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.345205                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.345205                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.426402                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.426402                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 77842014                       # number of integer regfile reads
-system.cpu.int_regfile_writes                42572961                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    166584                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   175742                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 2001057                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 939419                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           1405448                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.994324                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            12624146                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1405960                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.979022                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          26885500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.994324                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
+system.cpu.commit.op_class_0::total          56159642                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               2035576                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    187788618                       # The number of ROB reads
+system.cpu.rob.rob_writes                   139599579                       # The number of ROB writes
+system.cpu.timesIdled                          556181                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         6093749                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3600396704                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    52969539                       # Number of Instructions Simulated
+system.cpu.committedOps                      52969539                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.447190                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.447190                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.408632                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.408632                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 77875565                       # number of integer regfile reads
+system.cpu.int_regfile_writes                42594378                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    166655                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   175866                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 2002132                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 939499                       # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           1405977                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.994060                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            12626898                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1406489                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.977602                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          28232500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.994060                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999988                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999988                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          415                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          414                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          67117469                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         67117469                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data      8015814                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         8015814                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4179783                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4179783                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       212605                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       212605                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       215671                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       215671                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      12195597                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         12195597                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     12195597                       # number of overall hits
-system.cpu.dcache.overall_hits::total        12195597                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1813103                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1813103                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1967603                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1967603                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        23208                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23208                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           90                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           90                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3780706                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3780706                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3780706                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3780706                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  42125006500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  42125006500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  80961387023                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  80961387023                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    351774000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    351774000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data      1258000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total      1258000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 123086393523                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 123086393523                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 123086393523                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 123086393523                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9828917                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9828917                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6147386                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6147386                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       235813                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       235813                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       215761                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       215761                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15976303                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15976303                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15976303                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15976303                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.184466                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.184466                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.320071                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.320071                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.098417                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.098417                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000417                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000417                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.236645                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.236645                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.236645                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.236645                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23233.653300                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 23233.653300                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41147.216701                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41147.216701                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15157.445708                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15157.445708                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13977.777778                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13977.777778                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32556.457319                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32556.457319                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32556.457319                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32556.457319                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      4549830                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         3359                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            133574                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              36                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    34.062243                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    93.305556                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       843871                       # number of writebacks
-system.cpu.dcache.writebacks::total            843871                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       713283                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       713283                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1678038                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1678038                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         6508                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         6508                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2391321                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2391321                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2391321                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2391321                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1099820                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1099820                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289565                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       289565                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16700                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        16700                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           90                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           90                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1389385                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1389385                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1389385                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1389385                       # number of overall MSHR misses
+system.cpu.dcache.tags.tag_accesses          67141007                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         67141007                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data      8018368                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         8018368                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4180367                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4180367                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       212226                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       212226                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       215667                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       215667                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      12198735                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         12198735                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     12198735                       # number of overall hits
+system.cpu.dcache.overall_hits::total        12198735                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1817070                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1817070                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1966374                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1966374                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        23459                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23459                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           98                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           98                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3783444                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3783444                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3783444                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3783444                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  45126424500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  45126424500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  92431305073                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  92431305073                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    416761500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    416761500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data      1368500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total      1368500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 137557729573                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 137557729573                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 137557729573                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 137557729573                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9835438                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9835438                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6146741                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6146741                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       235685                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       235685                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       215765                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       215765                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15982179                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15982179                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15982179                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15982179                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.184747                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.184747                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.319905                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.319905                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.099535                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.099535                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000454                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000454                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.236729                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.236729                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.236729                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.236729                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24834.719906                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24834.719906                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47005.963806                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47005.963806                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17765.527090                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17765.527090                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13964.285714                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13964.285714                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 36357.807747                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 36357.807747                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 36357.807747                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 36357.807747                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      4938618                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         4294                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            133157                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              28                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    37.088685                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   153.357143                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks       844399                       # number of writebacks
+system.cpu.dcache.writebacks::total            844399                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       716933                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       716933                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1676859                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1676859                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         6505                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         6505                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2393792                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2393792                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2393792                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2393792                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1100137                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1100137                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289515                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       289515                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16954                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        16954                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           98                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           98                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1389652                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1389652                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1389652                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1389652                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9598                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9598                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16528                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16528                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30901101000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  30901101000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12647974805                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12647974805                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    208768500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    208768500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data      1168000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total      1168000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  43549075805                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  43549075805                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  43549075805                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  43549075805                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1535163500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1535163500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1535163500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   1535163500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.111896                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.111896                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047104                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047104                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.070819                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.070819                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000417                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000417                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.086965                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.086965                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.086965                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.086965                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28096.507610                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28096.507610                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43679.225062                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43679.225062                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12501.107784                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12501.107784                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12977.777778                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12977.777778                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31344.138453                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 31344.138453                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31344.138453                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 31344.138453                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221524.314574                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221524.314574                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92882.593175                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92882.593175                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           1075014                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.176961                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             8765751                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1075522                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.150229                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       28399256500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.176961                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994486                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994486                       # Average percentage of cache occupancy
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9599                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total         9599                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16529                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        16529                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33017901000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33017901000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14364764991                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  14364764991                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    212848500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    212848500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data      1270500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total      1270500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  47382665991                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  47382665991                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  47382665991                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  47382665991                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1535128000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1535128000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1535128000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   1535128000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.111854                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.111854                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047101                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047101                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.071935                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.071935                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000454                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000454                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.086950                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.086950                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.086950                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.086950                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30012.535711                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30012.535711                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49616.651956                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49616.651956                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12554.470921                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12554.470921                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12964.285714                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12964.285714                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34096.785376                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 34096.785376                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34096.785376                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 34096.785376                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221519.191919                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221519.191919                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92874.826063                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92874.826063                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements           1076759                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.003606                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             8782144                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1077267                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.152245                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       30283847500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.003606                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.994148                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.994148                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          300                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          306                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10985459                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10985459                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst      8765751                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8765751                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8765751                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8765751                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8765751                       # number of overall hits
-system.cpu.icache.overall_hits::total         8765751                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1143868                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1143868                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1143868                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1143868                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1143868                       # number of overall misses
-system.cpu.icache.overall_misses::total       1143868                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  15979138992                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  15979138992                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  15979138992                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  15979138992                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  15979138992                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  15979138992                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9909619                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9909619                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9909619                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9909619                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9909619                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9909619                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115430                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.115430                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.115430                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.115430                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.115430                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.115430                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13969.390692                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13969.390692                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13969.390692                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13969.390692                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13969.390692                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13969.390692                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         7656                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          11005677                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         11005677                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst      8782144                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8782144                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8782144                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8782144                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8782144                       # number of overall hits
+system.cpu.icache.overall_hits::total         8782144                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1145952                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1145952                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1145952                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1145952                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1145952                       # number of overall misses
+system.cpu.icache.overall_misses::total       1145952                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16332614990                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16332614990                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16332614990                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16332614990                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16332614990                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16332614990                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9928096                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9928096                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9928096                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9928096                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9928096                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9928096                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115425                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.115425                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.115425                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.115425                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.115425                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.115425                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14252.442502                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14252.442502                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14252.442502                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14252.442502                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14252.442502                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14252.442502                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         8348                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               228                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               326                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    33.578947                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    25.607362                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      1075014                       # number of writebacks
-system.cpu.icache.writebacks::total           1075014                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        68028                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        68028                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        68028                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        68028                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        68028                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        68028                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1075840                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1075840                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1075840                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1075840                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1075840                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1075840                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14160831996                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  14160831996                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14160831996                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  14160831996                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14160831996                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  14160831996                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108565                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108565                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108565                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.108565                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108565                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.108565                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13162.581793                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13162.581793                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13162.581793                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13162.581793                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13162.581793                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13162.581793                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           338638                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65427.252545                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4555596                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           404160                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            11.271764                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       5985561000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   253.752588                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5311.170770                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 59862.329187                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.003872                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081042                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.913427                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.998341                       # Average percentage of cache occupancy
+system.cpu.icache.writebacks::writebacks      1076759                       # number of writebacks
+system.cpu.icache.writebacks::total           1076759                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        68371                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        68371                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        68371                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        68371                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        68371                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        68371                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1077581                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1077581                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1077581                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1077581                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1077581                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1077581                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14423902993                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  14423902993                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14423902993                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  14423902993                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14423902993                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  14423902993                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108539                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108539                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108539                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.108539                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108539                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.108539                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13385.446656                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13385.446656                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13385.446656                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13385.446656                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13385.446656                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13385.446656                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           338614                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65420.353665                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4559964                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           404136                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            11.283241                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       6414398000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   255.266765                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5296.205124                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 59868.881776                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.003895                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.080814                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.913527                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.998235                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          896                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          449                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5579                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        58592                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          448                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5602                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        58570                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         40086542                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        40086542                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       843871                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       843871                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1074552                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1074552                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           74                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           74                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           90                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total           90                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       185367                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       185367                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1060413                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1060413                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       831413                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       831413                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1060413                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1016780                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2077193                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1060413                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1016780                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2077193                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            8                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            8                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       114699                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       114699                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        15055                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        15055                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       274527                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       274527                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        15055                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       389226                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        404281                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        15055                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       389226                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       404281                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       387500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       387500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10326275500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10326275500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1274090500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1274090500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  20279625500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  20279625500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1274090500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  30605901000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  31879991500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1274090500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  30605901000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  31879991500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       843871                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       843871                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1074552                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1074552                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           82                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           82                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           90                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total           90                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       300066                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       300066                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1075468                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1075468                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1105940                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1105940                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1075468                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1406006                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2481474                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1075468                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1406006                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2481474                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.097561                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.097561                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.382246                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.382246                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.013999                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.013999                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.248230                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.248230                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.013999                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.276831                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.162920                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.013999                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.276831                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.162920                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 48437.500000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 48437.500000                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90029.342017                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90029.342017                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84629.060113                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84629.060113                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73871.151107                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73871.151107                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84629.060113                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78632.724946                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78856.022173                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84629.060113                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78632.724946                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78856.022173                       # average overall miss latency
+system.cpu.l2cache.tags.tag_accesses         40121077                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        40121077                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks       844399                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       844399                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1076079                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1076079                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           69                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           69                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           98                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total           98                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       185276                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       185276                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1062141                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1062141                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       832063                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       832063                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      1062141                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1017339                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2079480                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      1062141                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1017339                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2079480                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            9                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            9                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       114725                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       114725                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        15044                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        15044                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       274467                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       274467                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        15044                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       389192                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        404236                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        15044                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       389192                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       404236                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       418500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       418500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12044968500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  12044968500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1516847000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1516847000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  22392456000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  22392456000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1516847000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  34437424500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  35954271500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1516847000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  34437424500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  35954271500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       844399                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       844399                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1076079                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1076079                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           78                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           78                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           98                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total           98                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       300001                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       300001                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1077185                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1077185                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1106530                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1106530                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      1077185                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1406531                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2483716                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1077185                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1406531                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2483716                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.115385                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.115385                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.382415                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.382415                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.013966                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.013966                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.248043                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.248043                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.013966                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.276703                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.162755                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.013966                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.276703                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.162755                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        46500                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        46500                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104989.919372                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104989.919372                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 100827.373039                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 100827.373039                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81585.239756                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81585.239756                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 100827.373039                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88484.410008                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 88943.764286                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 100827.373039                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88484.410008                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 88943.764286                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        76126                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76126                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        75900                       # number of writebacks
+system.cpu.l2cache.writebacks::total            75900                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            8                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            8                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       114699                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       114699                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        15054                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        15054                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       274527                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       274527                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        15054                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       389226                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       404280                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        15054                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       389226                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       404280                       # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            9                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            9                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       114725                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       114725                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        15043                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        15043                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       274467                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       274467                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        15043                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       389192                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       404235                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        15043                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       389192                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       404235                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9598                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9598                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16528                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16528                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       307500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       307500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9179285500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9179285500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1123478500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1123478500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  17540240000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  17540240000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1123478500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26719525500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  27843004000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1123478500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26719525500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  27843004000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1448524000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1448524000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1448524000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1448524000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.097561                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.097561                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382246                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382246                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.013998                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.013998                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248230                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248230                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.013998                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.276831                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.162919                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.013998                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.276831                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.162919                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 38437.500000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 38437.500000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80029.342017                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80029.342017                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74629.899030                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74629.899030                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63892.586157                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63892.586157                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74629.899030                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68647.843412                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68870.594637                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74629.899030                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68647.843412                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68870.594637                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209022.222222                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209022.222222                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87640.609874                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87640.609874                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      4962480                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2480820                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2159                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          950                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          950                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9599                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9599                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16529                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16529                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       328500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       328500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  10897718500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  10897718500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1366325500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1366325500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  19653014500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  19653014500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1366325500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  30550733000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  31917058500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1366325500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  30550733000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  31917058500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1448486500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1448486500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1448486500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1448486500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.115385                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.115385                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382415                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382415                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.013965                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.013965                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248043                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248043                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.013965                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.276703                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.162754                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.013965                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.276703                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.162754                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        36500                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        36500                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94989.919372                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94989.919372                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90827.993086                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90827.993086                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71604.289405                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71604.289405                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90827.993086                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78497.844252                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78956.692271                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90827.993086                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78497.844252                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78956.692271                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209016.810967                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209016.810967                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87633.038901                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87633.038901                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      4967024                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2483092                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2362                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          951                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          951                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2188821                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9598                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9598                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       919997                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1075014                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       824089                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           82                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           90                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          172                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       300066                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       300066                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1075840                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1106100                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           45                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq          254                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3226322                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4251016                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7477338                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    137630848                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    144043380                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          281674228                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      339580                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               4905856                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      2837598                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001208                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.034736                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       2191157                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9599                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9599                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       920299                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1076759                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       824292                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           78                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           98                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          176                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       300001                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       300001                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1077581                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1106690                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           40                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq          237                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3231525                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4252605                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7484130                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    137852416                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    144111100                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          281963516                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      339563                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               4892928                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      2839828                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001278                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.035720                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2834170     99.88%     99.88% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3428      0.12%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2836200     99.87%     99.87% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               3628      0.13%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2837598                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4413188000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2839828                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4417734000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       291883                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1614811393                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1617399440                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2121037981                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2121770107                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1184,12 +1196,12 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51150                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51150                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5052                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51151                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51151                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5054                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1198,11 +1210,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        1812
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33056                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33058                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116506                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20208                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116508                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20216                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1211,50 +1223,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44148                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44156                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705756                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              5361000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2705764                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              5359000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               820500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               816500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              177500                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              178500                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            14040000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            14034000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             2177500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy             2179500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6050500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             6056500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               91500                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy               92500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           216173801                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           216222032                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23458000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23459000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.258860                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.265413                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1712294555000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.258860                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078679                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078679                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1714256790000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.265413                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.079088                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.079088                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
@@ -1263,14 +1275,14 @@ system.iocache.demand_misses::tsunami.ide        41725                       # n
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21845883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21845883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4858784918                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4858784918                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   4880630801                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4880630801                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   4880630801                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4880630801                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21932883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21932883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4939835149                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4939835149                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   4961768032                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4961768032                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   4961768032                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4961768032                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1287,19 +1299,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126276.780347                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126276.780347                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116932.636648                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 116932.636648                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 116971.379293                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 116971.379293                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 116971.379293                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 116971.379293                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             8                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126779.670520                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126779.670520                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118883.210170                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118883.210170                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 118915.950437                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 118915.950437                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 118915.950437                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 118915.950437                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs          2115                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   16                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            8                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs   132.187500                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
@@ -1311,14 +1323,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41725
 system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13195883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13195883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2778792164                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2778792164                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   2791988047                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2791988047                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   2791988047                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2791988047                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13282883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13282883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2859804565                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2859804565                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   2873087448                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2873087448                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   2873087448                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2873087448                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1327,75 +1339,75 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76276.780347                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76276.780347                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66875.052079                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66875.052079                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66914.033481                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 66914.033481                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66914.033481                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 66914.033481                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests        825555                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       380464                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76779.670520                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76779.670520                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68824.715176                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.715176                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.697975                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68857.697975                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.697975                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68857.697975                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests        825525                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       380458                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests          414                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296639                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9598                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9598                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       117638                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261892                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              135                       # Transaction distribution
+system.membus.trans_dist::ReadResp             296573                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9599                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9599                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       117412                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262094                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              137                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            114572                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           114572                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        289754                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           45                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            114597                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           114597                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        289683                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           40                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33056                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1145919                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           90                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1179065                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33058                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1145815                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           80                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1178953                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1262490                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30717248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30761396                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1262378                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44156                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30700160                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30744316                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33419124                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33402044                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              438                       # Total snoops (count)
 system.membus.snoopTraffic                      27840                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            462541                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001500                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.038706                       # Request fanout histogram
+system.membus.snoop_fanout::samples            462498                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.001464                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.038232                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  461847     99.85%     99.85% # Request fanout histogram
-system.membus.snoop_fanout::1                     694      0.15%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  461821     99.85%     99.85% # Request fanout histogram
+system.membus.snoop_fanout::1                     677      0.15%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              462541                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            28740000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              462498                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            28738500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1314155780                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1313413567                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               57000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               48500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2139053000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2137867250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy             918617                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy             917617                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1427,52 +1439,52 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865011607500                       # Cumulative time (in ticks) in various power states
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6439                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     210996                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74658     40.97%     40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.hwrei                     211030                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74670     40.97%     40.97% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1880      1.03%     42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105558     57.93%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182227                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73291     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22                    1881      1.03%     42.07% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105578     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182260                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73303     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1880      1.27%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73291     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148593                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1818067214500     97.64%     97.64% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                67498000      0.00%     97.64% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               564111500      0.03%     97.67% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             43342412500      2.33%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1862041236500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981690                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1881      1.27%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73303     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148618                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1819136783500     97.54%     97.54% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                67099500      0.00%     97.54% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               565538000      0.03%     97.57% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             45241360000      2.43%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1865010781000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981693                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694320                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815428                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694302                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815418                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -1511,29 +1523,29 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175110     91.22%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175141     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6785      3.53%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
-system.cpu.kern.callpal::rti                     5105      2.66%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5106      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 191955                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5851                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1739                       # number of protection mode switches
+system.cpu.kern.callpal::total                 191988                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5852                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1909                      
-system.cpu.kern.mode_good::user                  1739                      
+system.cpu.kern.mode_good::kernel                1908                      
+system.cpu.kern.mode_good::user                  1738                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.326269                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.326042                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.081107                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.394177                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29461996000      1.58%      1.58% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2701361000      0.15%      1.73% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1829877871500     98.27%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::total      0.393971                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29668657000      1.59%      1.59% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2761122500      0.15%      1.74% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1832580993500     98.26%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
index 2c979b67f..b49f55c8a 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles
+
4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
index c192e9ff7..8732f763e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
@@ -36,7 +36,7 @@ load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -208,7 +208,7 @@ useIndirect=true
 [system.cpu0.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -688,7 +688,7 @@ opClass=InstPrefetch
 [system.cpu0.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -748,7 +748,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -820,7 +820,7 @@ port=system.cpu0.toL2Bus.slave[2]
 [system.cpu0.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -1024,7 +1024,7 @@ useIndirect=true
 [system.cpu1.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1504,7 +1504,7 @@ opClass=InstPrefetch
 [system.cpu1.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1564,7 +1564,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -1636,7 +1636,7 @@ port=system.cpu1.toL2Bus.slave[2]
 [system.cpu1.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -1783,7 +1783,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -1829,7 +1829,7 @@ size=1024
 [system.l2c]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1927,27 +1927,27 @@ system=system
 
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -1967,6 +1967,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -1976,7 +1977,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1998,9 +1999,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -2353,7 +2354,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -2670,6 +2671,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -2677,7 +2679,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -2908,6 +2910,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -2915,7 +2918,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
index 2149b379f..4c439b2cd 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:42:06
-gem5 executing on e108600-lin, pid 23137
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:42:59
+gem5 executing on e108600-lin, pid 17317
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor-dual
 
 Global frequency set at 1000000000000 ticks per second
@@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2647778082500 because m5_exit instruction encountered
+Exiting @ tick 2848926718000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
index 14253ba3e..636a3faf7 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
@@ -1,162 +1,162 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.848172                       # Number of seconds simulated
-sim_ticks                                2848172284000                       # Number of ticks simulated
-final_tick                               2848172284000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.848927                       # Number of seconds simulated
+sim_ticks                                2848926718000                       # Number of ticks simulated
+final_tick                               2848926718000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 135409                       # Simulator instruction rate (inst/s)
-host_op_rate                                   163982                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3007675070                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 625764                       # Number of bytes of host memory used
-host_seconds                                   946.97                       # Real time elapsed on the host
-sim_insts                                   128228197                       # Number of instructions simulated
-sim_ops                                     155285827                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 113585                       # Simulator instruction rate (inst/s)
+host_op_rate                                   137549                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2529912934                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 622248                       # Number of bytes of host memory used
+host_seconds                                  1126.10                       # Real time elapsed on the host
+sim_insts                                   127907365                       # Number of instructions simulated
+sim_ops                                     154893549                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker         8960                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker         9536                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1677760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1343340                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8401088                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         1408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           221184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           660436                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       438272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1676224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1355764                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8486720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         1024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           229952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           664980                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       417216                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12753472                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1677760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       221184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1898944                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9008896                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12842440                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1676224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       229952                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1906176                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9074368                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9026460                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker          140                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           9091932                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          149                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             26215                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             21511                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       131267                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           22                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3456                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             10340                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         6848                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             26191                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             21707                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       132605                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           16                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3593                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             10411                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         6519                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                199815                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          140764                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                201207                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          141787                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               145155                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3146                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               146178                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3347                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              589065                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              471650                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2949642                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           494                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               77658                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              231881                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       153878                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              588370                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              475886                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2978918                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           359                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               80715                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              233414                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       146447                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4477774                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         589065                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          77658                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             666724                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3163045                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6153                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4507817                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         588370                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          80715                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             669086                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3185188                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6151                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3169211                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3163045                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3191353                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3185188                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3347                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             589065                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             477803                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2949642                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          494                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              77658                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             231895                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       153878                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             588370                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             482037                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2978918                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          359                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              80715                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             233428                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       146447                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7646985                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        199815                       # Number of read requests accepted
-system.physmem.writeReqs                       145155                       # Number of write requests accepted
-system.physmem.readBursts                      199815                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     145155                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12777984                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10176                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9038976                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12753472                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9026460                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      159                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::total                7699170                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        201207                       # Number of read requests accepted
+system.physmem.writeReqs                       146178                       # Number of write requests accepted
+system.physmem.readBursts                      201207                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     146178                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12868352                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8896                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9104640                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12842440                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9091932                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      139                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12196                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12508                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12943                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12617                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14662                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11885                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12499                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12704                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12537                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12319                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11826                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10998                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              12485                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              13119                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              12369                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11989                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8816                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9166                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9495                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9136                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8038                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8411                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8988                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8984                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9026                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8762                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8598                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8287                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9114                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9118                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8888                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8407                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               12387                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12818                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               13574                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               13051                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               15332                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12655                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12896                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               13054                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12485                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12494                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11451                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10701                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11947                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12784                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11815                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11624                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9013                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9459                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10048                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9447                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8653                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8898                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9273                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9228                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8869                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8977                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8270                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7926                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8743                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8906                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8530                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8020                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          34                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2848171745000                       # Total gap between requests
+system.physmem.numWrRetry                          92                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2848926179000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     552                       # Read request sizes (log2)
+system.physmem.readPktSize::2                     554                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  199235                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  200625                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 140764                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     87471                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     61591                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     11471                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9741                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7810                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6337                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5222                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4637                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3767                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       779                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      267                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      232                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      180                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      139                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 141787                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     84607                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     63376                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     11777                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9873                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      8134                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6758                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5703                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4957                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3992                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1032                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      281                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      278                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      160                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      136                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
@@ -185,162 +185,178 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2713                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4639                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6626                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7841                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8726                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9306                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7907                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      532                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      424                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      329                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      253                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       88                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        88570                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      246.323767                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     141.050118                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     301.878369                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          44937     50.74%     50.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18529     20.92%     71.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6585      7.43%     79.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3856      4.35%     83.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3004      3.39%     86.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1517      1.71%     88.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          921      1.04%     89.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1037      1.17%     90.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8184      9.24%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          88570                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7038                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.368144                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      555.266808                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7037     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2663                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4519                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6096                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6500                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7619                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8634                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9779                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8948                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    10048                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8490                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8247                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      530                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      465                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      348                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      262                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      215                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      295                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        89804                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      244.676495                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     140.021398                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     301.276619                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          45910     51.12%     51.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18733     20.86%     71.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6663      7.42%     79.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3737      4.16%     83.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2991      3.33%     86.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1528      1.70%     88.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          943      1.05%     89.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1048      1.17%     90.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8251      9.19%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          89804                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7084                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.382976                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      553.950604                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7082     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7038                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7038                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.067349                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.571017                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.392738                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5944     84.46%     84.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             388      5.51%     89.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              60      0.85%     90.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              46      0.65%     91.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             266      3.78%     95.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              21      0.30%     95.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              22      0.31%     95.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              25      0.36%     96.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              15      0.21%     96.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              13      0.18%     96.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               4      0.06%     96.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              13      0.18%     96.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             149      2.12%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.07%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               7      0.10%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              11      0.16%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               6      0.09%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               4      0.06%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               7      0.10%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             9      0.13%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.11%     99.83% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            7084                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7084                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.081875                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.511113                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.183489                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5975     84.35%     84.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             419      5.91%     90.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              68      0.96%     91.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              50      0.71%     91.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             261      3.68%     95.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              21      0.30%     95.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              13      0.18%     96.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              17      0.24%     96.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              10      0.14%     96.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               6      0.08%     96.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.11%     96.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               9      0.13%     96.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             144      2.03%     98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               9      0.13%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.07%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               4      0.06%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               8      0.11%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.01%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.03%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               5      0.07%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             9      0.13%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.03%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             3      0.04%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.01%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.04%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            11      0.16%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.03%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             4      0.06%     99.83% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::140-143             3      0.04%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             4      0.06%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7038                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5532611303                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9276161303                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    998280000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27710.72                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::148-151             1      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.03%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             3      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7084                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     9521946881                       # Total ticks spent queuing
+system.physmem.totMemAccLat               13291971881                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1005340000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       47356.85                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46460.72                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.49                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.17                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.48                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.17                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  66106.85                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.52                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.20                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.51                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.19                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.18                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     165300                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     87019                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.79                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  61.60                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8256288.21                       # Average gap between requests
-system.physmem.pageHitRate                      74.01                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  339738840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  185373375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 795709200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                460300320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           186028705200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83305465515                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1635827969250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1906943261700                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.532441                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2721218544299                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95106700000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     31846334451                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  329850360                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  179977875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 761599800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                454896000                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           186028705200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82993384530                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1636101724500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1906850138265                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.499746                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2721674822130                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95106700000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     31390664370                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.physmem.avgWrQLen                        25.49                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     166479                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     87044                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.80                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  61.18                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8201062.74                       # Average gap between requests
+system.physmem.pageHitRate                      73.84                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  339864000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  180642000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 755176380                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                386379180                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           5802201600.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5394350610                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              323555040                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       11564942040                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        8568107520                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       670261966035                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             703579433835                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              246.962980                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           2836248193267                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      586826713                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2465512000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   2788574898250                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  22312648073                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      9624892520                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  25361940444                       # Time in different power states
+system.physmem_1.actEnergy                  301343700                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  160164180                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 680449140                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                356218020                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           5736435120.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5416162800                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              310781280                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       10711678260                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        8807078880                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       670588805775                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             703071916065                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              246.784837                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           2836233678907                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      556712196                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2438058000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   2789808007000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  22935120354                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      9698204397                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  23490616053                       # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total          1344                       # Number of bytes read from this memory
@@ -359,30 +375,30 @@ system.realview.nvmem.bw_inst_read::total          472                       # I
 system.realview.nvmem.bw_total::cpu0.inst          180                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst          292                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total             472                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               20844041                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         13655604                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          1017556                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            13118749                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                8767800                       # Number of BTB hits
+system.cpu0.branchPred.lookups               20832099                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         13651765                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          1014112                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            13085676                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                8745572                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            66.834117                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                3422259                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            208349                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups         764708                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits            581484                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses          183224                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted       100888                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            66.833169                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                3412344                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            213562                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups         762387                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits            580471                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses          181916                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted        99152                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -412,61 +428,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                    67283                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               67283                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        46446                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        20837                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples        67283                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          67283    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        67283                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         6844                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12453.243717                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11569.675575                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  5895.982503                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         6363     92.97%     92.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767          412      6.02%     98.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151           59      0.86%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535            3      0.04%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            5      0.07%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         6844                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples    338010000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0      338010000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total    338010000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5263     76.90%     76.90% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1581     23.10%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6844                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        67283                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                    65584                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               65584                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        44931                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        20653                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples        65584                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          65584    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        65584                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         6815                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12330.961115                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11272.043541                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  9573.930789                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535         6808     99.90%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071            5      0.07%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         6815                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples    338892000                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0      338892000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total    338892000                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5268     77.30%     77.30% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1547     22.70%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6815                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        65584                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        67283                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6844                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        65584                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6815                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6844                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        74127                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6815                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        72399                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    17352300                       # DTB read hits
-system.cpu0.dtb.read_misses                     60872                       # DTB read misses
-system.cpu0.dtb.write_hits                   14551648                       # DTB write hits
-system.cpu0.dtb.write_misses                     6411                       # DTB write misses
+system.cpu0.dtb.read_hits                    17333612                       # DTB read hits
+system.cpu0.dtb.read_misses                     59171                       # DTB read misses
+system.cpu0.dtb.write_hits                   14536785                       # DTB write hits
+system.cpu0.dtb.write_misses                     6413                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3450                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1427                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1946                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3455                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1366                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1951                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      519                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                17413172                       # DTB read accesses
-system.cpu0.dtb.write_accesses               14558059                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      521                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                17392783                       # DTB read accesses
+system.cpu0.dtb.write_accesses               14543198                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         31903948                       # DTB hits
-system.cpu0.dtb.misses                          67283                       # DTB misses
-system.cpu0.dtb.accesses                     31971231                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                         31870397                       # DTB hits
+system.cpu0.dtb.misses                          65584                       # DTB misses
+system.cpu0.dtb.accesses                     31935981                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -496,42 +509,41 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                     3992                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                3992                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1          306                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3686                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples         3992                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           3992    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         3992                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2438                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12900.533224                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 12073.120538                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  5370.959057                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191          392     16.08%     16.08% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383         1803     73.95%     90.03% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575          168      6.89%     96.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           38      1.56%     98.48% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959           34      1.39%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2438                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples    337545500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0      337545500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total    337545500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2137     87.65%     87.65% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          301     12.35%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2438                       # Table walker page sizes translated
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                     3993                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                3993                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1          304                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3689                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         3993                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           3993    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         3993                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2420                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12562.190083                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11733.706609                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5199.448662                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          453     18.72%     18.72% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383         1764     72.89%     91.61% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575          139      5.74%     97.36% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           35      1.45%     98.80% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959           27      1.12%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-106495            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2420                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples    338263500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      338263500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total    338263500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2121     87.64%     87.64% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          299     12.36%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2420                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3992                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3992                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3993                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3993                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2438                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2438                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         6430                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    38811638                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3992                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2420                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2420                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         6413                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    38722571                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3993                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -540,45 +552,44 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2175                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2160                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     7061                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     7056                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                38815630                       # ITB inst accesses
-system.cpu0.itb.hits                         38811638                       # DTB hits
-system.cpu0.itb.misses                           3992                       # DTB misses
-system.cpu0.itb.accesses                     38815630                       # DTB accesses
-system.cpu0.numPwrStateTransitions               3698                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         1849                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    1494392801.532720                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   23960009045.887756                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         1074     58.09%     58.09% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10          768     41.54%     99.62% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.05%     99.68% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.05%     99.73% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses                38726564                       # ITB inst accesses
+system.cpu0.itb.hits                         38722571                       # DTB hits
+system.cpu0.itb.misses                           3993                       # DTB misses
+system.cpu0.itb.accesses                     38726564                       # DTB accesses
+system.cpu0.numPwrStateTransitions               3692                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         1846                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    1496527734.232936                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   23959432114.332718                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         1066     57.75%     57.75% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10          773     41.87%     99.62% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11            2      0.11%     99.73% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.78% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.22%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 499963441540                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           1849                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON    85039993966                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763132290034                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       170082548                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 499963466540                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           1846                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON    86336520606                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762590197394                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       172675597                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   79775908                       # Number of instructions committed
-system.cpu0.committedOps                     96002231                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                      5290576                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     1849                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                  5526291371                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.132004                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.469042                       # IPC: instructions per cycle
+system.cpu0.committedInsts                   79702454                       # Number of instructions committed
+system.cpu0.committedOps                     95912008                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                      5263315                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     1846                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                  5525206368                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.166503                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.461573                       # IPC: instructions per cycle
 system.cpu0.op_class_0::No_OpClass               2273      0.00%      0.00% # Class of committed instruction
-system.cpu0.op_class_0::IntAlu               63778191     66.43%     66.44% # Class of committed instruction
-system.cpu0.op_class_0::IntMult                 92152      0.10%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::IntAlu               63720470     66.44%     66.44% # Class of committed instruction
+system.cpu0.op_class_0::IntMult                 92091      0.10%     66.53% # Class of committed instruction
 system.cpu0.op_class_0::IntDiv                      0      0.00%     66.53% # Class of committed instruction
 system.cpu0.op_class_0::FloatAdd                    0      0.00%     66.53% # Class of committed instruction
 system.cpu0.op_class_0::FloatCmp                    0      0.00%     66.53% # Class of committed instruction
@@ -602,740 +613,739 @@ system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     66.53% # Cl
 system.cpu0.op_class_0::SimdFloatCmp                0      0.00%     66.53% # Class of committed instruction
 system.cpu0.op_class_0::SimdFloatCvt                0      0.00%     66.53% # Class of committed instruction
 system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     66.53% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMisc            8115      0.01%     66.54% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMisc            8071      0.01%     66.54% # Class of committed instruction
 system.cpu0.op_class_0::SimdFloatMult               0      0.00%     66.54% # Class of committed instruction
 system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     66.54% # Class of committed instruction
 system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     66.54% # Class of committed instruction
-system.cpu0.op_class_0::MemRead              16825163     17.53%     84.07% # Class of committed instruction
-system.cpu0.op_class_0::MemWrite             15296337     15.93%    100.00% # Class of committed instruction
+system.cpu0.op_class_0::MemRead              16807812     17.52%     84.07% # Class of committed instruction
+system.cpu0.op_class_0::MemWrite             15281291     15.93%    100.00% # Class of committed instruction
 system.cpu0.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
 system.cpu0.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
-system.cpu0.op_class_0::total                96002231                       # Class of committed instruction
+system.cpu0.op_class_0::total                95912008                       # Class of committed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1849                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      121004168                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                       49078380                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements           716277                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          496.364938                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           30460734                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           716789                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            42.496096                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        356009000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.364938                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.969463                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.969463                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                    1846                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      120803038                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                       51872559                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements           716043                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          497.070686                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           30430864                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           716555                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            42.468288                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        356904000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.070686                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970841                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.970841                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          127                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          317                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          330                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           74                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63863131                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63863131                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     15863909                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       15863909                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     13436402                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      13436402                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       320993                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       320993                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365530                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       365530                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361278                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       361278                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     29300311                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        29300311                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     29621304                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       29621304                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       439369                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       439369                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       580672                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       580672                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       135956                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       135956                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21086                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        21086                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20448                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20448                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1020041                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1020041                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1155997                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1155997                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6148409000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   6148409000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10121621500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  10121621500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    324178500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    324178500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    483049500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    483049500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       688000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       688000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  16270030500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  16270030500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  16270030500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  16270030500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     16303278                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     16303278                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     14017074                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     14017074                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       456949                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       456949                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386616                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       386616                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381726                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       381726                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     30320352                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     30320352                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     30777301                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     30777301                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.026950                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.026950                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041426                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.041426                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.297530                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.297530                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054540                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054540                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053567                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053567                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.033642                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.033642                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.037560                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.037560                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13993.725092                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13993.725092                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17430.875778                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 17430.875778                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15374.110784                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15374.110784                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23623.312793                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23623.312793                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         63800570                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63800570                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     15847676                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       15847676                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     13422923                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      13422923                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       320765                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       320765                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365692                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       365692                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361178                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       361178                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     29270599                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        29270599                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     29591364                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       29591364                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       438302                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       438302                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       581071                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       581071                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       135874                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       135874                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20748                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        20748                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20391                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20391                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1019373                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1019373                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1155247                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1155247                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6426011500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   6426011500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  11337499000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  11337499000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    330321500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    330321500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    481265000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    481265000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       655500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       655500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  17763510500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  17763510500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  17763510500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  17763510500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     16285978                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     16285978                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     14003994                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     14003994                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       456639                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       456639                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386440                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       386440                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381569                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       381569                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     30289972                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     30289972                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     30746611                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     30746611                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.026913                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.026913                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041493                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.041493                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.297552                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.297552                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.053690                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053690                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053440                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053440                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.033654                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.033654                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.037573                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.037573                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14661.150303                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14661.150303                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19511.383291                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19511.383291                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15920.642954                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15920.642954                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23601.834143                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23601.834143                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15950.369152                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15950.369152                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14074.457373                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14074.457373                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17425.918187                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 17425.918187                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15376.374490                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15376.374490                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       716277                       # number of writebacks
-system.cpu0.dcache.writebacks::total           716277                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        44943                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        44943                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       255413                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       255413                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14625                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14625                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data       300356                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       300356                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data       300356                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       300356                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       394426                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       394426                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       325259                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       325259                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       102388                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       102388                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6461                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6461                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20448                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20448                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       719685                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       719685                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       822073                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       822073                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20384                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20384                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19085                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19085                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39469                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39469                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5005155000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5005155000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5561809000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5561809000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1663563000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1663563000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     98784500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     98784500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    462621500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    462621500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       668000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       668000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10566964000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  10566964000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  12230527000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  12230527000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4556252000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4556252000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4556252000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4556252000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024193                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024193                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023204                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023204                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224069                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224069                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016712                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016712                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053567                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053567                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023736                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023736                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026710                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.026710                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12689.718731                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12689.718731                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17099.631371                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17099.631371                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16247.636442                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16247.636442                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15289.351494                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15289.351494                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22624.290884                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22624.290884                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       716044                       # number of writebacks
+system.cpu0.dcache.writebacks::total           716044                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        44411                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        44411                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       255478                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       255478                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14411                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14411                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data       299889                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       299889                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data       299889                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       299889                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       393891                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       393891                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       325593                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       325593                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       102318                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       102318                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6337                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6337                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20391                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20391                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       719484                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       719484                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       821802                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       821802                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20577                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20577                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19270                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19270                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39847                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39847                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5265212000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5265212000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6193589500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6193589500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1698431500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1698431500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    100630000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    100630000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    460892000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    460892000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       637500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       637500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11458801500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  11458801500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13157233000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  13157233000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4606601500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4606601500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4606601500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4606601500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024186                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024186                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023250                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023250                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224068                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224068                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016398                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016398                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053440                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053440                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023753                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.023753                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026728                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.026728                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13367.180261                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13367.180261                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19022.489734                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19022.489734                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16599.537716                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16599.537716                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15879.753827                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15879.753827                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22602.716885                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22602.716885                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14682.762598                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14682.762598                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14877.665365                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14877.665365                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223520.996860                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223520.996860                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115438.749398                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115438.749398                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          1970602                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.774874                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           36833218                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1971114                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            18.686498                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6638665000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.774874                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999560                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999560                       # Average percentage of cache occupancy
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15926.416015                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15926.416015                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16010.222657                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16010.222657                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223871.385528                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223871.385528                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115607.235175                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115607.235175                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          1964076                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.773099                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           36750687                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1964588                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            18.706562                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6697445000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.773099                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999557                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999557                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          244                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          100                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          104                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         79579816                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        79579816                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     36833218                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       36833218                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     36833218                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        36833218                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     36833218                       # number of overall hits
-system.cpu0.icache.overall_hits::total       36833218                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1971127                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1971127                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1971127                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1971127                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1971127                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1971127                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  19380486500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  19380486500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  19380486500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  19380486500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  19380486500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  19380486500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     38804345                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     38804345                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     38804345                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     38804345                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     38804345                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     38804345                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050797                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.050797                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050797                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.050797                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050797                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.050797                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9832.185597                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9832.185597                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9832.185597                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9832.185597                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9832.185597                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9832.185597                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         79395176                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        79395176                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst     36750687                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       36750687                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     36750687                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        36750687                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     36750687                       # number of overall hits
+system.cpu0.icache.overall_hits::total       36750687                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1964601                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1964601                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1964601                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1964601                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1964601                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1964601                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  19791309500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  19791309500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  19791309500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  19791309500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  19791309500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  19791309500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     38715288                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     38715288                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     38715288                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     38715288                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     38715288                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     38715288                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050745                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.050745                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050745                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.050745                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050745                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.050745                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10073.958783                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10073.958783                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10073.958783                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10073.958783                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.958783                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10073.958783                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      1970602                       # number of writebacks
-system.cpu0.icache.writebacks::total          1970602                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1971127                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1971127                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1971127                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1971127                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1971127                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1971127                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3448                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total         3448                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3448                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total         3448                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  18394923500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  18394923500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  18394923500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  18394923500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  18394923500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  18394923500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    319413000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    319413000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    319413000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    319413000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.050797                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.050797                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.050797                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.050797                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.050797                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.050797                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9332.185851                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9332.185851                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9332.185851                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9332.185851                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9332.185851                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9332.185851                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92637.180974                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92637.180974                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1842994                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1843099                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit           91                       # number of redundant prefetches already in prefetch queue
+system.cpu0.icache.writebacks::writebacks      1964076                       # number of writebacks
+system.cpu0.icache.writebacks::total          1964076                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1964601                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1964601                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1964601                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1964601                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1964601                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1964601                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3277                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total         3277                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3277                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total         3277                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  18809009500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  18809009500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  18809009500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  18809009500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  18809009500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  18809009500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    323882000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    323882000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    323882000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    323882000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.050745                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.050745                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.050745                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.050745                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.050745                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.050745                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9573.959038                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9573.959038                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9573.959038                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9573.959038                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9573.959038                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9573.959038                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1843459                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1843558                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit           87                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       234669                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements          289615                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       15618.929391                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           2598682                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          305234                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            8.513737                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       234570                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.tags.replacements          289188                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15635.373554                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           2589127                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          304798                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            8.494567                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14506.516440                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    65.609020                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.093662                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1046.710270                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.885407                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004004                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000006                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.063886                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.953304                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022          240                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14528.592543                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    65.479311                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.075767                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1041.225933                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.886755                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003997                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000005                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.063551                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.954307                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          228                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15363                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           27                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          131                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           75                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          299                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1118                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         7270                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5493                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1183                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.014648                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15366                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           19                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          147                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           59                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            7                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          246                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1155                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         7305                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5549                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1111                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.013916                       # Percentage of cache occupancy per task id
 system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000977                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.937683                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        91638891                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       91638891                       # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        79804                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         5347                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         85151                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks       482674                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total       482674                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      2161538                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      2161538                       # number of WritebackClean hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            1                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       221695                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       221695                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1879215                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1879215                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       389061                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       389061                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        79804                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         5347                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1879215                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       610756                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        2575122                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        79804                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         5347                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1879215                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       610756                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       2575122                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          923                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          182                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total         1105                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        56710                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        56710                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20446                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        20446                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.937866                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        91385031                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       91385031                       # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        77639                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         5220                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total         82859                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks       481305                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total       481305                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      2156745                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      2156745                       # number of WritebackClean hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       222879                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       222879                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1872794                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      1872794                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       388786                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total       388786                       # number of ReadSharedReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        77639                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker         5220                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1872794                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data       611665                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        2567318                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        77639                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker         5220                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1872794                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       611665                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       2567318                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          934                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          150                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total         1084                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        56829                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        56829                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20390                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        20390                       # number of SCUpgradeReq misses
 system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
 system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        46862                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        46862                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        91912                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total        91912                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       114207                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       114207                       # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          923                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          182                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        91912                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       161069                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       254086                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          923                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          182                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        91912                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       161069                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       254086                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     32732000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4240000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total     36972000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data     42663000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total     42663000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data      9483000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total      9483000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       635999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       635999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2305357000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   2305357000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   4072700500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total   4072700500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3450099996                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3450099996                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     32732000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4240000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4072700500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   5755456996                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   9865129496                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     32732000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4240000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4072700500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   5755456996                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   9865129496                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        80727                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5529                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total        86256                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks       482674                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total       482674                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      2161538                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      2161538                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56710                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        56710                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20447                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        20447                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        45892                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total        45892                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        91807                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total        91807                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       113754                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       113754                       # number of ReadSharedReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          934                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          150                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        91807                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       159646                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       252537                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          934                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          150                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        91807                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       159646                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       252537                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     44624500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3518000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total     48142500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data     45750500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total     45750500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data      9568000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total      9568000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       607499                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       607499                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2923141000                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   2923141000                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   4535079000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   4535079000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3749547498                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3749547498                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     44624500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3518000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4535079000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   6672688498                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  11255909998                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     44624500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3518000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4535079000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   6672688498                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  11255909998                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        78573                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5370                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        83943                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks       481305                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total       481305                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      2156745                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      2156745                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56829                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        56829                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20390                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        20390                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       268557                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       268557                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1971127                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      1971127                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       503268                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total       503268                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        80727                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5529                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      1971127                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       771825                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      2829208                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        80727                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5529                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1971127                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       771825                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      2829208                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.011434                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.032917                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.012811                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       268771                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       268771                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1964601                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1964601                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       502540                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       502540                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        78573                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5370                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1964601                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       771311                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      2819855                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        78573                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5370                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1964601                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       771311                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2819855                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.011887                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.027933                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.012914                       # miss rate for ReadReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999951                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999951                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.174496                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.174496                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.046629                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.046629                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.226931                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.226931                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.011434                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.032917                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.046629                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.208686                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.089808                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.011434                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.032917                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.046629                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.208686                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.089808                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35462.621885                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23296.703297                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33458.823529                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   752.301181                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   752.301181                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   463.807102                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   463.807102                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       635999                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       635999                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49194.592634                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49194.592634                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44310.868004                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44310.868004                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30209.181539                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30209.181539                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35462.621885                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23296.703297                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44310.868004                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35732.866014                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 38825.946711                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35462.621885                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23296.703297                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44310.868004                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35732.866014                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 38825.946711                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs           38                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.170748                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.170748                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.046731                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.046731                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.226358                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.226358                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.011887                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.027933                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.046731                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.206980                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.089557                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.011887                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.027933                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.046731                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.206980                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.089557                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47777.837259                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23453.333333                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44411.900369                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   805.055517                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   805.055517                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   469.249632                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   469.249632                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       607499                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       607499                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63696.090822                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63696.090822                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49397.965297                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49397.965297                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32961.895828                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32961.895828                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47777.837259                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23453.333333                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49397.965297                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41796.778485                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 44571.330134                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47777.837259                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23453.333333                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49397.965297                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41796.778485                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 44571.330134                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           19                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches           11131                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks       233184                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          233184                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.unused_prefetches           10760                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks       232550                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          232550                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
 system.cpu0.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2845                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         2845                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           59                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           59                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          394                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          394                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           59                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3239                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         3299                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            1                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           59                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3239                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         3299                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          923                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          181                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total         1104                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       263706                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       263706                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        56710                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        56710                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20446                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20446                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         3193                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         3193                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           56                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           56                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          400                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          400                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           56                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3593                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         3650                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           56                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3593                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         3650                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          933                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          150                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total         1083                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264017                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       264017                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        56829                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        56829                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20390                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20390                       # number of SCUpgradeReq MSHR misses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        44017                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        44017                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        91853                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        91853                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       113813                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       113813                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          923                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          181                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        91853                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       157830                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       250787                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          923                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          181                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        91853                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       157830                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       263706                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       514493                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3448                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20384                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        23832                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19085                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19085                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3448                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        39469                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        42917                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     27194000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3129500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     30323500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14352533313                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  14352533313                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    980881500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    980881500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    308321499                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    308321499                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       515999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       515999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1725463000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1725463000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3519932500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3519932500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2745701996                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2745701996                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     27194000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3129500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3519932500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4471164996                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   8021420996                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     27194000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3129500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3519932500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4471164996                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14352533313                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  22373954309                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    291829000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4393084500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4684913500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    291829000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4393084500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4684913500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.011434                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.032736                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.012799                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42699                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        42699                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        91751                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        91751                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       113354                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       113354                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          933                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          150                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        91751                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       156053                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       248887                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          933                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          150                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        91751                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       156053                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       264017                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total       512904                       # number of overall MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3277                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20577                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        23854                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19270                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19270                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3277                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        39847                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        43124                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     39007500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2618000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     41625500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  16806240735                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  16806240735                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    985974500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    985974500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    307077498                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    307077498                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       499499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       499499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2171871000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2171871000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3982642000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3982642000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   3045418498                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   3045418498                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     39007500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2618000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3982642000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5217289498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   9241556998                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     39007500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2618000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3982642000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5217289498                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  16806240735                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  26047797733                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    297666000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4441867000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4739533000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    297666000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4441867000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4739533000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.011874                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.027933                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.012902                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999951                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999951                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.163902                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.163902                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.046599                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.046599                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.226148                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.226148                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.011434                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.032736                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.046599                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.204489                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.088642                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.011434                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.032736                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.046599                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.204489                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.158868                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.158868                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.046702                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.046702                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.225562                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.225562                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.011874                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.027933                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.046702                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.202322                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.088262                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.011874                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.027933                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.046702                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.202322                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.181851                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27466.938406                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54426.267559                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 54426.267559                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17296.446835                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17296.446835                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15079.795510                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15079.795510                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       515999                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       515999                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39199.922757                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39199.922757                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38321.366749                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38321.366749                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24124.678165                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24124.678165                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38321.366749                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28328.993195                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31984.995219                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38321.366749                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28328.993195                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54426.267559                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43487.383325                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215516.311813                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196580.794730                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111304.682156                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109162.185148                       # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests      5528539                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2785631                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        42665                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       220679                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       216467                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4212                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq        119671                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2643248                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        19085                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        19085                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       716138                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      2204203                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict       105351                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       312801                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        88645                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43001                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       114336                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           29                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       287716                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       284337                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1971127                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       603215                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3113                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5919751                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2595390                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13207                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       168847                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          8697195                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    252491264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     99508828                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        22116                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       322908                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         352345116                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     940127                       # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic             19140516                       # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples      3787201                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.076346                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.269706                       # Request fanout histogram
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.181890                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38435.364728                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63655.903730                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63655.903730                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17349.847789                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17349.847789                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15060.200981                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15060.200981                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       499499                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       499499                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50864.680672                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50864.680672                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43407.069133                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43407.069133                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26866.440514                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26866.440514                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43407.069133                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33432.804868                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37131.537597                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43407.069133                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33432.804868                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63655.903730                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50784.937791                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215865.626671                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198689.234510                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111473.059452                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109904.763009                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests      5514708                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2778846                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        42068                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       220650                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       216436                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4214                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq        117829                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2634124                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        19270                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        19270                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       714129                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      2198813                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict       105915                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       313152                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        88836                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42982                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       114292                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           15                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           32                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       287887                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       284399                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1964601                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       602822                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3087                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5899831                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2594741                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13052                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       164810                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          8672434                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    251644992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     99451448                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        21480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       314292                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         351432212                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     940964                       # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic             19090924                       # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples      3779220                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.076318                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.269673                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           3502276     92.48%     92.48% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            280713      7.41%     99.89% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              4212      0.11%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           3495013     92.48%     92.48% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            279993      7.41%     99.89% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              4214      0.11%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3787201                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    5519275492                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       3779220                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    5504902494                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    116183079                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    115882925                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   2962129461                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   2952081467                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1227256511                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1226789533                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy      7683988                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy      7686990                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     88134970                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     86252968                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups               19426531                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          6224342                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           651829                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            10038478                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                3634441                       # Number of BTB hits
+system.cpu1.branchPred.lookups               19393527                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          6185527                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           769783                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             9956759                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                3606289                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            36.205100                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                8674574                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            447731                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        3678807                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits           3614078                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses           64729                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted        23620                       # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu1.branchPred.BTBHitPct            36.219507                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                8702764                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            566393                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        3646067                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           3582470                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses           63597                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted        23601                       # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1365,66 +1375,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                    27735                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               27735                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        21301                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         6434                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples        27735                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0          27735    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        27735                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         2744                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12429.118076                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11482.413236                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6276.586572                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191          644     23.47%     23.47% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1820     66.33%     89.80% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575          198      7.22%     97.01% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767           63      2.30%     99.31% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959            9      0.33%     99.64% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151            4      0.15%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-57343            1      0.04%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::57344-65535            1      0.04%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::90112-98303            1      0.04%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-106495            1      0.04%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::114688-122879            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         2744                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  -1939283032                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    -1939283032    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  -1939283032                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         2036     74.20%     74.20% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          708     25.80%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2744                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        27735                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                    26638                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               26638                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        20208                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         6430                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples        26638                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0          26638    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        26638                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         2684                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 12533.532042                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11490.379150                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  8690.810286                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767         2656     98.96%     98.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535           26      0.97%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         2684                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -1849661032                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1849661032    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -1849661032                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1998     74.44%     74.44% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          686     25.56%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2684                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        26638                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        27735                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2744                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        26638                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2684                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2744                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        30479                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2684                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        29322                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    11374009                       # DTB read hits
-system.cpu1.dtb.read_misses                     25676                       # DTB read misses
-system.cpu1.dtb.write_hits                    7084428                       # DTB write hits
-system.cpu1.dtb.write_misses                     2059                       # DTB write misses
+system.cpu1.dtb.read_hits                    11320530                       # DTB read hits
+system.cpu1.dtb.read_misses                     24586                       # DTB read misses
+system.cpu1.dtb.write_hits                    7061626                       # DTB write hits
+system.cpu1.dtb.write_misses                     2052                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1996                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      172                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   434                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1992                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      148                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   300                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      262                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                11399685                       # DTB read accesses
-system.cpu1.dtb.write_accesses                7086487                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      267                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                11345116                       # DTB read accesses
+system.cpu1.dtb.write_accesses                7063678                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         18458437                       # DTB hits
-system.cpu1.dtb.misses                          27735                       # DTB misses
-system.cpu1.dtb.accesses                     18486172                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                         18382156                       # DTB hits
+system.cpu1.dtb.misses                          26638                       # DTB misses
+system.cpu1.dtb.accesses                     18408794                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1454,46 +1456,45 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                     2480                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                2480                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                     2499                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                2499                       # Table walker walks initiated with short descriptors
 system.cpu1.itb.walker.walksShortTerminationLevel::Level1          180                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2300                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         2480                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           2480    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         2480                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1130                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12659.734513                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11853.270475                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5315.711785                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          183     16.19%     16.19% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          614     54.34%     70.53% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          213     18.85%     89.38% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479           45      3.98%     93.36% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575           23      2.04%     95.40% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           28      2.48%     97.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767           15      1.33%     99.20% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863            2      0.18%     99.38% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959            4      0.35%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.09%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::53248-57343            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1130                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  -1939872532                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    -1939872532    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  -1939872532                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          965     85.40%     85.40% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          165     14.60%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         1130                       # Table walker page sizes translated
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2319                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         2499                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           2499    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         2499                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1128                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 12699.024823                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11989.496313                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  4984.320484                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          166     14.72%     14.72% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          634     56.21%     70.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          206     18.26%     89.18% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           49      4.34%     93.53% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575           22      1.95%     95.48% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           28      2.48%     97.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767           16      1.42%     99.38% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            3      0.27%     99.65% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            2      0.18%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         1128                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -1850303532                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1850303532    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1850303532                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          963     85.37%     85.37% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          165     14.63%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         1128                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2480                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2480                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2499                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2499                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1130                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1130                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         3610                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    39704875                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2480                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1128                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1128                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         3627                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    39699373                       # ITB inst hits
+system.cpu1.itb.inst_misses                      2499                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1502,777 +1503,777 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1100                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1101                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1840                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1838                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                39707355                       # ITB inst accesses
-system.cpu1.itb.hits                         39704875                       # DTB hits
-system.cpu1.itb.misses                           2480                       # DTB misses
-system.cpu1.itb.accesses                     39707355                       # DTB accesses
-system.cpu1.numPwrStateTransitions               5533                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         2767                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    1008221990.514637                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   25700822378.312321                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         1966     71.05%     71.05% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10          797     28.80%     99.86% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses                39701872                       # ITB inst accesses
+system.cpu1.itb.hits                         39699373                       # DTB hits
+system.cpu1.itb.misses                           2499                       # DTB misses
+system.cpu1.itb.accesses                     39701872                       # DTB accesses
+system.cpu1.numPwrStateTransitions               5523                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         2762                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    1010212132.618392                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   25718871891.755051                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         1964     71.11%     71.11% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10          794     28.75%     99.86% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.04%     99.93% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11            1      0.04%     99.96% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.04%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 949980874116                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           2767                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON    58422036246                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789750247754                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                       116847616                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value 949979704076                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           2762                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON    58720807708                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790205910292                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                       117445100                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   48452289                       # Number of instructions committed
-system.cpu1.committedOps                     59283596                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                      5163197                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     2767                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                  5578862239                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.411602                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.414662                       # IPC: instructions per cycle
+system.cpu1.committedInsts                   48204911                       # Number of instructions committed
+system.cpu1.committedOps                     58981541                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                      5132548                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     2762                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                  5579768700                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.436372                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.410446                       # IPC: instructions per cycle
 system.cpu1.op_class_0::No_OpClass                 66      0.00%      0.00% # Class of committed instruction
-system.cpu1.op_class_0::IntAlu               40834570     68.88%     68.88% # Class of committed instruction
-system.cpu1.op_class_0::IntMult                 45625      0.08%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::IntDiv                      0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::FloatAdd                    0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::FloatCmp                    0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::FloatCvt                    0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::FloatMult                   0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::FloatDiv                    0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::FloatSqrt                   0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdAdd                     0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdAlu                     0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdCmp                     0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdCvt                     0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdMisc                    0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdMult                    0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdShift                   0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdSqrt                    0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMisc            3333      0.01%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMult               0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     68.96% # Class of committed instruction
-system.cpu1.op_class_0::MemRead              11200779     18.89%     87.86% # Class of committed instruction
-system.cpu1.op_class_0::MemWrite              7199223     12.14%    100.00% # Class of committed instruction
+system.cpu1.op_class_0::IntAlu               40607989     68.85%     68.85% # Class of committed instruction
+system.cpu1.op_class_0::IntMult                 45709      0.08%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::IntDiv                      0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::FloatAdd                    0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::FloatCmp                    0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::FloatCvt                    0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::FloatMult                   0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::FloatDiv                    0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::FloatSqrt                   0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdAdd                     0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdAlu                     0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdCmp                     0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdCvt                     0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdMisc                    0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdMult                    0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdShift                   0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdSqrt                    0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMisc            3353      0.01%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMult               0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     68.93% # Class of committed instruction
+system.cpu1.op_class_0::MemRead              11147247     18.90%     87.83% # Class of committed instruction
+system.cpu1.op_class_0::MemWrite              7177177     12.17%    100.00% # Class of committed instruction
 system.cpu1.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
 system.cpu1.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
-system.cpu1.op_class_0::total                59283596                       # Class of committed instruction
+system.cpu1.op_class_0::total                58981541                       # Class of committed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2767                       # number of quiesce instructions executed
-system.cpu1.tickCycles                       94150450                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                       22697166                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements           195596                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          473.279573                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           18031187                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           195963                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            92.013222                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      91237126000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   473.279573                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.924374                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.924374                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          367                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          310                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           57                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.716797                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         36965565                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        36965565                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data     10998874                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       10998874                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      6796614                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       6796614                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50142                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        50142                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        80008                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        80008                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71567                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        71567                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     17795488                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        17795488                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     17845630                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       17845630                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       148727                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       148727                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       145387                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       145387                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30687                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        30687                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16966                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        16966                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23611                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23611                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       294114                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        294114                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       324801                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       324801                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2356620500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2356620500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3915884500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   3915884500                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    322199000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    322199000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    556849500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    556849500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       389000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       389000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   6272505000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   6272505000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   6272505000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   6272505000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     11147601                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     11147601                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      6942001                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      6942001                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        80829                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        80829                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96974                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        96974                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        95178                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        95178                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     18089602                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     18089602                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     18170431                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     18170431                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.013342                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.013342                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.020943                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.020943                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.379653                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.379653                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.174954                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.174954                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.248072                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.248072                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.016259                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.016259                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.017875                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.017875                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15845.276917                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15845.276917                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26934.213513                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 26934.213513                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18990.864081                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18990.864081                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23584.325103                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23584.325103                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    2762                       # number of quiesce instructions executed
+system.cpu1.tickCycles                       94223774                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                       23221326                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements           197231                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          476.160023                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           17961880                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           197583                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            90.908023                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      91326739500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   476.160023                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.930000                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.930000                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          352                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          283                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           69                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.687500                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         36815018                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        36815018                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data     10942799                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       10942799                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      6773317                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       6773317                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50710                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        50710                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        80304                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        80304                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71747                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        71747                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     17716116                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        17716116                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     17766826                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       17766826                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       150509                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       150509                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       145770                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       145770                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30651                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        30651                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16960                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        16960                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23697                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23697                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       296279                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        296279                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       326930                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       326930                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2503108000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2503108000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4131089000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   4131089000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    325863000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    325863000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    557327500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    557327500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       612000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       612000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   6634197000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   6634197000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   6634197000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   6634197000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     11093308                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     11093308                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      6919087                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      6919087                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        81361                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        81361                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        97264                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        97264                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        95444                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        95444                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     18012395                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     18012395                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     18093756                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     18093756                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.013568                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.013568                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.021068                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.021068                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.376728                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.376728                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.174371                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.174371                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.248282                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.248282                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.016449                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.016449                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.018069                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.018069                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16630.952302                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16630.952302                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28339.774988                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 28339.774988                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19213.620283                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19213.620283                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23518.905347                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23518.905347                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21326.781452                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 21326.781452                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19311.840173                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 19311.840173                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22391.721992                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 22391.721992                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20292.408161                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20292.408161                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks       195596                       # number of writebacks
-system.cpu1.dcache.writebacks::total           195596                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data         5710                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total         5710                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        52879                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        52879                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12082                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12082                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        58589                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        58589                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        58589                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        58589                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       143017                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       143017                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        92508                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        92508                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29859                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        29859                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4884                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4884                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23611                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23611                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       235525                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       235525                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       265384                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       265384                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14595                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14595                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11928                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11928                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        26523                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        26523                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2115141000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2115141000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2362860000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2362860000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    507235000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    507235000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     82984000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     82984000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    533247500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    533247500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       380000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       380000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4478001000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4478001000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4985236000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4985236000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2537758000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2537758000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2537758000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2537758000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.012829                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.012829                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013326                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.013326                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.369409                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.369409                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050364                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050364                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.248072                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.248072                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.013020                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.013020                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.014605                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.014605                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14789.437619                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14789.437619                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25542.223375                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25542.223375                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16987.675408                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16987.675408                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16990.990991                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16990.990991                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22584.706281                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22584.706281                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       197231                       # number of writebacks
+system.cpu1.dcache.writebacks::total           197231                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data         5831                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total         5831                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        53065                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total        53065                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12062                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12062                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        58896                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        58896                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        58896                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        58896                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       144678                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       144678                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        92705                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        92705                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29814                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        29814                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4898                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4898                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23697                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23697                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       237383                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       237383                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       267197                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       267197                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14423                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14423                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11756                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11756                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        26179                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        26179                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2254716500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2254716500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2475419500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2475419500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    516532000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    516532000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     86654500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     86654500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    533644500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    533644500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       598000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       598000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4730136000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4730136000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5246668000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5246668000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2493280000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2493280000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2493280000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2493280000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013042                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.013042                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013398                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.013398                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.366441                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.366441                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050358                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050358                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.248282                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.248282                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.013179                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.013179                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.014767                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.014767                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15584.377030                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15584.377030                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26702.114233                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26702.114233                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17325.149259                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17325.149259                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17691.812985                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17691.812985                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22519.496139                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22519.496139                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19012.847893                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19012.847893                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18784.990806                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18784.990806                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173878.588558                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173878.588558                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95681.408589                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95681.408589                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements           948026                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.199607                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           38754409                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           948538                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            40.856991                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      72914784000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.199607                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974999                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.974999                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19926.178370                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19926.178370                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19635.953996                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19635.953996                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172868.335298                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172868.335298                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95239.695939                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95239.695939                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements           951926                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.186802                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           38745002                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           952438                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            40.679815                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      73025806000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.186802                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974974                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.974974                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          461                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          463                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           49                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         80354432                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        80354432                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst     38754409                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       38754409                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     38754409                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        38754409                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     38754409                       # number of overall hits
-system.cpu1.icache.overall_hits::total       38754409                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       948538                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       948538                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       948538                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        948538                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       948538                       # number of overall misses
-system.cpu1.icache.overall_misses::total       948538                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8680888000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   8680888000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   8680888000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   8680888000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   8680888000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   8680888000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     39702947                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     39702947                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     39702947                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     39702947                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     39702947                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     39702947                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.023891                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.023891                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.023891                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.023891                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.023891                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.023891                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9151.861075                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9151.861075                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9151.861075                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9151.861075                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9151.861075                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9151.861075                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         80347318                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        80347318                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst     38745002                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       38745002                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     38745002                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        38745002                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     38745002                       # number of overall hits
+system.cpu1.icache.overall_hits::total       38745002                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       952438                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       952438                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       952438                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        952438                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       952438                       # number of overall misses
+system.cpu1.icache.overall_misses::total       952438                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8816320000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   8816320000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   8816320000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   8816320000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   8816320000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   8816320000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     39697440                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     39697440                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     39697440                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     39697440                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     39697440                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     39697440                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.023992                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.023992                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.023992                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.023992                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.023992                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.023992                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9256.581531                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9256.581531                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9256.581531                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9256.581531                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9256.581531                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9256.581531                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks       948026                       # number of writebacks
-system.cpu1.icache.writebacks::total           948026                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       948538                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       948538                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       948538                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       948538                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       948538                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       948538                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks       951926                       # number of writebacks
+system.cpu1.icache.writebacks::total           951926                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       952438                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       952438                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       952438                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       952438                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       952438                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       952438                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8206619000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   8206619000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8206619000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   8206619000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8206619000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   8206619000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10719000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10719000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10719000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     10719000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023891                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.023891                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023891                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.023891                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023891                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.023891                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8651.861075                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8651.861075                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8651.861075                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8651.861075                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8651.861075                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8651.861075                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95705.357143                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95705.357143                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95705.357143                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95705.357143                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       199515                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       199547                       # number of prefetch candidates identified
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8340101000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   8340101000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8340101000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   8340101000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8340101000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   8340101000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     11130500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     11130500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     11130500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     11130500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023992                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.023992                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023992                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.023992                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023992                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.023992                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8756.581531                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8756.581531                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8756.581531                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8756.581531                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8756.581531                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8756.581531                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99379.464286                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99379.464286                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99379.464286                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99379.464286                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       201450                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       201482                       # number of prefetch candidates identified
 system.cpu1.l2cache.prefetcher.pfBufferHit           28                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        59237                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements           51581                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       14798.019682                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1058904                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           65844                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           16.082012                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        57990                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.tags.replacements           53299                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       14769.496108                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1064390                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           67600                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           15.745414                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14409.418299                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    42.207150                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.101777                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   346.292455                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.879481                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002576                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.021136                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.903199                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          289                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           42                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13932                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14396.977583                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    38.648393                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.118214                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   333.751919                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.878722                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002359                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000007                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.020371                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.901459                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          279                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           41                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13981                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          101                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          185                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           12                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           19                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1267                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         7924                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4741                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.017639                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002563                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.850342                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        39538104                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       39538104                       # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        30011                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         3192                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         33203                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks       117770                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total       117770                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      1005566                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      1005566                       # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27881                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        27881                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       913030                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       913030                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       102798                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total       102798                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        30011                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         3192                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       913030                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       130679                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        1076912                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        30011                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         3192                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       913030                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       130679                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       1076912                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          718                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          296                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total         1014                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29883                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29883                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23611                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        23611                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34746                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        34746                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        35508                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        35508                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        74962                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        74962                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          718                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          296                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        35508                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       109708                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       146230                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          718                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          296                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        35508                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       109708                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       146230                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     16837500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      6001500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     22839000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     13404000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total     13404000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     19834500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     19834500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       366500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       366500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1396405497                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1396405497                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1255643000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1255643000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1755754987                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1755754987                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     16837500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      6001500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1255643000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3152160484                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   4430642484                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     16837500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      6001500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1255643000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3152160484                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   4430642484                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        30729                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         3488                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total        34217                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks       117770                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total       117770                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks      1005566                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total      1005566                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29883                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        29883                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23611                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23611                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62627                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        62627                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       948538                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       948538                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       177760                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       177760                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        30729                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         3488                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       948538                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       240387                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total      1223142                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        30729                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         3488                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       948538                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       240387                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total      1223142                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.023366                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.084862                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.029634                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           82                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          194                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           14                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           18                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1305                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         7821                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4855                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.017029                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002502                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.853333                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        39716759                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       39716759                       # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        29141                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         3302                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total         32443                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks       117742                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total       117742                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks      1011389                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total      1011389                       # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27835                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        27835                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       916991                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       916991                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       103815                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total       103815                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        29141                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         3302                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       916991                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       131650                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        1081084                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        29141                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         3302                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       916991                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       131650                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       1081084                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          704                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          285                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          989                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        30019                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        30019                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23697                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        23697                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34851                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        34851                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        35447                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        35447                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        75575                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        75575                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          704                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          285                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        35447                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data       110426                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       146862                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          704                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          285                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        35447                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       110426                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       146862                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     18655500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5724000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     24379500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     14027500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total     14027500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     17693000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     17693000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       577000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       577000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1507211500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1507211500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1359433500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1359433500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1899319493                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1899319493                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     18655500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5724000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1359433500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3406530993                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   4790343993                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     18655500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5724000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1359433500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3406530993                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   4790343993                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        29845                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         3587                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total        33432                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks       117742                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total       117742                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks      1011389                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total      1011389                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        30019                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        30019                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23697                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23697                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62686                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        62686                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       952438                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       952438                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       179390                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       179390                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        29845                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         3587                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       952438                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       242076                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total      1227946                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        29845                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         3587                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       952438                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       242076                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total      1227946                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.023589                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.079454                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.029582                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.554809                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.554809                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.037434                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.037434                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.421703                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.421703                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.023366                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.084862                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.037434                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.456381                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.119553                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.023366                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.084862                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.037434                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.456381                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.119553                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23450.557103                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20275.337838                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22523.668639                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   448.549342                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   448.549342                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   840.053365                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   840.053365                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.555961                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.555961                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.037217                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.037217                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.421289                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.421289                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.023589                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.079454                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.037217                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.456163                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.119600                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.023589                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.079454                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.037217                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.456163                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.119600                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 26499.289773                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20084.210526                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24650.657230                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   467.287385                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   467.287385                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   746.634595                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   746.634595                       # average SCUpgradeReq miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40188.956916                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40188.956916                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35362.256393                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35362.256393                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23421.933606                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23421.933606                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23450.557103                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20275.337838                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35362.256393                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28732.275531                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 30299.134815                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23450.557103                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20275.337838                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35362.256393                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28732.275531                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 30299.134815                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          120                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43247.295630                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43247.295630                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38351.158067                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38351.158067                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 25131.584426                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 25131.584426                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 26499.289773                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20084.210526                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38351.158067                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30848.993833                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 32617.995077                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 26499.289773                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20084.210526                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38351.158067                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30848.993833                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 32617.995077                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs           44                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           40                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           44                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches             854                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks        34916                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           34916                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            2                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.unused_prefetches             874                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks        36491                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           36491                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            3                       # number of ReadReq MSHR hits
 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            2                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          211                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          211                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           16                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           16                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           85                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           85                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            2                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          204                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          204                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           18                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           18                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           78                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           78                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            2                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           16                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          296                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total          316                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            2                       # number of overall MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           18                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data          282                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total          305                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            3                       # number of overall MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            2                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           16                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          296                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total          316                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          716                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          294                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total         1010                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        25917                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        25917                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29883                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29883                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23611                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23611                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34535                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        34535                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        35492                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        35492                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        74877                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        74877                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          716                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          294                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        35492                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       109412                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       145914                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          716                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          294                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        35492                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       109412                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        25917                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       171831                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           18                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data          282                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total          305                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          701                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          283                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total          984                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        26312                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        26312                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        30019                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        30019                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23697                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23697                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34647                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        34647                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        35429                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        35429                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        75497                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        75497                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          701                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          283                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        35429                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data       110144                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       146557                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          701                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          283                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        35429                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data       110144                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        26312                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       172869                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        14595                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        14707                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11928                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11928                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        14423                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        14535                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11756                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11756                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        26523                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        26635                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     12503500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4198500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     16702000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    979860887                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    979860887                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    459895000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    459895000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    354696000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    354696000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       312500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       312500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1165426499                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1165426499                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst   1042424000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total   1042424000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1304028987                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1304028987                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     12503500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4198500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   1042424000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2469455486                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   3528581486                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     12503500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4198500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   1042424000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2469455486                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    979860887                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4508442373                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9823000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2420981000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2430804000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9823000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2420981000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2430804000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.023300                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.084289                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.029517                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        26179                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        26291                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     14391500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3995000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     18386500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    996240965                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    996240965                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    460605000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    460605000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    354483500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    354483500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       493000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       493000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1271760500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1271760500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst   1146491500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total   1146491500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1443582493                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1443582493                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     14391500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3995000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   1146491500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2715342993                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3880220993                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     14391500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3995000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   1146491500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2715342993                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    996240965                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4876461958                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10234500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2377871000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2388105500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     10234500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2377871000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2388105500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.023488                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.078896                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.029433                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.551439                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.551439                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.037418                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.037418                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.421225                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.421225                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.023300                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.084289                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.037418                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.455149                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.119294                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.023300                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.084289                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.037418                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.455149                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.552707                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.552707                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.037198                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.037198                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.420854                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.420854                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.023488                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.078896                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.037198                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.454998                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.119351                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.023488                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.078896                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.037198                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.454998                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.140483                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16536.633663                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37807.650847                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37807.650847                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15389.853763                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15389.853763                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15022.489518                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15022.489518                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.140779                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18685.467480                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37862.608886                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37862.608886                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.782271                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15343.782271                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.003249                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.003249                       # average SCUpgradeReq mshr miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33746.242913                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33746.242913                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29370.675082                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29370.675082                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17415.614768                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17415.614768                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29370.675082                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22570.243538                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24182.610894                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29370.675082                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22570.243538                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37807.650847                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26237.654282                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87705.357143                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165877.423775                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165282.110560                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87705.357143                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91278.550692                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91263.525436                       # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests      2396557                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1207646                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        20286                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       118595                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       110586                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         8009                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq         53656                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      1217922                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        11928                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        11928                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       153983                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      1025852                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict        34704                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        31184                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        74094                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41981                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        86038                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           20                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           29                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        69927                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        67092                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       948538                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       295426                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq           64                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2845326                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       911410                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         8268                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        64898                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          3829902                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    121387264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     30723028                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        13952                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       122916                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         152247160                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     369470                       # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic              5053360                       # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples      1597738                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.098519                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.314386                       # Request fanout histogram
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36706.222761                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36706.222761                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32360.255723                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32360.255723                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19121.057698                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19121.057698                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32360.255723                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24652.663722                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26475.848939                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32360.255723                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24652.663722                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37862.608886                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28209.001949                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91379.464286                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164866.601955                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164300.343997                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91379.464286                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90831.238779                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90833.574227                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests      2407842                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1213344                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        20026                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       118526                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       110630                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         7896                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq         52421                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      1221670                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        11756                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        11756                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       155519                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      1031415                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        35412                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        31701                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        73485                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42116                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        86132                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           18                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           32                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        69767                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        67286                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       952438                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       295145                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq           55                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2857026                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       915642                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         8405                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        62913                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          3843986                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    121886464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     30908928                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        14348                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       119380                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         152929120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     368607                       # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic              5126040                       # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples      1602092                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.097939                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.313375                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0           1448339     90.65%     90.65% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            141390      8.85%     99.50% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              8009      0.50%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0           1453081     90.70%     90.70% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            141115      8.81%     99.51% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              7896      0.49%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1597738                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    2375408982                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1602092                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    2385821492                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     79990687                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     79306117                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   1423068313                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    409788212                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   1428899351                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy    412338887                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      4783493                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      4820495                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     34178481                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     33080974                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                31003                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31003                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                31015                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31015                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
@@ -2295,9 +2296,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       107916                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180850                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180874                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
@@ -2318,34 +2319,34 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       162796                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2483972                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             48331500                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2484068                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             48391001                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               110000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               111500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               333000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               334500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                28000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                13500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                88500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                91000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               620000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               622500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               20000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               47000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
@@ -2353,58 +2354,58 @@ system.iobus.reqLayer19.occupancy                2500                       # La
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6355500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6378000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            39060500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            38950500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187669353                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187782564                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36758000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                36449                       # number of replacements
-system.iocache.tags.tagsinuse               14.473969                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements                36461                       # number of replacements
+system.iocache.tags.tagsinuse               14.472132                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36465                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36477                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         271637878000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.473969                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.904623                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.904623                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         272036828000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.472132                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.904508                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.904508                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
-system.iocache.tags.data_accesses              328203                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
+system.iocache.tags.data_accesses              328311                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide        36467                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             36467                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide        36467                       # number of overall misses
-system.iocache.overall_misses::total            36467                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     31680877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     31680877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4302277476                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4302277476                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   4333958353                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4333958353                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   4333958353                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4333958353                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide        36479                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36479                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36479                       # number of overall misses
+system.iocache.overall_misses::total            36479                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     33219876                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     33219876                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4376166688                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4376166688                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4409386564                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4409386564                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4409386564                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4409386564                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide        36467                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           36467                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide        36467                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          36467                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36479                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36479                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36479                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36479                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -2413,38 +2414,38 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 130373.979424                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 130373.979424                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118768.702407                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118768.702407                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 118846.034853                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 118846.034853                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 118846.034853                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 118846.034853                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            25                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 130274.023529                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 130274.023529                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120808.488516                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 120808.488516                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 120874.655665                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 120874.655665                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 120874.655665                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 120874.655665                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             3                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    6                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     4.166667                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            3                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36206                       # number of writebacks
 system.iocache.writebacks::total                36206                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide        36467                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        36467                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide        36467                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        36467                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19530877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19530877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2488777487                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2488777487                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   2508308364                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2508308364                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   2508308364                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2508308364                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide        36479                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36479                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36479                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36479                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     20469876                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     20469876                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2562591001                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2562591001                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2583060877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2583060877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2583060877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2583060877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2453,592 +2454,591 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80373.979424                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 80373.979424                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68705.208895                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68705.208895                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68782.964434                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68782.964434                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68782.964434                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68782.964434                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   143192                       # number of replacements
-system.l2c.tags.tagsinuse                65154.235518                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     608270                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   208652                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.915237                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              94157771000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks    6329.103935                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    78.467327                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.034862                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     8953.646572                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6857.938638                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35058.708510                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    16.060603                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2144.069552                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3463.562714                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2252.642806                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.096574                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001197                       # Average percentage of cache occupancy
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80274.023529                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 80274.023529                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70742.905284                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70742.905284                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 70809.530881                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70809.530881                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 70809.530881                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70809.530881                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                   145308                       # number of replacements
+system.l2c.tags.tagsinuse                65153.014694                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     608197                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   210799                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.885199                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle              94570968000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks    6725.818981                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    88.835717                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.039308                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     8741.022578                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6775.934473                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34864.204134                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    12.618119                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2235.319135                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3466.513349                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2242.708901                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.102628                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001356                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.136622                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.104644                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.534953                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000245                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.032716                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.052850                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.034373                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.994175                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        31682                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023           69                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        33709                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          141                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         4562                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        26979                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu0.inst       0.133377                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.103393                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.531986                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000193                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.034108                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.052895                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.034221                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.994156                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        31590                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023           60                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        33841                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          126                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         4772                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        26692                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           67                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2           98                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         1943                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        31665                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.483429                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.001053                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.514359                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  6826219                       # Number of tag accesses
-system.l2c.tags.data_accesses                 6826219                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks       268100                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          268100                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data           43283                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            5296                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               48579                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          2814                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          2244                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              5058                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             4306                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             1499                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 5805                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          471                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker          104                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        69073                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        63736                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        47705                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker          122                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           31                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst        32133                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        13324                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5520                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           232219                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           471                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker           104                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               69073                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               68042                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        47705                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker           122                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            31                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               32133                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               14823                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher         5520                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  238024                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          471                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker          104                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              69073                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              68042                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher        47705                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker          122                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           31                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              32133                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              14823                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher         5520                       # number of overall hits
-system.l2c.overall_hits::total                 238024                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data           486                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           293                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total               779                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data           96                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          129                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             225                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          11283                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           8662                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              19945                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          140                       # number of ReadSharedReq misses
+system.l2c.tags.age_task_id_blocks_1023::4           58                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          103                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         1899                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        31836                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.482025                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000916                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.516373                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  6845829                       # Number of tag accesses
+system.l2c.tags.data_accesses                 6845829                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks       269041                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          269041                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data           43018                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            5569                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               48587                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          2756                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          2348                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total              5104                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data             4245                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data             1488                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                 5733                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          501                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker           88                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst        68822                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data        63059                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        47426                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker          132                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker           22                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst        31931                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data        13672                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5861                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           231514                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker           501                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker            88                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst               68822                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data               67304                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher        47426                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker           132                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker            22                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst               31931                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               15160                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher         5861                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  237247                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker          501                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker           88                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst              68822                       # number of overall hits
+system.l2c.overall_hits::cpu0.data              67304                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher        47426                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker          132                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker           22                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst              31931                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              15160                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher         5861                       # number of overall hits
+system.l2c.overall_hits::total                 237247                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data           567                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           233                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total               800                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data           71                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data           57                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             128                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          11330                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           8671                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              20001                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          149                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu0.itb.walker            1                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        22779                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         9863                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       131424                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           22                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst         3359                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         1662                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6848                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         176098                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker          140                       # number of demand (read+write) misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        22928                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data        10009                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       132762                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           16                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst         3498                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data         1729                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6519                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         177611                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker          149                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             22779                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             21146                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       131424                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           22                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              3359                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             10324                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher         6848                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                196043                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker          140                       # number of overall misses
+system.l2c.demand_misses::cpu0.inst             22928                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             21339                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       132762                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker           16                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              3498                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             10400                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher         6519                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                197612                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker          149                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            22779                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            21146                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       131424                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           22                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             3359                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            10324                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher         6848                       # number of overall misses
-system.l2c.overall_misses::total               196043                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data      9317500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data       600500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      9918000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       570500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       622000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      1192500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   1120360000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    722454500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1842814500                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     12725000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker        84000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1853877000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data    886562000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  13504616525                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      2056500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst    279082000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    150096500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    863540144                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  17552639669                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker     12725000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker        84000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1853877000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   2006922000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13504616525                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker      2056500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    279082000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    872551000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    863540144                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     19395454169                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker     12725000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker        84000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1853877000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   2006922000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13504616525                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker      2056500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    279082000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    872551000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    863540144                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    19395454169                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       268100                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       268100                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        43769                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5589                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           49358                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         2910                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         2373                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          5283                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data        15589                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        10161                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            25750                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          611                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker          105                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst        91852                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data        73599                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       179129                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker          144                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           31                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst        35492                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data        14986                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        12368                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       408317                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker          611                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker          105                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           91852                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           89188                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       179129                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker          144                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           31                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           35492                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           25147                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher        12368                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              434067                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker          611                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker          105                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          91852                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          89188                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       179129                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker          144                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           31                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          35492                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          25147                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher        12368                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             434067                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.011104                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.052424                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.015783                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.032990                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.054362                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.042589                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.723780                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.852475                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.774563                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.229133                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.009524                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.247997                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.134010                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.733684                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.152778                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.094641                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.110904                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.553687                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.431278                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.229133                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.009524                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.247997                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.237095                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.733684                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.152778                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.094641                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.410546                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.553687                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.451642                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.229133                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.009524                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.247997                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.237095                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.733684                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.152778                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.094641                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.410546                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.553687                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.451642                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19171.810700                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2049.488055                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 12731.707317                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5942.708333                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4821.705426                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total         5300                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99296.286449                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83405.045024                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 92394.810730                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90892.857143                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        84000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81385.354932                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89887.660955                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 102756.091163                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 93477.272727                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83084.846681                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90310.770156                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 126101.072430                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 99675.406132                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90892.857143                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        84000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 81385.354932                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 94907.878559                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 102756.091163                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93477.272727                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 83084.846681                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 84516.757071                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 126101.072430                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 98934.693761                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90892.857143                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        84000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 81385.354932                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 94907.878559                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 102756.091163                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93477.272727                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 83084.846681                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 84516.757071                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 126101.072430                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 98934.693761                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                94                       # number of cycles access was blocked
+system.l2c.overall_misses::cpu0.inst            22928                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            21339                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       132762                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker           16                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             3498                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            10400                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher         6519                       # number of overall misses
+system.l2c.overall_misses::total               197612                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data      7996500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data       709500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      8706000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       618000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data        99500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       717500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   1582862000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    826941000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   2409803000                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     24166000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker        90000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2324658500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data   1196554000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  15972256455                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      3966500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst    386401500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data    279812500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    875704589                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  21063610044                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker     24166000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker        90000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   2324658500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   2779416000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  15972256455                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker      3966500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    386401500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   1106753500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    875704589                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     23473413044                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker     24166000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker        90000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   2324658500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   2779416000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  15972256455                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker      3966500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    386401500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1106753500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    875704589                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    23473413044                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks       269041                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       269041                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        43585                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5802                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           49387                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         2827                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         2405                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          5232                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15575                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        10159                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            25734                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          650                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           89                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        91750                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        73068                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       180188                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker          148                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           22                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        35429                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        15401                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        12380                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       409125                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          650                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           89                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           91750                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           88643                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       180188                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker          148                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           22                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           35429                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           25560                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher        12380                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              434859                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          650                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           89                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          91750                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          88643                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       180188                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker          148                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           22                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          35429                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          25560                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        12380                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             434859                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.013009                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.040159                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.016199                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.025115                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.023701                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.024465                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.727448                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.853529                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.777221                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.229231                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.011236                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.249896                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.136982                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.736797                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.108108                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.098733                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.112265                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.526575                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.434124                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.229231                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.011236                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.249896                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.240730                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.736797                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.108108                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.098733                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.406886                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.526575                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.454428                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.229231                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.011236                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.249896                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.240730                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.736797                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.108108                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.098733                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.406886                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.526575                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.454428                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14103.174603                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3045.064378                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 10882.500000                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  8704.225352                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1745.614035                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  5605.468750                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139705.383936                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 95368.584938                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 120484.125794                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 162187.919463                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        90000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 101389.501919                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 119547.806974                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 120307.440796                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 247906.250000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110463.550600                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 161834.875651                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134331.122718                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 118594.062552                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 162187.919463                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker        90000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 101389.501919                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 130250.527204                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 120307.440796                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 247906.250000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 110463.550600                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 106418.605769                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134331.122718                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 118785.362448                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 162187.919463                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        90000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 101389.501919                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 130250.527204                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 120307.440796                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 247906.250000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 110463.550600                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 106418.605769                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134331.122718                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 118785.362448                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        4                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     23.500000                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks              104558                       # number of writebacks
-system.l2c.writebacks::total                   104558                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            1                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            2                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            3                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  3                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 3                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         4654                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         4654                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data          486                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          293                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total          779                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           96                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          129                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total          225                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        11283                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         8662                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         19945                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          140                       # number of ReadSharedReq MSHR misses
+system.l2c.writebacks::writebacks              105581                       # number of writebacks
+system.l2c.writebacks::total                   105581                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            3                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            4                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            7                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  7                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 7                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         4797                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         4797                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data          567                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          233                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total          800                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           71                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           57                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total          128                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        11330                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         8671                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         20001                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          149                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        22778                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9863                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       131424                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           22                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         3357                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1662                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6848                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       176095                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker          140                       # number of demand (read+write) MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        22925                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data        10009                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       132762                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           16                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         3494                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1729                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6519                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       177604                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker          149                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        22778                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        21146                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       131424                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           22                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         3357                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        10324                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6848                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           196040                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker          140                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        22925                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        21339                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       132762                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker           16                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         3494                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        10400                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6519                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           197605                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker          149                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        22778                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        21146                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       131424                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           22                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         3357                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        10324                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6848                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          196040                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3448                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20384                       # number of ReadReq MSHR uncacheable
+system.l2c.overall_mshr_misses::cpu0.inst        22925                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        21339                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       132762                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker           16                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         3494                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        10400                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6519                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          197605                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3277                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20577                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14592                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        38536                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19085                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11928                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        31013                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3448                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        39469                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14420                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        38386                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19270                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11756                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        31026                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3277                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        39847                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26520                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        69549                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     10685000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      6544500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     17229500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      2535500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2989500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total      5525000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1007530000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    635834500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1643364500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     11325000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker        74000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1626074003                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    787932000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  12190373531                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      1836500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    245369000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    133475003                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    795059645                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  15791518682                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     11325000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        74000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1626074003                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   1795462000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  12190373531                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1836500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    245369000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    769309503                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    795059645                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  17434883182                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     11325000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        74000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1626074003                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   1795462000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  12190373531                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1836500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    245369000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    769309503                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    795059645                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  17434883182                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    219420500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4026148500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7471000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2158248500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6411288500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    219420500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4026148500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7471000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2158248500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   6411288500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26176                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        69412                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     13077000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4990500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     18067500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1886000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      1373500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total      3259500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1469562000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    740230501                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   2209792501                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     22676000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker        80000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   2094658500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1096464000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14644634459                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      3806500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    351259500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    262522001                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    810514090                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  19286615050                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     22676000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        80000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   2094658500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   2566026000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  14644634459                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      3806500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    351259500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1002752502                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    810514090                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  21496407551                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     22676000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        80000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   2094658500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   2566026000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14644634459                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      3806500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    351259500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1002752502                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    810514090                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  21496407551                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    228848500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4071417000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7882500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2118238500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6426386500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    228848500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4071417000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7882500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2118238500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   6426386500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.011104                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.052424                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.015783                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.032990                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.054362                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.042589                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.723780                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.852475                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.774563                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.229133                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.009524                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.247986                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.134010                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.733684                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.152778                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.094585                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.110904                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.553687                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.431270                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.229133                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.009524                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.247986                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.237095                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.733684                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.152778                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.094585                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.410546                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.553687                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.451635                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.229133                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.009524                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.247986                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.237095                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.733684                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.152778                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.094585                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.410546                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.553687                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.451635                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21985.596708                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22336.177474                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22117.458280                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26411.458333                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23174.418605                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24555.555556                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89296.286449                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73405.045024                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 82394.810730                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80892.857143                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71387.918298                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79887.660955                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92756.068382                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 83477.272727                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73091.748585                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80309.869434                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 89676.133235                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80892.857143                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71387.918298                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84907.878559                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92756.068382                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83477.272727                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73091.748585                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74516.612069                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 88935.335554                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80892.857143                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71387.918298                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84907.878559                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92756.068382                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83477.272727                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73091.748585                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74516.612069                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 88935.335554                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197515.134419                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66705.357143                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147906.284265                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166371.405958                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102007.866934                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66705.357143                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81381.919306                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 92183.762527                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        516977                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       290556                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          569                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.013009                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.040159                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.016199                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.025115                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.023701                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.024465                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.727448                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.853529                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.777221                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.229231                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.011236                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.249864                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.136982                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.736797                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.108108                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.098620                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.112265                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.526575                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.434107                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.229231                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011236                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.249864                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.240730                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.736797                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.108108                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.098620                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.406886                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.526575                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.454412                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.229231                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011236                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.249864                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.240730                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.736797                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.108108                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.098620                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.406886                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.526575                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.454412                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23063.492063                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21418.454936                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22584.375000                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26563.380282                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24096.491228                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25464.843750                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129705.383936                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 85368.527390                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 110484.100845                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        80000                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91370.054526                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 109547.806974                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100532.198054                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 151834.587045                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108593.359665                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        80000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91370.054526                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 120250.527204                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100532.198054                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96418.509808                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 108784.734956                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        80000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91370.054526                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 120250.527204                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100532.198054                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96418.509808                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 108784.734956                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197862.516402                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70379.464286                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146895.873786                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167414.851769                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102176.249153                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70379.464286                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80922.925581                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 92583.220481                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests        519453                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       291586                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          583                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               38536                       # Transaction distribution
-system.membus.trans_dist::ReadResp             214874                       # Transaction distribution
-system.membus.trans_dist::WriteReq              31013                       # Transaction distribution
-system.membus.trans_dist::WriteResp             31013                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       140764                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            19586                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            64644                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          38971                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               38386                       # Transaction distribution
+system.membus.trans_dist::ReadResp             216245                       # Transaction distribution
+system.membus.trans_dist::WriteReq              31026                       # Transaction distribution
+system.membus.trans_dist::WriteResp             31026                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       141787                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            20009                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            64008                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          38952                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             40377                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            19925                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        176338                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             40468                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19978                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        177859                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14120                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       656690                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       778768                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72931                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72931                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 851699                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14184                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       660292                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       782434                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72955                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72955                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 855389                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19461788                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     19654168                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28368                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19616228                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19808736                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21972312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           123613                       # Total snoops (count)
-system.membus.snoopTraffic                      36288                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            426105                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.011500                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.106618                       # Request fanout histogram
+system.membus.pkt_size::total                22126880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           123082                       # Total snoops (count)
+system.membus.snoopTraffic                      37120                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            426925                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.011573                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.106956                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  421205     98.85%     98.85% # Request fanout histogram
-system.membus.snoop_fanout::1                    4900      1.15%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  421984     98.84%     98.84% # Request fanout histogram
+system.membus.snoop_fanout::1                    4941      1.16%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              426105                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            95080500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              426925                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            95052999                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               22828                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               23328                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            12459499                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            12480499                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1008366249                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1015492813                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1144784655                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1151697269                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1337127                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1408128                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -3070,77 +3070,77 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      1122676                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       592030                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       210689                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          28909                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        27742                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops         1167                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq              38539                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            569123                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             31013                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            31013                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       372658                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          153621                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          113203                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         44029                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         157232                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           29                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           29                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            51954                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           51954                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       530586                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq         4329                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1344687                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       405982                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1750669                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     38363344                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7028808                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               45392152                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          398871                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  16195724                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples           956902                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.408687                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.494066                       # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests      1122951                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       592347                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       209143                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          29689                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        28433                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops         1256                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq              38389                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            568851                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             31026                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            31026                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       374622                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          155080                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          112572                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         44056                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         156628                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           32                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           32                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            51647                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           51647                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       530464                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq         4356                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1342563                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       408877                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1751440                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     38341228                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7151796                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               45493024                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          399228                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                  16183244                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples           957878                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.406657                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.493872                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 566996     59.25%     59.25% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 388739     40.62%     99.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                   1167      0.12%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 569606     59.47%     59.47% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 387016     40.40%     99.87% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                   1256      0.13%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             956902                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          952868265                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             957878                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          953761642                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           342123                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           360622                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         724877328                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         722683237                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         285789223                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         286574903                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
index f97cdd248..6291ea543 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
@@ -36,7 +36,7 @@ load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -208,7 +208,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -688,7 +688,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -748,7 +748,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -820,7 +820,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -937,7 +937,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -982,7 +982,7 @@ size=1024
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -994,7 +994,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -1026,29 +1026,36 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -1068,6 +1075,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -1077,7 +1085,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1099,9 +1107,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -1454,7 +1462,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -1771,6 +1779,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1778,7 +1787,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -2009,6 +2018,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -2016,7 +2026,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
index 6bd9bc23a..f91395bf5 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:38:21
-gem5 executing on e108600-lin, pid 23070
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:53:08
+gem5 executing on e108600-lin, pid 17485
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor
 
 Global frequency set at 1000000000000 ticks per second
@@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2858997339500 because m5_exit instruction encountered
+Exiting @ tick 2854925996500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index 4972770ec..f3f991d90 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.853344                       # Number of seconds simulated
-sim_ticks                                2853343899500                       # Number of ticks simulated
-final_tick                               2853343899500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.854926                       # Number of seconds simulated
+sim_ticks                                2854925996500                       # Number of ticks simulated
+final_tick                               2854925996500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 139312                       # Simulator instruction rate (inst/s)
-host_op_rate                                   168444                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3544495637                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 589148                       # Number of bytes of host memory used
-host_seconds                                   805.01                       # Real time elapsed on the host
-sim_insts                                   112146750                       # Number of instructions simulated
-sim_ops                                     135598813                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 115917                       # Simulator instruction rate (inst/s)
+host_op_rate                                   140154                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2954234125                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 584856                       # Number of bytes of host memory used
+host_seconds                                   966.38                       # Real time elapsed on the host
+sim_insts                                   112020669                       # Number of instructions simulated
+sim_ops                                     135443008                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker         7680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1675712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9177004                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker         7040                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1667200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9190572                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10861420                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1675712                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1675712                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7976832                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10865900                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1667200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1667200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7979712                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7994356                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker          120                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              26183                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             143912                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           7997236                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker          110                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              26050                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             144124                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170231                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          124638                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170301                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129019                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           2692                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               587280                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3216228                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               129064                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           2466                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             45                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               583973                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3219198                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3806558                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          587280                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             587280                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2795608                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6142                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2801750                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2795608                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          2692                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              587280                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3222369                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 3806018                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          583973                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             583973                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2795068                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6138                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2801206                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2795068                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          2466                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            45                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              583973                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3225336                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6608308                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170231                       # Number of read requests accepted
-system.physmem.writeReqs                       129019                       # Number of write requests accepted
-system.physmem.readBursts                      170231                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129019                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10886144                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8640                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8006976                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10861420                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7994356                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      135                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6607224                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170301                       # Number of read requests accepted
+system.physmem.writeReqs                       129064                       # Number of write requests accepted
+system.physmem.readBursts                      170301                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     129064                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10890496                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8768                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8010048                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10865900                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7997236                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      137                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10508                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10518                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10699                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10590                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13367                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10649                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10947                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11320                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10289                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10353                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10214                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9210                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10497                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11112                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10041                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9782                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7781                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7920                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8383                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8149                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7457                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7755                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7974                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8419                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7882                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7909                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7627                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7117                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7926                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8274                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7391                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7145                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10638                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10529                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10665                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10242                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13390                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10196                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10392                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10920                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10199                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10416                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10277                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9652                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10777                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11476                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10256                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10139                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7926                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7916                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8341                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7830                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7635                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7427                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7524                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8090                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7812                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7846                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7622                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7450                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8154                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8593                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7575                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7416                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2853343449000                       # Total gap between requests
+system.physmem.numWrRetry                          56                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2854925546000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  169674                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  169744                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 124638                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    162184                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      7619                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       281                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 124683                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    160221                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      9636                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       294                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
@@ -160,120 +160,124 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6085                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6753                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6440                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6861                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7833                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7817                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8977                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7605                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7382                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      340                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      278                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       11                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        60538                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      312.085896                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     184.679507                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.366687                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22012     36.36%     36.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14640     24.18%     60.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6552     10.82%     71.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3435      5.67%     77.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2639      4.36%     81.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1745      2.88%     84.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1057      1.75%     86.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1062      1.75%     87.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7396     12.22%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          60538                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6241                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.253805                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      580.495916                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6239     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1833                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2641                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5947                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6539                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6635                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7561                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7557                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8594                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7531                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7083                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6851                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6591                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      453                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      463                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      366                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      255                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      256                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      209                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      231                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      138                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        60414                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      312.849340                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     185.889118                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     328.883375                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          21657     35.85%     35.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14616     24.19%     60.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6864     11.36%     71.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3516      5.82%     77.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2636      4.36%     81.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1611      2.67%     84.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1067      1.77%     86.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          953      1.58%     87.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7494     12.40%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          60414                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6196                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.463041                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      582.417033                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6195     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6241                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6241                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.046307                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.379346                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.281323                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5473     87.69%     87.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              55      0.88%     88.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              66      1.06%     89.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              37      0.59%     90.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             284      4.55%     94.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              48      0.77%     95.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              17      0.27%     95.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              11      0.18%     95.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               9      0.14%     96.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               6      0.10%     96.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               4      0.06%     96.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              13      0.21%     96.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             157      2.52%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.06%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.05%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               5      0.08%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               5      0.08%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.03%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               4      0.06%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             8      0.13%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            15      0.24%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.03%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             3      0.05%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6241                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1691091750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4880391750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    850480000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9941.98                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6196                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6196                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.199645                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.300177                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       15.412164                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5485     88.52%     88.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              67      1.08%     89.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              43      0.69%     90.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              35      0.56%     90.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             272      4.39%     95.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              29      0.47%     95.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               8      0.13%     95.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              11      0.18%     96.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              11      0.18%     96.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               3      0.05%     96.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               4      0.06%     96.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               7      0.11%     96.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             138      2.23%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               3      0.05%     98.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               2      0.03%     98.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               7      0.11%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.10%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.02%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            13      0.21%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             2      0.03%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.05%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            12      0.19%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             6      0.10%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             4      0.06%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.05%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.03%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.02%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             3      0.05%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.02%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.02%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             4      0.06%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             4      0.06%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6196                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4595967000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                7786542000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    850820000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27009.04                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28691.98                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.82                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  45759.04                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.81                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.81                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.80                       # Average system write bandwidth in MiByte/s
@@ -282,42 +286,52 @@ system.physmem.busUtil                           0.05                       # Da
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.93                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     140142                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94524                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.39                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.54                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9534982.29                       # Average gap between requests
-system.physmem.pageHitRate                      79.49                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  235894680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  128712375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 691064400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                413670240                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           186366389040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83561921055                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1638705050250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1910102702040                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.426569                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2725994839000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95279340000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32067469750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  221772600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  121006875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 635676600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                397036080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           186366389040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82367679285                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1639752630750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1909862191230                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.342278                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2727746913750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95279340000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30317548250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.physmem.avgWrQLen                        23.01                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     140583                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     94323                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.62                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.35                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9536604.30                       # Average gap between requests
+system.physmem.pageHitRate                      79.54                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  218405460                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  116085255                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 620980080                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                327236580                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           6016710960.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             4587085260                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              376629120                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       12457025670                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        8414413920                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       671932680540                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             705069857835                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              246.966071                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           2843548486750                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      708499000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2558586000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   2794649429000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  21912527500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      7778804250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  27318150750                       # Time in different power states
+system.physmem_1.actEnergy                  212957640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  113185875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 593990880                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                326082960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           6113824080.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             4455367380                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              374460480                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       12365716800                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        8661645120                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       671979444945                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             705199696980                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              247.011550                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           2844173514000                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      705782750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2600572000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   2794499397250                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  22556418250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      7446062750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  27117763500                       # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          512                       # Number of instructions bytes read from this memory
@@ -330,30 +344,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst          179
 system.realview.nvmem.bw_inst_read::total          179                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst          179                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total             179                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                31062999                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16869066                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           2486744                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18728785                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                10415318                       # Number of BTB hits
+system.cpu.branchPred.lookups                31074836                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16867509                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           2481345                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18655029                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                10408802                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             55.611285                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7833584                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1520957                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         3075291                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            2886933                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses           188358                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       109527                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             55.796225                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7856601                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1514233                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         3068747                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            2872226                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses           196521                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       109392                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -383,59 +397,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                     68003                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                68003                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        44606                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23397                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples        68003                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0           68003    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        68003                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples         7897                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 10035.266557                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  8419.099443                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  6813.200210                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383         7021     88.91%     88.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767          869     11.00%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::81920-98303            5      0.06%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::147456-163839            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-212991            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total         7897                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples    271390000                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0       271390000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total    271390000                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6503     82.35%     82.35% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1394     17.65%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7897                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        68003                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                     68070                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                68070                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        44787                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23283                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples        68070                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0           68070    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        68070                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples         7877                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 10134.378571                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  8445.879455                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  9567.630419                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535         7869     99.90%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071            6      0.08%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total         7877                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples    276581000                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0       276581000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total    276581000                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6513     82.68%     82.68% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1364     17.32%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7877                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        68070                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        68003                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7897                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        68070                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7877                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7897                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        75900                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7877                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        75947                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24771188                       # DTB read hits
-system.cpu.dtb.read_misses                      61134                       # DTB read misses
-system.cpu.dtb.write_hits                    19449290                       # DTB write hits
-system.cpu.dtb.write_misses                      6869                       # DTB write misses
+system.cpu.dtb.read_hits                     24743648                       # DTB read hits
+system.cpu.dtb.read_misses                      61017                       # DTB read misses
+system.cpu.dtb.write_hits                    19435570                       # DTB write hits
+system.cpu.dtb.write_misses                      7053                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4279                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1418                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   1775                       # Number of TLB faults due to prefetch
+system.cpu.dtb.align_faults                      1461                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   1806                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       770                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24832322                       # DTB read accesses
-system.cpu.dtb.write_accesses                19456159                       # DTB write accesses
+system.cpu.dtb.perms_faults                       755                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 24804665                       # DTB read accesses
+system.cpu.dtb.write_accesses                19442623                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44220478                       # DTB hits
-system.cpu.dtb.misses                           68003                       # DTB misses
-system.cpu.dtb.accesses                      44288481                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                          44179218                       # DTB hits
+system.cpu.dtb.misses                           68070                       # DTB misses
+system.cpu.dtb.accesses                      44247288                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -465,39 +478,39 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                      5856                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                 5856                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1          325                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         5531                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples         5856                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0            5856    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total         5856                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3193                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 10411.838396                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  8598.635311                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  6896.589649                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191         1843     57.72%     57.72% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383          807     25.27%     82.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575          535     16.76%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::24576-32767            7      0.22%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3193                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples    270980500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       270980500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total    270980500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2883     90.29%     90.29% # Table walker page sizes translated
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                      5855                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                 5855                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1          322                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         5533                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples         5855                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0            5855    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total         5855                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3194                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 10424.389480                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  8603.860466                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  6932.586443                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         1846     57.80%     57.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383          798     24.98%     82.78% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          544     17.03%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::24576-32767            5      0.16%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::90112-98303            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         3194                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples    276141500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       276141500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total    276141500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2884     90.29%     90.29% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::1M           310      9.71%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3193                       # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3194                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5856                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total         5856                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5855                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total         5855                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3193                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3193                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3194                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3194                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin::total         9049                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     57483193                       # ITB inst hits
-system.cpu.itb.inst_misses                       5856                       # ITB inst misses
+system.cpu.itb.inst_hits                     57481594                       # ITB inst hits
+system.cpu.itb.inst_misses                       5855                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -506,45 +519,45 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2912                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2915                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      8279                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      8308                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 57489049                       # ITB inst accesses
-system.cpu.itb.hits                          57483193                       # DTB hits
-system.cpu.itb.misses                            5856                       # DTB misses
-system.cpu.itb.accesses                      57489049                       # DTB accesses
+system.cpu.itb.inst_accesses                 57487449                       # ITB inst accesses
+system.cpu.itb.hits                          57481594                       # DTB hits
+system.cpu.itb.misses                            5855                       # DTB misses
+system.cpu.itb.accesses                      57487449                       # DTB accesses
 system.cpu.numPwrStateTransitions                6066                       # Number of power state transitions
 system.cpu.pwrStateClkGateDist::samples          3033                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     888351102.639301                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    17445509399.919735                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows         2969     97.89%     97.89% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10           58      1.91%     99.80% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     887934091.386746                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    17437787888.707882                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows         2968     97.86%     97.86% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10           59      1.95%     99.80% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.03%     99.87% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.03%     99.90% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 499967553028                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 499966196768                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::total            3033                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    158975005195                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 2694368894305                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        317952965                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    161821897324                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2693104099176                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        323646748                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   112146750                       # Number of instructions committed
-system.cpu.committedOps                     135598813                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       7821624                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts                   112020669                       # Number of instructions committed
+system.cpu.committedOps                     135443008                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       7814596                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                      3033                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   5388799101                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.835151                       # CPI: cycles per instruction
-system.cpu.ipc                               0.352715                       # IPC: instructions per cycle
+system.cpu.quiesceCycles                   5386269471                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.889170                       # CPI: cycles per instruction
+system.cpu.ipc                               0.346120                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                2337      0.00%      0.00% # Class of committed instruction
-system.cpu.op_class_0::IntAlu                90918529     67.05%     67.05% # Class of committed instruction
-system.cpu.op_class_0::IntMult                 113133      0.08%     67.13% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                90804901     67.04%     67.04% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 113201      0.08%     67.13% # Class of committed instruction
 system.cpu.op_class_0::IntDiv                       0      0.00%     67.13% # Class of committed instruction
 system.cpu.op_class_0::FloatAdd                     0      0.00%     67.13% # Class of committed instruction
 system.cpu.op_class_0::FloatCmp                     0      0.00%     67.13% # Class of committed instruction
@@ -568,663 +581,663 @@ system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     67.13% # Cl
 system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     67.13% # Class of committed instruction
 system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     67.13% # Class of committed instruction
 system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     67.13% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc             8487      0.01%     67.14% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.14% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.14% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.14% # Class of committed instruction
-system.cpu.op_class_0::MemRead               24279497     17.91%     85.05% # Class of committed instruction
-system.cpu.op_class_0::MemWrite              20276830     14.95%    100.00% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc             8481      0.01%     67.13% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.13% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.13% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.13% # Class of committed instruction
+system.cpu.op_class_0::MemRead               24250620     17.90%     85.04% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              20263468     14.96%    100.00% # Class of committed instruction
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::total                135598813                       # Class of committed instruction
+system.cpu.op_class_0::total                135443008                       # Class of committed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
-system.cpu.tickCycles                       217828985                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       100123980                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements            845168                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.946266                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42678256                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            845680                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             50.466200                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         322165500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.946266                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999895                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999895                       # Average percentage of cache occupancy
+system.cpu.tickCycles                       217947056                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       105699692                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements            844723                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.945160                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42637807                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            845235                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             50.444914                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         330588500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.945160                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999893                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999893                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          354                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          360                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         176368054                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        176368054                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     23126363                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23126363                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18288488                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18288488                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       357151                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        357151                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       443374                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       443374                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       459996                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       459996                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41414851                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41414851                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41772002                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41772002                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       466466                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        466466                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       547177                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       547177                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       169147                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       169147                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22423                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22423                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         176206878                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        176206878                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     23101260                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23101260                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18273431                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18273431                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       356861                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        356861                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443340                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443340                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460050                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460050                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41374691                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41374691                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41731552                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41731552                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       465078                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        465078                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       548776                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       548776                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       169103                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       169103                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22503                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22503                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      1013643                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1013643                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1182790                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1182790                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   6859105500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   6859105500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  23368526480                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  23368526480                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    290513500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    290513500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       169000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       169000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  30227631980                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  30227631980                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  30227631980                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  30227631980                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23592829                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23592829                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     18835665                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     18835665                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       526298                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       526298                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465797                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       465797                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       459998                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       459998                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42428494                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42428494                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42954792                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42954792                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.019772                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.019772                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029050                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.029050                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.321390                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.321390                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048139                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048139                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data      1013854                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1013854                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1182957                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1182957                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   7334484000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   7334484000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  26875060480                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  26875060480                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    306737000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    306737000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       171000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       171000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  34209544480                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34209544480                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  34209544480                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34209544480                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23566338                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23566338                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     18822207                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     18822207                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       525964                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       525964                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465843                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       465843                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460052                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460052                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     42388545                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42388545                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42914509                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42914509                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.019735                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.019735                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029156                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.029156                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.321511                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.321511                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048306                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048306                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023891                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023891                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.027536                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.027536                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14704.406109                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14704.406109                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42707.435583                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 42707.435583                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12956.049592                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12956.049592                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        84500                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        84500                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29820.786983                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29820.786983                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25556.211990                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25556.211990                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          210                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.023918                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.023918                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.027565                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.027565                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15770.438507                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15770.438507                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48972.732918                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48972.732918                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13630.938097                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13630.938097                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        85500                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        85500                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33742.081680                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33742.081680                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28918.671160                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28918.671160                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          224                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                21                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           10                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.666667                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       700399                       # number of writebacks
-system.cpu.dcache.writebacks::total            700399                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        45619                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        45619                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       248851                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       248851                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14095                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        14095                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       294470                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       294470                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       294470                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       294470                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       420847                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       420847                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298326                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       298326                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121014                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       121014                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8328                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8328                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       702249                       # number of writebacks
+system.cpu.dcache.writebacks::total            702249                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        45641                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        45641                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249535                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       249535                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14278                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        14278                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       295176                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       295176                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       295176                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       295176                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       419437                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       419437                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299241                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       299241                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121149                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       121149                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8225                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8225                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       719173                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       719173                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       840187                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       840187                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        31128                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6004353500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6004353500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12472700000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12472700000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1605906500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1605906500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    111255000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    111255000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       167000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       167000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18477053500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  18477053500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20082960000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  20082960000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6301797000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6301797000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6301797000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6301797000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017838                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017838                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015838                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015838                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.229934                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.229934                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017879                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017879                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data       718678                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       718678                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       839827                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       839827                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        31130                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6447841000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6447841000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14303453000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  14303453000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1653166500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1653166500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    121747500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    121747500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       169000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       169000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  20751294000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  20751294000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22404460500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  22404460500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6305636000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6305636000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6305636000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6305636000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017798                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017798                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015898                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015898                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230337                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230337                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017656                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017656                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016950                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016950                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019560                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019560                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14267.307359                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14267.307359                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41808.960667                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41808.960667                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.419125                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.419125                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13359.149856                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13359.149856                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        83500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        83500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25692.084519                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25692.084519                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23902.964459                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23902.964459                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202447.860447                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202447.860447                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107335.882543                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107335.882543                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           2889133                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.392140                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            54584955                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           2889645                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             18.889848                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       15688442500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.392140                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998813                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998813                       # Average percentage of cache occupancy
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016955                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016955                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019570                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019570                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15372.608997                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15372.608997                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47799.108411                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47799.108411                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13645.729639                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13645.729639                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14802.127660                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14802.127660                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        84500                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        84500                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28874.258013                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28874.258013                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26677.471074                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26677.471074                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202558.175394                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202558.175394                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107395.782948                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107395.782948                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements           2891615                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.370867                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            54580851                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           2892127                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.872218                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       16116545500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.370867                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998771                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998771                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          193                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60364268                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60364268                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     54584955                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        54584955                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      54584955                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         54584955                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     54584955                       # number of overall hits
-system.cpu.icache.overall_hits::total        54584955                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      2889657                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       2889657                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      2889657                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        2889657                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      2889657                       # number of overall misses
-system.cpu.icache.overall_misses::total       2889657                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  39245614500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  39245614500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  39245614500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  39245614500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  39245614500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  39245614500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     57474612                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     57474612                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     57474612                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     57474612                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     57474612                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     57474612                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050277                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.050277                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.050277                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.050277                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.050277                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.050277                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13581.409316                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13581.409316                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13581.409316                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13581.409316                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13581.409316                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13581.409316                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          60365128                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         60365128                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     54580851                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        54580851                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      54580851                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         54580851                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     54580851                       # number of overall hits
+system.cpu.icache.overall_hits::total        54580851                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      2892139                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       2892139                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      2892139                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        2892139                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      2892139                       # number of overall misses
+system.cpu.icache.overall_misses::total       2892139                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  39804335500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  39804335500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  39804335500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  39804335500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  39804335500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  39804335500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     57472990                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     57472990                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     57472990                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     57472990                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     57472990                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     57472990                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050322                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.050322                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.050322                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.050322                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.050322                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.050322                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13762.939990                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13762.939990                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13762.939990                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13762.939990                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13762.939990                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13762.939990                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      2889133                       # number of writebacks
-system.cpu.icache.writebacks::total           2889133                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2889657                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      2889657                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      2889657                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      2889657                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      2889657                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      2889657                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3267                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total         3267                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3267                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total         3267                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36355958500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  36355958500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36355958500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  36355958500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36355958500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  36355958500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    258265000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    258265000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    258265000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    258265000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050277                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050277                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050277                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.050277                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050277                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.050277                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12581.409662                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12581.409662                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12581.409662                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12581.409662                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12581.409662                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12581.409662                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 79052.647689                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 79052.647689                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 79052.647689                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 79052.647689                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements            96859                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65151.144064                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            7317028                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           162271                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            45.091409                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      94922732000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    70.044406                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.023437                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 12290.016649                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 52791.059572                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001069                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.187531                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.805528                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.994128                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           63                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65349                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           63                       # Occupied blocks per task id
+system.cpu.icache.writebacks::writebacks      2891615                       # number of writebacks
+system.cpu.icache.writebacks::total           2891615                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2892139                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      2892139                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      2892139                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      2892139                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      2892139                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      2892139                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3119                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total         3119                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3119                       # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total         3119                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36912197500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  36912197500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36912197500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  36912197500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36912197500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  36912197500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    265216500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    265216500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    265216500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    265216500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050322                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050322                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050322                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.050322                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050322                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.050322                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12762.940336                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12762.940336                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12762.940336                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12762.940336                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12762.940336                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12762.940336                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements            97098                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65145.315179                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            7321379                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           162490                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            45.057413                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     271905816000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    69.248317                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.032949                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 12118.407979                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 52957.625933                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001057                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000001                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.184912                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.808069                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994039                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           50                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65342                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           50                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2           80                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4600                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        60668                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000961                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997147                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         60051875                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        60051875                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        67793                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3314                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          71107                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       700399                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       700399                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      2838445                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      2838445                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         2804                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         2804                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       166282                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       166282                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2866680                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      2866680                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       535530                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       535530                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        67793                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         3314                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      2866680                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       701812                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         3639599                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        67793                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         3314                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      2866680                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       701812                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        3639599                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          120                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          121                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           63                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4586                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        60692                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000763                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997040                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         60089878                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        60089878                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        68391                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3372                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          71763                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       702249                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       702249                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      2840964                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      2840964                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         2784                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         2784                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       166689                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       166689                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2869145                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      2869145                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       534458                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       534458                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        68391                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         3372                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst      2869145                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       701147                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         3642055                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        68391                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         3372                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      2869145                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       701147                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        3642055                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          110                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          112                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       129240                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       129240                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22945                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        22945                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14654                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        14654                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker          120                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        22945                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143894                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        166960                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker          120                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            1                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        22945                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143894                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       166960                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     10289000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker        83500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     10372500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       145500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       145500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       164000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total       164000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10239764000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10239764000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1854577500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1854577500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1232673000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1232673000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     10289000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker        83500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1854577500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  11472437000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  13337387000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     10289000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker        83500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1854577500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  11472437000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  13337387000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        67913                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3315                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        71228                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       700399                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       700399                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      2838445                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      2838445                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2809                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2809                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses::cpu.data       129768                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       129768                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22956                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        22956                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14347                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        14347                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker          110                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        22956                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       144115                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        167183                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker          110                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        22956                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       144115                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       167183                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     35753500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       193000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     35946500                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       174000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       174000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       166000                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::total       166000                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12066822500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  12066822500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2380927500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   2380927500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1746972000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1746972000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     35753500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       193000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   2380927500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  13813794500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  16230668500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     35753500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       193000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   2380927500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  13813794500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  16230668500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        68501                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3374                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        71875                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       702249                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       702249                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      2840964                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      2840964                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2790                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2790                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       295522                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       295522                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      2889625                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      2889625                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       550184                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       550184                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        67913                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         3315                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      2889625                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       845706                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      3806559                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        67913                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         3315                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      2889625                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       845706                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      3806559                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001767                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000302                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.001699                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.001780                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.001780                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       296457                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       296457                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      2892101                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      2892101                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       548805                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       548805                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        68501                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         3374                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      2892101                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       845262                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      3809238                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        68501                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         3374                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      2892101                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       845262                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      3809238                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001606                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000593                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.001558                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.002151                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.002151                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.437328                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.437328                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007940                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007940                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026635                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026635                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001767                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000302                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007940                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.170147                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.043861                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001767                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000302                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007940                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.170147                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.043861                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85741.666667                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        83500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 85723.140496                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        29100                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        29100                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        82000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        82000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79230.609718                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79230.609718                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80827.086511                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80827.086511                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84118.534189                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84118.534189                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85741.666667                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        83500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80827.086511                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79728.390343                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79883.726641                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85741.666667                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        83500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80827.086511                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79728.390343                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79883.726641                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.437730                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.437730                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007937                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007937                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026142                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026142                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001606                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000593                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007937                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.170497                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.043889                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001606                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000593                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007937                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.170497                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.043889                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 325031.818182                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        96500                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 320950.892857                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        29000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        29000                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        83000                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        83000                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92987.658745                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92987.658745                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103717.002091                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103717.002091                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121765.665296                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121765.665296                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 325031.818182                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        96500                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103717.002091                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95852.579537                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 97083.247100                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 325031.818182                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        96500                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103717.002091                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95852.579537                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 97083.247100                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        88448                       # number of writebacks
-system.cpu.l2cache.writebacks::total            88448                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           18                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           18                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          136                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          136                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           18                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          136                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          154                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           18                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          136                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          154                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          120                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          121                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        88493                       # number of writebacks
+system.cpu.l2cache.writebacks::total            88493                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           14                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           14                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          145                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          145                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data          145                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          159                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           14                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data          145                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total          159                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          110                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          112                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       129240                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       129240                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22927                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22927                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14518                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14518                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          120                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        22927                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       143758                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       166806                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          120                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        22927                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       143758                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       166806                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3267                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34395                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3267                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61978                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      9089000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        73500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      9162500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        95500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        95500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       144000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       144000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8947364000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8947364000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1624414500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1624414500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1078119000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1078119000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      9089000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        73500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1624414500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10025483000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11659060000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      9089000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        73500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1624414500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10025483000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  11659060000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    207499500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5912622000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6120121500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    207499500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5912622000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6120121500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001767                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000302                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001699                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.001780                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.001780                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       129768                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       129768                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22942                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22942                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14202                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14202                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          110                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        22942                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       143970                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       167024                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          110                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        22942                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       143970                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       167024                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3119                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34249                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3119                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61833                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     34653500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       173000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     34826500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       114000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       114000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       146000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       146000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  10769142500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  10769142500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2149471500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2149471500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1592398000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1592398000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     34653500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       173000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2149471500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12361540500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  14545838500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     34653500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       173000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2149471500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12361540500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  14545838500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    216819500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5916431500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6133251000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    216819500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5916431500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6133251000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001606                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000593                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001558                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.002151                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.002151                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.437328                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.437328                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007934                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007934                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026388                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.026388                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001767                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000302                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007934                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.169986                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.043821                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001767                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000302                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007934                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.169986                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.043821                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        73500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75723.140496                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        19100                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        19100                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        72000                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        72000                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69230.609718                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69230.609718                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70851.594190                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70851.594190                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74260.848602                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74260.848602                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        73500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70851.594190                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69738.609330                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69895.927005                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        73500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70851.594190                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69738.609330                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69895.927005                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63513.774105                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189945.451041                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 177936.371566                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63513.774105                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100707.226925                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98746.676240                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      7504035                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      3768706                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58030                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          170                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          170                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.437730                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.437730                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007933                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007933                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025878                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025878                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001606                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000593                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007933                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.170326                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.043847                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001606                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000593                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007933                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.170326                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.043847                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        86500                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 310950.892857                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        19000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        19000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        73000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        73000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82987.658745                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82987.658745                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93691.548252                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93691.548252                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 112124.911984                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112124.911984                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        86500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93691.548252                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85861.919150                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87088.313656                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        86500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93691.548252                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85861.919150                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87088.313656                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190055.621587                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179078.250460                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100766.963586                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99190.577847                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      7507397                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      3770030                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58003                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          175                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          175                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq         137182                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3577165                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         27583                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        27583                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       788847                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      2889133                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       153180                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2809                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq         136990                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3578080                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       790742                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      2891615                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       151079                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2790                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2811                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       295522                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       295522                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      2889657                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       550405                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2792                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296457                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296457                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      2892139                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       549026                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq         4412                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8674948                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2659767                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14702                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       159313                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          11508730                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    370049536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     99142941                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        13260                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       271652                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          469477389                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      133226                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               5798108                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      4004431                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.022424                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.148057                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8682092                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2658406                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14762                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       159854                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          11515114                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    370357376                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     99233193                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        13496                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       274004                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          469878069                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      132782                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               5798856                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      4006498                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.022233                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.147442                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3914637     97.76%     97.76% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              89794      2.24%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3917420     97.78%     97.78% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              89078      2.22%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4004431                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     7421943500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4006498                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     7428208500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       275377                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       281377                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    4339894977                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    4343459350                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1315039189                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1314433554                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      11390493                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      11390994                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      91431936                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      91384437                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
@@ -1275,66 +1288,66 @@ system.iobus.pkt_size_system.bridge.master::total       159125
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             46364500                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             46308000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               107000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               324000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               327000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                88000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                88500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               618000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               618500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               22000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               50000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               52000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6096500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6088500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            39117500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            39091500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187733842                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187755828                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.032370                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.033906                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         270830421000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.032370                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.064523                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.064523                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         272036495000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.033906                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.064619                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.064619                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
 system.iocache.tags.data_accesses              328122                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
@@ -1343,14 +1356,14 @@ system.iocache.demand_misses::realview.ide        36458                       #
 system.iocache.demand_misses::total             36458                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide        36458                       # number of overall misses
 system.iocache.overall_misses::total            36458                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     29494377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     29494377                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4278402465                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4278402465                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   4307896842                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4307896842                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   4307896842                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4307896842                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     37411877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     37411877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4363182951                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4363182951                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4400594828                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4400594828                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4400594828                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4400594828                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1367,14 +1380,14 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 126044.346154                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126044.346154                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118109.608685                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118109.608685                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 118160.536563                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 118160.536563                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 118160.536563                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 118160.536563                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 159879.816239                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 159879.816239                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120450.059381                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 120450.059381                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 120703.133140                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 120703.133140                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 120703.133140                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 120703.133140                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1391,14 +1404,14 @@ system.iocache.demand_mshr_misses::realview.ide        36458
 system.iocache.demand_mshr_misses::total        36458                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide        36458                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        36458                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17794377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17794377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2465093924                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2465093924                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   2482888301                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2482888301                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   2482888301                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2482888301                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     25711877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     25711877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2549871160                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2549871160                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2575583037                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2575583037                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2575583037                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2575583037                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1407,90 +1420,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76044.346154                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76044.346154                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68051.400287                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68051.400287                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68102.701766                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68102.701766                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68102.701766                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68102.701766                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests        336558                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       137845                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          488                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109879.816239                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 109879.816239                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.761263                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.761263                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 70645.209200                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70645.209200                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 70645.209200                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70645.209200                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests        337068                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       138136                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          489                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               34395                       # Transaction distribution
-system.membus.trans_dist::ReadResp              72195                       # Transaction distribution
-system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
-system.membus.trans_dist::WriteResp             27583                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       124638                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8645                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               34249                       # Transaction distribution
+system.membus.trans_dist::ReadResp              71739                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       124683                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8839                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              128                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129117                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129117                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         37800                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129646                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129646                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         37490                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446466                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       554028                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2074                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446846                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       554414                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72897                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        72897                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 626925                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 627311                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16538656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16702429                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4148                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16546016                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16709801                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19019549                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              504                       # Total snoops (count)
-system.membus.snoopTraffic                      32128                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            265249                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.018541                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.134898                       # Request fanout histogram
+system.membus.pkt_size::total                19026921                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              505                       # Total snoops (count)
+system.membus.snoopTraffic                      32192                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            265323                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.018540                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.134893                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  260331     98.15%     98.15% # Request fanout histogram
-system.membus.snoop_fanout::1                    4918      1.85%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  260404     98.15%     98.15% # Request fanout histogram
+system.membus.snoop_fanout::1                    4919      1.85%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              265249                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            92904500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              265323                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            92820000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                8000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1693000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1700500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           906764526                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           905922529                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          989491000                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          989794500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1228623                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1230123                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1522,28 +1535,28 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 567a187d7..18a433388 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -36,7 +36,7 @@ load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -229,7 +229,7 @@ useIndirect=true
 [system.cpu0.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -591,7 +591,7 @@ pipelined=true
 [system.cpu0.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -723,7 +723,7 @@ port=system.cpu0.toL2Bus.slave[2]
 [system.cpu0.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -948,7 +948,7 @@ useIndirect=true
 [system.cpu1.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1310,7 +1310,7 @@ pipelined=true
 [system.cpu1.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1442,7 +1442,7 @@ port=system.cpu1.toL2Bus.slave[2]
 [system.cpu1.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -1589,7 +1589,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -1635,7 +1635,7 @@ size=1024
 [system.l2c]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1733,27 +1733,27 @@ system=system
 
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -1773,6 +1773,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -1782,7 +1783,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1804,9 +1805,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -2159,7 +2160,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -2476,6 +2477,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -2483,7 +2485,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -2714,6 +2716,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -2721,7 +2724,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
index 8041988f0..716e8ee64 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
@@ -35,7 +35,6 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
 warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
 warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
 warn: allocating bonus target for snoop
-warn: allocating bonus target for snoop
 warn: Returning zero for read from miscreg pmcr
 warn: Ignoring write to miscreg pmcntenclr
 warn: Ignoring write to miscreg pmintenclr
@@ -46,3 +45,4 @@ warn: Ignoring write to miscreg pmintenclr
 warn: Ignoring write to miscreg pmovsr
 warn: Ignoring write to miscreg pmcr
 warn: 	instruction 'mcr dcisw' unimplemented
+warn: CP14 unimplemented crn[3], opc1[5], crm[8], opc2[0]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index e697726d2..78776277c 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:31:02
-gem5 executing on e108600-lin, pid 12561
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:00:48
+gem5 executing on e108600-lin, pid 17551
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual
 
 Global frequency set at 1000000000000 ticks per second
@@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2825947406000 because m5_exit instruction encountered
+Exiting @ tick 2826594924500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index ab0dc0047..a281a2cd6 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,161 +1,161 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.826111                       # Number of seconds simulated
-sim_ticks                                2826111083000                       # Number of ticks simulated
-final_tick                               2826111083000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.826595                       # Number of seconds simulated
+sim_ticks                                2826594924500                       # Number of ticks simulated
+final_tick                               2826594924500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  93135                       # Simulator instruction rate (inst/s)
-host_op_rate                                   112984                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2190118612                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 627176                       # Number of bytes of host memory used
-host_seconds                                  1290.39                       # Real time elapsed on the host
-sim_insts                                   120180681                       # Number of instructions simulated
-sim_ops                                     145794019                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  79087                       # Simulator instruction rate (inst/s)
+host_op_rate                                    95944                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1861516367                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 623016                       # Number of bytes of host memory used
+host_seconds                                  1518.44                       # Real time elapsed on the host
+sim_insts                                   120088860                       # Number of instructions simulated
+sim_ops                                     145685275                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker         1920                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker         1856                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1301824                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1315176                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8404800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1324752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1304168                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8428096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           186528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           599252                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       416192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           175008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           586900                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       427200                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12227420                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1301824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       186528                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1488352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8794944                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12249452                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1324752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       175008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1499760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8803008                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8812508                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           30                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8820572                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           29                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             22588                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             21070                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       131325                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            8                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             22950                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             20898                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       131689                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2982                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              9384                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         6503                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2802                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              9191                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         6675                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                193909                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          137421                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                194257                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          137547                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               141812                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           679                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               141938                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           657                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            68                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              460641                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              465366                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2973981                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           181                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              468674                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              461392                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2981713                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker            91                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               66002                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              212041                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       147267                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               61915                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              207635                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       151136                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4326589                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         460641                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          66002                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             526643                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3112031                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6201                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4333643                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         468674                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          61915                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             530589                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3114351                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6200                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3118245                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3112031                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          679                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3120565                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3114351                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          657                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             460641                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             471567                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2973981                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          181                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             468674                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             467592                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2981713                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker           91                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              66002                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             212055                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       147267                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              61915                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             207649                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       151136                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7444834                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        193910                       # Number of read requests accepted
-system.physmem.writeReqs                       141812                       # Number of write requests accepted
-system.physmem.readBursts                      193910                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     141812                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12399936                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10304                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8824960                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12227484                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8812508                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      161                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::total                7454207                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        194258                       # Number of read requests accepted
+system.physmem.writeReqs                       141938                       # Number of write requests accepted
+system.physmem.readBursts                      194258                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     141938                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12422976                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9472                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8833536                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12249516                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8820572                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      148                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12140                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12135                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12398                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12886                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14558                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12353                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12494                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12590                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12207                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12490                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11644                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10772                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11273                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11534                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11359                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10916                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8885                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8987                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9257                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9509                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8433                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8902                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9078                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8908                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8674                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9007                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8474                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8031                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8318                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8000                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7983                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7444                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               12130                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12140                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12480                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12151                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14882                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12677                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12709                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12606                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11844                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11522                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11334                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10175                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11497                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12486                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11961                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11515                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8842                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8923                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9151                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8834                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8743                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9257                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9174                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9022                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8380                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8199                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8228                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7543                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8493                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8795                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8486                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7954                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2826110796000                       # Total gap between requests
+system.physmem.numWrRetry                          65                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2826594637500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
-system.physmem.readPktSize::4                    3086                       # Read request sizes (log2)
+system.physmem.readPktSize::4                    3091                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  190245                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  190588                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 137421                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     59620                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     70390                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     15526                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     12745                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      8439                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7276                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      6358                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      5209                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      4584                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1421                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      930                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      679                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      302                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      262                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 137547                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     58416                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     70500                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     15616                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     12705                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      8571                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7500                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      6655                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      5421                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      4753                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1522                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      747                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      307                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      270                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
@@ -189,162 +189,179 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2582                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3484                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5590                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5845                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6981                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7513                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8598                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9940                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10692                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8918                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7922                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      642                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      329                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       19                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        84734                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      250.487785                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     142.325533                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     306.970890                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          42837     50.55%     50.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17738     20.93%     71.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6168      7.28%     78.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3519      4.15%     82.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2713      3.20%     86.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1549      1.83%     87.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          945      1.12%     89.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1056      1.25%     90.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8209      9.69%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          84734                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6846                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.300175                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      562.386287                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6844     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2470                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3315                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3918                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4463                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5299                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5685                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6574                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9581                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8838                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9296                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    10600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8664                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8349                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      743                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      518                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      422                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      276                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      306                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      291                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      207                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      156                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        84597                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      251.267917                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     142.709069                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     307.432600                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          42654     50.42%     50.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17739     20.97%     71.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6092      7.20%     78.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3470      4.10%     82.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2903      3.43%     86.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1534      1.81%     87.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          962      1.14%     89.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          998      1.18%     90.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8245      9.75%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          84597                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6823                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.448923                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      563.375084                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6821     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6846                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6846                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.141689                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.636499                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.164291                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5708     83.38%     83.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             378      5.52%     88.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              91      1.33%     90.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              47      0.69%     90.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             276      4.03%     94.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              33      0.48%     95.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              21      0.31%     95.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              23      0.34%     96.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              19      0.28%     96.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              10      0.15%     96.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               2      0.03%     96.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               9      0.13%     96.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             166      2.42%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               9      0.13%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.06%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              11      0.16%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               6      0.09%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.03%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.04%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.03%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             3      0.04%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.03%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             3      0.04%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             7      0.10%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.03%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             3      0.04%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6846                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     6600075879                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10232869629                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    968745000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       34065.08                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  52815.08                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.39                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.12                       # Average achieved write bandwidth in MiByte/s
+system.physmem.rdPerTurnAround::total            6823                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6823                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.229225                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.516304                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.191757                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5762     84.45%     84.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             386      5.66%     90.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              77      1.13%     91.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              44      0.64%     91.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             244      3.58%     95.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              18      0.26%     95.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              14      0.21%     95.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              12      0.18%     96.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              17      0.25%     96.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               2      0.03%     96.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.07%     96.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               8      0.12%     96.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             140      2.05%     98.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.09%     98.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.07%     98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              10      0.15%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              12      0.18%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.01%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.04%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               4      0.06%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.04%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             8      0.12%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             2      0.03%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.03%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            13      0.19%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.01%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.01%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.03%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             4      0.06%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             4      0.06%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             4      0.06%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6823                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    10063104165                       # Total ticks spent queuing
+system.physmem.totMemAccLat               13702647915                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    970545000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       51842.28                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      4999.97                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  70592.18                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.40                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.13                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        4.33                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        3.12                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.81                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     161373                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     85531                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.29                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  62.02                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8418008.94                       # Average gap between requests
-system.physmem.pageHitRate                      74.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  338612400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  184758750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 792121200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                466294320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           184587446160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            79311033765                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1626092117250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1891772383845                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.392029                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2705053539598                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94369860000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     26681946652                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  301976640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  164769000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 719113200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                427232880                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           184587446160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            78534447525                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1626773333250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1891508318655                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.298592                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2706191706230                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94369860000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     25549496770                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.32                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     161915                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     85621                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.41                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  62.03                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8407579.62                       # Average gap between requests
+system.physmem.pageHitRate                      74.52                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  318172680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  169112790                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 726673500                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                375558120                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           4535428560.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             4774700760                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              244257600                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy        9148762200                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        6477825120                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       667571113185                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             694343780025                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              245.646723                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           2815396783365                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      428149701                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1926538000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   2778550744250                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  16869300047                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      8757031934                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  20063160568                       # Time in different power states
+system.physmem_1.actEnergy                  285849900                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  151932825                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 659264760                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                344927160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           4569848400.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             4671042840                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              250741920                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy        8727797820                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        6816319680                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       667684488600                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             694164121065                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              245.583162                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           2815694283339                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      440101951                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1941710000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   2778803468000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  17750764755                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      8518829210                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  19140050584                       # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst          112                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          176                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           288                       # Number of bytes read from this memory
@@ -363,30 +380,30 @@ system.realview.nvmem.bw_inst_read::total          102                       # I
 system.realview.nvmem.bw_total::cpu0.inst           40                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           62                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total             102                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               23913557                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         15655751                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           926443                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            14584665                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                9536401                       # Number of BTB hits
+system.cpu0.branchPred.lookups               53161527                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         24432585                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           935077                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            32150468                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               13984916                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            65.386493                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                3854213                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             33180                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        1360238                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           1204672                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses          155566                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted        48773                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            43.498328                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15489494                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             33173                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups       10133739                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           9977658                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses          156081                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted        49006                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -416,84 +433,83 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                    65918                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               65918                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        25327                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        18922                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        21669                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        44249                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   506.926710                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  3129.335275                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-8191        43005     97.19%     97.19% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-16383          929      2.10%     99.29% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-24575          148      0.33%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-32767          108      0.24%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-40959           23      0.05%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-49151           20      0.05%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-57343            1      0.00%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::57344-65535           13      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                    66483                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               66483                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        25519                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        19054                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        21910                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        44573                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   499.046508                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  3114.296115                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191        43354     97.27%     97.27% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383          917      2.06%     99.32% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575          125      0.28%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767          116      0.26%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959           24      0.05%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151           21      0.05%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::57344-65535           14      0.03%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        44249                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        16055                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 11307.848022                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  9898.999015                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  6813.334576                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383        14595     90.91%     90.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1294      8.06%     98.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151          134      0.83%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535            9      0.06%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            4      0.02%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687           17      0.11%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::114688-131071            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        16055                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  85920956152                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.541941                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.508329                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1  85862493152     99.93%     99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3     40323000      0.05%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5      8212500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7      5190500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9      2626000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11       844500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13       886000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15       336500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17        44000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  85920956152                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5102     78.63%     78.63% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1387     21.37%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6489                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        65918                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::total        44573                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        16394                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 11498.017567                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9809.718618                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 10152.442305                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383        14883     90.78%     90.78% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1339      8.17%     98.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151          129      0.79%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535           18      0.11%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687            2      0.01%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::114688-131071            6      0.04%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.01%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::245760-262143           16      0.10%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        16394                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  86404933652                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.566419                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.506005                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  86345641152     99.93%     99.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     41095500      0.05%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5      8202000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      4970000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      2695000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11       946000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13       940000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15       429500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17        14500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  86404933652                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5203     78.33%     78.33% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1439     21.67%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6642                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        66483                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        65918                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6489                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        66483                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6642                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6489                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        72407                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6642                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        73125                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    17729387                       # DTB read hits
-system.cpu0.dtb.read_misses                     55806                       # DTB read misses
-system.cpu0.dtb.write_hits                   14606301                       # DTB write hits
-system.cpu0.dtb.write_misses                    10112                       # DTB write misses
+system.cpu0.dtb.read_hits                    23680324                       # DTB read hits
+system.cpu0.dtb.read_misses                     56461                       # DTB read misses
+system.cpu0.dtb.write_hits                   17598903                       # DTB write hits
+system.cpu0.dtb.write_misses                    10022                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3431                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      353                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2188                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3449                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      156                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2246                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      939                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                17785193                       # DTB read accesses
-system.cpu0.dtb.write_accesses               14616413                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      902                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                23736785                       # DTB read accesses
+system.cpu0.dtb.write_accesses               17608925                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         32335688                       # DTB hits
-system.cpu0.dtb.misses                          65918                       # DTB misses
-system.cpu0.dtb.accesses                     32401606                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                         41279227                       # DTB hits
+system.cpu0.dtb.misses                          66483                       # DTB misses
+system.cpu0.dtb.accesses                     41345710                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -523,58 +539,58 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    10845                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort               10845                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3752                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6021                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore         1072                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples         9773                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean   438.606364                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  2276.348067                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-4095         9409     96.28%     96.28% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::4096-8191          161      1.65%     97.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-12287          121      1.24%     99.16% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::12288-16383           47      0.48%     99.64% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-20479            7      0.07%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::20480-24575           16      0.16%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-28671            6      0.06%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-36863            4      0.04%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::36864-40959            2      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         9773                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         3657                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12272.627837                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11484.483595                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  4878.254960                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191          514     14.06%     14.06% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383         2884     78.86%     92.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575          170      4.65%     97.57% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           55      1.50%     99.07% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959           31      0.85%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-57343            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         3657                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  21495635712                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.820169                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.384194                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     3866725500     17.99%     17.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    17627832712     82.01%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2        1008500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3          69000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  21495635712                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2254     87.20%     87.20% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          331     12.80%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2585                       # Table walker page sizes translated
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                    11041                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort               11041                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         4028                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5930                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore         1083                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples         9958                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean   410.574413                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  2129.037976                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-4095         9588     96.28%     96.28% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::4096-8191          186      1.87%     98.15% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-12287          118      1.18%     99.34% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::12288-16383           38      0.38%     99.72% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-20479            5      0.05%     99.77% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::20480-24575           15      0.15%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-28671            4      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-36863            2      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::36864-40959            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::40960-45055            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         9958                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         3663                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12262.353262                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11250.035596                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5522.553888                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          663     18.10%     18.10% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383         2695     73.57%     91.67% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575          173      4.72%     96.40% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           79      2.16%     98.55% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959           49      1.34%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-57343            3      0.08%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         3663                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  21980185712                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.834654                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.371618                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     3635314000     16.54%     16.54% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    18343952712     83.46%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2         868500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3          50500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  21980185712                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2243     86.94%     86.94% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          337     13.06%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2580                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        10845                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        10845                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        11041                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        11041                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2585                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2585                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        13430                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    37503849                       # ITB inst hits
-system.cpu0.itb.inst_misses                     10845                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2580                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2580                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        13621                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    72829698                       # ITB inst hits
+system.cpu0.itb.inst_misses                     11041                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -583,1055 +599,1039 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2291                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2280                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1944                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1929                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                37514694                       # ITB inst accesses
-system.cpu0.itb.hits                         37503849                       # DTB hits
-system.cpu0.itb.misses                          10845                       # DTB misses
-system.cpu0.itb.accesses                     37514694                       # DTB accesses
-system.cpu0.numPwrStateTransitions               3712                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         1856                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    1487215700.959052                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   23895599673.728432                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         1080     58.19%     58.19% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10          769     41.43%     99.62% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11            2      0.11%     99.73% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.78% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.22%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses                72840739                       # ITB inst accesses
+system.cpu0.itb.hits                         72829698                       # DTB hits
+system.cpu0.itb.misses                          11041                       # DTB misses
+system.cpu0.itb.accesses                     72840739                       # DTB accesses
+system.cpu0.numPwrStateTransitions               3740                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         1870                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    1456796210.372727                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   23672658216.113400                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         1093     58.45%     58.45% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10          772     41.28%     99.73% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.79% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.21%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 499971395296                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           1856                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON    65838742020                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 2760272340980                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       131678547                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 499970757520                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           1870                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   102386011103                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724208913397                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       204773026                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          19262499                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     112028029                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   23913557                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          14595286                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    106047706                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                2739238                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    149116                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               57008                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       423158                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       407524                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles        94244                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 37503537                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               259263                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   5228                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         127810874                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.056272                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.258048                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          20714269                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     196101622                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   53161527                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          39452068                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    175603283                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                5698298                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    148281                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               57647                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       420719                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       418648                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       100050                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 72829386                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               258768                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   5384                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         200312046                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.196487                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.307164                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                65678610     51.39%     51.39% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                21331326     16.69%     68.08% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 8731054      6.83%     74.91% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                32069884     25.09%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                95293979     47.57%     47.57% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                30393228     15.17%     62.75% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                14596992      7.29%     70.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                60027847     29.97%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           127810874                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.181606                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.850769                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                19867897                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             60850603                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 41086114                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              4967748                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1038512                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             3035925                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               335186                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             110135169                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              3776324                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1038512                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                25520251                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               12577304                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      37369361                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 40264186                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             11041260                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             105172145                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              1006076                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              1476626                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                165177                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                 58768                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               6832387                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands          109365921                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            480109573                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       120259513                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             9447                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             98266494                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                11099416                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1228555                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1085594                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 12372656                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            18663457                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           16076197                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1697816                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2228906                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 102290291                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1693186                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                100457201                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           451571                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        9045594                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     21384310                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        120136                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    127810874                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.785983                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.028831                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           200312046                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.259612                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.957654                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                25714917                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            108196913                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 58914772                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              4966892                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               2518552                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             3065050                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               334861                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             154468947                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              3822056                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               2518552                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                34338225                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               12857218                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      83619486                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 55122113                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             11856452                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             137773765                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              1037168                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              1494015                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                163408                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                 59807                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               7647937                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands          141868428                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            635547314                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       152852010                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             9442                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            130675877                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                11192540                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           2699923                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       2556575                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 22590232                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            24607184                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           19088589                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1696558                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2229617                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 134839557                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1714900                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                132985122                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           452743                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       10598058                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     21682682                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        119247                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    200312046                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.663890                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       0.961819                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           71664386     56.07%     56.07% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           23315575     18.24%     74.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           22454220     17.57%     91.88% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            9273638      7.26%     99.14% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            1103003      0.86%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                 52      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          123495652     61.65%     61.65% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           33655276     16.80%     78.45% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           31282184     15.62%     94.07% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           10750314      5.37%     99.44% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            1128564      0.56%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                 56      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      127810874                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      200312046                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                9324082     40.55%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                    74      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               5582954     24.28%     64.83% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              8086742     35.17%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               10816144     43.95%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                    73      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     43.95% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               5628152     22.87%     66.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              8167261     33.18%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             2273      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             66279940     65.98%     65.98% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               93468      0.09%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          8018      0.01%     66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            18419781     18.34%     84.42% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           15653721     15.58%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             89847428     67.56%     67.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult              110447      0.08%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  1      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          7864      0.01%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            1      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            24369410     18.32%     85.98% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           18647698     14.02%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             100457201                       # Type of FU issued
-system.cpu0.iq.rate                          0.762897                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   22993852                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.228892                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         352138149                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        113036952                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     98428366                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              32549                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes             11294                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         9716                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             123427553                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                  21227                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          365954                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             132985122                       # Type of FU issued
+system.cpu0.iq.rate                          0.649427                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   24611630                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.185071                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         491314323                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        147160457                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    129454820                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              32339                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes             11262                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         9717                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             157573424                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                  21055                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          367821                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1901526                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2478                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        19250                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       882682                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1916447                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2461                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        19267                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       901714                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       110051                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       360569                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       120909                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       362204                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1038512                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                1592668                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               210705                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          104136429                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               2518552                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                1651189                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               246744                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          136707359                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             18663457                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            16076197                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            876152                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 28505                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               158159                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         19250                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        253073                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       398879                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              651952                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             99436169                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             17977378                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           955231                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             24607184                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            19088589                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            876464                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 27795                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               194810                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         19267                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        261439                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       400306                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              661745                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            131953488                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             23926851                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           965273                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       152952                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    33471315                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                16838084                       # Number of branches executed
-system.cpu0.iew.exec_stores                  15493937                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.755143                       # Inst execution rate
-system.cpu0.iew.wb_sent                      98890175                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     98438082                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 51269761                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 84681895                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.747564                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.605439                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts        8044326                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1573050                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           595336                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    126126769                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.753686                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.472161                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       152902                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    42414312                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                25613561                       # Number of branches executed
+system.cpu0.iew.exec_stores                  18487461                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.644389                       # Inst execution rate
+system.cpu0.iew.wb_sent                     131398393                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    129464537                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 66052971                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                106772912                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.632234                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.618630                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts        9569777                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1595653                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           604480                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    197147849                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.639512                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.336739                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     81783872     64.84%     64.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     24707932     19.59%     84.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      8259395      6.55%     90.98% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      3211630      2.55%     93.53% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      3438301      2.73%     96.25% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      1493917      1.18%     97.44% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1163537      0.92%     98.36% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       551177      0.44%     98.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1517008      1.20%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    136598241     69.29%     69.29% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     33559109     17.02%     86.31% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     12649949      6.42%     92.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      3238672      1.64%     94.37% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      4912875      2.49%     96.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      2898818      1.47%     98.33% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1203082      0.61%     98.94% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       557487      0.28%     99.22% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1529616      0.78%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    126126769                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            79016795                       # Number of instructions committed
-system.cpu0.commit.committedOps              95059926                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    197147849                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           104125280                       # Number of instructions committed
+system.cpu0.commit.committedOps             126078442                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      31955445                       # Number of memory references committed
-system.cpu0.commit.loads                     16761930                       # Number of loads committed
-system.cpu0.commit.membars                     647782                       # Number of memory barriers committed
-system.cpu0.commit.branches                  16235143                       # Number of branches committed
+system.cpu0.commit.refs                      40877611                       # Number of memory references committed
+system.cpu0.commit.loads                     22690736                       # Number of loads committed
+system.cpu0.commit.membars                     648887                       # Number of memory barriers committed
+system.cpu0.commit.branches                  25008531                       # Number of branches committed
 system.cpu0.commit.fp_insts                      9708                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 81982870                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             1931434                       # Number of function calls committed.
+system.cpu0.commit.int_insts                110051272                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             4840996                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        63005341     66.28%     66.28% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          91123      0.10%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         8017      0.01%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       16761930     17.63%     84.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      15193515     15.98%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        85084925     67.49%     67.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult         108043      0.09%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         7863      0.01%     67.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       22690736     18.00%     85.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      18186875     14.43%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         95059926                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1517008                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   223519030                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  207883288                       # The number of ROB writes
-system.cpu0.timesIdled                         136700                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        3867673                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5520543918                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   78894743                       # Number of Instructions Simulated
-system.cpu0.committedOps                     94937874                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.669041                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.669041                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.599147                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.599147                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               110427579                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               59611828                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     8185                       # number of floating regfile reads
+system.cpu0.commit.op_class_0::total        126078442                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1529616                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   307952651                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  274451297                       # The number of ROB writes
+system.cpu0.timesIdled                         137106                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        4460980                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5448417066                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  104003228                       # Number of Instructions Simulated
+system.cpu0.committedOps                    125956390                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.968910                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.968910                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.507895                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.507895                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               142940096                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               81795281                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     8203                       # number of floating regfile reads
 system.cpu0.fp_regfile_writes                    2264                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                350340790                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                41062621                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              252371624                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes               1225237                       # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements           711089                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          494.347987                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           28802334                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           711601                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            40.475398                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        278078500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.347987                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.965523                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.965523                       # Average percentage of cache occupancy
+system.cpu0.cc_regfile_reads                465685863                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                49834738                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              394201906                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes               1226279                       # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements           711042                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          497.782039                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           37710898                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           711554                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            52.997943                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        296154500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.782039                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.972231                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.972231                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          338                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          321                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           14                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63463455                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63463455                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     15558905                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       15558905                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     12019658                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      12019658                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       308619                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       308619                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       363044                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       363044                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361281                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       361281                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     27578563                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        27578563                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     27887182                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       27887182                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       648058                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       648058                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1895809                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1895809                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       147818                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       147818                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25317                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        25317                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20174                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20174                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2543867                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2543867                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2691685                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2691685                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8928091500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   8928091500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  29690163364                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  29690163364                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    404195500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    404195500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    475433000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    475433000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       570500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       570500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  38618254864                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  38618254864                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  38618254864                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  38618254864                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     16206963                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     16206963                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     13915467                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     13915467                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       456437                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       456437                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       388361                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       388361                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381455                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       381455                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     30122430                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     30122430                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     30578867                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     30578867                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.039986                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.039986                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.136238                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.136238                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.323852                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.323852                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.065189                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.065189                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052887                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052887                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084451                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.084451                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.088024                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.088024                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13776.685883                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13776.685883                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15660.946522                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 15660.946522                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15965.378994                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15965.378994                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23566.620402                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23566.620402                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         81278285                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        81278285                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     21483760                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       21483760                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     15003255                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15003255                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       307803                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       307803                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       363087                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       363087                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361616                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       361616                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     36487015                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        36487015                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     36794818                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       36794818                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       647587                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       647587                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1894796                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1894796                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       148778                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       148778                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25560                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        25560                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20165                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20165                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2542383                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2542383                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2691161                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2691161                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   9361035000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   9361035000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  33017805879                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  33017805879                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    412521000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    412521000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    476921000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    476921000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       443000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       443000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  42378840879                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  42378840879                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  42378840879                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  42378840879                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     22131347                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     22131347                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     16898051                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     16898051                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       456581                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       456581                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       388647                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       388647                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381781                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       381781                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     39029398                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     39029398                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     39485979                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     39485979                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.029261                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.029261                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.112131                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.112131                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.325852                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.325852                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.065767                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.065767                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052818                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052818                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.065140                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.065140                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.068155                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.068155                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14455.254661                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14455.254661                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17425.520150                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 17425.520150                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16139.319249                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16139.319249                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23650.929829                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23650.929829                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15180.925286                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15180.925286                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14347.241547                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14347.241547                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         1034                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      4271446                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               48                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         202383                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.541667                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    21.105755                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       711089                       # number of writebacks
-system.cpu0.dcache.writebacks::total           711089                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       260039                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       260039                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1570278                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1570278                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18696                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18696                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1830317                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1830317                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1830317                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1830317                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       388019                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       388019                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       325531                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       325531                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       101607                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       101607                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6621                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6621                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20174                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20174                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       713550                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       713550                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       815157                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       815157                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20336                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20336                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19032                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19032                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39368                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39368                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4833813000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4833813000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5968230399                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5968230399                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1672759500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1672759500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    104692000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    104692000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    455274000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    455274000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       555500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       555500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10802043399                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  10802043399                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  12474802899                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  12474802899                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4534406000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4534406000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4534406000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4534406000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.023941                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.023941                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023393                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023393                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.222609                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.222609                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017049                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.017049                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052887                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052887                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023688                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023688                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026658                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.026658                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12457.670887                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12457.670887                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18333.831184                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18333.831184                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16463.034043                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16463.034043                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15812.112974                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15812.112974                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22567.363934                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22567.363934                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16668.944403                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16668.944403                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15747.419377                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15747.419377                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs          660                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      4996394                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               33                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         202489                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs           20                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    24.674891                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks       711042                       # number of writebacks
+system.cpu0.dcache.writebacks::total           711042                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       260652                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       260652                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1569869                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1569869                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18798                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18798                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1830521                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1830521                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1830521                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1830521                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       386935                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       386935                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       324927                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       324927                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       102518                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       102518                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6762                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6762                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20165                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20165                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       711862                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       711862                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       814380                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       814380                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31782                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31782                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28457                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28457                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60239                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60239                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5003581000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5003581000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6626488404                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6626488404                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1706140000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1706140000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    107183000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    107183000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    456767000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    456767000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       432000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       432000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11630069404                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  11630069404                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13336209404                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  13336209404                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6624172500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6624172500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6624172500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6624172500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017484                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017484                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019229                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019229                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224534                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224534                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017399                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.017399                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052818                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052818                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018239                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.018239                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020625                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.020625                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12931.321798                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12931.321798                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20393.775845                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20393.775845                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16642.345734                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16642.345734                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15850.783792                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15850.783792                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22651.475329                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22651.475329                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15138.453366                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15138.453366                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15303.558577                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15303.558577                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222974.331235                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222974.331235                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115179.993904                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115179.993904                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          1254577                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.762789                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           36189840                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1255088                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            28.834504                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6511134000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.762789                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999537                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999537                       # Average percentage of cache occupancy
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16337.533685                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16337.533685                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16375.904865                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16375.904865                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208425.287899                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208425.287899                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109964.848354                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109964.848354                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          1252192                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.757674                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           71518552                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1252703                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            57.091387                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6585004000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.757674                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999527                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999527                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          130                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          237                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          131                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         76255085                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        76255085                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     36189843                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       36189843                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     36189843                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        36189843                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     36189843                       # number of overall hits
-system.cpu0.icache.overall_hits::total       36189843                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1310126                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1310126                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1310126                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1310126                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1310126                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1310126                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13674177457                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  13674177457                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  13674177457                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  13674177457                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  13674177457                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  13674177457                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     37499969                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     37499969                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     37499969                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     37499969                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     37499969                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     37499969                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.034937                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.034937                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.034937                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.034937                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.034937                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.034937                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10437.299509                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10437.299509                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10437.299509                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10437.299509                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10437.299509                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10437.299509                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1615389                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          855                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           113956                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets             10                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.175550                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets    85.500000                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      1254577                       # number of writebacks
-system.cpu0.icache.writebacks::total          1254577                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        54978                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        54978                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        54978                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        54978                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        54978                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        54978                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1255148                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1255148                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1255148                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1255148                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1255148                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1255148                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12423139434                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  12423139434                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12423139434                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  12423139434                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12423139434                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  12423139434                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    269145498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    269145498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    269145498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    269145498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033471                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033471                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033471                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.033471                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033471                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.033471                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9897.748659                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9897.748659                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9897.748659                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9897.748659                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9897.748659                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9897.748659                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1846782                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1849282                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         2270                       # number of redundant prefetches already in prefetch queue
+system.cpu0.icache.tags.tag_accesses        146904258                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       146904258                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst     71518555                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       71518555                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     71518555                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        71518555                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     71518555                       # number of overall hits
+system.cpu0.icache.overall_hits::total       71518555                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1307201                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1307201                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1307201                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1307201                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1307201                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1307201                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14223203310                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  14223203310                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14223203310                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  14223203310                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14223203310                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  14223203310                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     72825756                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     72825756                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     72825756                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     72825756                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     72825756                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     72825756                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.017950                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.017950                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.017950                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.017950                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.017950                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.017950                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10880.655163                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10880.655163                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10880.655163                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10880.655163                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10880.655163                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10880.655163                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1774060                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets         1996                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           116060                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets             13                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.285714                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets   153.538462                       # average number of cycles each access was blocked
+system.cpu0.icache.writebacks::writebacks      1252192                       # number of writebacks
+system.cpu0.icache.writebacks::total          1252192                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        54454                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        54454                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        54454                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        54454                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        54454                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        54454                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1252747                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1252747                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1252747                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1252747                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1252747                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1252747                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3008                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total         3008                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3008                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total         3008                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12840860811                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  12840860811                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12840860811                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  12840860811                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12840860811                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  12840860811                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    287646998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    287646998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    287646998                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    287646998                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017202                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017202                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017202                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.017202                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017202                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.017202                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10250.162891                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10250.162891                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10250.162891                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10250.162891                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10250.162891                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10250.162891                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1846192                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1848788                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         2354                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       236718                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements          273792                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       15633.615902                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           1886952                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          289401                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.520199                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       238916                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.tags.replacements          272116                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15645.226913                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           1883031                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          287760                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            6.543755                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14449.190897                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    12.342760                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.746834                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1171.335411                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.881909                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000753                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000046                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.071493                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.954200                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022          271                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14543.018555                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    11.670469                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     1.025524                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1089.512365                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.887635                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000712                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000063                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.066499                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.954909                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          261                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.occ_task_id_blocks::1023           10                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15328                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           66                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15373                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           61                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          120                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           81                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          311                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1438                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         7629                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4500                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1450                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.016541                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           79                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          318                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1446                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         7384                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4965                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1260                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.015930                       # Percentage of cache occupancy per task id
 system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000610                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.935547                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        67735071                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       67735071                       # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        55557                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        13221                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         68778                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks       483131                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total       483131                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      1451301                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      1451301                       # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data            4                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       221119                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       221119                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1183848                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1183848                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       387908                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       387908                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        55557                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker        13221                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1183848                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       609027                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1861653                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        55557                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker        13221                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1183848                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       609027                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1861653                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          499                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          185                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total          684                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55776                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        55776                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20170                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        20170                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        48817                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        48817                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        71252                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total        71252                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       108229                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       108229                       # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          499                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          185                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        71252                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       157046                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       228982                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          499                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          185                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        71252                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       157046                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       228982                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     14052000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4306000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total     18358000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data     37654000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total     37654000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data      9570500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total      9570500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       531998                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       531998                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2721932500                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   2721932500                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3344074000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3344074000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3294040496                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3294040496                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     14052000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4306000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3344074000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   6015972996                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   9378404996                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     14052000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4306000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3344074000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   6015972996                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   9378404996                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        56056                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        13406                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total        69462                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks       483131                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total       483131                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      1451301                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      1451301                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55780                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        55780                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20170                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        20170                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269936                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       269936                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1255100                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      1255100                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       496137                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total       496137                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        56056                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        13406                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      1255100                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       766073                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      2090635                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        56056                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        13406                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1255100                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       766073                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      2090635                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.008902                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.013800                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.009847                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999928                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999928                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.938293                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        67637085                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       67637085                       # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        55351                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        13068                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total         68419                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks       481133                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total       481133                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      1450737                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      1450737                       # number of WritebackClean hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       220760                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       220760                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1181751                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      1181751                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       388592                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total       388592                       # number of ReadSharedReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        55351                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker        13068                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1181751                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data       609352                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        1859522                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        55351                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker        13068                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1181751                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       609352                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       1859522                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          507                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          200                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total          707                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55745                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        55745                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20165                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        20165                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        48603                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total        48603                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        70953                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total        70953                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       107504                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       107504                       # number of ReadSharedReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          507                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          200                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        70953                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       156107                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       227767                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          507                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          200                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        70953                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       156107                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       227767                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     15335000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4771500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total     20106500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data     35671000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total     35671000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data      9320000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total      9320000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       415000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       415000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   3386740000                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   3386740000                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3777812500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3777812500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3493890998                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3493890998                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     15335000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4771500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3777812500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   6880630998                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  10678549998                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     15335000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4771500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3777812500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   6880630998                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  10678549998                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        55858                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        13268                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        69126                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks       481133                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total       481133                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      1450737                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      1450737                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55745                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        55745                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20165                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        20165                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269363                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       269363                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1252704                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1252704                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       496096                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       496096                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        55858                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        13268                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1252704                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       765459                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      2087289                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        55858                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        13268                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1252704                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       765459                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2087289                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009077                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.015074                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.010228                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.180847                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.180847                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.056770                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.056770                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.218143                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.218143                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.008902                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.013800                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.056770                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.205001                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.109527                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.008902                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.013800                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.056770                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.205001                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.109527                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28160.320641                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23275.675676                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26839.181287                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   675.093230                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   675.093230                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   474.491820                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   474.491820                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 132999.500000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 132999.500000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55757.881476                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55757.881476                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 46933.054511                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 46933.054511                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30435.839710                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30435.839710                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28160.320641                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23275.675676                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46933.054511                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38307.075608                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 40956.952931                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28160.320641                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23275.675676                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46933.054511                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38307.075608                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 40956.952931                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          201                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.180437                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.180437                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.056640                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.056640                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.216700                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.216700                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009077                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.015074                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.056640                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.203939                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.109121                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009077                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.015074                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.056640                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.203939                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.109121                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30246.548323                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23857.500000                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28439.179632                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   639.895955                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   639.895955                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   462.186958                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   462.186958                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69681.706891                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69681.706891                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53243.872704                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53243.872704                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32500.102303                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32500.102303                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30246.548323                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.500000                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53243.872704                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44076.377088                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 46883.657413                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30246.548323                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.500000                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53243.872704                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44076.377088                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 46883.657413                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs          102                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    33.500000                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches           10619                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks       231332                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          231332                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            4                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5717                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         5717                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.unused_prefetches           10599                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks       230738                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          230738                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            2                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5942                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         5942                       # number of ReadExReq MSHR hits
 system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           36                       # number of ReadCleanReq MSHR hits
 system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           36                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          739                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          739                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            4                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          741                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          741                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            2                       # number of demand (read+write) MSHR hits
 system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           36                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6456                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         6497                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            4                       # number of overall MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6683                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         6721                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            2                       # number of overall MSHR hits
 system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           36                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6456                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         6497                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          498                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          181                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          679                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       265620                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       265620                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55776                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55776                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20170                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20170                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        43100                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        43100                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        71216                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        71216                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       107490                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       107490                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          498                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          181                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        71216                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       150590                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       222485                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          498                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          181                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        71216                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       150590                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       265620                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       488105                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20336                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        23339                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19032                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19032                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        39368                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        42371                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     11046000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3157500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     14203500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  15282370178                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  15282370178                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    964881000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    964881000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    302897000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    302897000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       441998                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       441998                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1759055000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1759055000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2915623000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2915623000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2607419996                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2607419996                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     11046000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3157500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2915623000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4366474996                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   7296301496                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     11046000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3157500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2915623000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4366474996                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  15282370178                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  22578671674                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    246621000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4371369500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4617990500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    246621000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4371369500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4617990500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008884                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.013501                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.009775                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6683                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         6721                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          507                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          198                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total          705                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       262695                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       262695                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55745                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55745                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20165                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20165                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42661                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        42661                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        70917                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        70917                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       106763                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       106763                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          507                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          198                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        70917                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       149424                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       221046                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          507                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          198                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        70917                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       149424                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       262695                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total       483741                       # number of overall MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3008                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31782                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        34790                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28457                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28457                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3008                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60239                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63247                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     12293000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3546000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     15839000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  17363724717                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  17363724717                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    962038500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    962038500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    304268499                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    304268499                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       349000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       349000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2236694000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2236694000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3350952500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3350952500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2808325998                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2808325998                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     12293000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3546000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3350952500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5045019998                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   8411811498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     12293000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3546000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3350952500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5045019998                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  17363724717                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  25775536215                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    265086000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6369584000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6634670000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    265086000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6369584000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6634670000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009077                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.014923                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.010199                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999928                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999928                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.159667                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.159667                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.056741                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.056741                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.216654                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.216654                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008884                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.013501                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.056741                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.196574                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.106420                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008884                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.013501                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.056741                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.196574                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.158377                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.158377                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.056611                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.056611                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.215206                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.215206                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009077                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.014923                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.056611                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.195208                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.105901                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009077                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.014923                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.056611                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.195208                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.233472                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20918.262150                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 57534.711912                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17299.214716                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17299.214716                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15017.203768                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15017.203768                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 110499.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 110499.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40813.341067                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40813.341067                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 40940.561110                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 40940.561110                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24257.326226                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24257.326226                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 40940.561110                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28995.783226                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32794.577145                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 40940.561110                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28995.783226                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46257.816810                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214957.194138                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197865.825442                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111038.648141                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108989.414930                       # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests      4083931                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2062737                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        31284                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       216422                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       214567                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         1855                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq        102316                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1901889                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        19032                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        19032                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       714747                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      1482534                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict        90142                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       335134                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        87548                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42677                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       113494                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            8                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           19                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       288350                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       285091                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1255148                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       586492                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3253                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3770830                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2574893                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        29200                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       119227                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          6494150                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    160667312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     98708808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        53624                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       224224                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         259653968                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     933771                       # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic             18925704                       # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples      3041721                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.089004                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.286883                       # Request fanout histogram
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.231756                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22466.666667                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66098.421047                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66098.421047                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17257.843753                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17257.843753                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15088.941185                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15088.941185                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52429.478915                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52429.478915                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47251.752048                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47251.752048                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26304.300160                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26304.300160                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47251.752048                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33763.117023                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38054.574604                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47251.752048                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33763.117023                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66098.421047                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53283.753527                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200414.826002                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190706.237425                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105738.541476                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104900.943918                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests      4079155                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2060991                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        31388                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       213571                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       211819                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         1752                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq        114320                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1911393                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28457                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28457                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       712151                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      1482098                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict        89271                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       330960                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        87226                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42590                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       113358                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           15                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           26                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       287646                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       284122                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1252747                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       585259                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3214                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3763658                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2614734                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        29156                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       119485                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          6527033                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    160361408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     98721444                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        53072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       223432                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         259359356                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     926756                       # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic             18862496                       # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples      3052726                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.087981                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.285286                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           2772852     91.16%     91.16% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            267014      8.78%     99.94% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              1855      0.06%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           2785896     91.26%     91.26% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            265078      8.68%     99.94% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              1752      0.06%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3041721                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    4067278494                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       3052726                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    4077518993                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    114026414                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    113316466                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1886176090                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1882577097                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1218391120                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1233739845                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy     15802982                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy     15895485                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     63205426                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     63655441                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups               33853439                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         11509465                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           280542                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            18730917                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                5987349                       # Number of BTB hits
+system.cpu1.branchPred.lookups                4630228                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2728889                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           266806                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2406642                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                1541904                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            31.965061                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               12496464                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              7318                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        9007806                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits           8970953                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses           36853                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted        10907                       # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu1.branchPred.BTBHitPct            64.068690                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 874664                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              7405                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups         249240                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits            213278                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses           35962                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted        10619                       # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1661,89 +1661,93 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                    21636                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               21636                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8665                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         5933                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore         7038                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        14598                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   649.780792                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  3376.631612                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095        13908     95.27%     95.27% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::4096-8191          186      1.27%     96.55% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::8192-12287          234      1.60%     98.15% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::12288-16383          108      0.74%     98.89% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-20479           46      0.32%     99.21% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::20480-24575           30      0.21%     99.41% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-28671            8      0.05%     99.47% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::28672-32767           66      0.45%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-36863            4      0.03%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::36864-40959            4      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::40960-45055            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                    21137                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               21137                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8393                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         5852                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore         6892                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        14245                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   645.419445                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  3393.467484                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095        13571     95.27%     95.27% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::4096-8191          196      1.38%     96.64% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-12287          230      1.61%     98.26% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::12288-16383          102      0.72%     98.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-20479           28      0.20%     99.17% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::20480-24575           27      0.19%     99.36% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-28671           10      0.07%     99.43% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::28672-32767           64      0.45%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-36863            5      0.04%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::36864-40959           10      0.07%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::45056-49151            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::53248-57343            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        14598                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         5531                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11435.002712                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10101.039860                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6336.393968                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191         1833     33.14%     33.14% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         3041     54.98%     88.12% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575          457      8.26%     96.38% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767          138      2.50%     98.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959           31      0.56%     99.44% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151           23      0.42%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-57343            4      0.07%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::57344-65535            2      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-106495            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         5531                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  68460974968                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.179525                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.388721                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1  68438733968     99.97%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3     17027000      0.02%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5      2383000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7      1817500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9       437500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11       205000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13       153500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15       216500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17         1000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  68460974968                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1927     75.51%     75.51% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          625     24.49%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2552                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        21636                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::53248-57343            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        14245                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         5483                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11374.338866                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  9975.216104                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6340.433585                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191         1893     34.52%     34.52% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383         2927     53.38%     87.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575          431      7.86%     95.77% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767          169      3.08%     98.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959           33      0.60%     99.45% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151           24      0.44%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-57343            5      0.09%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-106495            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         5483                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  77531116060                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.220578                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.418371                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    60476667848     78.00%     78.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    17032378712     21.97%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2       12865500      0.02%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::3        4248000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4        1183000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::5        1086000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6        1322500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::7         461500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8         217000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::9         174500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10        136000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::11         33500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12        198000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::13         27000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14         21000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::15         96000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  77531116060                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1915     74.80%     74.80% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          645     25.20%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2560                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        21137                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        21636                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2552                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        21137                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2560                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2552                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        24188                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2560                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        23697                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    10130487                       # DTB read hits
-system.cpu1.dtb.read_misses                     18672                       # DTB read misses
-system.cpu1.dtb.write_hits                    6476473                       # DTB write hits
-system.cpu1.dtb.write_misses                     2964                       # DTB write misses
+system.cpu1.dtb.read_hits                     4149269                       # DTB read hits
+system.cpu1.dtb.read_misses                     18244                       # DTB read misses
+system.cpu1.dtb.write_hits                    3464998                       # DTB write hits
+system.cpu1.dtb.write_misses                     2893                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1961                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                       63                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   385                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1955                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                       48                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   410                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      370                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                10149159                       # DTB read accesses
-system.cpu1.dtb.write_accesses                6479437                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      410                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 4167513                       # DTB read accesses
+system.cpu1.dtb.write_accesses                3467891                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         16606960                       # DTB hits
-system.cpu1.dtb.misses                          21636                       # DTB misses
-system.cpu1.dtb.accesses                     16628596                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                          7614267                       # DTB hits
+system.cpu1.dtb.misses                          21137                       # DTB misses
+system.cpu1.dtb.accesses                      7635404                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1773,57 +1777,63 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                     6064                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                6064                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2840                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2623                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore          601                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         5463                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean   343.950211                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  2166.504505                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-4095         5312     97.24%     97.24% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::4096-8191           57      1.04%     98.28% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-12287           43      0.79%     99.07% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::12288-16383           29      0.53%     99.60% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-20479            6      0.11%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::20480-24575            5      0.09%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-28671            5      0.09%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::28672-32767            5      0.09%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-36863            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         5463                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1764                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12147.108844                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11115.999882                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5636.944380                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191          277     15.70%     15.70% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383         1298     73.58%     89.29% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575          111      6.29%     95.58% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767           59      3.34%     98.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959            9      0.51%     99.43% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151            7      0.40%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-57343            2      0.11%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                     5745                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                5745                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2522                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2644                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore          579                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         5166                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean   354.045683                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  2100.129090                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-2047         4967     96.15%     96.15% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::2048-4095           43      0.83%     96.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::4096-6143           47      0.91%     97.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::6144-8191           21      0.41%     98.30% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-10239           19      0.37%     98.66% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::10240-12287           23      0.45%     99.11% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::12288-14335           19      0.37%     99.48% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::14336-16383            7      0.14%     99.61% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-18431            6      0.12%     99.73% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::18432-20479            1      0.02%     99.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::20480-22527            4      0.08%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::22528-24575            1      0.02%     99.85% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-26623            2      0.04%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::26624-28671            3      0.06%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::28672-30719            3      0.06%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         5166                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1734                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 12119.088812                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 10982.617612                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5990.262254                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191          321     18.51%     18.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383         1223     70.53%     89.04% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575          108      6.23%     95.27% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767           58      3.34%     98.62% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959           14      0.81%     99.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151            4      0.23%     99.65% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-57343            5      0.29%     99.94% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::65536-73727            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1764                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  16901758916                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.861276                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.345783                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     2345411264     13.88%     13.88% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    14555617152     86.12%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2         730500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  16901758916                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          989     85.04%     85.04% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          174     14.96%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         1163                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total         1734                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  17381208916                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.871345                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.334946                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     2236929264     12.87%     12.87% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    15143532152     87.13%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2         747500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  17381208916                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          985     85.28%     85.28% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          170     14.72%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         1155                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6064                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6064                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         5745                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         5745                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1163                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1163                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         7227                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    43493383                       # ITB inst hits
-system.cpu1.itb.inst_misses                      6064                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1155                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1155                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         6900                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                     8164971                       # ITB inst hits
+system.cpu1.itb.inst_misses                      5745                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1832,1023 +1842,1024 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1129                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1122                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                      581                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                      574                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                43499447                       # ITB inst accesses
-system.cpu1.itb.hits                         43493383                       # DTB hits
-system.cpu1.itb.misses                           6064                       # DTB misses
-system.cpu1.itb.accesses                     43499447                       # DTB accesses
-system.cpu1.numPwrStateTransitions               5513                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         2757                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    1005805033.413856                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   25768715425.209221                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         1955     70.91%     70.91% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10          798     28.94%     99.85% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses                 8170716                       # ITB inst accesses
+system.cpu1.itb.hits                          8164971                       # DTB hits
+system.cpu1.itb.misses                           5745                       # DTB misses
+system.cpu1.itb.accesses                      8170716                       # DTB accesses
+system.cpu1.numPwrStateTransitions               5463                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         2732                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    1028238405.084919                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   25963867647.326580                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         1944     71.16%     71.16% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10          782     28.62%     99.78% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11            2      0.07%     99.85% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.04%     99.93% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11            1      0.04%     99.96% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12            1      0.04%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 959983620244                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           2757                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON    53106605878                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773004477122                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                       106214002                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 959984033604                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           2732                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON    17447601808                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2809147322692                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                        34895980                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          10283907                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     108683336                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   33853439                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          27454766                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     92513470                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3739662                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     81877                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               30058                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       180666                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       303073                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles        23077                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 43492215                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               108878                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   2205                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         105285959                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.278787                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.339334                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           8706814                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      24545743                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    4630228                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           2629846                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     24236084                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 776070                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     77763                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               35252                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       165739                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       299959                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles        23654                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  8163829                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               107624                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   2029                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples          33933300                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.881300                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.218696                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                48617714     46.18%     46.18% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                13927599     13.23%     59.41% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 7511266      7.13%     66.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                35229380     33.46%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                20192419     59.51%     59.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 4836103     14.25%     73.76% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 1645003      4.85%     78.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 7259775     21.39%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           105285959                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.318729                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.023249                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                13161149                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             62754723                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 26539387                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1087783                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1742917                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              736717                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               129511                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              67619846                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              1094387                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1742917                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                17542611                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                2352209                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      57806856                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 23225004                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              2616362                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              54744976                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts               213737                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents               258070                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 37169                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 15433                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               1611507                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           54654605                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            258629758                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        58168286                       # Number of integer rename lookups
+system.cpu1.fetch.rateDist::total            33933300                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.132687                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.703397                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 7185713                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             16755217                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  8648276                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1081250                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                262844                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              705359                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               127834                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              23145137                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              1030723                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                262844                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 8592488                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                2388926                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      11714810                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  8302740                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              2671492                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              21985761                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts               184128                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents               260119                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 36299                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 16259                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               1667149                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           21955593                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            102445019                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        25352022                       # Number of integer rename lookups
 system.cpu1.rename.fp_rename_lookups             1683                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             52142746                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 2511859                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1875660                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1802517                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 13071586                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            10382439                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            6812181                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           622946                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          790955                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  53883918                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             580977                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 53654093                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            93763                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        3608749                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      5111945                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved         44050                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    105285959                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.509603                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       0.847754                       # Number of insts issued each cycle
+system.cpu1.rename.CommittedMaps             19598713                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 2356880                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            406325                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        333389                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2861472                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             4400097                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            3772059                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           619281                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          624174                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  21175375                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             559463                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 20999121                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            90560                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        2005952                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      4627057                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved         43664                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     33933300                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.618835                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       0.947092                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           72150462     68.53%     68.53% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           16497460     15.67%     84.20% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           13036209     12.38%     96.58% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            3323109      3.16%     99.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             278707      0.26%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5                 12      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           21549433     63.51%     63.51% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            6114741     18.02%     81.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            4178352     12.31%     93.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            1835426      5.41%     99.25% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             255342      0.75%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5                  6      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      105285959                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       33933300                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                2901953     45.47%     45.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   671      0.01%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     45.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               1666030     26.11%     71.59% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              1813313     28.41%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                1405486     29.50%     29.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   669      0.01%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     29.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               1602534     33.64%     63.16% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              1754875     36.84%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass               66      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             36596131     68.21%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               45838      0.09%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          3311      0.01%     68.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            10338451     19.27%     87.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            6670296     12.43%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             12960054     61.72%     61.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               27621      0.13%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          3265      0.02%     61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             4356029     20.74%     82.61% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            3652086     17.39%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              53654093                       # Type of FU issued
-system.cpu1.iq.rate                          0.505151                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    6381967                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.118947                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         219063644                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         58081406                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     51689844                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads               6231                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              2072                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         1788                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              60031897                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   4097                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           89933                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              20999121                       # Type of FU issued
+system.cpu1.iq.rate                          0.601763                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    4763564                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.226846                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          80779382                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         23748142                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     20541259                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads               6284                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              2076                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         1790                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              25758471                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   4148                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           87109                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       434041                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          639                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         9872                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       275866                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       405898                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          640                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         9457                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       249525                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads        52151                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        77961                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads        40585                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        76754                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1742917                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 520776                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               103336                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           54505946                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles                262844                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 543765                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               103558                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           21775845                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             10382439                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             6812181                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            296650                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  7746                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                89089                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          9872                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         44543                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       120099                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              164642                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             53411917                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             10242028                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           220561                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts              4400097                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             3772059                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            296163                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  7694                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                88949                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          9457                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         34239                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       118390                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              152629                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             20771745                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              4261184                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           206260                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        41051                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    16861277                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                11793508                       # Number of branches executed
-system.cpu1.iew.exec_stores                   6619249                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.502871                       # Inst execution rate
-system.cpu1.iew.wb_sent                      53270244                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     51691632                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 25129407                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 38339279                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.486674                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.655448                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts        3369485                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         536927                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           153628                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    103395222                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.492179                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.152090                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                        41007                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     7864490                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 3010595                       # Number of branches executed
+system.cpu1.iew.exec_stores                   3603306                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.595248                       # Inst execution rate
+system.cpu1.iew.wb_sent                      20641556                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     20543049                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 10275425                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 16109782                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.588694                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.637838                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts        1795274                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         515799                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           141615                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     33527734                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.589415                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.349112                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     77830115     75.27%     75.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     14293086     13.82%     89.10% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6071280      5.87%     94.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       693599      0.67%     95.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1980010      1.91%     97.56% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      1625143      1.57%     99.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       382099      0.37%     99.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       124911      0.12%     99.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       394979      0.38%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     24087304     71.84%     71.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      5545630     16.54%     88.38% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      1675188      5.00%     93.38% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       660381      1.97%     95.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       508267      1.52%     96.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       330740      0.99%     97.85% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       223183      0.67%     98.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       117603      0.35%     98.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       379438      1.13%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    103395222                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            41318794                       # Number of instructions committed
-system.cpu1.commit.committedOps              50889001                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     33527734                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            16118487                       # Number of instructions committed
+system.cpu1.commit.committedOps              19761740                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      16484713                       # Number of memory references committed
-system.cpu1.commit.loads                      9948398                       # Number of loads committed
-system.cpu1.commit.membars                     208127                       # Number of memory barriers committed
-system.cpu1.commit.branches                  11637916                       # Number of branches committed
+system.cpu1.commit.refs                       7516733                       # Number of memory references committed
+system.cpu1.commit.loads                      3994199                       # Number of loads committed
+system.cpu1.commit.membars                     208310                       # Number of memory barriers committed
+system.cpu1.commit.branches                   2858693                       # Number of branches committed
 system.cpu1.commit.fp_insts                      1784                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 45745086                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             3368055                       # Number of function calls committed.
+system.cpu1.commit.int_insts                 17575462                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              459876                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        34356210     67.51%     67.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          44767      0.09%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.60% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         3311      0.01%     67.61% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.61% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.61% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.61% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        9948398     19.55%     87.16% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       6536315     12.84%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        12215165     61.81%     61.81% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          26577      0.13%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         3265      0.02%     61.96% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     61.96% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.96% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.96% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        3994199     20.21%     82.17% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       3522534     17.83%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         50889001                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               394979                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                   137189075                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  110398979                       # The number of ROB writes
-system.cpu1.timesIdled                          58975                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         928043                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  5545446856                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   41285938                       # Number of Instructions Simulated
-system.cpu1.committedOps                     50856145                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              2.572644                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        2.572644                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.388705                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.388705                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                55995090                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               35603094                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                     1401                       # number of floating regfile reads
+system.cpu1.commit.op_class_0::total         19761740                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               379438                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                    53719965                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   43510270                       # The number of ROB writes
+system.cpu1.timesIdled                          58110                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         962680                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  5617725351                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   16085632                       # Number of Instructions Simulated
+system.cpu1.committedOps                     19728885                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              2.169388                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        2.169388                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.460959                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.460959                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                23317955                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               13332838                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                     1403                       # number of floating regfile reads
 system.cpu1.fp_regfile_writes                     516                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                190376100                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                15518701                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              209095836                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                386203                       # number of misc regfile writes
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements           187149                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          469.748213                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           15687000                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           187502                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            83.663108                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      93899473000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   469.748213                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.917477                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.917477                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          353                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          348                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.689453                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         32860265                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        32860265                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data      9540081                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        9540081                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      5893568                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       5893568                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48959                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        48959                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        77987                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        77987                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70168                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        70168                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     15433649                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        15433649                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     15482608                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       15482608                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       215586                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       215586                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       396166                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       396166                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30156                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        30156                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18335                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        18335                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23429                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23429                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       611752                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        611752                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       641908                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       641908                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3514528500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   3514528500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   9742278459                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   9742278459                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    360181500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    360181500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    551095500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    551095500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       166500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       166500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  13256806959                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  13256806959                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  13256806959                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  13256806959                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      9755667                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      9755667                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      6289734                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      6289734                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79115                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        79115                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96322                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        96322                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        93597                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        93597                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     16045401                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     16045401                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     16124516                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     16124516                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.022099                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.022099                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.062986                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.062986                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.381167                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.381167                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.190351                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.190351                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.250318                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.250318                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038126                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.038126                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.039809                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.039809                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16302.211183                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16302.211183                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24591.404762                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 24591.404762                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19644.477775                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19644.477775                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23521.938623                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23521.938623                       # average StoreCondReq miss latency
+system.cpu1.cc_regfile_reads                 74580678                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                 6681708                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads               69976526                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                387406                       # number of misc regfile writes
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements           185136                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          468.617373                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            6737062                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           185477                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            36.322897                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      89354157500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   468.617373                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.915268                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.915268                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          341                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          326                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           15                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.666016                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         14947542                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        14947542                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3587773                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3587773                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2897885                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2897885                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        49072                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        49072                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78768                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        78768                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70845                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        70845                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      6485658                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         6485658                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      6534730                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        6534730                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       212319                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       212319                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       390908                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       390908                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        29887                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        29887                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18355                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        18355                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23465                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23465                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       603227                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        603227                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       633114                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       633114                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3545506500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3545506500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   9944995958                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   9944995958                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    362846000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    362846000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    551070500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    551070500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       640500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       640500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  13490502458                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  13490502458                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  13490502458                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  13490502458                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3800092                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3800092                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      3288793                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      3288793                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        78959                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        78959                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        97123                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        97123                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94310                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        94310                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      7088885                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      7088885                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      7167844                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      7167844                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.055872                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.055872                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.118861                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.118861                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.378513                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.378513                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.188987                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.188987                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.248807                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.248807                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.085095                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.085095                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.088327                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.088327                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16698.960055                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16698.960055                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25440.758332                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 25440.758332                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19768.237537                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19768.237537                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23484.785851                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23484.785851                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21670.230680                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 21670.230680                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20652.191527                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 20652.191527                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs          350                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      1431753                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs               38                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets          39808                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.210526                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    35.966464                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks       187150                       # number of writebacks
-system.cpu1.dcache.writebacks::total           187150                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        79090                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        79090                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       306284                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       306284                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13036                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13036                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       385374                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       385374                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       385374                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       385374                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       136496                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       136496                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        89882                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        89882                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        28741                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        28741                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5299                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5299                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23429                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23429                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       226378                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       226378                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       255119                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       255119                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14517                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14517                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11855                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11855                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        26372                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        26372                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1963325500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1963325500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2363104967                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2363104967                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    488593500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    488593500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     93065000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     93065000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    527670500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    527670500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       162500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       162500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4326430467                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4326430467                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4815023967                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4815023967                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2528366000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2528366000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2528366000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2528366000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013991                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.013991                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014290                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014290                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.363281                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.363281                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.055013                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.055013                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.250318                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.250318                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014109                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.014109                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015822                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.015822                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14383.758498                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14383.758498                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26291.192530                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26291.192530                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16999.878223                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16999.878223                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17562.747688                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17562.747688                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22522.109352                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22522.109352                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22363.890307                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 22363.890307                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21308.172711                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 21308.172711                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs          334                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      1473013                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs               34                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets          39225                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.823529                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    37.552913                       # average number of cycles each access was blocked
+system.cpu1.dcache.writebacks::writebacks       185136                       # number of writebacks
+system.cpu1.dcache.writebacks::total           185136                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        77580                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        77580                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       301933                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       301933                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13088                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13088                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       379513                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       379513                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       379513                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       379513                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       134739                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       134739                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        88975                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        88975                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        28539                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        28539                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5267                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5267                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23465                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23465                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       223714                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       223714                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       252253                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       252253                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3386                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3386                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2740                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2740                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         6126                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         6126                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1970715500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1970715500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2395378969                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2395378969                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    480267000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    480267000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     94406500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     94406500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    527620500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    527620500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       625500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       625500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4366094469                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4366094469                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4846361469                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4846361469                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    459425000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    459425000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    459425000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    459425000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035457                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035457                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027054                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027054                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.361441                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.361441                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054230                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054230                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.248807                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.248807                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031558                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.031558                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035192                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035192                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14626.169854                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14626.169854                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26921.932779                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26921.932779                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16828.445285                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16828.445285                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17924.150370                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17924.150370                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22485.425101                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22485.425101                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19111.532335                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19111.532335                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18873.639231                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18873.639231                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174165.874492                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174165.874492                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95873.123009                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95873.123009                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements           589510                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.449637                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           42880129                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           590022                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            72.675475                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      79021423000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.449637                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975488                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975488                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19516.411440                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19516.411440                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19212.304587                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19212.304587                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135683.697578                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 135683.697578                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 74995.919034                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 74995.919034                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements           583486                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.437314                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            7557735                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           583998                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            12.941371                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      79127078000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.437314                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975464                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975464                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          496                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         87573930                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        87573930                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst     42880129                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       42880129                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     42880129                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        42880129                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     42880129                       # number of overall hits
-system.cpu1.icache.overall_hits::total       42880129                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       611823                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       611823                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       611823                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        611823                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       611823                       # number of overall misses
-system.cpu1.icache.overall_misses::total       611823                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5700309356                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   5700309356                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   5700309356                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   5700309356                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   5700309356                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   5700309356                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     43491952                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     43491952                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     43491952                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     43491952                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     43491952                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     43491952                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014067                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.014067                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014067                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.014067                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014067                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.014067                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9316.925575                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9316.925575                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9316.925575                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9316.925575                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9316.925575                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9316.925575                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       502398                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses         16911139                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        16911139                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst      7557735                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        7557735                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      7557735                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         7557735                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      7557735                       # number of overall hits
+system.cpu1.icache.overall_hits::total        7557735                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       605833                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       605833                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       605833                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        605833                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       605833                       # number of overall misses
+system.cpu1.icache.overall_misses::total       605833                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5683938295                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5683938295                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5683938295                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5683938295                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5683938295                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5683938295                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      8163568                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      8163568                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      8163568                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      8163568                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      8163568                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      8163568                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.074212                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.074212                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.074212                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.074212                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.074212                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.074212                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9382.021605                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9382.021605                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9382.021605                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9382.021605                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9382.021605                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9382.021605                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       514122                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs            42118                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs            41357                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    11.928344                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.431318                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks       589510                       # number of writebacks
-system.cpu1.icache.writebacks::total           589510                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        21797                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        21797                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        21797                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        21797                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        21797                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        21797                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       590026                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       590026                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       590026                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       590026                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       590026                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       590026                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks       583486                       # number of writebacks
+system.cpu1.icache.writebacks::total           583486                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        21830                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        21830                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        21830                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        21830                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        21830                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        21830                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       584003                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       584003                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       584003                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       584003                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       584003                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       584003                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          101                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          101                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          101                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          101                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5243631193                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   5243631193                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5243631193                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   5243631193                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5243631193                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   5243631193                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8747999                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8747999                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8747999                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8747999                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013566                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013566                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013566                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.013566                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013566                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.013566                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8887.118861                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8887.118861                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8887.118861                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8887.118861                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8887.118861                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8887.118861                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86613.851485                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86613.851485                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       195371                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       196016                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit          576                       # number of redundant prefetches already in prefetch queue
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5223422114                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5223422114                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5223422114                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5223422114                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5223422114                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5223422114                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9321999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9321999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9321999                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      9321999                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.071538                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.071538                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.071538                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.071538                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.071538                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.071538                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8944.170003                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8944.170003                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8944.170003                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8944.170003                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8944.170003                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8944.170003                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92297.019802                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92297.019802                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92297.019802                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92297.019802                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       192037                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       192612                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          514                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        57640                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements           44567                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       14592.313259                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs            696647                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           58721                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           11.863677                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        57820                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.tags.replacements           43247                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       14634.111672                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs            688069                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           57318                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           12.004414                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14188.463877                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    10.825483                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.061403                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   390.962497                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.865995                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000661                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000126                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.023862                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.890644                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          294                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           30                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13830                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          181                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          105                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14183.524826                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    11.708728                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.055002                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   436.823115                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.865694                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000715                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000125                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.026662                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.893195                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          321                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           27                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13723                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            5                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          183                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          133                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           12                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1785                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8625                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3420                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.017944                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001831                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.844116                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        27388422                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       27388422                       # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        17107                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         6359                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         23466                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks       113848                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total       113848                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks       650456                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total       650456                       # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        26908                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        26908                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       565476                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       565476                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        99207                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total        99207                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        17107                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         6359                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       565476                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       126115                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         715057                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        17107                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         6359                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       565476                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       126115                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        715057                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          487                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          295                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          782                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29684                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29684                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23429                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        23429                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        33964                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        33964                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        24548                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        24548                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        71313                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        71313                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          487                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          295                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        24548                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       105277                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       130607                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          487                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          295                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        24548                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       105277                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       130607                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     10682500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      6004000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     16686500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     13705500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total     13705500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     20860500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     20860500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       156500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       156500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1388167997                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1388167997                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    916991000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total    916991000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1624894996                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1624894996                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     10682500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      6004000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    916991000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3013062993                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   3946740493                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     10682500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      6004000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    916991000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3013062993                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   3946740493                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        17594                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         6654                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total        24248                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks       113848                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total       113848                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks       650456                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total       650456                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29684                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        29684                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23429                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23429                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        60872                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        60872                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       590024                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       590024                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       170520                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       170520                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        17594                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         6654                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       590024                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       231392                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total       845664                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        17594                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         6654                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       590024                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       231392                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       845664                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.027680                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.044334                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.032250                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           11                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1737                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8668                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3318                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.019592                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001648                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.837585                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        27096059                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       27096059                       # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        16526                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         5997                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total         22523                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks       112708                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total       112708                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks       643666                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total       643666                       # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        26963                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        26963                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       560151                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       560151                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        97699                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total        97699                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        16526                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         5997                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       560151                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       124662                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         707336                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        16526                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         5997                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       560151                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       124662                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        707336                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          498                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          291                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          789                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29191                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        29191                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23465                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        23465                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        33482                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        33482                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        23849                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        23849                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        70829                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        70829                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          498                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          291                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        23849                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data       104311                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       128949                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          498                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          291                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        23849                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       104311                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       128949                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     11142500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5993500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     17136000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     12596500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total     12596500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     19283000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     19283000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       603000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       603000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1436185500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1436185500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    937727500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    937727500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1638546999                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1638546999                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     11142500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5993500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst    937727500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3074732499                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   4029595999                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     11142500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5993500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst    937727500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3074732499                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   4029595999                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        17024                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         6288                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total        23312                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks       112708                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total       112708                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks       643666                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total       643666                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29191                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        29191                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23465                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23465                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        60445                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        60445                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       584000                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       584000                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       168528                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       168528                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        17024                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         6288                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       584000                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       228973                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total       836285                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        17024                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         6288                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       584000                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       228973                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total       836285                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.029253                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.046279                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.033845                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.557958                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.557958                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.041605                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.041605                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.418209                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.418209                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.027680                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.044334                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.041605                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.454973                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.154443                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.027680                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.044334                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.041605                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.454973                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.154443                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21935.318275                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20352.542373                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21338.235294                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   461.713381                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   461.713381                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   890.370908                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   890.370908                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.553925                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.553925                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.040837                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.040837                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.420280                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.420280                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.029253                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.046279                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.040837                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.455560                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.154193                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.029253                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.046279                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.040837                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.455560                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.154193                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22374.497992                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20596.219931                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21718.631179                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   431.519989                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   431.519989                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   821.777115                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   821.777115                       # average SCUpgradeReq miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40871.746467                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40871.746467                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37355.018739                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37355.018739                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22785.396716                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22785.396716                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21935.318275                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20352.542373                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37355.018739                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28620.334859                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 30218.445359                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21935.318275                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20352.542373                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37355.018739                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28620.334859                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 30218.445359                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          266                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42894.256615                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42894.256615                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39319.363495                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39319.363495                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23133.843468                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23133.843468                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22374.497992                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20596.219931                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39319.363495                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29476.589228                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 31249.532753                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22374.497992                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20596.219931                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39319.363495                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29476.589228                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 31249.532753                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs          127                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               7                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           38                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    31.750000                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches             797                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks        31759                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           31759                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            2                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          426                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          426                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.unused_prefetches             817                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks        30888                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           30888                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            1                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          456                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          456                       # number of ReadExReq MSHR hits
 system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            9                       # number of ReadCleanReq MSHR hits
 system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           74                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           74                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            2                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           69                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           69                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            1                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            9                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          500                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total          511                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            2                       # number of overall MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data          525                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total          535                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            1                       # number of overall MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            9                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          500                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total          511                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          487                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          293                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          780                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        24893                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        24893                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29684                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29684                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23429                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23429                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33538                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        33538                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        24539                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        24539                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        71239                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        71239                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          487                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          293                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        24539                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       104777                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       130096                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          487                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          293                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        24539                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       104777                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        24893                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       154989                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data          525                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total          535                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          498                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          290                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total          788                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        25130                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        25130                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29191                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29191                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23465                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23465                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33026                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        33026                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        23840                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        23840                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        70760                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        70760                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          498                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          290                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        23840                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data       103786                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       128414                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          498                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          290                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        23840                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data       103786                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        25130                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       153544                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          101                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        14517                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        14618                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11855                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11855                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3386                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3487                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2740                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2740                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          101                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        26372                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        26473                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      7760500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4210000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     11970500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1022179654                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1022179654                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    459449500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    459449500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    351583000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    351583000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       132500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       132500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1131738499                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1131738499                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    769613500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    769613500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1195688496                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1195688496                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      7760500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4210000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    769613500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2327426995                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   3109010995                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      7760500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4210000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    769613500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2327426995                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1022179654                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4131190649                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7990000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2412179500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2420169500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7990000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2412179500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2420169500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.027680                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.044034                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.032168                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         6126                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         6227                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      8154500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4235000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     12389500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1120294346                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1120294346                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    448208500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    448208500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    351353500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    351353500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       513000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       513000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1175287000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1175287000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    794529500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    794529500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1211572499                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1211572499                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      8154500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4235000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    794529500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2386859499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3193778499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      8154500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4235000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    794529500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2386859499                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1120294346                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4314072845                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8564000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    432303000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    440867000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8564000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    432303000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    440867000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.029253                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.046120                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.033802                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.550959                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.550959                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.041590                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.041590                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.417775                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.417775                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.027680                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.044034                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.041590                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.452812                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.153839                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.027680                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.044034                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.041590                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.452812                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.546381                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.546381                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.040822                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040822                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.419871                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.419871                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.029253                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.046120                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.040822                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.453267                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.153553                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.029253                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.046120                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.040822                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.453267                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.183275                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15346.794872                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41062.935524                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15478.018461                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15478.018461                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15006.316958                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15006.316958                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.183602                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15722.715736                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44579.958058                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44579.958058                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15354.338666                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15354.338666                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14973.513744                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14973.513744                       # average SCUpgradeReq mshr miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33744.960910                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33744.960910                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31362.871348                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31362.871348                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16784.184169                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16784.184169                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31362.871348                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22213.147876                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23897.821570                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31362.871348                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22213.147876                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26654.734523                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166162.395812                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165560.918046                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91467.446534                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91420.296151                       # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests      1661462                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests       840058                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        12360                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       115637                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       106952                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         8685                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq         43235                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       842502                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        11855                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        11855                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       146735                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean       662812                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict        29649                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        30154                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        72596                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41626                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        86297                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           15                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           19                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        68185                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        65527                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       590026                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       275295                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq          251                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1769762                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       885483                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        14740                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        38125                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2708110                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     75491792                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29665722                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        26616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        70376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         105254506                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     347103                       # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic              4899396                       # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples      1195777                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.122893                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.349738                       # Request fanout histogram
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35586.719554                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35586.719554                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33327.579698                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33327.579698                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17122.279522                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17122.279522                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33327.579698                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22997.894697                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24870.952536                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33327.579698                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22997.894697                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44579.958058                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28096.655324                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84792.079208                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127673.656232                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126431.603097                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84792.079208                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 70568.560235                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70799.261282                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests      1644268                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests       831312                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        12253                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       115055                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       106415                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         8640                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq         31394                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       822139                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2740                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2740                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       144852                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       655914                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        29483                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        30330                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        71834                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41698                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        85505                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           26                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        67721                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        64923                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       584003                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       271211                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq          307                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1751691                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       836213                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        14098                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        37121                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2639123                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     74720720                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29257698                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        25152                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        68096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         104071666                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     343275                       # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic              4808780                       # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples      1162877                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.125522                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.353024                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0           1057509     88.44%     88.44% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            129583     10.84%     99.27% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              8685      0.73%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0           1025550     88.19%     88.19% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            128687     11.07%     99.26% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              8640      0.74%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1195777                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1635737987                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1162877                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1604189995                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     81718473                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     80522049                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    885241795                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    876204799                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    395391898                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    375699214                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      8093984                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      7819481                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     20543974                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     20111970                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                31012                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31012                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59421                       # Transaction distribution
@@ -2899,33 +2910,33 @@ system.iobus.pkt_size_system.bridge.master::total       162794
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2484042                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             40381000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             40380000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               112500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               111500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               325000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               328000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                31000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                16500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                92000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                88000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               575500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               570500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               51500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               52000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
@@ -2933,32 +2944,32 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6080500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6100500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            33803000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33792000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187681355                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187796551                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84717000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36776000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                36458                       # number of replacements
-system.iocache.tags.tagsinuse               14.555440                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.553749                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         255145986000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.555440                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.909715                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.909715                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         255488373000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.553749                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.909609                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.909609                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
 system.iocache.tags.data_accesses              328284                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
@@ -2967,14 +2978,14 @@ system.iocache.demand_misses::realview.ide        36476                       #
 system.iocache.demand_misses::total             36476                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide        36476                       # number of overall misses
 system.iocache.overall_misses::total            36476                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32543877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32543877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4303510478                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4303510478                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   4336054355                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4336054355                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   4336054355                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4336054355                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     40604377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     40604377                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4366091174                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4366091174                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4406695551                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4406695551                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4406695551                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4406695551                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2991,19 +3002,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 129142.369048                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 129142.369048                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118802.740669                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118802.740669                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 118874.173566                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 118874.173566                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 118874.173566                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 118874.173566                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            36                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 161128.480159                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 161128.480159                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120530.343805                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 120530.343805                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 120810.822212                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 120810.822212                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 120810.822212                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 120810.822212                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            23                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    6                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    4                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            6                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     5.750000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36206                       # number of writebacks
 system.iocache.writebacks::total                36206                       # number of writebacks
@@ -3015,14 +3026,14 @@ system.iocache.demand_mshr_misses::realview.ide        36476
 system.iocache.demand_mshr_misses::total        36476                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide        36476                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        36476                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19943877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19943877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2489987873                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2489987873                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   2509931750                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2509931750                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   2509931750                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2509931750                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     28004377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     28004377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2552566881                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2552566881                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2580571258                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2580571258                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2580571258                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2580571258                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -3031,618 +3042,612 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79142.369048                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 79142.369048                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68738.622819                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68738.622819                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68810.498684                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68810.498684                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68810.498684                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68810.498684                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   136926                       # number of replacements
-system.l2c.tags.tagsinuse                65153.135165                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     554455                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   202299                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.740770                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              87124800000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks    6156.009081                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    17.876446                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     1.073086                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     8059.392106                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     7027.702710                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37061.403814                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     6.474451                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.906071                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1853.985065                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2995.751440                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1972.560896                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.093933                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000273                       # Average percentage of cache occupancy
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 111128.480159                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 111128.480159                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70466.179356                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70466.179356                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 70747.101053                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70747.101053                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 70747.101053                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70747.101053                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                   137609                       # number of replacements
+system.l2c.tags.tagsinuse                65136.051895                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     548833                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   202971                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.703997                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle              87466496000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks    5939.611941                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    15.674941                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     1.061639                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     8089.660546                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     7047.830837                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37514.795432                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.739703                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.908322                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1674.813935                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2903.059558                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1945.895041                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.090631                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000239                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000016                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.122977                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.107234                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.565512                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000099                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.123438                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.107541                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.572430                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000042                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.itb.walker     0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.028290                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.045712                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.030099                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.994158                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        33193                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023           24                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        32156                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          172                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         5974                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        27047                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu1.inst       0.025556                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.044297                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.029692                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.993897                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        33502                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023           21                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        31839                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          401                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         6111                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        26990                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          173                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4634                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        27347                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.506485                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000366                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.490662                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  6339538                       # Number of tag accesses
-system.l2c.tags.data_accesses                 6339538                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks       263091                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          263091                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data           41407                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            4842                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               46249                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          2692                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          2122                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              4814                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             3983                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             1501                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 5484                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          230                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker           86                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        51619                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        58109                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        47216                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           63                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           17                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst        21642                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        11731                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5163                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           195876                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           230                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            86                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               51619                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               62092                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        47216                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker            63                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            17                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               21642                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               13232                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher         5163                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  201360                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          230                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker           86                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              51619                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              62092                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher        47216                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker           63                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           17                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              21642                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              13232                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher         5163                       # number of overall hits
-system.l2c.overall_hits::total                 201360                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data           609                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           555                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1164                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data           50                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          135                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             185                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          11314                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           8283                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              19597                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker           30                       # number of ReadSharedReq misses
+system.l2c.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          161                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4972                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        26706                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.511200                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000320                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.485825                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  6298618                       # Number of tag accesses
+system.l2c.tags.data_accesses                 6298618                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks       261626                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          261626                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data           41310                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            4699                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               46009                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          2684                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          2210                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total              4894                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data             3978                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data             1342                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                 5320                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          248                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker          107                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst        50964                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data        57616                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        46197                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           67                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker           29                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst        21124                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data        11550                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         4807                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           192709                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker           248                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker           107                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst               50964                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data               61594                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher        46197                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker            67                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker            29                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst               21124                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               12892                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher         4807                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  198029                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker          248                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker          107                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst              50964                       # number of overall hits
+system.l2c.overall_hits::cpu0.data              61594                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher        46197                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker           67                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker           29                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst              21124                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              12892                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher         4807                       # number of overall hits
+system.l2c.overall_hits::total                 198029                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data           543                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           291                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total               834                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data           92                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          104                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             196                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          11177                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           8193                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              19370                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker           29                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu0.itb.walker            3                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        19597                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         9392                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       131482                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            8                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        19953                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data         9351                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       131846                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            4                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu1.itb.walker            1                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst         2894                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         1084                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6503                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         170994                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker           30                       # number of demand (read+write) misses
+system.l2c.ReadSharedReq_misses::cpu1.inst         2712                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data          981                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6675                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         171555                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker           29                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             19597                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             20706                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       131482                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker            8                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             19953                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             20528                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       131846                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker            4                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2894                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data              9367                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher         6503                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                190591                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker           30                       # number of overall misses
+system.l2c.demand_misses::cpu1.inst              2712                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data              9174                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher         6675                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                190925                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker           29                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            19597                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            20706                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       131482                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker            8                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            19953                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            20528                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       131846                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker            4                       # number of overall misses
 system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2894                       # number of overall misses
-system.l2c.overall_misses::cpu1.data             9367                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher         6503                       # number of overall misses
-system.l2c.overall_misses::total               190591                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data      8863500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      1613000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     10476500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       750000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       250000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      1000000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   1173434500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    698306000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1871740500                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      2901000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       241000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1645029500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data    865429500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  14426700203                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker       699000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker        83500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst    247656000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data     98290000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    907627854                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  18194657557                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker      2901000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker       241000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1645029500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   2038864000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  14426700203                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker       699000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker        83500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    247656000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    796596000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    907627854                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     20066398057                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker      2901000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker       241000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1645029500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   2038864000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  14426700203                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker       699000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker        83500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    247656000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    796596000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    907627854                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    20066398057                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       263091                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       263091                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        42016                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5397                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           47413                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         2742                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         2257                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          4999                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data        15297                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data         9784                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            25081                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          260                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           89                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst        71216                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data        67501                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       178698                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.overall_misses::cpu1.inst             2712                       # number of overall misses
+system.l2c.overall_misses::cpu1.data             9174                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher         6675                       # number of overall misses
+system.l2c.overall_misses::total               190925                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data      8706000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data       803000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      9509000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       672000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       510500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      1182500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   1649911000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    752041000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   2401952000                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      3955500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       249000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2094281000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data   1081713000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  16526295038                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker       903500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker        89500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst    288810000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data    120918000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1010031515                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  21127246053                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      3955500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       249000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   2094281000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   2731624000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  16526295038                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker       903500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker        89500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    288810000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    872959000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1010031515                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     23529198053                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      3955500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker       249000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   2094281000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   2731624000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  16526295038                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       903500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker        89500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    288810000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    872959000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1010031515                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    23529198053                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks       261626                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       261626                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        41853                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         4990                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           46843                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         2776                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         2314                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          5090                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15155                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data         9535                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            24690                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          277                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker          110                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        70917                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        66967                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       178043                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           71                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           18                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst        24536                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data        12815                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11666                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       366870                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker          260                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker           89                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           71216                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           82798                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       178698                       # number of demand (read+write) accesses
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           30                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        23836                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        12531                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11482                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       364264                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          277                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker          110                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           70917                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           82122                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       178043                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.dtb.walker           71                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           18                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           24536                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           22599                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11666                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              391951                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker          260                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           89                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          71216                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          82798                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       178698                       # number of overall (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           30                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           23836                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           22066                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11482                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              388954                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          277                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker          110                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          70917                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          82122                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       178043                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.dtb.walker           71                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           18                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          24536                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          22599                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11666                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             391951                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.014494                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.102835                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.024550                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.018235                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.059814                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.037007                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.739622                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.846586                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.781348                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.115385                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.033708                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.275177                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.139139                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.735778                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.112676                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.055556                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.117949                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.084588                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.557432                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.466089                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.115385                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.033708                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.275177                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.250079                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.735778                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.112676                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.055556                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.117949                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.414487                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.557432                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.486262                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.115385                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.033708                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.275177                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.250079                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.735778                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.112676                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.055556                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.117949                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.414487                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.557432                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.486262                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14554.187192                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2906.306306                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  9000.429553                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        15000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1851.851852                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5405.405405                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103715.264274                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84305.927804                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 95511.583406                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker        96700                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 80333.333333                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83942.924937                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 92145.389693                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 109723.766014                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker        87375                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        83500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85575.673808                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90673.431734                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 139570.637244                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 106405.239698                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        96700                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80333.333333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 83942.924937                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 98467.304163                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109723.766014                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        87375                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker        83500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 85575.673808                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 85042.809864                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 139570.637244                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 105285.129188                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        96700                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80333.333333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 83942.924937                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 98467.304163                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109723.766014                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        87375                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker        83500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 85575.673808                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 85042.809864                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 139570.637244                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 105285.129188                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               188                       # number of cycles access was blocked
+system.l2c.overall_accesses::cpu1.itb.walker           30                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          23836                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          22066                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11482                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             388954                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.012974                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.058317                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.017804                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.033141                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.044944                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.038507                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.737512                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.859255                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.784528                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.104693                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.027273                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.281357                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.139636                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.740529                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.056338                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.033333                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.113777                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.078286                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.581345                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.470963                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.104693                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.027273                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.281357                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.249970                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.740529                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.056338                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.033333                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.113777                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.415753                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.581345                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.490868                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.104693                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.027273                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.281357                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.249970                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.740529                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.056338                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.033333                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.113777                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.415753                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.581345                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.490868                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16033.149171                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2759.450172                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 11401.678657                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7304.347826                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4908.653846                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  6033.163265                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 147616.623423                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 91790.674966                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 124003.717088                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136396.551724                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        83000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 104960.707663                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 115678.857876                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 125345.441181                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       225875                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        89500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 106493.362832                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123259.938838                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 151315.582772                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 123151.444452                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136396.551724                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker        83000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 104960.707663                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 133068.199532                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 125345.441181                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       225875                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker        89500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 106493.362832                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 95155.766296                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 151315.582772                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 123237.910452                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136396.551724                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        83000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 104960.707663                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 133068.199532                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 125345.441181                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       225875                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker        89500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 106493.362832                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 95155.766296                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 151315.582772                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 123237.910452                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               225                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        5                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        9                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     37.600000                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs            25                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks              101215                       # number of writebacks
-system.l2c.writebacks::total                   101215                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            2                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            2                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            4                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  4                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 4                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         4022                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         4022                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data          609                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          555                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         1164                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           50                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          135                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total          185                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        11314                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         8283                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         19597                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker           30                       # number of ReadSharedReq MSHR misses
+system.l2c.writebacks::writebacks              101341                       # number of writebacks
+system.l2c.writebacks::total                   101341                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            1                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            1                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         4056                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         4056                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data          543                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          291                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total          834                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           92                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          104                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total          196                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        11177                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         8193                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         19370                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker           29                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            3                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19595                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9392                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       131482                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            8                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19952                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9351                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       131846                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2892                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1084                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6503                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       170990                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker           30                       # number of demand (read+write) MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2712                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data          981                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6675                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       171554                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker           29                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            3                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        19595                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        20706                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       131482                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker            8                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        19952                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        20528                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       131846                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2892                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         9367                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6503                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           190587                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker           30                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2712                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         9174                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6675                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           190924                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker           29                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            3                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        19595                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        20706                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       131482                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker            8                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        19952                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        20528                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       131846                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2892                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data         9367                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6503                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          190587                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20336                       # number of ReadReq MSHR uncacheable
+system.l2c.overall_mshr_misses::cpu1.inst         2712                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data         9174                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6675                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          190924                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3008                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31782                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          101                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14514                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        37954                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19032                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11855                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        30887                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        39368                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3383                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        38274                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28457                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2740                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        31197                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3008                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60239                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          101                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26369                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        68841                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     14170000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     12236500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     26406500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1349500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      3214500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total      4564000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1060294500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    615476000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1675770500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      2601000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       211000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1448949504                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    771509001                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13111874714                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker       619000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker        73500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    218669000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     87450000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    842596357                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  16484553076                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2601000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       211000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1448949504                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   1831803501                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  13111874714                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       619000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        73500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    218669000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    702926000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    842596357                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  18160323576                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2601000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       211000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1448949504                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   1831803501                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13111874714                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       619000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        73500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    218669000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    702926000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    842596357                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  18160323576                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    192566500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4005299000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6171000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2150864000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6354900500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    192566500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4005299000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6171000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2150864000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   6354900500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         6123                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        69471                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     12087000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      6019500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     18106500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      2426500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2307500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total      4734000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1538140501                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    670111000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   2208251501                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      3665500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       219000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1894738504                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    988203000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  15207829549                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker       863500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker        79500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    261689501                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    111108000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    943281016                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  19411677070                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      3665500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       219000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1894738504                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   2526343501                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  15207829549                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       863500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        79500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    261689501                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    781219000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    943281016                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  21619928571                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      3665500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       219000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1894738504                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   2526343501                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  15207829549                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       863500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        79500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    261689501                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    781219000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    943281016                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  21619928571                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    210941500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5797437001                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6745000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    371342000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6386465501                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    210941500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5797437001                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6745000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    371342000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   6386465501                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.014494                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.102835                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.024550                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.018235                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.059814                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.037007                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.739622                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.846586                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.781348                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.115385                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.033708                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.275149                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.139139                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735778                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.112676                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.055556                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.117868                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.084588                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.557432                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.466078                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.115385                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.033708                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.275149                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.250079                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735778                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.112676                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.055556                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.117868                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.414487                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.557432                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.486252                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.115385                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.033708                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.275149                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.250079                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735778                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.112676                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.055556                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.117868                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.414487                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.557432                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.486252                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23267.651888                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22047.747748                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22685.996564                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        26990                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23811.111111                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24670.270270                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93715.264274                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74305.927804                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 85511.583406                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker        86700                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73944.858586                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 82145.336563                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker        77375                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75611.687414                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80673.431734                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96406.532990                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        86700                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73944.858586                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88467.280064                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        77375                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75611.687414                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75042.809864                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 95286.265989                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        86700                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73944.858586                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88467.280064                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        77375                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75611.687414                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75042.809864                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 95286.265989                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196956.087726                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148192.365991                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167436.910471                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101739.966470                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81567.901703                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 92312.727880                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        505464                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       284514                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.012974                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.058317                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.017804                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.033141                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.044944                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.038507                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.737512                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.859255                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.784528                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.104693                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.027273                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.281343                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.139636                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.740529                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.056338                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.033333                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.113777                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.078286                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.581345                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.470961                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.104693                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.027273                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.281343                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.249970                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.740529                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.056338                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.033333                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.113777                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.415753                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.581345                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.490865                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.104693                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.027273                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.281343                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.249970                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.740529                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.056338                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.033333                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.113777                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.415753                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.581345                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.490865                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22259.668508                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20685.567010                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21710.431655                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        26375                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22187.500000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24153.061224                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137616.578778                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 81790.674966                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 114003.691327                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 94964.840818                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 105678.857876                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker       215875                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        79500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 96493.178835                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113259.938838                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113151.993367                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 94964.840818                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123068.175224                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       215875                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        79500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 96493.178835                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85155.766296                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 113238.401516                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 94964.840818                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123068.175224                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       215875                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        79500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 96493.178835                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85155.766296                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 113238.401516                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182412.592065                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66782.178218                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109767.070647                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166861.720777                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96240.591660                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66782.178218                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60647.068431                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 91929.949202                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests        504773                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       283620                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests          572                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               37954                       # Transaction distribution
-system.membus.trans_dist::ReadResp             209195                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30887                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30887                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       137421                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            16935                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            65286                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          38770                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               38274                       # Transaction distribution
+system.membus.trans_dist::ReadResp             210079                       # Transaction distribution
+system.membus.trans_dist::WriteReq              31197                       # Transaction distribution
+system.membus.trans_dist::WriteResp             31197                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       137547                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            17007                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            64594                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          38710                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             39566                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            19573                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        171242                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             38808                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19352                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        171806                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107914                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           36                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13620                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       638853                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       760423                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14870                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       638456                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       761276                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72949                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        72949                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 833372                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 834225                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18721784                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18912106                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29740                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18751880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18944702                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21230250                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           123250                       # Total snoops (count)
+system.membus.pkt_size::total                21262846                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           122284                       # Total snoops (count)
 system.membus.snoopTraffic                      36480                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            419934                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.012350                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.110440                       # Request fanout histogram
+system.membus.snoop_fanout::samples            419616                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.012440                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.110839                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  414748     98.77%     98.77% # Request fanout histogram
-system.membus.snoop_fanout::1                    5186      1.23%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  414396     98.76%     98.76% # Request fanout histogram
+system.membus.snoop_fanout::1                    5220      1.24%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              419934                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            81570000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              419616                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            81572000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               24500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11357000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            12355500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           987545766                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           987789803                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1099710840                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1102143190                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1385881                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1335877                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -3674,81 +3679,81 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      1051858                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       557134                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       188416                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          28173                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        27109                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops         1064                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq              37957                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            525508                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30887                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30887                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       364306                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          131438                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          111511                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         43584                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         155095                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           19                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           19                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            50612                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           50612                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       487554                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq         4612                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1267106                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       367019                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1634125                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     36291756                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5905726                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               42197482                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          390713                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  15836620                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples           903686                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.404217                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.493133                       # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests      1044068                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       554075                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       185190                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          28829                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        27647                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops         1182                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq              38277                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            522605                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             31197                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            31197                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       362967                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          130325                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          110585                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         43604                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         154189                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           26                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           26                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50073                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50073                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       484331                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq         4646                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1303151                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       320962                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1624113                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     36235416                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5679078                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               41914494                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          390245                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                  15796172                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples           900374                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.402074                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.492987                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 539465     59.70%     59.70% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 363157     40.19%     99.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                   1064      0.12%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 539539     59.92%     59.92% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 359653     39.94%     99.87% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                   1182      0.13%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             903686                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          901600874                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             900374                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          896925065                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           356119                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           355623                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         679704118                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         692605391                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         260937433                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         242340870                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1856                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    1870                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2757                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    2732                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
index d38aec98b..263610058 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
@@ -159,9 +159,9 @@ ata1.00: configured for UDMA/33
 scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
 sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
 sd 0:0:0:0: [sda] Write Protect is off
+sd 0:0:0:0: Attached scsi generic sg0 type 0
 sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
 sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-sd 0:0:0:0: Attached scsi generic sg0 type 0
  sda: sda1
 sd 0:0:0:0: [sda] Attached SCSI disk
 e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 39155f2aa..c0b6f00cc 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -36,7 +36,7 @@ load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -229,7 +229,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -591,7 +591,7 @@ pipelined=true
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -723,7 +723,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -840,7 +840,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -885,7 +885,7 @@ size=1024
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -897,7 +897,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -929,29 +929,36 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -971,6 +978,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -980,7 +988,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1002,9 +1010,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -1357,7 +1365,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -1674,6 +1682,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1681,7 +1690,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -1912,6 +1921,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1919,7 +1929,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
index af03e613f..2d99e9ceb 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:36:45
-gem5 executing on e108600-lin, pid 13212
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:43:01
+gem5 executing on e108600-lin, pid 17340
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3
 
 Global frequency set at 1000000000000 ticks per second
@@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2832894126500 because m5_exit instruction encountered
+Exiting @ tick 2829112944500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index fdcb3cf4d..85eda68ae 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,123 +1,123 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.827853                       # Number of seconds simulated
-sim_ticks                                2827853096000                       # Number of ticks simulated
-final_tick                               2827853096000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.829113                       # Number of seconds simulated
+sim_ticks                                2829112944500                       # Number of ticks simulated
+final_tick                               2829112944500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  94322                       # Simulator instruction rate (inst/s)
-host_op_rate                                   114411                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2357194570                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 589152                       # Number of bytes of host memory used
-host_seconds                                  1199.67                       # Real time elapsed on the host
-sim_insts                                   113155640                       # Number of instructions simulated
-sim_ops                                     137255479                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  77107                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93526                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1927521729                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 584852                       # Number of bytes of host memory used
+host_seconds                                  1467.75                       # Real time elapsed on the host
+sim_insts                                   113173049                       # Number of instructions simulated
+sim_ops                                     137272583                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker         1024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1322240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9790440                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker          896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1316512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9473064                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11115048                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1322240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1322240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8407168                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10791880                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1316512                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1316512                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8091648                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8424692                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           16                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22907                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             153496                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8109172                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           14                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22822                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             148537                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                176440                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131362                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                171395                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          126432                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               135743                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            362                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker            136                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               467577                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3462146                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               130813                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            317                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            158                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               465344                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3348422                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3930561                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          467577                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             467577                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2972986                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6197                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2979183                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2972986                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           362                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker           136                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              467577                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3468343                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 3814581                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          465344                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             465344                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2860136                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6194                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2866330                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2860136                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           317                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           158                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              465344                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3354616                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6909744                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        176441                       # Number of read requests accepted
-system.physmem.writeReqs                       135743                       # Number of write requests accepted
-system.physmem.readBursts                      176441                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     135743                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11282432                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9792                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8437824                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11115112                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8424692                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      153                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3886                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::total                6680911                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        171396                       # Number of read requests accepted
+system.physmem.writeReqs                       130813                       # Number of write requests accepted
+system.physmem.readBursts                      171396                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     130813                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10959744                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9536                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8121728                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10791944                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8109172                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      149                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11743                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11227                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11041                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10652                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13485                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11002                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11432                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11844                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10383                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10947                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10471                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9569                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10361                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11110                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10361                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10660                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8764                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8604                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8676                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8310                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8074                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8230                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8228                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8800                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7938                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8472                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8080                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7388                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8035                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8487                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7854                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7901                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10680                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10044                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10837                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10904                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13724                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10680                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11438                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11401                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10103                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10404                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10359                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9493                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10229                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11052                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10015                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9883                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8063                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7694                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8368                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8157                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8127                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8035                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8542                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8476                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7684                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7982                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7772                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7097                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7777                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8429                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7462                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7237                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2827852861000                       # Total gap between requests
+system.physmem.numWrRetry                          78                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2829112709500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
-system.physmem.readPktSize::4                    2996                       # Read request sizes (log2)
+system.physmem.readPktSize::4                    3002                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  172889                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  167838                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 131362                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    155219                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     17999                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2225                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       829                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 126432                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    150032                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     14994                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      5338                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       866                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -160,164 +160,181 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5951                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6509                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6942                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6801                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7733                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8271                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9582                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9943                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8031                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       10                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64990                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      303.434251                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.571710                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     325.070143                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24166     37.18%     37.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        15993     24.61%     61.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6821     10.50%     72.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3792      5.83%     78.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2758      4.24%     82.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1633      2.51%     84.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1086      1.67%     86.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1085      1.67%     88.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7656     11.78%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64990                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6662                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.461423                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      559.657587                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6661     99.98%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6662                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6662                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.790003                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.288798                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.351415                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5875     88.19%     88.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              70      1.05%     89.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              75      1.13%     90.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              36      0.54%     90.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             259      3.89%     94.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              62      0.93%     95.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              25      0.38%     96.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              19      0.29%     96.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               9      0.14%     96.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               7      0.11%     96.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               3      0.05%     96.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               4      0.06%     96.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             160      2.40%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.09%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               8      0.12%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               2      0.03%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               6      0.09%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.05%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111            10      0.15%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.12%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             2      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6662                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2116192000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5421592000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    881440000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12004.17                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30754.17                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.99                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.98                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.93                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.98                       # Average system write bandwidth in MiByte/s
+system.physmem.wrQLenPdf::15                     1809                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2587                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5567                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6032                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6526                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6397                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6800                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7716                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7672                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8616                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9083                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7704                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7368                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6858                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      546                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      532                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      455                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      387                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      299                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      279                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      291                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      250                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      207                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        61260                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      311.483382                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     183.687105                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.840241                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22553     36.82%     36.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14650     23.91%     60.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6334     10.34%     71.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3752      6.12%     77.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2675      4.37%     81.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1648      2.69%     84.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1058      1.73%     85.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1036      1.69%     87.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7554     12.33%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61260                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6323                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.072592                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      535.871052                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6321     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6323                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6323                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.069904                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.255220                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.875839                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5596     88.50%     88.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              82      1.30%     89.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              53      0.84%     90.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              37      0.59%     91.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             252      3.99%     95.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              36      0.57%     95.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               9      0.14%     95.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              12      0.19%     96.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               7      0.11%     96.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               4      0.06%     96.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.09%     96.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               6      0.09%     96.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             139      2.20%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              10      0.16%     98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.08%     98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               3      0.05%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               3      0.05%     99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.05%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            12      0.19%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             4      0.06%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            15      0.24%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             4      0.06%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.02%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.05%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.02%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.02%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.02%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.02%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             4      0.06%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6323                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4766161750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                7977024250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    856230000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27832.09                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      4999.97                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  46581.98                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.87                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.87                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.81                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.87                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.03                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     145153                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97985                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.34                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.31                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9058288.90                       # Average gap between requests
-system.physmem.pageHitRate                      78.90                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  256087440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  139730250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 720922800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                438605280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           184701363600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            81077227785                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1625589296250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1892923233405                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.386141                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2704185411500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94428100000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     29235954750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  235236960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  128353500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 654115800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                415724400                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           184701363600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            80292349755                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1626277785750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1892704929765                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.308944                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2705344853000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94428100000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     28080129500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.57                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     141751                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95137                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.78                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.96                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9361444.26                       # Average gap between requests
+system.physmem.pageHitRate                      79.45                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  229201140                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  121823295                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 640515120                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                341711640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           5262547680.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             4339877970                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              323354400                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       10814226390                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        7334392800                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       667253476395                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             696663805260                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              246.248141                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           2818581671250                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      598120000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2237496000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   2775932271000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  19100075750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      7529604250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  23715377500                       # Time in different power states
+system.physmem_1.actEnergy                  208195260                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  110658405                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 582181320                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                320716800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           5105199840.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             4092887280                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              324388800                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       10096669920                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        7288782240                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       667807505910                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             695939317005                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              245.992058                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           2819287837500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      611681500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2171134000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   2778164795750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  18981177000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      7042291500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  22141864750                       # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst          112                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           112                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          112                       # Number of instructions bytes read from this memory
@@ -330,30 +347,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst           40
 system.realview.nvmem.bw_inst_read::total           40                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst           40                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              40                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46859222                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          23995015                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1174256                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29489294                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13535968                       # Number of BTB hits
+system.cpu.branchPred.lookups                46887151                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          24003532                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1173792                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29506695                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13539046                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             45.901296                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11745095                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              35189                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         7931554                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            7786304                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses           145250                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted        60170                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             45.884658                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11754270                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              34776                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         7941183                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            7796256                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses           144927                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        60295                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -383,83 +400,91 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                     72426                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                72426                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29716                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23400                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        19310                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        53116                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   407.485503                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2469.018740                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-8191        51917     97.74%     97.74% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-16383          937      1.76%     99.51% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-24575          190      0.36%     99.86% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-32767           37      0.07%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-40959           15      0.03%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-49151           16      0.03%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::49152-57343            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::57344-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        53116                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17396                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean  9637.387905                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  7803.906851                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  6813.601039                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383        15561     89.45%     89.45% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767         1740     10.00%     99.45% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-49151           86      0.49%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::49152-65535            2      0.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-81919            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::81920-98303            4      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::147456-163839            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::245760-262143            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17396                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 117727604724                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.629848                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.489627                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  117677681224     99.96%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      34838500      0.03%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       7318000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       4585500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9        935500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11       533500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13      1306000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15       397000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17         9500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 117727604724                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6471     81.85%     81.85% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1435     18.15%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7906                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72426                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                     71256                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                71256                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29049                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23358                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        18849                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        52407                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   389.146488                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2289.126746                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-4095        50564     96.48%     96.48% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::4096-8191          708      1.35%     97.83% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-12287          582      1.11%     98.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::12288-16383          319      0.61%     99.55% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-20479           67      0.13%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::20480-24575          114      0.22%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-28671           32      0.06%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::28672-32767            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-36863            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::36864-40959            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-45055            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::45056-49151            7      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::49152-53247            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        52407                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        16824                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean  9444.513790                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  7664.409790                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  6506.438101                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-8191         8278     49.20%     49.20% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::8192-16383         6918     41.12%     90.32% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-24575         1373      8.16%     98.48% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::24576-32767          165      0.98%     99.47% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-40959           22      0.13%     99.60% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::40960-49151           59      0.35%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::49152-57343            1      0.01%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::57344-65535            1      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-73727            1      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::90112-98303            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::98304-106495            4      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::114688-122879            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total        16824                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 118987489224                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.630928                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.488775                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  118941247224     99.96%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      32120500      0.03%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       6765500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       4407000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9        968000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       470000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13      1161500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       338000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17        11500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 118987489224                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6321     82.34%     82.34% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1356     17.66%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7677                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        71256                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72426                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7906                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        71256                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7677                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7906                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        80332                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7677                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        78933                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25423365                       # DTB read hits
-system.cpu.dtb.read_misses                      62664                       # DTB read misses
-system.cpu.dtb.write_hits                    19868926                       # DTB write hits
-system.cpu.dtb.write_misses                      9762                       # DTB write misses
+system.cpu.dtb.read_hits                     25423703                       # DTB read hits
+system.cpu.dtb.read_misses                      61573                       # DTB read misses
+system.cpu.dtb.write_hits                    19869711                       # DTB write hits
+system.cpu.dtb.write_misses                      9683                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4289                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       358                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2236                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4259                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       365                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2214                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1258                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25486029                       # DTB read accesses
-system.cpu.dtb.write_accesses                19878688                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1309                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25485276                       # DTB read accesses
+system.cpu.dtb.write_accesses                19879394                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45292291                       # DTB hits
-system.cpu.dtb.misses                           72426                       # DTB misses
-system.cpu.dtb.accesses                      45364717                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                          45293414                       # DTB hits
+system.cpu.dtb.misses                           71256                       # DTB misses
+system.cpu.dtb.accesses                      45364670                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -489,58 +514,51 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                     12855                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                12855                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3590                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         7693                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore         1572                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11283                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   605.778605                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  2805.757421                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-8191        10907     96.67%     96.67% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-16383          327      2.90%     99.57% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-24575           40      0.35%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-32767            5      0.04%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::40960-49151            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-73727            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::81920-90111            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11283                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         4887                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean  8961.019030                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  7007.167188                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7172.888707                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191         3327     68.08%     68.08% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383          829     16.96%     85.04% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575          682     13.96%     99.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::24576-32767           38      0.78%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-40959            1      0.02%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::40960-49151            7      0.14%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::49152-57343            1      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::81920-90111            2      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         4887                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  23237381212                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.774797                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.417824                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0      5234024500     22.52%     22.52% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     18002578212     77.47%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2          696500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3           46500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4           35500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  23237381212                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2980     89.89%     89.89% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           335     10.11%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3315                       # Table walker page sizes translated
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                     12694                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                12694                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3385                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7744                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore         1565                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11129                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   587.519094                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  2554.039533                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095        10635     95.56%     95.56% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::4096-8191          121      1.09%     96.65% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287          223      2.00%     98.65% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383          105      0.94%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479           19      0.17%     99.77% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575           20      0.18%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::28672-32767            4      0.04%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::40960-45055            2      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total        11129                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         4883                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean  9054.884292                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  7027.204830                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 11165.478993                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535         4881     99.96%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         4883                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  24497265712                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.701353                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.457724                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      7316690500     29.87%     29.87% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     17179912712     70.13%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2          662500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total  24497265712                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2983     89.90%     89.90% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           335     10.10%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3318                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12855                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        12855                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12694                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        12694                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3315                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3315                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        16170                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     66060204                       # ITB inst hits
-system.cpu.itb.inst_misses                      12855                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3318                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3318                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        16012                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     65985862                       # ITB inst hits
+system.cpu.itb.inst_misses                      12694                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -549,21 +567,21 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3013                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3015                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2175                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2167                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66073059                       # ITB inst accesses
-system.cpu.itb.hits                          66060204                       # DTB hits
-system.cpu.itb.misses                           12855                       # DTB misses
-system.cpu.itb.accesses                      66073059                       # DTB accesses
+system.cpu.itb.inst_accesses                 65998556                       # ITB inst accesses
+system.cpu.itb.hits                          65985862                       # DTB hits
+system.cpu.itb.misses                           12694                       # DTB misses
+system.cpu.itb.accesses                      65998556                       # DTB accesses
 system.cpu.numPwrStateTransitions                6076                       # Number of power state transitions
 system.cpu.pwrStateClkGateDist::samples          3038                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     887319797.866359                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    17420812025.908409                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     887100825.703094                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    17420756349.556362                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::underflows         2966     97.63%     97.63% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1000-5e+10           66      2.17%     99.80% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
@@ -571,91 +589,91 @@ system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.03%     99.87%
 system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.03%     99.90% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 499973328096                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 499972215488                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::total            3038                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    132175550082                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 2695677545918                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        264351157                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    134100636014                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2695012308486                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        268201326                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          105007140                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184198118                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46859222                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33067367                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     149125653                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6062128                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     177509                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 8064                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        342285                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       500656                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          149                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66059105                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1061874                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6140                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          258192520                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.869926                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.232240                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          105037035                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      183958233                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46887151                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33089572                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     151917777                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6065436                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     178887                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8852                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        338530                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       869885                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          153                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  65984793                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                962400                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5953                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          261383837                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.858435                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.227931                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                159207105     61.66%     61.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29153243     11.29%     72.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14041371      5.44%     78.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55790801     21.61%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                162469808     62.16%     62.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29156945     11.15%     73.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14047249      5.37%     78.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55709835     21.31%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            258192520                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.177261                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.696793                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 78121728                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             109293057                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64347286                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3858820                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2571629                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3404933                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                467397                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157054266                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3508469                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2571629                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83876272                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                10707182                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       75777880                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62454434                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              22805123                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146493829                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                914752                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                447933                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  65579                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  19295                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               20059867                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150297562                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             677265731                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164029738                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             11047                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141819290                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8478266                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2841903                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2646616                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13881588                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26350743                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21216202                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1694356                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2155521                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143287156                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2116266                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143106706                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            261772                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8147939                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14286308                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         122067                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     258192520                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.554264                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.878016                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            261383837                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.174821                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.685896                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 78154489                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             112430645                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64386105                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3839531                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2573067                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3403885                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                467719                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157074107                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3510025                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2573067                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83905287                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11250556                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       76371084                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62477293                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              24806550                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146503885                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                915767                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                476463                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  65809                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  19068                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               22053632                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150297963                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             677315873                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164027698                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             11061                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141834071                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8463886                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2844043                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2648878                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13862484                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26350148                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21217553                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1695311                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2061783                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143296271                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2116715                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143117357                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            261040                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8140399                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14276109                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         121662                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     261383837                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.547537                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.874444                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           169987358     65.84%     65.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45210540     17.51%     83.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            31907168     12.36%     95.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10268019      3.98%     99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              819402      0.32%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           173081384     66.22%     66.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45405843     17.37%     83.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            31801280     12.17%     95.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10272399      3.93%     99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              822898      0.31%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -663,44 +681,44 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       258192520                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       261383837                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7338606     32.76%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     32      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5623411     25.10%     57.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9440852     42.14%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7335509     32.77%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     32      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5621614     25.12%     57.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9424915     42.11%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              95896760     67.01%     67.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               115009      0.08%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95907816     67.01%     67.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               114378      0.08%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.09% # Type of FU issued
@@ -724,99 +742,99 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.09% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8592      0.01%     67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8550      0.01%     67.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26141404     18.27%     85.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            20942604     14.63%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26140422     18.27%     85.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            20943854     14.63%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143106706                       # Type of FU issued
-system.cpu.iq.rate                           0.541351                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22402901                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.156547                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          567034934                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         153556562                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140052264                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35671                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13288                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        11499                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165483986                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23284                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           324130                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              143117357                       # Type of FU issued
+system.cpu.iq.rate                           0.533619                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22382070                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156390                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          570225766                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         153558624                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140063898                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35895                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13316                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        11500                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              165473596                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23494                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           325086                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1434023                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses          698                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18538                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       619510                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1430934                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          704                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18603                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       620075                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        88631                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6598                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        88534                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6404                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2571629                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  994929                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                316385                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145584227                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2573067                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1155549                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                418674                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145593643                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26350743                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21216202                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1093451                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17658                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                280514                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18538                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         277676                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       470698                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               748374                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142207045                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25746206                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            827350                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26350148                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21217553                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1093742                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17678                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                382838                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18603                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         276771                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       470806                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               747577                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142219738                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25746846                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            826473                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        180805                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46576895                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26509940                       # Number of branches executed
-system.cpu.iew.exec_stores                   20830689                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.537948                       # Inst execution rate
-system.cpu.iew.wb_sent                      141837731                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140063763                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63261975                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95760288                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.529840                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660628                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         7362260                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1994199                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            714821                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    255299551                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.538232                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.139550                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        180657                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46578356                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26518178                       # Number of branches executed
+system.cpu.iew.exec_stores                   20831510                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.530272                       # Inst execution rate
+system.cpu.iew.wb_sent                      141851208                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140075398                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63278837                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95827539                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.522277                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660341                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         7356149                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995053                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            714141                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    258490005                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.531655                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.132637                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    181839086     71.23%     71.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43295063     16.96%     88.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15470047      6.06%     94.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4367483      1.71%     95.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6400805      2.51%     98.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1643674      0.64%     99.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       799411      0.31%     99.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       417134      0.16%     99.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1066848      0.42%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    184915208     71.54%     71.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43409459     16.79%     88.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15465173      5.98%     94.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4364887      1.69%     96.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6512039      2.52%     98.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1543037      0.60%     99.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       797927      0.31%     99.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       416081      0.16%     99.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1066194      0.41%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    255299551                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113310545                       # Number of instructions committed
-system.cpu.commit.committedOps              137410384                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    258490005                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113327954                       # Number of instructions committed
+system.cpu.commit.committedOps              137427488                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45513412                       # Number of memory references committed
-system.cpu.commit.loads                      24916720                       # Number of loads committed
-system.cpu.commit.membars                      814165                       # Number of memory barriers committed
-system.cpu.commit.branches                   26044798                       # Number of branches committed
+system.cpu.commit.refs                       45516692                       # Number of memory references committed
+system.cpu.commit.loads                      24919214                       # Number of loads committed
+system.cpu.commit.membars                      814556                       # Number of memory barriers committed
+system.cpu.commit.branches                   26054279                       # Number of branches committed
 system.cpu.commit.fp_insts                      11492                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120233477                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4891928                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120246700                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4895002                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91774855     66.79%     66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          113526      0.08%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91789332     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          112915      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
@@ -840,689 +858,689 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         8591      0.01%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         8549      0.01%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24916720     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20596692     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24919214     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20597478     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137410384                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1066848                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    376774257                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292425270                       # The number of ROB writes
-system.cpu.timesIdled                          893722                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         6158637                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5391355036                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113155640                       # Number of Instructions Simulated
-system.cpu.committedOps                     137255479                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.336173                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.336173                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.428050                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.428050                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155596461                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88540193                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9674                       # number of floating regfile reads
+system.cpu.commit.op_class_0::total         137427488                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1066194                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    379949809                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292448043                       # The number of ROB writes
+system.cpu.timesIdled                          895006                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         6817489                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5390024564                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113173049                       # Number of Instructions Simulated
+system.cpu.committedOps                     137272583                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.369834                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.369834                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.421971                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.421971                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155600043                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88544133                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9688                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502394909                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53149715                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               449419252                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1520020                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements            839084                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.954165                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40069527                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            839596                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.724771                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         270911500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.954165                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999910                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999910                       # Average percentage of cache occupancy
+system.cpu.cc_regfile_reads                 502437138                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53153343                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               452546223                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521066                       # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements            835143                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.950856                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40081033                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            835655                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.963613                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         291735500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.950856                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999904                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999904                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          360                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           29                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179200286                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179200286                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     23273566                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23273566                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15547100                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15547100                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       345314                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        345314                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441102                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441102                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       459566                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       459566                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38820666                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38820666                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39165980                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39165980                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       709196                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        709196                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3610101                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3610101                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177382                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177382                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        26835                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        26835                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4319297                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4319297                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4496679                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4496679                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  10317292500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  10317292500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 150336233192                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 150336233192                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    369753500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    369753500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       213000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       213000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 160653525692                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 160653525692                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 160653525692                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 160653525692                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23982762                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23982762                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19157201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19157201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       522696                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       522696                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       467937                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       467937                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       459571                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       459571                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43139963                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43139963                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43662659                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43662659                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029571                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029571                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188446                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.188446                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339360                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339360                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057347                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057347                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.100123                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.100123                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102987                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102987                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14547.871815                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14547.871815                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41643.220838                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41643.220838                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13778.777716                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13778.777716                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        42600                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        42600                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37194.368827                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37194.368827                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35727.150124                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35727.150124                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       590933                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses         179197279                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179197279                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     23277440                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23277440                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15552456                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15552456                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       346215                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        346215                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441873                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441873                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460172                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460172                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38829896                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38829896                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39176111                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39176111                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       703989                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        703989                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3604729                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3604729                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       176925                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       176925                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        26598                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        26598                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            4                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      4308718                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4308718                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4485643                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4485643                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11027261000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11027261000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 167170360202                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 167170360202                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    370603000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    370603000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       196000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       196000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 178197621202                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 178197621202                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 178197621202                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 178197621202                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23981429                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23981429                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19157185                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19157185                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       523140                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       523140                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468471                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       468471                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460176                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460176                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     43138614                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43138614                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43661754                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43661754                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029356                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029356                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188166                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.188166                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.338198                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.338198                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.056776                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.056776                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000009                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.099881                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.099881                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.102736                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.102736                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15663.967761                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15663.967761                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46375.292068                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 46375.292068                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13933.491240                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13933.491240                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        49000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        49000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41357.457416                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41357.457416                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39726.215662                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39726.215662                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       633494                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              7520                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              7037                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    78.581516                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    90.023305                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       696178                       # number of writebacks
-system.cpu.dcache.writebacks::total            696178                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       295013                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       295013                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3309632                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3309632                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18459                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18459                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3604645                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3604645                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3604645                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3604645                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414183                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       414183                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300469                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       300469                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119358                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119358                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8376                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8376                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       714652                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       714652                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       834010                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       834010                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks       694028                       # number of writebacks
+system.cpu.dcache.writebacks::total            694028                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       292192                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       292192                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3305480                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3305480                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18304                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18304                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3597672                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3597672                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3597672                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3597672                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       411797                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       411797                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299249                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       299249                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119132                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       119132                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8294                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8294                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            4                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       711046                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       711046                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       830178                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       830178                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31127                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31127                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5890415000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5890415000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13426039479                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  13426039479                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1622684000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1622684000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    130358500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    130358500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       208000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       208000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19316454479                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  19316454479                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20939138479                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  20939138479                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6279502000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6279502000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6279502000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6279502000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017270                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017270                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015684                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015684                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228351                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228351                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017900                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017900                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016566                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016566                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019101                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019101                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14221.769121                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14221.769121                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44683.609554                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44683.609554                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13595.100454                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13595.100454                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15563.335721                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15563.335721                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        41600                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        41600                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27029.175709                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 27029.175709                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25106.579632                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25106.579632                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201738.105182                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201738.105182                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.141098                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.141098                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           1887810                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.341026                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64075895                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1888322                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             33.932716                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       13715039500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.341026                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998713                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998713                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6168747500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6168747500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14918046982                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  14918046982                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1646074000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1646074000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126955500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126955500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       192000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       192000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21086794482                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  21086794482                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22732868482                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  22732868482                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6281936500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6281936500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6281936500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6281936500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017171                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017171                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015621                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015621                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227725                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227725                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017704                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017704                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016483                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016483                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019014                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019014                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14980.069063                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14980.069063                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49851.618492                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49851.618492                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13817.227949                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13817.227949                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15306.908609                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15306.908609                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        48000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        48000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29656.020120                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29656.020120                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27383.125645                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 27383.125645                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201816.317024                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201816.317024                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106997.606922                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106997.606922                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements           1888653                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.315245                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64000443                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1889165                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.877635                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       14109307500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.315245                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998663                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998663                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          164                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          221                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          162                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          217                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          67944454                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         67944454                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     64075895                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64075895                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64075895                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64075895                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64075895                       # number of overall hits
-system.cpu.icache.overall_hits::total        64075895                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1980206                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1980206                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1980206                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1980206                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1980206                       # number of overall misses
-system.cpu.icache.overall_misses::total       1980206                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  26984355494                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  26984355494                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  26984355494                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  26984355494                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  26984355494                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  26984355494                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66056101                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66056101                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66056101                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66056101                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66056101                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66056101                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029978                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029978                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029978                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029978                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029978                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029978                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13627.044607                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13627.044607                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13627.044607                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13627.044607                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13627.044607                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13627.044607                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         2643                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          67870984                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         67870984                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     64000443                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64000443                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64000443                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64000443                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     64000443                       # number of overall hits
+system.cpu.icache.overall_hits::total        64000443                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1981341                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1981341                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1981341                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1981341                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1981341                       # number of overall misses
+system.cpu.icache.overall_misses::total       1981341                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  27584584993                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  27584584993                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  27584584993                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  27584584993                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  27584584993                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  27584584993                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     65981784                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     65981784                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     65981784                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     65981784                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     65981784                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     65981784                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.030029                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.030029                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.030029                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.030029                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.030029                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.030029                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13922.179470                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13922.179470                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13922.179470                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13922.179470                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13922.179470                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13922.179470                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         3020                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               125                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               145                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    21.144000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    20.827586                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      1887810                       # number of writebacks
-system.cpu.icache.writebacks::total           1887810                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91852                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        91852                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        91852                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        91852                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        91852                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        91852                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1888354                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1888354                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1888354                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1888354                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1888354                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1888354                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3003                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3003                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  24226536497                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  24226536497                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  24226536497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  24226536497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  24226536497                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  24226536497                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    229048500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    229048500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    229048500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    229048500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028587                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028587                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028587                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028587                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028587                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028587                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12829.446437                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12829.446437                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12829.446437                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12829.446437                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12829.446437                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12829.446437                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76273.226773                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76273.226773                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76273.226773                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76273.226773                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           103423                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65159.012032                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5300281                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           168782                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            31.403118                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      93779484000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     9.961762                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     3.729813                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10177.791609                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 54967.528848                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000152                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000057                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.155301                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.838738                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.994248                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65345                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          175                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5571                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        59599                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000214                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997086                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         43992446                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        43992446                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        54341                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10212                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          64553                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       696178                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       696178                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1850381                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1850381                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         2757                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         2757                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       158824                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       158824                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1868353                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1868353                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       527348                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       527348                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        54341                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        10212                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1868353                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       686172                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2619078                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        54341                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        10212                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1868353                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       686172                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2619078                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           16                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total           22                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           11                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           11                       # number of UpgradeReq misses
+system.cpu.icache.writebacks::writebacks      1888653                       # number of writebacks
+system.cpu.icache.writebacks::total           1888653                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        92140                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        92140                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        92140                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        92140                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        92140                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        92140                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1889201                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1889201                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1889201                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1889201                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1889201                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1889201                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3009                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total         3009                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3009                       # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total         3009                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  24719841497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  24719841497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  24719841497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  24719841497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  24719841497                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  24719841497                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    246809500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    246809500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    246809500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    246809500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028632                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028632                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028632                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.028632                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028632                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.028632                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13084.812837                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13084.812837                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13084.812837                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13084.812837                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13084.812837                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13084.812837                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82023.762047                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82023.762047                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82023.762047                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82023.762047                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements            98099                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65152.234049                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5297886                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           163487                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            32.405549                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      91189853000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     7.921050                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     4.702137                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10408.149180                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 54731.461682                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000121                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000072                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.158816                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.835136                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994144                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65375                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5397                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        59667                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000198                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997543                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         43918819                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        43918819                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52413                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10038                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          62451                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       694028                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       694028                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1850699                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1850699                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         2792                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         2792                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       161486                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       161486                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1869293                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1869293                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       525699                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       525699                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        52413                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker        10038                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst      1869293                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       687185                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2618929                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        52413                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        10038                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      1869293                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       687185                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2618929                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           14                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            7                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total           21                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       139010                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       139010                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        19937                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        19937                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14436                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        14436                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           16                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        19937                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       153446                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        173405                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           16                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        19937                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       153446                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       173405                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      1497500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       502000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total      1999500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       320500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       320500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       167000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total       167000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  11275740500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  11275740500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1659086000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1659086000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1242944500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1242944500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      1497500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       502000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1659086000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  12518685000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  14179770500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      1497500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       502000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1659086000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  12518685000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  14179770500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        54357                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10218                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        64575                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       696178                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       696178                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1850381                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1850381                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2768                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2768                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       297834                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       297834                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1888290                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1888290                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       541784                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       541784                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        54357                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        10218                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1888290                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       839618                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2792483                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        54357                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        10218                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1888290                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       839618                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2792483                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000294                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000587                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000341                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.003974                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.003974                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.466737                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.466737                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010558                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010558                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026645                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026645                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000294                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000587                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010558                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.182757                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.062097                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000294                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000587                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010558                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.182757                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.062097                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93593.750000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83666.666667                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 90886.363636                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29136.363636                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29136.363636                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        83500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        83500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81114.599669                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81114.599669                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83216.431760                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83216.431760                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86100.339429                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86100.339429                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93593.750000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83666.666667                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83216.431760                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81583.651578                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81772.558461                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93593.750000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83666.666667                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83216.431760                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81583.651578                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81772.558461                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_misses::cpu.data       135095                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       135095                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        19848                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        19848                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        13395                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        13395                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           14                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker            7                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        19848                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       148490                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        168359                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           14                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            7                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        19848                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       148490                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       168359                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3912000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker      1698000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total      5610000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       143500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       143500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       164000                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::total       164000                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12742200000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  12742200000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2140966000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   2140966000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1561950000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1561950000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3912000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker      1698000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   2140966000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  14304150000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  16450726000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3912000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker      1698000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   2140966000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  14304150000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  16450726000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        52427                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10045                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        62472                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       694028                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       694028                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1850699                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1850699                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2797                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2797                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            4                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total            4                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       296581                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       296581                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1889141                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1889141                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       539094                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       539094                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        52427                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker        10045                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      1889141                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       835675                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2787288                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        52427                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker        10045                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1889141                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       835675                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2787288                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000267                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000697                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000336                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.001788                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.001788                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.455508                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.455508                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010506                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010506                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.024847                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024847                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000267                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000697                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010506                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.177689                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.060402                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000267                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000697                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010506                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.177689                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.060402                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 279428.571429                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 242571.428571                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 267142.857143                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        28700                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        28700                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        82000                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        82000                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94320.293127                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94320.293127                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107868.097541                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107868.097541                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 116606.942889                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 116606.942889                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 279428.571429                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 242571.428571                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107868.097541                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96330.729342                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 97712.186459                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 279428.571429                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 242571.428571                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107868.097541                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96330.729342                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 97712.186459                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        95172                       # number of writebacks
-system.cpu.l2cache.writebacks::total            95172                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           23                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           23                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          112                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          112                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           23                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          112                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          135                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           23                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          112                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          135                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           16                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total           22                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           11                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           11                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        90242                       # number of writebacks
+system.cpu.l2cache.writebacks::total            90242                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           25                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           25                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          113                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          113                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           25                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data          113                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          138                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           25                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data          113                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total          138                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           14                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total           21                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       139010                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       139010                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19914                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19914                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14324                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14324                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           16                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        19914                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       153334                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       173270                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           16                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        19914                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       153334                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       173270                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3003                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135095                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       135095                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19823                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19823                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13282                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13282                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           14                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        19823                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       148377                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       168221                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           14                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        19823                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       148377                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       168221                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3009                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31127                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34130                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34136                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3003                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3009                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61714                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1337500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       442000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      1779500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       210500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       210500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       147000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       147000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9885640500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9885640500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1458480000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1458480000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1091561500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1091561500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1337500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       442000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1458480000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10977202000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  12437461500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1337500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       442000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1458480000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10977202000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  12437461500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    191510500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5890404500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6081915000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    191510500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5890404500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6081915000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000294                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000587                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000341                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.003974                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.003974                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.466737                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.466737                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010546                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010546                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026439                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.026439                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000294                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000587                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010546                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.182624                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.062049                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000294                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000587                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010546                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.182624                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.062049                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73666.666667                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80886.363636                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19136.363636                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19136.363636                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        73500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        73500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71114.599669                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71114.599669                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73238.927388                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73238.927388                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76205.075398                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76205.075398                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73666.666667                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73238.927388                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.136565                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71780.813182                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73666.666667                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73238.927388                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.136565                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71780.813182                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63773.060273                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189237.783917                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178198.505713                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63773.060273                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100328.805505                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98550.004861                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      5488560                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2760615                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        44763                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          238                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          238                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61720                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3772000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker      1628000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      5400000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        93500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        93500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       144000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       144000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  11391250000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11391250000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1940936500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1940936500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1418400000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1418400000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3772000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker      1628000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1940936500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12809650000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  14755986500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3772000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker      1628000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1940936500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12809650000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  14755986500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    209196500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5892839000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6102035500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    209196500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5892839000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6102035500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000267                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000697                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000336                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.001788                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.001788                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.455508                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.455508                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010493                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010493                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024638                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024638                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000267                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000697                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010493                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177553                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060353                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000267                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000697                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010493                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177553                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060353                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 232571.428571                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 257142.857143                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        18700                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        18700                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        72000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        72000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84320.293127                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84320.293127                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97913.358220                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97913.358220                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 106791.145912                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 106791.145912                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 232571.428571                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97913.358220                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86331.776488                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87717.862217                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 232571.428571                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97913.358220                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86331.776488                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87717.862217                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69523.595879                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189315.995759                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178756.605929                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69523.595879                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100370.271329                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98866.420933                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      5483646                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2758798                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        45074                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          178                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          178                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq         129622                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2559974                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq         128774                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2557224                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       791350                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1887810                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       151157                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2768                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2773                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       297834                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       297834                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1888354                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       542004                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq         4368                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5670459                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2641503                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        29194                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       130873                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8472029                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241718384                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98487773                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       217428                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          340464457                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      139207                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               6232532                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      2995964                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.025358                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.157210                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty       784270                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1888653                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       148972                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2797                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            4                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2801                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296581                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296581                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1889201                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       539301                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq         4612                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5673012                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2629673                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        28918                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128192                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8459795                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241826896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98094045                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40180                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       209708                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          340170829                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      135300                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               5917976                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      2986955                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025939                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.158953                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2919992     97.46%     97.46% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              75972      2.54%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2909477     97.41%     97.41% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              77478      2.59%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2995964                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5405204997                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2986955                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5400390498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       383377                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       295626                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2836467127                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2837677759                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1305988986                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1300010143                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      18982487                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      18878489                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      76565899                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      75816896                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                30169                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30169                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
@@ -1545,9 +1563,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72914                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72914                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  178392                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72888                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72888                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178366                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
@@ -1568,22 +1586,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321096                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321096                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2480221                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             43094500                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2320992                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2320992                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480117                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             43090000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               325500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               326000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                28000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                91500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                91000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               649500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               649000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               20500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -1605,56 +1623,56 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6172500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6166500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            33854000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33827500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187760330                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187658622                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36738000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36712000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                36423                       # number of replacements
-system.iocache.tags.tagsinuse                1.000676                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements                36410                       # number of replacements
+system.iocache.tags.tagsinuse                1.001835                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36439                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36426                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         252706881000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.000676                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062542                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062542                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         253680812000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.001835                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062615                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062615                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328113                       # Number of tag accesses
-system.iocache.tags.data_accesses              328113                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide          233                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              233                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               327996                       # Number of tag accesses
+system.iocache.tags.data_accesses              327996                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.iocache.ReadReq_misses::realview.ide          220                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              220                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide        36457                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             36457                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide        36457                       # number of overall misses
-system.iocache.overall_misses::total            36457                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28964877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28964877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4277512453                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4277512453                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   4306477330                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4306477330                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   4306477330                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4306477330                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          233                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            233                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide        36444                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36444                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36444                       # number of overall misses
+system.iocache.overall_misses::total            36444                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     35726876                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     35726876                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4357072746                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4357072746                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4392799622                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4392799622                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4392799622                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4392799622                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          220                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            220                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide        36457                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           36457                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide        36457                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          36457                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36444                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36444                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36444                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36444                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1663,38 +1681,38 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124312.776824                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124312.776824                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.039007                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118085.039007                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 118124.841046                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 118124.841046                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 118124.841046                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 118124.841046                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 162394.890909                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 162394.890909                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120281.381018                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 120281.381018                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 120535.605916                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 120535.605916                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 120535.605916                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 120535.605916                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            10                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            5                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          233                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          233                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide          220                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          220                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide        36457                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        36457                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide        36457                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        36457                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17314877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17314877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2464212681                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2464212681                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   2481527558                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2481527558                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   2481527558                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2481527558                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide        36444                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36444                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36444                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36444                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     24726876                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     24726876                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2543825241                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2543825241                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2568552117                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2568552117                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2568552117                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2568552117                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1703,90 +1721,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74312.776824                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 74312.776824                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68027.072687                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68027.072687                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68067.245193                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68067.245193                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68067.245193                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68067.245193                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests        349590                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       144366                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          482                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112394.890909                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 112394.890909                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70224.857581                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70224.857581                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 70479.423691                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70479.423691                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 70479.423691                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70479.423691                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests        339259                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       139343                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          469                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               34130                       # Transaction distribution
-system.membus.trans_dist::ReadResp              68622                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               34136                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67481                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       131362                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8484                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              130                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       126432                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8077                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              126                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            138891                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           138891                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         34493                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            134974                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           134974                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         33346                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       465445                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       573007                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72895                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72895                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 645902                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450027                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       557589                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72869                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72869                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 630458                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          112                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17222620                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     17385997                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16583932                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16747309                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19703117                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              497                       # Total snoops (count)
-system.membus.snoopTraffic                      31680                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            271454                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.017933                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.132708                       # Request fanout histogram
+system.membus.pkt_size::total                19064429                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              484                       # Total snoops (count)
+system.membus.snoopTraffic                      30848                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            266392                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.019141                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.137021                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  266586     98.21%     98.21% # Request fanout histogram
-system.membus.snoop_fanout::1                    4868      1.79%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  261293     98.09%     98.09% # Request fanout histogram
+system.membus.snoop_fanout::1                    5099      1.91%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              271454                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            84464500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              266392                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            84425500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                9000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1723499                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1729999                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           908168519                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           876952960                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1012308500                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          984786250                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1273123                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1178374                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1818,29 +1836,29 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500                       # Cumulative time (in ticks) in various power states
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     3038                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
index ce640090c..bcf1aa128 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
@@ -36,7 +36,7 @@ load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM64
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -208,7 +208,7 @@ useIndirect=true
 [system.cpu0.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -688,7 +688,7 @@ opClass=InstPrefetch
 [system.cpu0.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -748,7 +748,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -820,7 +820,7 @@ port=system.cpu0.toL2Bus.slave[2]
 [system.cpu0.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -1024,7 +1024,7 @@ useIndirect=true
 [system.cpu1.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1504,7 +1504,7 @@ opClass=InstPrefetch
 [system.cpu1.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1564,7 +1564,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -1636,7 +1636,7 @@ port=system.cpu1.toL2Bus.slave[2]
 [system.cpu1.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -1783,7 +1783,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -1829,7 +1829,7 @@ size=1024
 [system.l2c]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1927,27 +1927,27 @@ system=system
 
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -1967,6 +1967,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -1976,7 +1977,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1998,9 +1999,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -2353,7 +2354,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -2666,10 +2667,11 @@ pio=system.iobus.master[21]
 type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
-conf_table_reported=true
+conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -2677,7 +2679,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -2908,6 +2910,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -2915,7 +2918,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout
index 2aa1c9ae0..d0bf1da85 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 15:03:52
-gem5 executing on e108600-lin, pid 24173
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:43:00
+gem5 executing on e108600-lin, pid 17333
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor-dual
 
 Selected 64-bit ARM architecture, updating default disk image...
@@ -15,4 +15,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 47445489241000 because m5_exit instruction encountered
+Exiting @ tick 47554910274000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index 539176c94..202c4ef0d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -1,170 +1,170 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.276773                       # Number of seconds simulated
-sim_ticks                                47276772827000                       # Number of ticks simulated
-final_tick                               47276772827000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.554910                       # Number of seconds simulated
+sim_ticks                                47554910274000                       # Number of ticks simulated
+final_tick                               47554910274000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 146674                       # Simulator instruction rate (inst/s)
-host_op_rate                                   172507                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7728246229                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 772984                       # Number of bytes of host memory used
-host_seconds                                  6117.40                       # Real time elapsed on the host
-sim_insts                                   897262562                       # Number of instructions simulated
-sim_ops                                    1055295890                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 172972                       # Simulator instruction rate (inst/s)
+host_op_rate                                   203472                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9377554592                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 769556                       # Number of bytes of host memory used
+host_seconds                                  5071.14                       # Real time elapsed on the host
+sim_insts                                   877166784                       # Number of instructions simulated
+sim_ops                                    1031833041                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker       117376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        90560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          7953664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         13400200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     16005120                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       165760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       157376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3942400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         13075216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     14708224                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        454784                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             70070680                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      7953664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3942400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        11896064                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     81443392                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker       127616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       113728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          7300032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         13854920                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     13786176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       105536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        93440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3887680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          9545552                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     11958848                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        442112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             61215640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      7300032                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3887680                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        11187712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     74339904                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          81463976                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1834                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1415                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            124276                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            209391                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       250080                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2590                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2459                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             61600                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            204313                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       229816                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           7106                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1094880                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1272553                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          74360488                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1994                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1777                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            114063                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            216496                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       215409                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1649                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1460                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             60745                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            149162                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       186857                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6908                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                956520                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1161561                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1275127                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2483                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1916                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              168236                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              283442                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       338541                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3506                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          3329                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               83390                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              276567                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       311109                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9620                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1482138                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         168236                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          83390                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             251626                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1722694                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                435                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1164135                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2684                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2392                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              153507                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              291346                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       289900                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2219                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          1965                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               81751                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              200727                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       251475                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9297                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1287262                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         153507                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          81751                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             235259                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1563243                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1723129                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1722694                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2483                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1916                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             168236                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             283877                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       338541                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3506                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         3329                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              83390                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             276568                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       311109                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9620                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3205266                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1094880                       # Number of read requests accepted
-system.physmem.writeReqs                      1275127                       # Number of write requests accepted
-system.physmem.readBursts                     1094880                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1275127                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 70042240                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     30080                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  81461504                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  70070680                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               81463976                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      470                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2260                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1563676                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1563243                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2684                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2392                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             153507                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             291778                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       289900                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2219                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         1965                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              81751                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             200727                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       251475                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9297                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2850939                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        956520                       # Number of read requests accepted
+system.physmem.writeReqs                      1164135                       # Number of write requests accepted
+system.physmem.readBursts                      956520                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1164135                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 61192448                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     24832                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  74357824                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  61215640                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               74360488                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      388                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2263                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               60604                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               71691                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               59265                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               66946                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               67906                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               80109                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               61949                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               69447                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               60494                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              115448                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              56514                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              69665                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              63387                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              66346                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              64421                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              60218                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               77101                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               84577                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               74746                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               81276                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               79990                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               87328                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               77464                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               81707                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               78209                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               81569                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              73819                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              80687                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              78674                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              80970                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              77560                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              77159                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               50657                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               60930                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               49716                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               55090                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               56536                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               68947                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               58003                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               60908                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               53263                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              106420                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              50504                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              59458                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              56712                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              60494                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              55357                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              53137                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               68064                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               74120                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               68663                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               72095                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               73476                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               80505                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               71958                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               74882                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               69253                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               72875                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              68876                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              75926                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              72095                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              75544                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              71950                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              71559                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          62                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47276770796500                       # Total gap between requests
+system.physmem.numWrRetry                         408                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47554908178500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1094850                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  956490                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1272553                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    725931                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    132585                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     49587                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     38066                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     32959                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     30077                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     28140                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     24582                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     22148                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4123                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1854                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1222                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      970                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      697                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      398                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      328                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      280                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      226                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      134                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       85                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1161561                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    589555                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    157739                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     46445                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     36293                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     27945                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     25583                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     23391                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     20914                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     18402                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      4361                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1587                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1163                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      874                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      609                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      336                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      287                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      249                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      205                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      102                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       84                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -189,172 +189,188 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    26459                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    34937                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    52906                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    61188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    67814                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    70802                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    73289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    75619                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    78304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    78281                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    81577                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    85157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    81436                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    80619                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    87129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    77597                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    71470                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    67901                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     3383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     2425                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1908                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1516                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      902                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      564                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      462                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      470                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      380                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      357                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      412                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      412                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      339                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      296                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      225                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      212                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1013795                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      149.441747                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     100.507639                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     197.056675                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         662057     65.30%     65.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       208347     20.55%     85.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        52181      5.15%     91.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23884      2.36%     93.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        17639      1.74%     95.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11113      1.10%     96.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7357      0.73%     96.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         6249      0.62%     97.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        24968      2.46%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1013795                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         63452                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        17.247415                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      156.483425                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          63450    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    24143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    31849                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    48338                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    55864                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    61058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    64206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    66032                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    67782                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    70569                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    70728                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    73352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    74938                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    72063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    70410                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    71450                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    74135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    66609                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    62837                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     4834                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2922                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2290                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1924                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1530                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1398                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      863                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      908                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      855                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      896                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      762                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      737                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      763                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      757                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      750                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      714                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      687                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      740                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      794                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      717                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      562                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      748                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                     1309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                     1089                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      448                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      933                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       917155                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      147.793592                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      99.753334                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     195.501852                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         602356     65.68%     65.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       188931     20.60%     86.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        45653      4.98%     91.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20839      2.27%     93.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        15350      1.67%     95.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         9574      1.04%     96.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         6849      0.75%     96.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5486      0.60%     97.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22117      2.41%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         917155                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         56545                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        16.908586                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      165.794592                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          56543    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::29696-30719            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           63452                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         63452                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.059825                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.482738                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.878895                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           55385     87.29%     87.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            2264      3.57%     90.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             727      1.15%     92.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             608      0.96%     92.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35            1019      1.61%     94.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             457      0.72%     95.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             338      0.53%     95.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             295      0.46%     96.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             198      0.31%     96.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             179      0.28%     96.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59             127      0.20%     97.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63             154      0.24%     97.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             464      0.73%     98.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71             118      0.19%     98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75             142      0.22%     98.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             119      0.19%     98.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              89      0.14%     98.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              71      0.11%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91              72      0.11%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              80      0.13%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             103      0.16%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103            73      0.12%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107            46      0.07%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111            54      0.09%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115            48      0.08%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119            39      0.06%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123            53      0.08%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127            25      0.04%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            49      0.08%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135            20      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139            13      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             6      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             6      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-243             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           63452                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    38795138463                       # Total ticks spent queuing
-system.physmem.totMemAccLat               59315325963                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5472050000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       35448.45                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           56545                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         56545                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.547193                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.712168                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.106429                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           48673     86.08%     86.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            2227      3.94%     90.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             713      1.26%     91.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             569      1.01%     92.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             930      1.64%     93.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             406      0.72%     94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             286      0.51%     95.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             280      0.50%     95.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             183      0.32%     95.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             127      0.22%     96.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59             115      0.20%     96.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63             143      0.25%     96.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             579      1.02%     97.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71             140      0.25%     97.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75             130      0.23%     98.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             128      0.23%     98.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             106      0.19%     98.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              75      0.13%     98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91              85      0.15%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              94      0.17%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              75      0.13%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103            62      0.11%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            61      0.11%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            71      0.13%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            39      0.07%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119            37      0.07%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            45      0.08%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127            34      0.06%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            51      0.09%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135            18      0.03%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139            12      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143            17      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             4      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             3      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             3      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             3      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           56545                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    49127716705                       # Total ticks spent queuing
+system.physmem.totMemAccLat               67055191705                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4780660000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       51381.73                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  54198.45                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.48                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.72                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.48                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.72                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  70131.73                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.29                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.56                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.57                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     817920                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    535530                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.74                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  42.07                       # Row buffer hit rate for writes
-system.physmem.avgGap                     19947945.64                       # Average gap between requests
-system.physmem.pageHitRate                      57.17                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 3880003680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2117065500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4195752600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4174344720                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3087888847680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1190314271070                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27321927289500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31614497574750                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.711016                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45452122728628                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1578675280000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    245973030122                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3784278960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2064834750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4340583000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4073632560                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3087888847680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1186461286245                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27325307092500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31613920555695                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.698811                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45457733356018                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1578675280000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    240362584982                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.physmem.avgRdQLen                         1.24                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.69                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     713884                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    486930                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   74.66                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.91                       # Row buffer hit rate for writes
+system.physmem.avgGap                     22424632.10                       # Average gap between requests
+system.physmem.pageHitRate                      56.70                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3312517320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1760633325                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3290019180                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3047242860                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           39654114240.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            43514746200                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             2086179840                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       77547983010                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       55697482080                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       11319929946090                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             11549857795695                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              242.874137                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           47454012976233                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     3696049077                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     16847240000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   47138905885000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 145045339612                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     80353958440                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 170061801871                       # Time in different power states
+system.physmem_1.actEnergy                 3235997940                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1719969900                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3536763300                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3017567160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           38496747120.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            44079949650                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             2012350560                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       72751641060                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       54144086400                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       11323086477345                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             11546099446905                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              242.795105                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           47452962329328                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     3512995347                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     16356664000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   47152420144750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 141000345458                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     82076677575                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 159543446870                       # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          640                       # Number of bytes read from this memory
@@ -370,41 +386,41 @@ system.realview.nvmem.num_reads::cpu1.data            1                       #
 system.realview.nvmem.num_reads::total             27                       # Number of read requests responded to by this memory
 system.realview.nvmem.bw_read::cpu0.inst           15                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           14                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           13                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::total               29                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu0.inst           15                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           13                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::total           28                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst           15                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           14                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           13                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              29                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              132137665                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         93617551                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5999845                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            98810350                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               69427031                       # Number of BTB hits
+system.cpu0.branchPred.lookups              137627857                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         96352530                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6353129                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups           102612546                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               71378761                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            70.262914                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               15260285                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect           1044115                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        3387017                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           2259695                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses         1127322                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted       409659                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            69.561436                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               16463463                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect           1088270                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        3669510                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           2436336                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         1233174                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       447439                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -434,64 +450,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                   271762                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               271762                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10351                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        74846                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples       271762                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         271762    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       271762                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        85197                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23819.195512                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 22123.263295                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 14060.055266                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535        84296     98.94%     98.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          776      0.91%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607           35      0.04%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           41      0.05%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           35      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        85197                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples    734573704                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0      734573704    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total    734573704                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        74846     87.85%     87.85% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        10351     12.15%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        85197                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       271762                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                   282889                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               282889                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         9418                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        82700                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples       282889                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         282889    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       282889                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        92118                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 24516.006644                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 22528.646157                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 18042.498572                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535        90947     98.73%     98.73% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          867      0.94%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          159      0.17%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           56      0.06%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           44      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           20      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359           17      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        92118                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples   1049600704                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     1049600704    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total   1049600704                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        82700     89.78%     89.78% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M         9418     10.22%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        92118                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       282889                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       271762                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        85197                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       282889                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        92118                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        85197                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       356959                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        92118                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       375007                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    82756248                       # DTB read hits
-system.cpu0.dtb.read_misses                    224730                       # DTB read misses
-system.cpu0.dtb.write_hits                   74117187                       # DTB write hits
-system.cpu0.dtb.write_misses                    47032                       # DTB write misses
+system.cpu0.dtb.read_hits                    87675894                       # DTB read hits
+system.cpu0.dtb.read_misses                    234519                       # DTB read misses
+system.cpu0.dtb.write_hits                   78239753                       # DTB write hits
+system.cpu0.dtb.write_misses                    48370                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              42591                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1052                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   34573                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     2108                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9506                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              40666                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   38151                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     2038                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  9397                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    11030                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                82980978                       # DTB read accesses
-system.cpu0.dtb.write_accesses               74164219                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    11689                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                87910413                       # DTB read accesses
+system.cpu0.dtb.write_accesses               78288123                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        156873435                       # DTB hits
-system.cpu0.dtb.misses                         271762                       # DTB misses
-system.cpu0.dtb.accesses                    157145197                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                        165915647                       # DTB hits
+system.cpu0.dtb.misses                         282889                       # DTB misses
+system.cpu0.dtb.accesses                    166198536                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -521,906 +539,899 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    60398                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                60398                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          589                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        51882                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        60398                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          60398    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        60398                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        52471                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 25793.819443                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 24019.609428                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 15089.787613                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767        46836     89.26%     89.26% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535         4750      9.05%     98.31% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303           22      0.04%     98.36% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071          772      1.47%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839           22      0.04%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607           15      0.03%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375           26      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143            9      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447            9      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        52471                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples    733851204                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0      733851204    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total    733851204                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        51882     98.88%     98.88% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          589      1.12%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        52471                       # Table walker page sizes translated
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                    69273                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                69273                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          583                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        61330                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        69273                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          69273    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        69273                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        61913                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 26255.972090                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 24021.087370                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 22669.077424                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        60695     98.03%     98.03% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071          852      1.38%     99.41% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          248      0.40%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           49      0.08%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           14      0.02%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           11      0.02%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751            4      0.01%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            1      0.00%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359           39      0.06%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        61913                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples   1048830204                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     1048830204    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total   1048830204                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        61330     99.06%     99.06% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          583      0.94%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        61913                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        60398                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        60398                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        69273                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        69273                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52471                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52471                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       112869                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   234456044                       # ITB inst hits
-system.cpu0.itb.inst_misses                     60398                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        61913                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        61913                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       131186                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   244690597                       # ITB inst hits
+system.cpu0.itb.inst_misses                     69273                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              42591                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1052                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   24118                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              40666                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   27059                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   160109                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   167788                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               234516442                       # ITB inst accesses
-system.cpu0.itb.hits                        234456044                       # DTB hits
-system.cpu0.itb.misses                          60398                       # DTB misses
-system.cpu0.itb.accesses                    234516442                       # DTB accesses
-system.cpu0.numPwrStateTransitions               8178                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         4089                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    11447226771.455124                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   162386644618.467285                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         2836     69.36%     69.36% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         1230     30.08%     99.44% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.02%     99.46% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            2      0.05%     99.51% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            2      0.05%     99.56% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11            1      0.02%     99.58% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.02%     99.61% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            1      0.02%     99.63% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11            1      0.02%     99.66% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows           14      0.34%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses               244759870                       # ITB inst accesses
+system.cpu0.itb.hits                        244690597                       # DTB hits
+system.cpu0.itb.misses                          69273                       # DTB misses
+system.cpu0.itb.accesses                    244759870                       # DTB accesses
+system.cpu0.numPwrStateTransitions              27904                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples        13952                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    3372797482.084218                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   110921496988.059006                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         3863     27.69%     27.69% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10        10067     72.15%     99.84% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11           11      0.08%     99.92% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.93% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.94% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11            1      0.01%     99.94% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows            8      0.06%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 7470355608744                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           4089                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   469062558520                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 46807710268480                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       938130839                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 7351146409252                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total          13952                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   497639803961                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 47057270470039                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       995321471                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  430200528                       # Number of instructions committed
-system.cpu0.committedOps                    505771410                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                     45690974                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     3904                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                 93616054941                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.180683                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.458572                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  452001209                       # Number of instructions committed
+system.cpu0.committedOps                    531851100                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                     46239027                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     5092                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                 94115325169                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.202033                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.454126                       # IPC: instructions per cycle
 system.cpu0.op_class_0::No_OpClass                  1      0.00%      0.00% # Class of committed instruction
-system.cpu0.op_class_0::IntAlu              351125189     69.42%     69.42% # Class of committed instruction
-system.cpu0.op_class_0::IntMult               1073769      0.21%     69.64% # Class of committed instruction
-system.cpu0.op_class_0::IntDiv                  52983      0.01%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::FloatAdd                    0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::FloatCmp                    0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::FloatCvt                    0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::FloatMult                   0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::FloatDiv                    0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::FloatSqrt                   0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdAdd                     0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdAlu                     0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdCmp                     0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdCvt                     0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdMisc                    0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdMult                    0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdShift                   0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdSqrt                    0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatAdd                8      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatCmp               13      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatCvt               21      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     69.65% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMisc           68782      0.01%     69.66% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMult               0      0.00%     69.66% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     69.66% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     69.66% # Class of committed instruction
-system.cpu0.op_class_0::MemRead              79655364     15.75%     85.41% # Class of committed instruction
-system.cpu0.op_class_0::MemWrite             73795280     14.59%    100.00% # Class of committed instruction
+system.cpu0.op_class_0::IntAlu              368287155     69.25%     69.25% # Class of committed instruction
+system.cpu0.op_class_0::IntMult               1118982      0.21%     69.46% # Class of committed instruction
+system.cpu0.op_class_0::IntDiv                  57276      0.01%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::FloatAdd                    0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::FloatCmp                    0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::FloatCvt                    0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::FloatMult                   0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::FloatDiv                    0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::FloatSqrt                   0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdAdd                     0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdAlu                     0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdCmp                     0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdCvt                     0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdMisc                    0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdMult                    0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdShift                   0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdSqrt                    0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAdd                8      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCmp               13      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCvt               21      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     69.47% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMisc           85306      0.02%     69.48% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMult               0      0.00%     69.48% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     69.48% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     69.48% # Class of committed instruction
+system.cpu0.op_class_0::MemRead              84402084     15.87%     85.35% # Class of committed instruction
+system.cpu0.op_class_0::MemWrite             77900254     14.65%    100.00% # Class of committed instruction
 system.cpu0.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
 system.cpu0.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
-system.cpu0.op_class_0::total               505771410                       # Class of committed instruction
+system.cpu0.op_class_0::total               531851100                       # Class of committed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    4089                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      697846091                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                      240284748                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          5497391                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          500.377946                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          148839422                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5497903                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.072035                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       5039429000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   500.377946                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.977301                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.977301                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                   13952                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      729574114                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                      265747357                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements          5787900                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          490.209920                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          157471988                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5788412                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.204696                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       5354308000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   490.209920                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.957441                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.957441                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          383                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          397                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        316768421                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       316768421                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     75978032                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       75978032                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     68482955                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      68482955                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       264842                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       264842                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       244065                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       244065                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1687572                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1687572                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1654235                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1654235                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    144705052                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       144705052                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    144969894                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      144969894                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3066734                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3066734                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      2419958                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2419958                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       670609                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       670609                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       786129                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       786129                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       148878                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       148878                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       181031                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       181031                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      6272821                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       6272821                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      6943430                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      6943430                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  47243422000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  47243422000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  49248110500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  49248110500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  26231986000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  26231986000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2187373500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2187373500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4323764500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4323764500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2754000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2754000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 122723518500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 122723518500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 122723518500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 122723518500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     79044766                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     79044766                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     70902913                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     70902913                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       935451                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       935451                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1030194                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1030194                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1836450                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      1836450                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1835266                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1835266                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    150977873                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    150977873                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    151913324                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    151913324                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.038797                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.038797                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.034131                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.034131                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.716883                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.716883                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.763088                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.763088                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.081068                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.081068                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098640                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098640                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.041548                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.041548                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.045707                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.045707                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15405.125453                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15405.125453                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20350.812080                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 20350.812080                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33368.551472                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33368.551472                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14692.389070                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14692.389070                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23884.111009                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23884.111009                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses        334937152                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       334937152                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     80549957                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       80549957                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     72496805                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      72496805                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       269794                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       269794                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       177007                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       177007                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1734640                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1734640                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1715473                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1715473                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    153223769                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       153223769                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    153493563                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      153493563                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3263198                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3263198                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      2445366                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2445366                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       673099                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       673099                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       844507                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       844507                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       169054                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       169054                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       187078                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       187078                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      6553071                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       6553071                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      7226170                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      7226170                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  52395902500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  52395902500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  52490790500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  52490790500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  27335813500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  27335813500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2555333500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2555333500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4463485500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4463485500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2023000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2023000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 132222506500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 132222506500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 132222506500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 132222506500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     83813155                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     83813155                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     74942171                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     74942171                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       942893                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       942893                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1021514                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1021514                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1903694                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1903694                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1902551                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1902551                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    159776840                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    159776840                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    160719733                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    160719733                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.038934                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.038934                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.032630                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.032630                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.713866                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.713866                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.826721                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.826721                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088803                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088803                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098330                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098330                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.041014                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.041014                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.044961                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.044961                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16056.611490                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 16056.611490                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21465.412744                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 21465.412744                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32368.960234                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32368.960234                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15115.486768                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15115.486768                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23858.954554                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23858.954554                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19564.326561                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19564.326561                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17674.768594                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17674.768594                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20177.182042                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 20177.182042                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18297.729849                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 18297.729849                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      5497393                       # number of writebacks
-system.cpu0.dcache.writebacks::total          5497393                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       200047                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       200047                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1012976                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1012976                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           94                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total           94                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        39271                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        39271                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           90                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total           90                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1213117                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1213117                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1213117                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1213117                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2866687                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2866687                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1406982                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1406982                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       668415                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       668415                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       786035                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       786035                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       109607                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       109607                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       180941                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       180941                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      5059704                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      5059704                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5728119                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5728119                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20634                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20634                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        22275                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        22275                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        42909                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        42909                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  39457015000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  39457015000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  27671793000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  27671793000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  15966528000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  15966528000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  25439405000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  25439405000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1452927000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1452927000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4140525000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4140525000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2476500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2476500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  92568213000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  92568213000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108534741000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 108534741000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4015086500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4015086500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4015086500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4015086500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036267                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036267                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019844                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019844                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.714538                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.714538                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.762997                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.762997                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059684                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059684                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098591                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098591                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.033513                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.033513                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.037706                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.037706                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13763.977372                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13763.977372                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19667.481887                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19667.481887                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23887.147954                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23887.147954                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32364.214062                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32364.214062                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13255.786583                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13255.786583                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22883.287923                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22883.287923                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      5787917                       # number of writebacks
+system.cpu0.dcache.writebacks::total          5787917                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       205447                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       205447                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1015907                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1015907                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           99                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total           99                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        45884                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        45884                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           37                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::total           37                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1221453                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1221453                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1221453                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1221453                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3057751                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3057751                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1429459                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1429459                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       670780                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       670780                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       844408                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       844408                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       123170                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       123170                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       187041                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       187041                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      5331618                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      5331618                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      6002398                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      6002398                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31212                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31212                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        30755                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        30755                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        61967                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        61967                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  44254087500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  44254087500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  29600010500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  29600010500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  15858321000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  15858321000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  26484603000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  26484603000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1676878500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1676878500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4275603000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4275603000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1773000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1773000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 100338701000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 100338701000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116197022000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 116197022000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6038825000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6038825000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6038825000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6038825000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036483                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036483                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019074                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019074                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.711406                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.711406                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.826624                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.826624                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064701                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064701                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098311                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098311                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.033369                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.033369                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.037347                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.037347                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14472.757102                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14472.757102                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20707.142003                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20707.142003                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23641.612749                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23641.612749                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31364.699292                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31364.699292                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13614.341966                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13614.341966                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22859.175261                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22859.175261                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18295.183473                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18295.183473                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.710584                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.710584                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194585.950373                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194585.950373                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93572.129390                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93572.129390                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          9280608                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.932285                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          225009210                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          9281120                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            24.243756                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      22204306000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.932285                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999868                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999868                       # Average percentage of cache occupancy
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18819.559278                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18819.559278                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19358.433413                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19358.433413                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193477.668845                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193477.668845                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97452.272984                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97452.272984                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          9773833                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.928996                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          234741496                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          9774345                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            24.016085                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      22886662000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.928996                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999861                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999861                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          312                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           79                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          368                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           45                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        477861809                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       477861809                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    225009210                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      225009210                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    225009210                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       225009210                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    225009210                       # number of overall hits
-system.cpu0.icache.overall_hits::total      225009210                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      9281130                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      9281130                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      9281130                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       9281130                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      9281130                       # number of overall misses
-system.cpu0.icache.overall_misses::total      9281130                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  94226606500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  94226606500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  94226606500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  94226606500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  94226606500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  94226606500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    234290340                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    234290340                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    234290340                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    234290340                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    234290340                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    234290340                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039614                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.039614                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039614                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.039614                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039614                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.039614                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10152.492908                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10152.492908                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10152.492908                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10152.492908                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10152.492908                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10152.492908                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        498806059                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       498806059                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst    234741496                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      234741496                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    234741496                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       234741496                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    234741496                       # number of overall hits
+system.cpu0.icache.overall_hits::total      234741496                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      9774356                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      9774356                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      9774356                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       9774356                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      9774356                       # number of overall misses
+system.cpu0.icache.overall_misses::total      9774356                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  99441985000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  99441985000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  99441985000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  99441985000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  99441985000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  99441985000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    244515852                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    244515852                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    244515852                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    244515852                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    244515852                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    244515852                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039974                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.039974                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039974                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.039974                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039974                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.039974                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10173.763366                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10173.763366                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10173.763366                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10173.763366                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10173.763366                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10173.763366                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      9280608                       # number of writebacks
-system.cpu0.icache.writebacks::total          9280608                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9281130                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      9281130                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      9281130                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      9281130                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      9281130                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      9281130                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52300                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total        52300                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52300                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total        52300                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  89586042000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  89586042000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  89586042000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  89586042000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  89586042000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  89586042000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4836784500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4836784500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4836784500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   4836784500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039614                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039614                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039614                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.039614                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039614                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.039614                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9652.492962                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9652.492962                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9652.492962                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9652.492962                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9652.492962                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9652.492962                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92481.539197                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92481.539197                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7507862                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7509065                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         1069                       # number of redundant prefetches already in prefetch queue
+system.cpu0.icache.writebacks::writebacks      9773833                       # number of writebacks
+system.cpu0.icache.writebacks::total          9773833                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9774356                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      9774356                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      9774356                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      9774356                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      9774356                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      9774356                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52284                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total        52284                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52284                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total        52284                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  94554807500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  94554807500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  94554807500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  94554807500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  94554807500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  94554807500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5161606000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5161606000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   5161606000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   5161606000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039974                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039974                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039974                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.039974                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039974                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.039974                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9673.763417                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9673.763417                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9673.763417                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9673.763417                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9673.763417                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9673.763417                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98722.477240                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98722.477240                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7608993                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7610336                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         1188                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       942183                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements         2584098                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       15590.889787                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          13248667                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2600019                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            5.095604                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle      5661168000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15296.249521                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    39.752726                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    22.010194                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   232.877346                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.933609                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002426                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001343                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.014214                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.951592                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022          376                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           68                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15477                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           12                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           15                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          104                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          124                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          121                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           21                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           33                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1649                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4407                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5650                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3577                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.022949                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004150                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.944641                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       507607175                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      507607175                       # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       496900                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       154788                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        651688                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks      3675506                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      3675506                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks     11099665                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total     11099665                       # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       891359                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       891359                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8598093                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      8598093                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2690347                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      2690347                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       202108                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       202108                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       496900                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       154788                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      8598093                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3581706                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       12831487                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       496900                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       154788                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      8598093                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3581706                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      12831487                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        19803                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         9619                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        29422                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       245426                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       245426                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       180938                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       180938                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       278613                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       278613                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       683036                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       683036                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       953863                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       953863                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       581978                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       581978                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        19803                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         9619                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       683036                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1232476                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1944934                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        19803                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         9619                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       683036                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1232476                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1944934                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    614702000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    331371000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total    946073000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    874372000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    874372000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    295339000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    295339000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2383999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2383999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  13650875999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  13650875999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  23732034500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  23732034500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  33660637494                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  33660637494                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    333947500                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total    333947500                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    614702000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    331371000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  23732034500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  47311513493                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  71989620993                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    614702000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    331371000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  23732034500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  47311513493                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  71989620993                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       516703                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       164407                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       681110                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3675506                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total      3675506                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks     11099665                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total     11099665                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       245426                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       245426                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       180938                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       180938                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1169972                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1169972                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      9281129                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      9281129                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3644210                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      3644210                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       784086                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       784086                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       516703                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       164407                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      9281129                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      4814182                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     14776421                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       516703                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       164407                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      9281129                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      4814182                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     14776421                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.038326                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.058507                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.043197                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.prefetcher.pfSpanPage      1005416                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.tags.replacements         2646552                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15691.473570                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          14028250                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2662377                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            5.269070                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle      5985886000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15348.189818                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    32.039011                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     8.868609                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   302.376132                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.936779                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.001956                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000541                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.018456                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.957732                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          352                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           63                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15410                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            7                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          163                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3           65                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          117                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           37                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           24                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1727                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         6563                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4041                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2911                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.021484                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003845                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.940552                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       534452534                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      534452534                       # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       527649                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       180298                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        707947                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks      3832122                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total      3832122                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks     11726658                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total     11726658                       # number of WritebackClean hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data            1                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       904488                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       904488                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      9076171                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      9076171                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2875219                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      2875219                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       241369                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       241369                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       527649                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       180298                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      9076171                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      3779707                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total       13563825                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       527649                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       180298                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      9076171                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3779707                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      13563825                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        21665                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        10120                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        31785                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       246294                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       246294                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       187036                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       187036                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       286789                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       286789                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       698184                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       698184                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       976175                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       976175                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       601118                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       601118                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        21665                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker        10120                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       698184                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1262964                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      1992933                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        21665                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker        10120                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       698184                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1262964                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      1992933                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    696360500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    404225000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total   1100585500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    910928500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    910928500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    289294500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    289294500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1705497                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1705497                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  15428607998                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  15428607998                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  25059292500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  25059292500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  37051733995                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  37051733995                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    336301500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total    336301500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    696360500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    404225000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  25059292500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  52480341993                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  78640219993                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    696360500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    404225000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  25059292500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  52480341993                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  78640219993                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       549314                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       190418                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       739732                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3832122                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total      3832122                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks     11726658                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total     11726658                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       246295                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       246295                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       187036                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       187036                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1191277                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1191277                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      9774355                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      9774355                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3851394                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      3851394                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       842487                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       842487                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       549314                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       190418                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      9774355                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      5042671                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     15556758                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       549314                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       190418                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      9774355                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      5042671                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     15556758                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.039440                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.053146                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.042968                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999996                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999996                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.238136                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.238136                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.073594                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.073594                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.261748                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.261748                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.742237                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.742237                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.038326                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.058507                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.073594                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.256009                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.131624                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.038326                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.058507                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.073594                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.256009                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.131624                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31040.852396                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 34449.630939                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32155.291958                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3562.670622                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3562.670622                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1632.266301                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1632.266301                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 794666.333333                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 794666.333333                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48995.832926                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48995.832926                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34744.924865                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34744.924865                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35288.754773                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35288.754773                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   573.814646                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   573.814646                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31040.852396                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 34449.630939                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34744.924865                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38387.371026                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 37013.914607                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31040.852396                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 34449.630939                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34744.924865                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38387.371026                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 37013.914607                       # average overall miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.240741                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.240741                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.071430                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.071430                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.253460                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.253460                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.713504                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.713504                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.039440                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.053146                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.071430                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.250455                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.128107                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.039440                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.053146                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.071430                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.250455                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.128107                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32142.187861                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39943.181818                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34625.939909                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3698.541174                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3698.541174                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1546.731645                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1546.731645                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 341099.400000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 341099.400000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53797.767690                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53797.767690                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35892.103657                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35892.103657                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37956.036566                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37956.036566                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   559.460039                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   559.460039                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32142.187861                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39943.181818                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35892.103657                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41553.315845                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 39459.540282                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32142.187861                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39943.181818                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35892.103657                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41553.315845                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 39459.540282                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches           44195                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks      1595582                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1595582                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker           11                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker           92                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total          103                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         9447                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         9447                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.unused_prefetches           45829                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks      1629804                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1629804                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker           24                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker           98                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total          122                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         8277                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         8277                       # number of ReadExReq MSHR hits
 system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           12                       # number of ReadCleanReq MSHR hits
 system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          778                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          778                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            2                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker           11                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker           92                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          866                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          866                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            3                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::total            3                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker           24                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker           98                       # number of demand (read+write) MSHR hits
 system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           12                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        10225                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        10340                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker           11                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker           92                       # number of overall MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         9143                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         9277                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker           24                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker           98                       # number of overall MSHR hits
 system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           12                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        10225                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        10340                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        19792                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         9527                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        29319                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       781759                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       781759                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       245426                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       245426                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       180938                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       180938                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       269166                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       269166                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       683024                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       683024                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       953085                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       953085                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       581976                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       581976                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        19792                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         9527                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       683024                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1222251                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      1934594                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        19792                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         9527                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       683024                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1222251                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       781759                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2716353                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52300                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20634                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        72934                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        22275                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        22275                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52300                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        42909                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        95209                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    495686000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    272683000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    768369000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  38385674547                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  38385674547                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4516919997                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4516919997                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2779143996                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2779143996                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2017999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2017999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10852711499                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10852711499                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  19633488000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  19633488000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  27859151994                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  27859151994                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  19308557500                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  19308557500                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    495686000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    272683000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  19633488000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  38711863493                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  59113720493                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    495686000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    272683000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  19633488000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  38711863493                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  38385674547                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  97499395040                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4418384500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3849707000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8268091500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4418384500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   3849707000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8268091500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.038304                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.057948                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.043046                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         9143                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         9277                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        21641                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        10022                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        31663                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       782860                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       782860                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       246294                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       246294                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       187036                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       187036                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       278512                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       278512                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       698172                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       698172                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       975309                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       975309                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       601115                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       601115                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        21641                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        10022                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       698172                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1253821                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total      1983656                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        21641                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        10022                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       698172                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1253821                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       782860                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total      2766516                       # number of overall MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52284                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31212                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        83496                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        30755                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        30755                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52284                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        61967                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       114251                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    565944000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    342540500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    908484500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  36299233693                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  36299233693                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4539562995                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4539562995                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2868254998                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2868254998                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1441497                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1441497                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  12630779498                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  12630779498                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  20869901000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  20869901000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  31074032995                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  31074032995                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  19885865000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  19885865000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    565944000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    342540500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  20869901000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  43704812493                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  65483197993                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    565944000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    342540500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  20869901000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  43704812493                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  36299233693                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total 101782431686                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4743334000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5788958500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  10532292500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4743334000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5788958500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10532292500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.039396                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.052632                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.042803                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999996                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999996                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.230062                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.230062                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.073593                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.073593                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.261534                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.261534                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.742235                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.742235                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.038304                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.057948                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.073593                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.253885                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.130924                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.038304                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.057948                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.073593                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.253885                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.233793                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.233793                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.071429                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.071429                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.253235                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.253235                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.713501                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.713501                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.039396                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.052632                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.071429                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.248642                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.127511                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.039396                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.052632                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.071429                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.248642                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.183830                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26207.203520                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49101.672698                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18404.407019                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18404.407019                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15359.648034                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15359.648034                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 672666.333333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672666.333333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40319.771067                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40319.771067                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28744.946005                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28744.946005                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29230.500946                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29230.500946                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33177.583784                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33177.583784                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28744.946005                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31672.597112                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30556.137615                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28744.946005                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31672.597112                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35893.492134                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186571.047785                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113364.020896                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89717.937962                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86841.490825                       # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests     30377137                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     15497883                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2826                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       666100                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       666086                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops           14                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq        826394                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     13852976                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        22275                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        22275                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      5277668                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean     11102490                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      1369040                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       998456                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       452524                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       330100                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       496609                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           57                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          115                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1203701                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1179860                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9281130                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4723846                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       838465                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       784086                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     27947466                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17813968                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       344869                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1089699                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         47196002                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side   1191298304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    667170422                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1315256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4133624                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1863917606                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    5747559                       # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic            110232304                       # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples     21648150                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.044453                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.206103                       # Request fanout histogram
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.177834                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28692.306478                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46367.465055                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46367.465055                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18431.480243                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18431.480243                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15335.309769                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15335.309769                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 288299.400000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 288299.400000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45350.934602                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45350.934602                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29892.205646                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29892.205646                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31860.705679                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31860.705679                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33081.631635                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33081.631635                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29892.205646                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34857.298205                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33011.367895                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29892.205646                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34857.298205                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46367.465055                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36790.834279                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185472.206203                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126141.282217                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93420.021947                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 92185.560739                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests     31945858                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     16286466                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2971                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       662323                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       662303                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops           20                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq        897088                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     14618500                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        30756                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        30755                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5466694                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean     11729628                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      1381452                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1000780                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       445154                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       338634                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       499902                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           83                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1222912                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1199223                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9774356                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4899750                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       895142                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       842487                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     29427111                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18719100                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       397503                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1155819                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         49699533                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side   1254430144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    699985190                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1523344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4394512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1960333190                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    5744069                       # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic            111836388                       # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples     22520641                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.042476                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.201677                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          20685836     95.55%     95.55% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            962300      4.45%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2                14      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          21564077     95.75%     95.75% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            956544      4.25%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2                20      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      21648150                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   30255355989                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      22520641                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   31868357980                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    202143120                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    188944290                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy  14002739292                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy  14742648604                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   7861824025                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   8252120363                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    180564794                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    207185798                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    573087816                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    606624760                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              142890193                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted        101173603                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6378415                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups           107083119                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               74895456                       # Number of BTB hits
+system.cpu1.branchPred.lookups              130393488                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         92735412                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5902942                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            97710710                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               68499677                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            69.941422                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               16732142                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect           1061167                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        3812146                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits           2601182                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses         1210964                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted       435637                       # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu1.branchPred.BTBHitPct            70.104574                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               15029088                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            982146                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        3431599                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           2322480                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         1109119                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted       398100                       # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1450,63 +1461,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                   301450                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               301450                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        14052                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        94528                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples       301450                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0         301450    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       301450                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       108580                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23842.945294                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21967.326975                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15932.247293                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       107036     98.58%     98.58% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1312      1.21%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607           57      0.05%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           69      0.06%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           74      0.07%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           19      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751            9      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       108580                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   -588118056                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     -588118056    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   -588118056                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        94528     87.06%     87.06% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        14052     12.94%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       108580                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       301450                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                   266586                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               266586                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         9178                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        75276                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples       266586                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         266586    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       266586                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        84454                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23652.319606                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21901.867132                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15135.594089                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535        83574     98.96%     98.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071          653      0.77%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          133      0.16%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           39      0.05%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           30      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        84454                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples    112342944                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0      112342944    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total    112342944                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        75276     89.13%     89.13% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         9178     10.87%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        84454                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       266586                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       301450                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       108580                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       266586                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        84454                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       108580                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       410030                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        84454                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       351040                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    92214946                       # DTB read hits
-system.cpu1.dtb.read_misses                    251350                       # DTB read misses
-system.cpu1.dtb.write_hits                   79863458                       # DTB write hits
-system.cpu1.dtb.write_misses                    50100                       # DTB write misses
+system.cpu1.dtb.read_hits                    83602508                       # DTB read hits
+system.cpu1.dtb.read_misses                    221634                       # DTB read misses
+system.cpu1.dtb.write_hits                   72407946                       # DTB write hits
+system.cpu1.dtb.write_misses                    44952                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              42591                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1052                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   41485                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     1017                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  8355                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              40666                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   35586                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     1113                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  7045                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    11459                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                92466296                       # DTB read accesses
-system.cpu1.dtb.write_accesses               79913558                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    10293                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                83824142                       # DTB read accesses
+system.cpu1.dtb.write_accesses               72452898                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        172078404                       # DTB hits
-system.cpu1.dtb.misses                         301450                       # DTB misses
-system.cpu1.dtb.accesses                    172379854                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                        156010454                       # DTB hits
+system.cpu1.dtb.misses                         266586                       # DTB misses
+system.cpu1.dtb.accesses                    156277040                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1536,892 +1548,893 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                    68405                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                68405                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          536                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        57692                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        68405                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          68405    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        68405                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        58228                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 26184.473106                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23792.146832                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18243.083639                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        52664     90.44%     90.44% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535         3935      6.76%     97.20% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303           14      0.02%     97.23% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071         1454      2.50%     99.72% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839           38      0.07%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           17      0.03%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375           63      0.11%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143           12      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911           10      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679           10      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        58228                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   -588816556                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     -588816556    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   -588816556                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        57692     99.08%     99.08% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          536      0.92%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        58228                       # Table walker page sizes translated
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                    60007                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                60007                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          568                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        49765                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        60007                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          60007    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        60007                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        50333                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 25530.089603                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23478.456634                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 19036.287161                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        49435     98.22%     98.22% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071          638      1.27%     99.48% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          189      0.38%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           38      0.08%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           10      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359           14      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        50333                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples    111619444                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0      111619444    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total    111619444                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        49765     98.87%     98.87% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          568      1.13%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        50333                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        68405                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        68405                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        60007                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        60007                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        58228                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        58228                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       126633                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   253981708                       # ITB inst hits
-system.cpu1.itb.inst_misses                     68405                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        50333                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        50333                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       110340                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   231314016                       # ITB inst hits
+system.cpu1.itb.inst_misses                     60007                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              42591                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1052                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   29878                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              40666                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   25531                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   186858                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   167507                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               254050113                       # ITB inst accesses
-system.cpu1.itb.hits                        253981708                       # DTB hits
-system.cpu1.itb.misses                          68405                       # DTB misses
-system.cpu1.itb.accesses                    254050113                       # DTB accesses
-system.cpu1.numPwrStateTransitions              29008                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples        14504                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    3226000342.121070                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   122202778079.734619                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         4515     31.13%     31.13% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         9966     68.71%     99.84% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            7      0.05%     99.89% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            3      0.02%     99.91% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.92% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.92% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.93% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows           10      0.07%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses               231374023                       # ITB inst accesses
+system.cpu1.itb.hits                        231314016                       # DTB hits
+system.cpu1.itb.misses                          60007                       # DTB misses
+system.cpu1.itb.accesses                    231374023                       # DTB accesses
+system.cpu1.numPwrStateTransitions               9626                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         4813                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    9788374174.243299                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   115006828751.685410                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         3303     68.63%     68.63% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10         1483     30.81%     99.44% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.02%     99.46% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            1      0.02%     99.48% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            4      0.08%     99.56% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11            1      0.02%     99.58% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            1      0.02%     99.61% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.02%     99.63% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows           18      0.37%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 11813587669000                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total          14504                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   486863864876                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 46789908962124                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                       973770006                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value 1988779353616                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           4813                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON   443465373367                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 47111444900633                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                       886937326                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  467062034                       # Number of instructions committed
-system.cpu1.committedOps                    549524480                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                     49354477                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     5829                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                 93580668477                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.084884                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.479643                       # IPC: instructions per cycle
+system.cpu1.committedInsts                  425165575                       # Number of instructions committed
+system.cpu1.committedOps                    499981941                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                     45360018                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     4813                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                 94223530921                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.086099                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.479364                       # IPC: instructions per cycle
 system.cpu1.op_class_0::No_OpClass                  0      0.00%      0.00% # Class of committed instruction
-system.cpu1.op_class_0::IntAlu              379758717     69.11%     69.11% # Class of committed instruction
-system.cpu1.op_class_0::IntMult               1174710      0.21%     69.32% # Class of committed instruction
-system.cpu1.op_class_0::IntDiv                  62873      0.01%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::FloatAdd                    0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::FloatCmp                    0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::FloatCvt                    0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::FloatMult                   0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::FloatDiv                    0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::FloatSqrt                   0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdAdd                     0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdAlu                     0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdCmp                     0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdCvt                     0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdMisc                    0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdMult                    0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdShift                   0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdSqrt                    0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     69.33% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMisc           42788      0.01%     69.34% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMult               0      0.00%     69.34% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     69.34% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     69.34% # Class of committed instruction
-system.cpu1.op_class_0::MemRead              88942339     16.19%     85.53% # Class of committed instruction
-system.cpu1.op_class_0::MemWrite             79543053     14.47%    100.00% # Class of committed instruction
+system.cpu1.op_class_0::IntAlu              346104827     69.22%     69.22% # Class of committed instruction
+system.cpu1.op_class_0::IntMult               1095440      0.22%     69.44% # Class of committed instruction
+system.cpu1.op_class_0::IntDiv                  59698      0.01%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::FloatAdd                    0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::FloatCmp                    0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::FloatCvt                    0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::FloatMult                   0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::FloatDiv                    0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::FloatSqrt                   0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdAdd                     0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdAlu                     0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdCmp                     0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdCvt                     0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdMisc                    0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdMult                    0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdShift                   0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdSqrt                    0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     69.45% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMisc           26657      0.01%     69.46% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMult               0      0.00%     69.46% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     69.46% # Class of committed instruction
+system.cpu1.op_class_0::MemRead              80579122     16.12%     85.58% # Class of committed instruction
+system.cpu1.op_class_0::MemWrite             72116197     14.42%    100.00% # Class of committed instruction
 system.cpu1.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
 system.cpu1.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
-system.cpu1.op_class_0::total               549524480                       # Class of committed instruction
+system.cpu1.op_class_0::total               499981941                       # Class of committed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   14504                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      754340504                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                      219429502                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements          5584308                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          440.375822                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          163963779                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5584818                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            29.358840                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8377741807000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   440.375822                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.860109                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.860109                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          162                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          234                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        347150058                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       347150058                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data     84821089                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       84821089                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     74565342                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      74565342                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       240493                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       240493                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data        73857                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total        73857                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1888770                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1888770                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1879546                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1879546                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    159460288                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       159460288                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    159700781                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      159700781                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      3413550                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      3413550                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      2348662                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      2348662                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       664960                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       664960                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       462804                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       462804                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       186013                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       186013                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       193851                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       193851                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      6225016                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       6225016                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      6889976                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      6889976                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  52244752500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  52244752500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  43500498500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  43500498500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  11517052000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  11517052000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2853085500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2853085500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4630433000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4630433000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2585500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2585500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 107262303000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 107262303000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 107262303000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 107262303000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     88234639                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     88234639                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     76914004                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     76914004                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       905453                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       905453                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       536661                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       536661                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2074783                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      2074783                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2073397                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      2073397                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    165685304                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    165685304                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    166590757                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    166590757                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038687                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.038687                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030536                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.030536                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.734395                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.734395                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.862377                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.862377                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.089654                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.089654                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.093494                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.093494                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.037571                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.037571                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.041359                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.041359                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15305.108318                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15305.108318                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18521.395799                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18521.395799                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24885.376963                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24885.376963                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15338.097337                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15338.097337                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23886.557201                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23886.557201                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    4813                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      688160387                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                      198776939                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements          4915770                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          461.565771                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          148821179                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          4916282                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            30.271083                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8378532705500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   461.565771                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.901496                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.901496                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          154                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          267                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        314637839                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       314637839                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data     76998524                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       76998524                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     67544283                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      67544283                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       228025                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       228025                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       143759                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       143759                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1733263                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1733263                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1698082                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1698082                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    144686566                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       144686566                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    144914591                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      144914591                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      2997503                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      2997503                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      2132920                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      2132920                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       598160                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       598160                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       396373                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       396373                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       156072                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       156072                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       190006                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       190006                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      5526796                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       5526796                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      6124956                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      6124956                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  46710580500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  46710580500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  40169374000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  40169374000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  10226397500                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  10226397500                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2373794500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2373794500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4526922000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   4526922000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1761500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1761500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  97106352000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  97106352000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  97106352000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  97106352000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     79996027                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     79996027                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     69677203                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     69677203                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       826185                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       826185                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       540132                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       540132                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1889335                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1889335                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1888088                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1888088                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    150213362                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    150213362                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    151039547                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    151039547                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037471                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.037471                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030611                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.030611                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.724002                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.724002                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.733845                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.733845                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.082607                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.082607                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100634                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100634                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.036793                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.036793                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040552                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.040552                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15583.163887                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15583.163887                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18833.042965                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 18833.042965                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25799.934658                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25799.934658                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15209.611590                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15209.611590                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23825.152890                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23825.152890                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17230.847760                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17230.847760                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15567.877595                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15567.877595                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17570.098842                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 17570.098842                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15854.212177                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15854.212177                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks      5584335                       # number of writebacks
-system.cpu1.dcache.writebacks::total          5584335                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       169267                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       169267                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       957224                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       957224                       # number of WriteReq MSHR hits
+system.cpu1.dcache.writebacks::writebacks      4915771                       # number of writebacks
+system.cpu1.dcache.writebacks::total          4915771                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       147995                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       147995                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       874601                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       874601                       # number of WriteReq MSHR hits
 system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           58                       # number of WriteLineReq MSHR hits
 system.cpu1.dcache.WriteLineReq_mshr_hits::total           58                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44866                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44866                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           87                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total           87                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1126549                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1126549                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1126549                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1126549                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3244283                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      3244283                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1391438                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1391438                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       664681                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       664681                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       462746                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       462746                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       141147                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       141147                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       193764                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       193764                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      5098467                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      5098467                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5763148                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5763148                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        17608                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        17608                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        15853                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        15853                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        33461                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        33461                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  45298654500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  45298654500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  25106196000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  25106196000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14639124500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14639124500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  11050641000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  11050641000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1898988000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1898988000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4434665000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4434665000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2119500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2119500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  81455491500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  81455491500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  96094616000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  96094616000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2936127500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2936127500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2936127500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2936127500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036769                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036769                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018091                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018091                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.734087                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.734087                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.862269                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.862269                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.068030                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.068030                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.093452                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.093452                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030772                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.030772                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034595                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.034595                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13962.608841                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13962.608841                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18043.345086                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18043.345086                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22024.286086                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22024.286086                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23880.575953                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23880.575953                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13453.973517                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13453.973517                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22886.939782                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22886.939782                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        38344                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        38344                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           50                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total           50                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1022654                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1022654                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1022654                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1022654                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2849508                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2849508                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1258319                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1258319                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       597912                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       597912                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       396315                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       396315                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       117728                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       117728                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       189956                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       189956                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4504142                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4504142                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5102054                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5102054                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         7183                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         7183                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         7509                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         7509                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        14692                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        14692                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  40476665500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  40476665500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  23125073000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  23125073000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13939684500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13939684500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   9826633500                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total   9826633500                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1586206000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1586206000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4335749000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4335749000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1584500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1584500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  73428372000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  73428372000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  87368056500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  87368056500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    918087500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    918087500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    918087500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    918087500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035621                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035621                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018059                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018059                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.723702                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.723702                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.733737                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.733737                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062312                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.062312                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100608                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100608                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029985                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.029985                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033780                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.033780                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14204.790967                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14204.790967                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18377.750793                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18377.750793                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23313.940011                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23313.940011                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 24795.007759                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 24795.007759                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13473.481245                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13473.481245                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22825.017372                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22825.017372                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15976.467338                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15976.467338                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16673.980262                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16673.980262                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166749.630850                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166749.630850                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87747.751113                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 87747.751113                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements          9521452                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          507.043038                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          244267020                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          9521964                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            25.653008                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8368158607000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.043038                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990318                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.990318                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16302.410537                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16302.410537                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17124.094825                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17124.094825                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127813.935681                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 127813.935681                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 62488.939559                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 62488.939559                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements          8832346                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          507.234959                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          222308626                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          8832858                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            25.168369                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8368864848000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.234959                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990693                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.990693                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          273                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           81                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        517099934                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       517099934                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst    244267020                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      244267020                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    244267020                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       244267020                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    244267020                       # number of overall hits
-system.cpu1.icache.overall_hits::total      244267020                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      9521965                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      9521965                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      9521965                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       9521965                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      9521965                       # number of overall misses
-system.cpu1.icache.overall_misses::total      9521965                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  96688620500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  96688620500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  96688620500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  96688620500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  96688620500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  96688620500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    253788985                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    253788985                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    253788985                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    253788985                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    253788985                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    253788985                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037519                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.037519                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037519                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.037519                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037519                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.037519                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10154.271781                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10154.271781                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10154.271781                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10154.271781                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10154.271781                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10154.271781                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        471115826                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       471115826                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst    222308626                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      222308626                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    222308626                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       222308626                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    222308626                       # number of overall hits
+system.cpu1.icache.overall_hits::total      222308626                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      8832858                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      8832858                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      8832858                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       8832858                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      8832858                       # number of overall misses
+system.cpu1.icache.overall_misses::total      8832858                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  91672034000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  91672034000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  91672034000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  91672034000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  91672034000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  91672034000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    231141484                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    231141484                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    231141484                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    231141484                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    231141484                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    231141484                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.038214                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.038214                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.038214                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.038214                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.038214                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.038214                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10378.524595                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10378.524595                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10378.524595                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10378.524595                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10378.524595                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10378.524595                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks      9521452                       # number of writebacks
-system.cpu1.icache.writebacks::total          9521452                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9521965                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      9521965                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      9521965                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      9521965                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      9521965                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      9521965                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks      8832346                       # number of writebacks
+system.cpu1.icache.writebacks::total          8832346                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      8832858                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      8832858                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      8832858                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      8832858                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      8832858                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      8832858                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           95                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           95                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           95                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           95                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  91927638500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  91927638500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  91927638500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  91927638500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  91927638500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  91927638500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9070500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9070500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9070500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      9070500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037519                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037519                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037519                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.037519                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037519                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.037519                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9654.271834                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9654.271834                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9654.271834                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  9654.271834                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9654.271834                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  9654.271834                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95478.947368                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95478.947368                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7586302                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7586460                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit          136                       # number of redundant prefetches already in prefetch queue
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  87255605000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  87255605000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  87255605000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  87255605000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  87255605000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  87255605000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9824500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9824500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9824500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      9824500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.038214                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.038214                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.038214                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.038214                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.038214                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.038214                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9878.524595                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9878.524595                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9878.524595                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9878.524595                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9878.524595                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9878.524595                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 103415.789474                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 103415.789474                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 103415.789474                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 103415.789474                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      6928823                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      6928917                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           84                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       987804                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements         2406613                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13125.467163                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          13856134                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2421819                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            5.721375                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage       861587                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.tags.replacements         2157597                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13047.513497                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          12560684                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2173028                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            5.780268                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12849.276806                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    27.086630                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    14.305413                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   234.798314                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.784258                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001653                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000873                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.014331                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.801115                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          271                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           79                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14856                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          106                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          108                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           47                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           65                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          402                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          743                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         6180                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6756                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          775                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.016541                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004822                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.906738                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       519862521                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      519862521                       # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       578094                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       171981                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        750075                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks      3464322                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total      3464322                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks     11639503                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total     11639503                       # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       901874                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       901874                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8781698                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      8781698                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3023137                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      3023137                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       191670                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       191670                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       578094                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       171981                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      8781698                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3925011                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total       13456784                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       578094                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       171981                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      8781698                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3925011                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total      13456784                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        22586                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        11050                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        33636                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       232349                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       232349                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       193761                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       193761                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12721.719403                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    48.343114                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    32.192156                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   245.258823                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.776472                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002951                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.001965                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.014969                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.796357                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          270                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           73                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15088                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          102                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          107                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           61                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           42                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          273                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          832                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         6150                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6722                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1111                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.016479                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004456                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.920898                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       472979438                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      472979438                       # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       496781                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       150336                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        647117                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3051311                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3051311                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks     10695223                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total     10695223                       # number of WritebackClean hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data            2                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total            2                       # number of UpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       813214                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       813214                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8132856                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      8132856                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2632220                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2632220                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       143613                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       143613                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       496781                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       150336                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      8132856                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3445434                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total       12225407                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       496781                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       150336                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      8132856                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3445434                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total      12225407                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        19778                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9507                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        29285                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       216104                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       216104                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       189953                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       189953                       # number of SCUpgradeReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            3                       # number of SCUpgradeFailReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       259533                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       259533                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       740267                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       740267                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1026659                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total      1026659                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       269262                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       269262                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        22586                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker        11050                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       740267                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1286192                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      2060095                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        22586                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker        11050                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       740267                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1286192                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      2060095                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    726971000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    437240000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total   1164211000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    947721000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    947721000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    273329000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    273329000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2036499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2036499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  11444500498                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  11444500498                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  24621036000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  24621036000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  35849827996                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  35849827996                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    304696500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total    304696500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    726971000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    437240000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  24621036000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  47294328494                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  73079575494                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    726971000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    437240000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  24621036000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  47294328494                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  73079575494                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       600680                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       183031                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       783711                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3464322                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total      3464322                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks     11639503                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total     11639503                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       232349                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       232349                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       193761                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       193761                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       231177                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       231177                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       700002                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       700002                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       932644                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total       932644                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       250983                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       250983                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        19778                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9507                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       700002                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1163821                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1893108                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        19778                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9507                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       700002                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1163821                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1893108                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    605384500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    346513000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total    951897500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    912243000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    912243000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    268121000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    268121000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1526000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1526000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10578569498                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total  10578569498                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  24914386500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  24914386500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  33296141988                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  33296141988                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    300579500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total    300579500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    605384500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    346513000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  24914386500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  43874711486                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  69740995486                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    605384500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    346513000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  24914386500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  43874711486                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  69740995486                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       516559                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       159843                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       676402                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3051311                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      3051311                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks     10695223                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total     10695223                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       216106                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       216106                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       189953                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       189953                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1161407                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1161407                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      9521965                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      9521965                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4049796                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      4049796                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       460932                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       460932                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       600680                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       183031                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      9521965                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      5211203                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     15516879                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       600680                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       183031                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      9521965                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      5211203                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     15516879                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.037601                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.060372                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.042919                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1044391                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1044391                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      8832858                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      8832858                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3564864                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3564864                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       394596                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       394596                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       516559                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       159843                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      8832858                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4609255                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     14118515                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       516559                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       159843                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      8832858                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4609255                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     14118515                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.038288                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.059477                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.043295                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.999991                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999991                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.223464                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.223464                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.077743                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.077743                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.253509                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.253509                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.584169                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.584169                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.037601                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.060372                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.077743                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.246813                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.132765                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.037601                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.060372                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.077743                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.246813                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.132765                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32186.797131                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 39569.230769                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34612.052563                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4078.868426                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4078.868426                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1410.650234                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1410.650234                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       678833                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       678833                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44096.513730                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44096.513730                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33259.669822                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33259.669822                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34918.924391                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34918.924391                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1131.598592                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1131.598592                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32186.797131                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 39569.230769                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33259.669822                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36770.815317                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 35473.886153                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32186.797131                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 39569.230769                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33259.669822                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36770.815317                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 35473.886153                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.221351                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.221351                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.079250                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.079250                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.261621                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.261621                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.636051                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.636051                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.038288                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.059477                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.079250                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.252497                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.134087                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.038288                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.059477                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.079250                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.252497                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.134087                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30608.984731                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36448.196066                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32504.609869                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4221.314737                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4221.314737                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1411.512321                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1411.512321                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 508666.666667                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 508666.666667                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45759.610593                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45759.610593                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35591.879023                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35591.879023                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35700.805439                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35700.805439                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1197.609001                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1197.609001                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30608.984731                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36448.196066                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35591.879023                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37698.848436                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 36839.417237                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30608.984731                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36448.196066                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35591.879023                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37698.848436                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 36839.417237                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches           49424                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks      1233392                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1233392                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker           16                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          110                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          126                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         7522                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         7522                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.unused_prefetches           43184                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks      1062517                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1062517                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker           15                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           83                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total           98                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         6377                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         6377                       # number of ReadExReq MSHR hits
 system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            2                       # number of ReadCleanReq MSHR hits
 system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          653                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          653                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker           16                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          110                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          790                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          790                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            1                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::total            1                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker           15                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           83                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         8175                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         8303                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker           16                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          110                       # number of overall MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7167                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         7267                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker           15                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           83                       # number of overall MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            2                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         8175                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         8303                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        22570                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        10940                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        33510                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       779944                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       779944                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       232349                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       232349                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       193761                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       193761                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         7167                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         7267                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        19763                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9424                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        29187                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       714287                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       714287                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       216104                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       216104                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       189953                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       189953                       # number of SCUpgradeReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       252011                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       252011                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       740265                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       740265                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data      1026006                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total      1026006                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       269262                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       269262                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        22570                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        10940                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       740265                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1278017                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      2051792                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        22570                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        10940                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       740265                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1278017                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       779944                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2831736                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       224800                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       224800                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       700000                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       700000                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       931854                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       931854                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       250982                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       250982                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        19763                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9424                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       700000                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1156654                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1885841                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        19763                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9424                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       700000                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1156654                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       714287                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total      2600128                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           95                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        17608                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17703                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        15853                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        15853                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         7183                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         7278                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         7509                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         7509                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           95                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        33461                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        33556                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    591166500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    369748000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    960914500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  34084097769                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  34084097769                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4320296500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4320296500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2976407492                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2976407492                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1712499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1712499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8961948498                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8961948498                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  20179405000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  20179405000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  29636625496                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  29636625496                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   7368901000                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   7368901000                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    591166500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    369748000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  20179405000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  38598573994                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  59738893494                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    591166500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    369748000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  20179405000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  38598573994                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  34084097769                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  93822991263                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8310500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2795199500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2803510000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8310500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2795199500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2803510000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.037574                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.059771                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.042758                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        14692                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        14787                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    486444500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    288576500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    775021000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  30894742332                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  30894742332                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4083186496                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4083186496                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2906568497                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2906568497                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1292000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1292000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8335690998                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8335690998                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  20714350500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  20714350500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  27592853988                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  27592853988                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6684154500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6684154500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    486444500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    288576500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  20714350500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  35928544986                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  57417916486                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    486444500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    288576500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  20714350500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  35928544986                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  30894742332                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  88312658818                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9064500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    860524000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    869588500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9064500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    860524000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    869588500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.038259                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.058958                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.043150                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.999991                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.999991                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.216988                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.216988                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.077743                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.077743                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.253348                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.253348                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.584169                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.584169                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.037574                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.059771                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.077743                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.245244                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.132230                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.037574                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.059771                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.077743                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.245244                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.215245                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.215245                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.079250                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.079250                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.261400                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.261400                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.636048                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.636048                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.038259                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.058958                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.079250                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.250942                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.133572                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.038259                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.058958                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.079250                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.250942                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.182494                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28675.455088                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43700.698728                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18593.996531                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18593.996531                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15361.231063                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15361.231063                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       570833                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       570833                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35561.735393                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35561.735393                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27259.704295                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27259.704295                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28885.430978                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28885.430978                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27367.029139                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27367.029139                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27259.704295                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30201.925322                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29115.472472                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27259.704295                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30201.925322                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33132.675950                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158745.996138                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158363.554200                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 83536.041959                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 83547.204673                       # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests     31064178                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     15870221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1958                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       609547                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       609525                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops           22                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq        891069                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     14544906                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        15853                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        15853                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      4703319                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean     11641461                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      1517999                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       982833                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       435735                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       338791                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       485404                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           64                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          115                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1187635                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1166992                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      9521965                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5021918                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       508584                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       460932                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     28565571                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17994817                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       387517                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1269560                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         48217465                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side   1218784704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    696648341                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1464248                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4805440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1921702733                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    5371031                       # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic             85625912                       # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples     21661443                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.043843                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.204751                       # Request fanout histogram
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.184164                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26553.636893                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43252.561410                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43252.561410                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18894.543812                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18894.543812                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15301.514043                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15301.514043                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 430666.666667                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 430666.666667                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37080.475970                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37080.475970                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29591.929286                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29591.929286                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29610.705098                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29610.705098                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26632.007475                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26632.007475                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29591.929286                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31062.482805                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30446.849170                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29591.929286                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31062.482805                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43252.561410                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33964.735128                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95415.789474                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119800.083531                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119481.794449                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95415.789474                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 58570.922951                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 58807.635085                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests     28307892                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     14471357                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1579                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       577788                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       577774                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops           14                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq        765944                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     13251577                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         7509                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         7509                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4119049                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean     10696803                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      1405207                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       907922                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp            3                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       426575                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       338167                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       466317                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           47                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           83                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1072889                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1050772                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      8832858                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4591457                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       449471                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       394596                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     26498252                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15919614                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       339109                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1095958                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         43852933                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side   1130579136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    615678398                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1278736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4132472                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1751668742                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    5086460                       # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic             75030592                       # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples     19865784                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.045122                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.207576                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          20711756     95.62%     95.62% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            949665      4.38%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2                22      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          18969410     95.49%     95.49% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            896360      4.51%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2                14      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      21661443                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   30930175985                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      19865784                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   28134048478                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    161428122                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    171886209                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy  14285968218                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy  13252138560                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   8290126100                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7328947477                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    204584802                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    179350830                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    668995768                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    579510776                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40347                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40347                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136610                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136610                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47638                       # Packet count per connected master and slave (bytes)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40272                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40272                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136595                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136595                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47628                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2432,15 +2445,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122572                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231262                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231262                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122510                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231144                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231144                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353914                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47658                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353734                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47648                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2451,105 +2464,105 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155679                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339064                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7339064                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155640                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338592                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338592                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496829                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             41998503                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496318                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             42593000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               312000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               316000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               15500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               16000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25719009                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25879501                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            34474500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            34434000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           569697884                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           569469195                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92693000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92646000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147958000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147840000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115612                       # number of replacements
-system.iocache.tags.tagsinuse               11.289058                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115567                       # number of replacements
+system.iocache.tags.tagsinuse               11.304352                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115628                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115583                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9127814531000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.847615                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.441443                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.240476                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.465090                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.705566                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9167343261000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.387949                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.916404                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.461747                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.244775                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706522                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1041036                       # Number of tag accesses
-system.iocache.tags.data_accesses             1041036                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1040505                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040505                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8903                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8940                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8844                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8881                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115631                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115671                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115572                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115612                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115631                       # number of overall misses
-system.iocache.overall_misses::total           115671                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5198500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1683130463                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1688328963                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115572                       # number of overall misses
+system.iocache.overall_misses::total           115612                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5196500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1979797452                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1984993952                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12860878921                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12860878921                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5567500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14544009384                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14549576884                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5567500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14544009384                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14549576884                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13211000243                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13211000243                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5565500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15190797695                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15196363195                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5565500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15190797695                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15196363195                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8903                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8940                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8844                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8881                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115631                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115671                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115572                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115612                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115631                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115671                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115572                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115612                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2563,53 +2576,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet       140500                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 189052.056947                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 188851.114430                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 223857.694708                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 223510.184889                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120501.451550                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 120501.451550                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125779.500169                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125784.136767                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125779.500169                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125784.136767                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         33720                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123781.952655                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 123781.952655                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 131440.121266                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 131442.784443                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 131440.121266                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 131442.784443                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         49739                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3566                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3574                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.455973                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    13.916900                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks          106694                       # number of writebacks
-system.iocache.writebacks::total               106694                       # number of writebacks
+system.iocache.writebacks::writebacks          106693                       # number of writebacks
+system.iocache.writebacks::total               106693                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8903                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8940                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8844                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8881                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115631                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115671                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115572                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115612                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115631                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115671                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3348500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1237980463                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1241328963                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115572                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115612                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3346500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1537597452                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1540943952                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7515783412                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7515783412                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3567500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8753763875                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8757331375                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3567500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8753763875                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8757331375                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7865666947                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7865666947                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3565500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9403264399                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9406829899                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3565500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9403264399                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9406829899                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2623,661 +2636,661 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        90500                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139052.056947                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 138851.114430                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90445.945946                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 173857.694708                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 173510.184889                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70419.978000                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70419.978000                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75704.299669                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75708.962272                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75704.299669                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75708.962272                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1555997                       # number of replacements
-system.l2c.tags.tagsinuse                65230.630092                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    7273929                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1617589                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.496772                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               7807986500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks    8906.310468                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    15.466536                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     9.611192                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3875.011018                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     9658.633081                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  3787.473530                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   432.466953                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   495.764320                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3981.420883                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    15318.580710                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 18749.891401                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.135900                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000236                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000147                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.059128                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.147379                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.057792                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.006599                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.007565                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.060752                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.233743                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.286101                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.995340                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        10605                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          254                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        50733                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2           57                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          363                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        10181                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            7                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          246                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          110                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1499                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4720                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        44382                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.161819                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003876                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.774124                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 80901066                       # Number of tag accesses
-system.l2c.tags.data_accesses                80901066                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks      2828973                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         2828973                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data          204859                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data          171268                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total              376127                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data         49678                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data         57164                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total            106842                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            57243                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            53868                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               111111                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        12667                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5625                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       610867                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       589040                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       292600                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        12537                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4791                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       678625                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       607071                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       308630                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          3122453                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       131047                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       131317                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           262364                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         12667                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          5625                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              610867                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              646283                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       292600                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         12537                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4791                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              678625                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              660939                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       308630                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3233564                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        12667                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         5625                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             610867                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             646283                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       292600                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        12537                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4791                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             678625                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             660939                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       308630                       # number of overall hits
-system.l2c.overall_hits::total                3233564                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         21060                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         26656                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             47716                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          518                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          636                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1154                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          76722                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          60050                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             136772                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1834                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1415                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        72156                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       133347                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       250233                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2590                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2459                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        61640                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       144790                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       229898                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         900362                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       438466                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       125863                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         564329                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1834                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1415                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             72156                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            210069                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       250233                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2590                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2459                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             61640                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            204840                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       229898                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1037134                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1834                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1415                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            72156                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           210069                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       250233                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2590                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2459                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            61640                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           204840                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       229898                       # number of overall misses
-system.l2c.overall_misses::total              1037134                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    165743500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    162277500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    328021000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      8669000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      8803000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total     17472000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   7005748000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   5240435998                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  12246183998                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    169372000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    128340500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6167992000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  12302035500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  33104444764                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    231186000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    216219500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   5316209000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  13039902500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  28612287454                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  99287989218                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data     31523000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data     29313000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total     60836000                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    169372000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    128340500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   6167992000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  19307783500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  33104444764                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    231186000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    216219500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   5316209000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  18280338498                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  28612287454                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    111534173216                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    169372000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    128340500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   6167992000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  19307783500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  33104444764                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    231186000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    216219500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   5316209000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  18280338498                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  28612287454                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   111534173216                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks      2828973                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      2828973                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data       225919                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data       197924                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          423843                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        50196                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        57800                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total        107996                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       133965                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       113918                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247883                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        14501                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7040                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       683023                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       722387                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       542833                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        15127                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7250                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       740265                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       751861                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       538528                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      4022815                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       569513                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       257180                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total       826693                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        14501                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         7040                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          683023                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          856352                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       542833                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        15127                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         7250                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          740265                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          865779                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       538528                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4270698                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        14501                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         7040                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         683023                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         856352                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       542833                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        15127                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         7250                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         740265                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         865779                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       538528                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4270698                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.093219                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.134678                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.112579                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.010320                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.011003                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.010686                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.572702                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.527134                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.551760                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.126474                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.200994                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.105642                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.184592                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.460976                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.171217                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.339172                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.083267                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.192575                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.426901                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.223814                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.769896                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.489397                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.682634                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.126474                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.200994                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.105642                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.245307                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.460976                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.171217                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.339172                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.083267                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.236596                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.426901                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.242849                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.126474                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.200994                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.105642                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.245307                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.460976                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.171217                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.339172                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.083267                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.236596                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.426901                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.242849                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  7870.061728                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6087.841387                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6874.444631                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16735.521236                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13841.194969                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 15140.381282                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91313.417273                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 87267.876736                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 89537.215205                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 92351.145038                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        90700                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85481.345973                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 92255.810029                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 132294.480600                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89261.003861                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 87929.849532                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86246.090201                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90060.794944                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 124456.443527                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 110275.632710                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    71.893830                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   232.896085                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total   107.802364                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92351.145038                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        90700                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 85481.345973                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 91911.626656                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 132294.480600                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89261.003861                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87929.849532                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 86246.090201                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 89242.035237                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 124456.443527                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 107540.754826                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92351.145038                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        90700                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 85481.345973                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 91911.626656                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 132294.480600                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89261.003861                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87929.849532                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 86246.090201                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 89242.035237                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 124456.443527                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 107540.754826                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               751                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73698.251134                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73698.251134                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 81362.824897                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 81365.514817                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 81362.824897                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 81365.514817                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                  1396284                       # number of replacements
+system.l2c.tags.tagsinuse                65138.751942                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    7016729                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1457215                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.815164                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               8133240500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   10857.852094                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   193.720367                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   194.423316                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4494.530949                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    16342.707209                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  9582.831884                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   263.988799                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   269.731759                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4576.542600                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     8162.860696                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10199.562268                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.165678                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002956                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.002967                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.068581                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.249370                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.146222                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004028                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.004116                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.069832                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.124555                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.155633                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.993938                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022         9763                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          241                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        50927                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2           80                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          414                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         9269                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          241                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1371                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4645                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        44789                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.148972                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003677                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.777084                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 77350226                       # Number of tag accesses
+system.l2c.tags.data_accesses                77350226                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks      2692321                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2692321                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data          204225                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          155483                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              359708                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         52320                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         51074                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total            103394                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            55531                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            51791                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               107322                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        13410                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5332                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       636242                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       595342                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       315678                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        10946                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4404                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       639193                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       560416                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       301207                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          3082170                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       138800                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       132737                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           271537                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         13410                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          5332                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              636242                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              650873                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       315678                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         10946                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          4404                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              639193                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              612207                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       301207                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 3189492                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        13410                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         5332                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             636242                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             650873                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       315678                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        10946                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         4404                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             639193                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             612207                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       301207                       # number of overall hits
+system.l2c.overall_hits::total                3189492                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         22618                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         28127                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             50745                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          499                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          689                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1188                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          80171                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          45173                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             125344                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1994                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1777                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        61929                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       136966                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       215441                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1649                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1460                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst        60807                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       104797                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       187062                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         773882                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       449504                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data       106576                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         556080                       # number of InvalidateReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         1994                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         1777                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             61929                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            217137                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       215441                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         1649                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         1460                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             60807                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            149970                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher       187062                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                899226                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         1994                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         1777                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            61929                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           217137                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       215441                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         1649                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         1460                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            60807                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           149970                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher       187062                       # number of overall misses
+system.l2c.overall_misses::total               899226                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    166509500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    180855500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    347365000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      6105500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      8200500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total     14306000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   8647457500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   4904092500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  13551550000                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    211493000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    194819500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6896332000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  15165548000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  30671403248                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    166890000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    150626500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst   6689940000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data  12141260000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  25575724378                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  97864036626                       # number of ReadSharedReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu0.data     46615500                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data     36764000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::total     83379500                       # number of InvalidateReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    211493000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    194819500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   6896332000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  23813005500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  30671403248                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    166890000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    150626500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   6689940000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  17045352500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  25575724378                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    111415586626                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    211493000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    194819500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   6896332000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  23813005500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  30671403248                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    166890000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker    150626500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   6689940000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  17045352500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  25575724378                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   111415586626                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks      2692321                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      2692321                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data       226843                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data       183610                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          410453                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        52819                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        51763                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total        104582                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       135702                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        96964                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           232666                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        15404                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7109                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       698171                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       732308                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       531119                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        12595                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5864                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       700000                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       665213                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       488269                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3856052                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       588304                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       239313                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total       827617                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        15404                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         7109                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          698171                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          868010                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       531119                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        12595                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         5864                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          700000                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          762177                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       488269                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             4088718                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        15404                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         7109                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         698171                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         868010                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       531119                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        12595                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         5864                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         700000                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         762177                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       488269                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4088718                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.099708                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.153189                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.123632                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.009447                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.013311                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.011360                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.590787                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.465874                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.538729                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.129447                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.249965                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.088702                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.187033                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.405636                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.130925                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.248977                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.086867                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.157539                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.383113                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.200693                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.764068                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.445341                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.671905                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.129447                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.249965                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.088702                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.250155                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.405636                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.130925                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.248977                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.086867                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.196765                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.383113                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.219929                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.129447                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.249965                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.088702                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.250155                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.405636                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.130925                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.248977                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.086867                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.196765                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.383113                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.219929                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  7361.813600                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6429.960536                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6845.304956                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12235.470942                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11902.031930                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 12042.087542                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 107862.662309                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108562.470945                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 108114.867884                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 106064.694082                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 109633.933596                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 111358.684946                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 110724.909832                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 101206.791995                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103168.835616                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110019.241206                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115855.034018                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 126458.603025                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   103.704305                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   344.955712                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total   149.941555                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 106064.694082                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 109633.933596                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 111358.684946                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 109668.115061                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 101206.791995                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103168.835616                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 110019.241206                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 113658.415016                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 123901.651672                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 106064.694082                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 109633.933596                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 111358.684946                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 109668.115061                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 101206.791995                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103168.835616                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 110019.241206                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 113658.415016                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 123901.651672                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               622                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       17                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       12                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     44.176471                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     51.833333                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1165859                       # number of writebacks
-system.l2c.writebacks::total                  1165859                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          169                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           21                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          110                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           17                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          317                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            169                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             21                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            110                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             17                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                317                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           169                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            21                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           110                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            17                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               317                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        72347                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        72347                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        21060                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        26656                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        47716                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          518                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          636                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1154                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        76722                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        60050                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        136772                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1834                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1415                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        71987                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       133326                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       250233                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2590                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         2459                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        61530                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       144773                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       229898                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       900045                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data       438466                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data       125863                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       564329                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         1834                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         1415                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        71987                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       210048                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       250233                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         2590                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         2459                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        61530                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       204823                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       229898                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1036817                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         1834                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         1415                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        71987                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       210048                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       250233                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         2590                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         2459                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        61530                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       204823                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       229898                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1036817                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        52300                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20634                       # number of ReadReq MSHR uncacheable
+system.l2c.writebacks::writebacks             1054868                       # number of writebacks
+system.l2c.writebacks::total                  1054868                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          139                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data           25                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          132                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           14                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total          311                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst            139                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             25                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst            132                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             14                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                311                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst           139                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            25                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst           132                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data            14                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               311                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks        56418                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total        56418                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        22618                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        28127                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        50745                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          499                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          689                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1188                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        80171                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        45173                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        125344                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1994                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1777                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        61790                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       136941                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       215440                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1649                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1460                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        60675                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data       104783                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       187062                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       773571                       # number of ReadSharedReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu0.data       449504                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu1.data       106576                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::total       556080                       # number of InvalidateReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker         1994                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker         1777                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        61790                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       217112                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       215440                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker         1649                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker         1460                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        60675                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data       149956                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       187062                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           898915                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker         1994                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker         1777                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        61790                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       217112                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       215440                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker         1649                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker         1460                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        60675                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data       149956                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       187062                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          898915                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        52284                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31212                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           95                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17606                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        90635                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        22275                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        15853                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        38128                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        52300                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        42909                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         7181                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        90772                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        30755                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         7509                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        38264                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        52284                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        61967                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           95                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        33459                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total       128763                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    428042501                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    541214000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    969256501                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     12312000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     15177000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     27489000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6238487583                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4639903563                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  10878391146                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    151031002                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    114190001                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   5436084068                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  10966992245                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  30601839845                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    205285501                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    191629001                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   4693018541                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  11590786168                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  26313170250                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  90264026622                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   9157417500                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2543921000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total  11701338500                       # number of InvalidateReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    151031002                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    114190001                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   5436084068                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  17205479828                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  30601839845                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    205285501                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    191629001                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   4693018541                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  16230689731                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  26313170250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 101142417768                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    151031002                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    114190001                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   5436084068                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  17205479828                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  30601839845                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    205285501                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    191629001                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   4693018541                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  16230689731                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  26313170250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 101142417768                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3320084000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3477966008                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6312000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2478199000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   9282561008                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3320084000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3477966008                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6312000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2478199000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   9282561008                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        14690                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       129036                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    461841000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    578903500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   1040744500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     11863000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     16565000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     28428000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7845723550                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4452337552                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  12298061102                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    191553000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    177048502                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   6267361033                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  13793559696                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  28516814074                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    150400000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    136026500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   6069566554                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  11092033207                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  23704989123                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  90099351689                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   9394175000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2170818500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  11564993500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    191553000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    177048502                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   6267361033                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  21639283246                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  28516814074                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    150400000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    136026500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   6069566554                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  15544370759                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  23704989123                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 102397412791                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    191553000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    177048502                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   6267361033                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  21639283246                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  28516814074                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    150400000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    136026500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   6069566554                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  15544370759                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  23704989123                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 102397412791                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3645369500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5226952503                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7066500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    731143001                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   9610531504                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3645369500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5226952503                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7066500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    731143001                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   9610531504                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.093219                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.134678                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.112579                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.010320                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.011003                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.010686                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.572702                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.527134                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.551760                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.126474                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.200994                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.105395                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.184563                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.460976                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.171217                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.339172                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.083119                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.192553                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.426901                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.223735                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.769896                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.489397                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.682634                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.126474                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.200994                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.105395                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.245282                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.460976                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.171217                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.339172                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.083119                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.236577                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.426901                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.242775                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.126474                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.200994                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.105395                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.245282                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.460976                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.171217                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.339172                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.083119                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.236577                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.426901                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.242775                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20324.905081                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20303.646459                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20313.029194                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23768.339768                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23863.207547                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23820.623917                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 81312.890475                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 77267.336603                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 79536.682552                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75514.802228                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 82256.965971                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76272.038697                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80061.794451                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 100288.348496                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20885.125643                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20211.825556                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20734.958685                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75514.802228                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81912.133550                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76272.038697                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79242.515396                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 97550.886770                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75514.802228                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81912.133550                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76272.038697                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79242.515396                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 97550.886770                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168555.103615                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140758.775417                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102416.958217                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81054.464285                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74066.738396                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 72090.282208                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests       3909047                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      2292243                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         2625                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.099708                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.153189                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.123632                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.009447                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.013311                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.011360                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.590787                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.465874                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.538729                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.129447                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.249965                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.088503                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.186999                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.405634                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.130925                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.248977                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.086679                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.157518                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383113                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.200612                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.764068                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.445341                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.671905                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.129447                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.249965                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.088503                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.250126                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.405634                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.130925                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.248977                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.086679                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.196747                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383113                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.219853                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.129447                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.249965                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.088503                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.250126                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.405634                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.130925                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.248977                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.086679                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.196747                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383113                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.219853                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20419.179415                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20581.771963                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20509.301409                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23773.547094                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24042.089985                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23929.292929                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97862.363573                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98561.918668                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 98114.477773                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 101430.021573                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100726.295967                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100034.059398                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105857.183007                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116471.987302                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20898.979764                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20368.736864                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20797.355596                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 101430.021573                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99668.757351                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100034.059398                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103659.545193                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 113912.230624                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 101430.021573                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99668.757351                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100034.059398                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103659.545193                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 113912.230624                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167466.118897                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74384.210526                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 101816.320986                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105875.506808                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84350.581810                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74384.210526                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 49771.477263                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 74479.459252                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests       3616665                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      2148581                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         2925                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               90635                       # Transaction distribution
-system.membus.trans_dist::ReadResp             999620                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38128                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38128                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1272553                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           289712                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           348270                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         267748                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              23                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               90772                       # Transaction distribution
+system.membus.trans_dist::ReadResp             873224                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38264                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38264                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1161561                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           250705                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           347946                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         273520                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              24                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            152656                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           136047                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        908985                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        669058                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122572                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq            139972                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           124377                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        782452                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        660097                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122510                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           54                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24944                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4823028                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4970598                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238389                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       238389                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5208987                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155679                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25584                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4392225                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4540373                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238087                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       238087                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4778460                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155640                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1388                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49888                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    144251456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    144458411                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7283200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7283200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               151741611                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           583612                       # Total snoops (count)
-system.membus.snoopTraffic                     163584                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2475487                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.012229                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.109905                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51168                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    128305664                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    128513860                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7270464                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7270464                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               135784324                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           584171                       # Total snoops (count)
+system.membus.snoopTraffic                     172608                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           2333030                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.013166                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.113984                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2445215     98.78%     98.78% # Request fanout histogram
-system.membus.snoop_fanout::1                   30272      1.22%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2302314     98.68%     98.68% # Request fanout histogram
+system.membus.snoop_fanout::1                   30716      1.32%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2475487                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           102607988                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2333030                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           103320999                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               34812                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            20962995                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21353996                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8793410200                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8035790677                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5849158337                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         5121349382                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           45598905                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           45284261                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -3320,78 +3333,78 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     12529275                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      6783970                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      2045593                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         207524                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       190768                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        16756                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq              90637                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4878287                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38128                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38128                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      3994832                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         3079472                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          721673                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        374590                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp        1096263                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          115                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          115                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           301835                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          301835                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4787847                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       854297                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp       826693                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9608901                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8808719                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              18417620                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    240252134                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    217815813                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              458067947                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2968837                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                 127024720                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          8725155                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.358566                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.483567                       # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests     12127091                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      6563266                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      2068389                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         180040                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       163507                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        16533                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq              90774                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4717359                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38264                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38264                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      3747189                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2956256                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          703976                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        376914                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1080890                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           83                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           83                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           286236                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          286236                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4627139                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       855379                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp       827617                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9817286                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8000729                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              17818015                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    243574806                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    194096942                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              437671748                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2816292                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                 120259472                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples          8375094                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.374182                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.487973                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                5613365     64.34%     64.34% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3095034     35.47%     99.81% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  16756      0.19%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                5257818     62.78%     62.78% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                3100743     37.02%     99.80% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  16533      0.20%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            8725155                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         9593262018                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            8375094                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         9230074402                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2632911                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2547405                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4411209152                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4495965489                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4336941336                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3978820805                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal
index 74f9afa7a..451380e54 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal
@@ -32,135 +32,135 @@
 [    0.000000] NR_IRQS:64 nr_irqs:64 0
 [    0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
 [    0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[    0.000023] Console: colour dummy device 80x25
-[    0.000025] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[    0.000027] pid_max: default: 32768 minimum: 301
-[    0.000038] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[    0.000039] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[    0.000155] hw perfevents: no hardware support available
-[    0.060041] CPU1: Booted secondary processor
+[    0.000024] Console: colour dummy device 80x25
+[    0.000027] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[    0.000028] pid_max: default: 32768 minimum: 301
+[    0.000039] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[    0.000040] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[    0.000160] hw perfevents: no hardware support available
+[    0.060042] CPU1: Booted secondary processor
 [    1.080079] CPU2: failed to come online
-[    2.100151] CPU3: failed to come online
-[    2.100154] Brought up 2 CPUs
-[    2.100155] SMP: Total of 2 processors activated.
+[    2.100148] CPU3: failed to come online
+[    2.100151] Brought up 2 CPUs
+[    2.100152] SMP: Total of 2 processors activated.
 [    2.100226] devtmpfs: initialized
-[    2.100722] atomic64_test: passed
-[    2.100767] regulator-dummy: no parameters
-[    2.101110] NET: Registered protocol family 16
-[    2.101240] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[    2.101248] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[    2.101651] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[    2.101655] Serial: AMBA PL011 UART driver
-[    2.101841] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[    2.101878] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[    2.102452] console [ttyAMA0] enabled
-[    2.102605] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[    2.102668] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[    2.102733] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[    2.102790] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[    2.140329] 3V3: 3300 mV 
-[    2.140389] vgaarb: loaded
-[    2.140455] SCSI subsystem initialized
-[    2.140504] libata version 3.00 loaded.
-[    2.140588] usbcore: registered new interface driver usbfs
-[    2.140613] usbcore: registered new interface driver hub
-[    2.140641] usbcore: registered new device driver usb
-[    2.140687] pps_core: LinuxPPS API ver. 1 registered
-[    2.140698] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[    2.140722] PTP clock support registered
-[    2.140900] Switched to clocksource arch_sys_counter
-[    2.142431] NET: Registered protocol family 2
-[    2.142518] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[    2.142535] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[    2.142552] TCP: Hash tables configured (established 2048 bind 2048)
-[    2.142574] TCP: reno registered
-[    2.142581] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[    2.142593] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[    2.142627] NET: Registered protocol family 1
-[    2.142670] RPC: Registered named UNIX socket transport module.
-[    2.142681] RPC: Registered udp transport module.
-[    2.142689] RPC: Registered tcp transport module.
-[    2.142698] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[    2.142710] PCI: CLS 0 bytes, default 64
-[    2.142942] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[    2.143052] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[    2.145204] fuse init (API version 7.23)
-[    2.145320] msgmni has been set to 469
-[    2.145427] io scheduler noop registered
-[    2.145479] io scheduler cfq registered (default)
-[    2.145859] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[    2.145872] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
-[    2.145883] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[    2.145896] pci_bus 0000:00: root bus resource [bus 00-ff]
-[    2.145906] pci_bus 0000:00: scanning bus
-[    2.145917] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[    2.145930] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[    2.145945] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[    2.145979] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[    2.145991] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]
-[    2.146002] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]
-[    2.146013] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]
-[    2.146024] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]
-[    2.146035] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]
-[    2.146046] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[    2.146081] pci_bus 0000:00: fixups for bus
-[    2.146089] pci_bus 0000:00: bus scan returning with max=00
-[    2.146101] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[    2.146121] pci 0000:00:00.0: fixup irq: got 33
-[    2.146129] pci 0000:00:00.0: assigning IRQ 33
-[    2.146140] pci 0000:00:01.0: fixup irq: got 34
-[    2.146149] pci 0000:00:01.0: assigning IRQ 34
-[    2.146160] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[    2.146173] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[    2.146186] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[    2.146199] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]
-[    2.146211] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]
-[    2.146222] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]
-[    2.146234] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]
-[    2.146245] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]
-[    2.146902] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[    2.147174] ata_piix 0000:00:01.0: version 2.13
-[    2.147184] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[    2.147208] ata_piix 0000:00:01.0: enabling bus mastering
-[    2.147469] scsi0 : ata_piix
-[    2.147563] scsi1 : ata_piix
-[    2.147592] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[    2.147605] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[    2.147706] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[    2.147719] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[    2.147733] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[    2.147745] e1000 0000:00:00.0: enabling bus mastering
-[    2.290935] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[    2.290946] ata1.00: 2096640 sectors, multi 0: LBA 
-[    2.290974] ata1.00: configured for UDMA/33
-[    2.291028] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
-[    2.291135] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[    2.291142] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[    2.291184] sd 0:0:0:0: [sda] Write Protect is off
-[    2.291194] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[    2.291214] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[    2.291351]  sda: sda1
-[    2.291468] sd 0:0:0:0: [sda] Attached SCSI disk
-[    2.411201] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[    2.411215] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[    2.411238] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[    2.411249] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[    2.411270] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[    2.411282] igb: Copyright (c) 2007-2014 Intel Corporation.
-[    2.411355] usbcore: registered new interface driver usb-storage
-[    2.411408] mousedev: PS/2 mouse device common for all mice
-[    2.411558] usbcore: registered new interface driver usbhid
-[    2.411568] usbhid: USB HID core driver
-[    2.411600] TCP: cubic registered
-[    2.411608] NET: Registered protocol family 17
-[    2.411950] VFS: Mounted root (ext2 filesystem) on device 8:1.
-[    2.411985] devtmpfs: mounted
-[    2.412018] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[    2.100728] atomic64_test: passed
+[    2.100773] regulator-dummy: no parameters
+[    2.101119] NET: Registered protocol family 16
+[    2.101251] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[    2.101259] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[    2.101662] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[    2.101665] Serial: AMBA PL011 UART driver
+[    2.101855] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[    2.101892] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[    2.102468] console [ttyAMA0] enabled
+[    2.102623] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[    2.102687] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[    2.102745] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[    2.102803] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[    2.140306] 3V3: 3300 mV 
+[    2.140354] vgaarb: loaded
+[    2.140400] SCSI subsystem initialized
+[    2.140435] libata version 3.00 loaded.
+[    2.140482] usbcore: registered new interface driver usbfs
+[    2.140500] usbcore: registered new interface driver hub
+[    2.140526] usbcore: registered new device driver usb
+[    2.140554] pps_core: LinuxPPS API ver. 1 registered
+[    2.140564] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[    2.140583] PTP clock support registered
+[    2.140715] Switched to clocksource arch_sys_counter
+[    2.142179] NET: Registered protocol family 2
+[    2.142255] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[    2.142273] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[    2.142290] TCP: Hash tables configured (established 2048 bind 2048)
+[    2.142312] TCP: reno registered
+[    2.142319] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[    2.142331] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[    2.142367] NET: Registered protocol family 1
+[    2.142431] RPC: Registered named UNIX socket transport module.
+[    2.142441] RPC: Registered udp transport module.
+[    2.142450] RPC: Registered tcp transport module.
+[    2.142458] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[    2.142471] PCI: CLS 0 bytes, default 64
+[    2.142634] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[    2.142729] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[    2.144357] fuse init (API version 7.23)
+[    2.144445] msgmni has been set to 469
+[    2.144792] io scheduler noop registered
+[    2.144847] io scheduler cfq registered (default)
+[    2.145229] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[    2.145243] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
+[    2.145255] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[    2.145268] pci_bus 0000:00: root bus resource [bus 00-ff]
+[    2.145278] pci_bus 0000:00: scanning bus
+[    2.145289] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[    2.145303] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[    2.145317] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[    2.145353] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[    2.145366] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]
+[    2.145377] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]
+[    2.145388] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]
+[    2.145399] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]
+[    2.145410] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]
+[    2.145421] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[    2.145456] pci_bus 0000:00: fixups for bus
+[    2.145464] pci_bus 0000:00: bus scan returning with max=00
+[    2.145476] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[    2.145496] pci 0000:00:00.0: fixup irq: got 33
+[    2.145505] pci 0000:00:00.0: assigning IRQ 33
+[    2.145516] pci 0000:00:01.0: fixup irq: got 34
+[    2.145525] pci 0000:00:01.0: assigning IRQ 34
+[    2.145537] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[    2.145551] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[    2.145564] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[    2.145577] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]
+[    2.145589] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]
+[    2.145601] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]
+[    2.145612] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]
+[    2.145624] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]
+[    2.146092] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[    2.146340] ata_piix 0000:00:01.0: version 2.13
+[    2.146352] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[    2.146375] ata_piix 0000:00:01.0: enabling bus mastering
+[    2.146628] scsi0 : ata_piix
+[    2.146701] scsi1 : ata_piix
+[    2.146733] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[    2.146746] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[    2.146850] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[    2.146863] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[    2.146877] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[    2.146889] e1000 0000:00:00.0: enabling bus mastering
+[    2.300748] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[    2.300759] ata1.00: 2096640 sectors, multi 0: LBA 
+[    2.300788] ata1.00: configured for UDMA/33
+[    2.300844] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
+[    2.300954] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[    2.300958] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[    2.300986] sd 0:0:0:0: [sda] Write Protect is off
+[    2.300996] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[    2.301021] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[    2.301150]  sda: sda1
+[    2.301268] sd 0:0:0:0: [sda] Attached SCSI disk
+[    2.421014] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[    2.421028] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[    2.421050] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[    2.421060] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[    2.421081] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[    2.421093] igb: Copyright (c) 2007-2014 Intel Corporation.
+[    2.421166] usbcore: registered new interface driver usb-storage
+[    2.421232] mousedev: PS/2 mouse device common for all mice
+[    2.421395] usbcore: registered new interface driver usbhid
+[    2.421405] usbhid: USB HID core driver
+[    2.421435] TCP: cubic registered
+[    2.421443] NET: Registered protocol family 17
+[    2.421846] VFS: Mounted root (ext2 filesystem) on device 8:1.
+[    2.421896] devtmpfs: mounted
+[    2.421929] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
 
INIT: version 2.88 booting

 Starting udev
-[    2.450547] udevd[609]: starting version 182
+[    2.460465] udevd[609]: starting version 182
 Starting Bootlog daemon: bootlogd.

-[    2.513635] random: dd urandom read with 17 bits of entropy available
+[    2.543480] random: dd urandom read with 18 bits of entropy available
 Populating dev cache

 net.ipv4.conf.default.rp_filter = 1

 net.ipv4.conf.all.rp_filter = 1

@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory

 
INIT: Entering runlevel: 5


 Configuring network interfaces... udhcpc (v1.21.1) started

-[    2.641130] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[    2.670941] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
 Sending discover...

 Sending discover...

 Sending discover...

@@ -181,4 +181,3 @@ done.
 rpcbind: cannot get uid of '': Success


 creating NFS state directory: done

 starting statd: done

-Starting auto-serial-console: done

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
index 72828743e..b088465c0 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
@@ -36,7 +36,7 @@ load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM64
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -208,7 +208,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -688,7 +688,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -748,7 +748,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -820,7 +820,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -937,7 +937,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -982,7 +982,7 @@ size=1024
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -994,7 +994,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -1026,29 +1026,36 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -1068,6 +1075,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -1077,7 +1085,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1099,9 +1107,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -1454,7 +1462,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -1767,10 +1775,11 @@ pio=system.iobus.master[21]
 type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
-conf_table_reported=true
+conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1778,7 +1787,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -2009,6 +2018,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -2016,7 +2026,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout
index 0ddf66a62..3120c88a0 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:41:22
-gem5 executing on e108600-lin, pid 23124
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:01:48
+gem5 executing on e108600-lin, pid 17560
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor
 
 Selected 64-bit ARM architecture, updating default disk image...
@@ -15,4 +15,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 51660717372000 because m5_exit instruction encountered
+Exiting @ tick 51688774990000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
index c77078f22..1319d3c2e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
@@ -1,139 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.687765                       # Number of seconds simulated
-sim_ticks                                51687764518000                       # Number of ticks simulated
-final_tick                               51687764518000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.688775                       # Number of seconds simulated
+sim_ticks                                51688774990000                       # Number of ticks simulated
+final_tick                               51688774990000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 151884                       # Simulator instruction rate (inst/s)
-host_op_rate                                   178474                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8204277049                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 687220                       # Number of bytes of host memory used
-host_seconds                                  6300.10                       # Real time elapsed on the host
-sim_insts                                   956884636                       # Number of instructions simulated
-sim_ops                                    1124405089                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 210815                       # Simulator instruction rate (inst/s)
+host_op_rate                                   247704                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            11507504763                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 684036                       # Number of bytes of host memory used
+host_seconds                                  4491.74                       # Real time elapsed on the host
+sim_insts                                   946928269                       # Number of instructions simulated
+sim_ops                                    1112623169                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker       423488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       359680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          10197440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          68348040                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        416768                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             79745416                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst     10197440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        10197440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     96812416                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker       401472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       331520                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          10196544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          65400968                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        425152                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             76755656                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst     10196544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        10196544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     93615936                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          96832996                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         6617                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         5620                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             159335                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1067951                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6512                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1246035                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1512694                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          93636516                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         6273                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         5180                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             159321                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1021903                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6643                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1199320                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1462749                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1515267                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           8193                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           6959                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               197289                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1322325                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8063                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1542830                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          197289                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             197289                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1873024                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1465322                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           7767                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           6414                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               197268                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1265284                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8225                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1484958                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          197268                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             197268                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1811146                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1873422                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1873024                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          8193                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          6959                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              197289                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1322723                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8063                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3416252                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1246035                       # Number of read requests accepted
-system.physmem.writeReqs                      1515267                       # Number of write requests accepted
-system.physmem.readBursts                     1246035                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1515267                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 79703040                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     43200                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  96830656                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  79745416                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               96832996                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      675                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2258                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1811544                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1811146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          7767                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          6414                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              197268                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1265682                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8225                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3296502                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1199320                       # Number of read requests accepted
+system.physmem.writeReqs                      1465322                       # Number of write requests accepted
+system.physmem.readBursts                     1199320                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1465322                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 76712512                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     43968                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  93634496                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  76755656                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               93636516                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      687                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2262                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               74796                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               76131                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               70862                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               68837                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               72123                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               84628                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               78694                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               74893                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               72007                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              129561                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              74825                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              74032                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              72055                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              77727                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              71057                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              73132                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               93267                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               94026                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               93600                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               92665                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               94539                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              102396                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               95600                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               94740                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               92115                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               99710                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              92671                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              94633                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              92127                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              95527                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              92160                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              93203                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               70144                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               74650                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               68418                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               68145                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               72367                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               76479                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               68140                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               71247                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               66581                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              125666                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              74635                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              76739                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              72169                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              75530                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              66172                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              71551                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               89120                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               91694                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               88427                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               87889                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               92386                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               94711                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               88472                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               91239                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               88274                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               94990                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              92874                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              94799                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              93039                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              95949                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              87664                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              91512                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51687762664000                       # Total gap between requests
+system.physmem.numWrRetry                         468                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51688773130000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1246020                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1199305                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1512694                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1180646                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     58552                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       634                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       329                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       497                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       483                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       610                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       505                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1300                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       338                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      384                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      179                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      187                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      133                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      123                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      114                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      100                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       83                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       54                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1462749                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1127245                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     64919                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       779                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       328                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       491                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       476                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       609                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       509                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      1056                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       628                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      296                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      301                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      207                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      165                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      104                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      102                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       93                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       80                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -160,173 +160,184 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    31478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    39945                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    83104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    89526                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    91633                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    87574                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    93055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    92225                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    93220                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    90182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    92806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    94606                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    92258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    89036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    87252                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    83915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    83414                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    82380                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1836                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      971                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      998                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      886                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      592                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      405                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      329                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      265                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      243                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      106                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       686907                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      256.997398                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     154.492038                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     292.459663                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         294027     42.80%     42.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       175466     25.54%     68.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        64376      9.37%     77.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        35669      5.19%     82.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        24767      3.61%     86.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        16380      2.38%     88.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        12324      1.79%     90.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        10264      1.49%     92.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        53634      7.81%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         686907                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         80666                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        15.437595                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      138.740748                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          80664    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    29655                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    37473                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    78822                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    84952                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    87044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    83743                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    88388                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    87662                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    88784                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    85626                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    88571                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    89853                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    87229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    84323                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    82904                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    81964                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    79861                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    79771                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2782                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2080                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1918                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1552                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1354                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      968                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      849                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      803                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      723                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      703                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      804                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      853                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      763                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      765                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      689                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      985                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                     1056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      910                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      634                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                     1027                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                     1982                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                     1362                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      537                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                     1066                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       662940                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      256.956322                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     154.084684                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     293.850288                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         284383     42.90%     42.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       170705     25.75%     68.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        61081      9.21%     77.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        33561      5.06%     82.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        23575      3.56%     86.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        15515      2.34%     88.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        11286      1.70%     90.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         9362      1.41%     91.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        53472      8.07%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         662940                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         77129                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        15.540445                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      141.912078                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          77126    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           80666                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         80666                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.756093                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.057108                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.363487                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           67894     84.17%     84.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            3915      4.85%     89.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            3350      4.15%     93.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            2485      3.08%     96.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35            1103      1.37%     97.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             521      0.65%     98.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             244      0.30%     98.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             153      0.19%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              79      0.10%     98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              83      0.10%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              83      0.10%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              89      0.11%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             450      0.56%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              43      0.05%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              41      0.05%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              30      0.04%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              23      0.03%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               5      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               4      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             6      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             9      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            18      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             7      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             4      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             5      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           80666                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    17151209707                       # Total ticks spent queuing
-system.physmem.totMemAccLat               40501709707                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6226800000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13772.09                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           77129                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         77129                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.968728                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.139558                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        8.416384                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           64621     83.78%     83.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            3761      4.88%     88.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27            3195      4.14%     92.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31            2420      3.14%     95.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35            1145      1.48%     97.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             346      0.45%     97.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             199      0.26%     98.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             173      0.22%     98.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             112      0.15%     98.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              62      0.08%     98.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              79      0.10%     98.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              69      0.09%     98.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             561      0.73%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              77      0.10%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75             111      0.14%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              54      0.07%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              32      0.04%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               4      0.01%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.00%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               3      0.00%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.00%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.00%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             3      0.00%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            13      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             7      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            17      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             5      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             4      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143            12      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             5      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             5      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195            12      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           77129                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    38956691672                       # Total ticks spent queuing
+system.physmem.totMemAccLat               61431060422                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5993165000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       32500.93                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32522.09                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.54                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.87                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.54                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.87                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  51250.93                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.48                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.81                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.48                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.81                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.30                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     964137                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1107294                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.42                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.18                       # Row buffer hit rate for writes
-system.physmem.avgGap                     18718619.94                       # Average gap between requests
-system.physmem.pageHitRate                      75.10                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2629783800                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1434901875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4687519200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4930197840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3375993173280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1305935149860                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29867098550250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34562709276105                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.682675                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49685845654409                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1725967880000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    275945978091                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2563233120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1398589500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                5026242000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4873906080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3375993173280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1305717731910                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29867289276000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34562862151890                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.685632                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49686132095770                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1725967880000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    275664064230                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.physmem.avgWrQLen                        24.35                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     929087                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1069644                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.51                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.11                       # Row buffer hit rate for writes
+system.physmem.avgGap                     19398017.87                       # Average gap between requests
+system.physmem.pageHitRate                      75.09                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2341677240                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1244627175                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4066872600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3778956360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           50725624560.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            43528474080                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             3238135680                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       96319832910                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       74142648000                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       12293580495315                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             12572988857670                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              243.244086                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           51584838283234                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     6009063000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     21570724000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   51180529926500                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 193079953190                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     76356875016                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 211228448294                       # Time in different power states
+system.physmem_1.actEnergy                 2391721500                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1271230125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4491367020                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3858107220                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           51763751520.000015                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            44789626440                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             3183541920                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       99591324540                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       75005755680                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       12290774240265                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             12577142748300                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              243.324450                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           51582206485554                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     5783812250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     22010710000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   51168482999000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 195327455894                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     78768252696                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 218401760160                       # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
@@ -343,30 +354,30 @@ system.realview.nvmem.bw_inst_read::total           14                       # I
 system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               264432116                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         184777930                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12360480                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            195121872                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               131792442                       # Number of BTB hits
+system.cpu.branchPred.lookups               261505306                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         182498706                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12291836                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            192874347                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               130159045                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             67.543654                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                32005520                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            2166164                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         7202634                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            5156312                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses          2046322                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       848562                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             67.483855                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                31722667                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            2144910                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         7175659                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            5109497                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          2066162                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       844099                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -396,70 +407,65 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                    584775                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                584775                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        23234                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       194431                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples       584775                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0          584775    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       584775                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       217665                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 25428.727632                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 21638.505013                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 16299.176879                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767       136227     62.59%     62.59% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535        78767     36.19%     98.77% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-98303         1401      0.64%     99.42% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::98304-131071          854      0.39%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-163839           27      0.01%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::163840-196607          133      0.06%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-229375           57      0.03%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::229376-262143           75      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-294911           47      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::294912-327679           26      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-360447           20      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::360448-393215           15      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-425983            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-491519            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       217665                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples    -10206296                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0       -10206296    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total    -10206296                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        194432     89.33%     89.33% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         23234     10.67%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       217666                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       584775                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                    574319                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                574319                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        21733                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       190269                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples       574319                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0          574319    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       574319                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       212002                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 25745.962302                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 21834.815515                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 18121.324193                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       209468     98.80%     98.80% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         2131      1.01%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607          103      0.05%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          132      0.06%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679           91      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           29      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           12      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287            3      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359           29      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::786432-851967            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       212002                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples    316311704                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0       316311704    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total    316311704                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        190270     89.75%     89.75% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         21733     10.25%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       212003                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       574319                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       584775                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       217666                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       574319                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       212003                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       217666                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       802441                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       212003                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       786322                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    184602893                       # DTB read hits
-system.cpu.dtb.read_misses                     481054                       # DTB read misses
-system.cpu.dtb.write_hits                   163948315                       # DTB write hits
-system.cpu.dtb.write_misses                    103721                       # DTB write misses
+system.cpu.dtb.read_hits                    182769858                       # DTB read hits
+system.cpu.dtb.read_misses                     473161                       # DTB read misses
+system.cpu.dtb.write_hits                   162201881                       # DTB write hits
+system.cpu.dtb.write_misses                    101158                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               47766                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1117                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    80755                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1436                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  15519                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid               47051                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1109                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    79796                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1477                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  15505                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     23435                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                185083947                       # DTB read accesses
-system.cpu.dtb.write_accesses               164052036                       # DTB write accesses
+system.cpu.dtb.perms_faults                     23270                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                183243019                       # DTB read accesses
+system.cpu.dtb.write_accesses               162303039                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         348551208                       # DTB hits
-system.cpu.dtb.misses                          584775                       # DTB misses
-system.cpu.dtb.accesses                     349135983                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                         344971739                       # DTB hits
+system.cpu.dtb.misses                          574319                       # DTB misses
+system.cpu.dtb.accesses                     345546058                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -489,72 +495,70 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                    136740                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                136740                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1077                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       118526                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples       136740                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          136740    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       136740                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       119603                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 27883.393393                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 23898.853743                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 18564.311346                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-32767        67731     56.63%     56.63% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-65535        48774     40.78%     97.41% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-98303         1154      0.96%     98.37% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::98304-131071         1639      1.37%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-163839           37      0.03%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::163840-196607          137      0.11%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-229375           43      0.04%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::229376-262143           18      0.02%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-294911           21      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::294912-327679           20      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-360447           18      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::360448-393215            9      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       119603                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples    -10844796                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       -10844796    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total    -10844796                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        118526     99.10%     99.10% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1077      0.90%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       119603                       # Table walker page sizes translated
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                    135751                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                135751                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1056                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       117755                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       135751                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          135751    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       135751                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       118811                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28810.606762                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 24143.293111                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 28291.561253                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       115975     97.61%     97.61% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         2399      2.02%     99.63% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607          123      0.10%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143          101      0.09%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           44      0.04%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           20      0.02%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751            3      0.00%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            3      0.00%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359          141      0.12%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       118811                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples    315425204                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       315425204    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total    315425204                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        117755     99.11%     99.11% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1056      0.89%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       118811                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       136740                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       136740                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       135751                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       135751                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       119603                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       119603                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       256343                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    457894474                       # ITB inst hits
-system.cpu.itb.inst_misses                     136740                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       118811                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       118811                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       254562                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    452655900                       # ITB inst hits
+system.cpu.itb.inst_misses                     135751                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               47766                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1117                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    57885                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               47051                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1109                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    57242                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    331252                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    322846                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                458031214                       # ITB inst accesses
-system.cpu.itb.hits                         457894474                       # DTB hits
-system.cpu.itb.misses                          136740                       # DTB misses
-system.cpu.itb.accesses                     458031214                       # DTB accesses
-system.cpu.numPwrStateTransitions               33262                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples         16631                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     3032078673.597498                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    59558384510.943253                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows         7336     44.11%     44.11% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         9260     55.68%     99.79% # Distribution of time spent in the clock gated state
+system.cpu.itb.inst_accesses                452791651                       # ITB inst accesses
+system.cpu.itb.hits                         452655900                       # DTB hits
+system.cpu.itb.misses                          135751                       # DTB misses
+system.cpu.itb.accesses                     452791651                       # DTB accesses
+system.cpu.numPwrStateTransitions               33180                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples         16590                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     3039388324.246233                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    59640903157.908096                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows         7293     43.96%     43.96% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10         9262     55.83%     99.79% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.82% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            2      0.01%     99.83% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            2      0.01%     99.84% # Distribution of time spent in the clock gated state
@@ -567,23 +571,23 @@ system.cpu.pwrStateClkGateDist::8.5e+11-9e+11            1      0.01%     99.89%
 system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::max_value 1988777698120                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total           16631                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    1261264097400                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50426500420600                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       2522582223                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::total           16590                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    1265322690755                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50423452299245                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       2530699433                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   956884636                       # Number of instructions committed
-system.cpu.committedOps                    1124405089                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      99545013                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      7771                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                 100854059486                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.636245                       # CPI: cycles per instruction
-system.cpu.ipc                               0.379327                       # IPC: instructions per cycle
+system.cpu.committedInsts                   946928269                       # Number of instructions committed
+system.cpu.committedOps                    1112623169                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      97851669                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      7730                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                 100847957157                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.672536                       # CPI: cycles per instruction
+system.cpu.ipc                               0.374177                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   1      0.00%      0.00% # Class of committed instruction
-system.cpu.op_class_0::IntAlu               779381648     69.32%     69.32% # Class of committed instruction
-system.cpu.op_class_0::IntMult                2317785      0.21%     69.52% # Class of committed instruction
-system.cpu.op_class_0::IntDiv                   99593      0.01%     69.53% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               771151081     69.31%     69.31% # Class of committed instruction
+system.cpu.op_class_0::IntMult                2302642      0.21%     69.52% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                   99189      0.01%     69.53% # Class of committed instruction
 system.cpu.op_class_0::FloatAdd                     0      0.00%     69.53% # Class of committed instruction
 system.cpu.op_class_0::FloatCmp                     0      0.00%     69.53% # Class of committed instruction
 system.cpu.op_class_0::FloatCvt                     0      0.00%     69.53% # Class of committed instruction
@@ -606,522 +610,520 @@ system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     69.53% # Cl
 system.cpu.op_class_0::SimdFloatCmp                13      0.00%     69.53% # Class of committed instruction
 system.cpu.op_class_0::SimdFloatCvt                21      0.00%     69.53% # Class of committed instruction
 system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     69.53% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc           108729      0.01%     69.54% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult                0      0.00%     69.54% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     69.54% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     69.54% # Class of committed instruction
-system.cpu.op_class_0::MemRead              179105650     15.93%     85.47% # Class of committed instruction
-system.cpu.op_class_0::MemWrite             163391641     14.53%    100.00% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc           108989      0.01%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::MemRead              177312606     15.94%     85.47% # Class of committed instruction
+system.cpu.op_class_0::MemWrite             161648619     14.53%    100.00% # Class of committed instruction
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::total               1124405089                       # Class of committed instruction
+system.cpu.op_class_0::total               1112623169                       # Class of committed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16631                       # number of quiesce instructions executed
-system.cpu.tickCycles                      1810679239                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       711902984                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements          11237287                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.957340                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           332608189                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          11237799                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.597272                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        4326295500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.957340                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999917                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999917                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                    16590                       # number of quiesce instructions executed
+system.cpu.tickCycles                      1791525295                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       739174138                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements          11091024                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.954083                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           329234475                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          11091536                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.683398                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        4655908500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.954083                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999910                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999910                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          392                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          384                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           62                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1395920077                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1395920077                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    170244902                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       170244902                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    153016106                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      153016106                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       525044                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        525044                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       336678                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       336678                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      4066137                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      4066137                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      4385244                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4385244                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     323597686                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        323597686                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    324122730                       # number of overall hits
-system.cpu.dcache.overall_hits::total       324122730                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      6163054                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       6163054                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      4362358                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      4362358                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1504058                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1504058                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1246141                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1246141                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       320841                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       320841                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1381544711                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1381544711                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    168600534                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       168600534                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    151416750                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      151416750                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       521238                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        521238                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       337307                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       337307                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      4005998                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4005998                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      4318996                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4318996                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     320354591                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        320354591                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    320875829                       # number of overall hits
+system.cpu.dcache.overall_hits::total       320875829                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      6093036                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       6093036                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      4287792                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      4287792                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1473735                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1473735                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1243168                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1243168                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       314729                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       314729                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     11771553                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       11771553                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     13275611                       # number of overall misses
-system.cpu.dcache.overall_misses::total      13275611                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 101076172500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 101076172500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 157713428000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 157713428000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  27433825500                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  27433825500                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4889648000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   4889648000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     11623996                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       11623996                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     13097731                       # number of overall misses
+system.cpu.dcache.overall_misses::total      13097731                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 107249746000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 107249746000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 169106972500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 169106972500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  27289591000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  27289591000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5063641000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   5063641000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        83000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total        83000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 286223426000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 286223426000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 286223426000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 286223426000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    176407956                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    176407956                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    157378464                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    157378464                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      2029102                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      2029102                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1582819                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1582819                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4386978                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      4386978                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      4385245                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      4385245                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    335369239                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    335369239                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    337398341                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    337398341                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.034936                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.034936                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027719                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.027719                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.741243                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.741243                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.787292                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.787292                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.073135                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.073135                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 303646309500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 303646309500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 303646309500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 303646309500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    174693570                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    174693570                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    155704542                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    155704542                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1994973                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1994973                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1580475                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1580475                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4320727                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4320727                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      4318997                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      4318997                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    331978587                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    331978587                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    333973560                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    333973560                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.034878                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.034878                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027538                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.027538                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.738724                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.738724                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786579                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.786579                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.072842                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.072842                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.035100                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.035100                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.039347                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.039347                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16400.338615                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16400.338615                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36153.251980                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36153.251980                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22015.025186                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22015.025186                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15240.097120                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15240.097120                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.035014                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.035014                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.039218                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.039218                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17602.020733                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17602.020733                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39439.173472                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39439.173472                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 21951.651748                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 21951.651748                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16088.892349                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16088.892349                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24314.839852                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24314.839852                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21560.094372                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21560.094372                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.368719                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26122.368719                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23183.123054                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23183.123054                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           19                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs           19                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      8619796                       # number of writebacks
-system.cpu.dcache.writebacks::total           8619796                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       315342                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       315342                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1930607                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1930607                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          154                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total          154                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70929                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        70929                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2246103                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2246103                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2246103                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2246103                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5847712                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5847712                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2431751                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2431751                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1496531                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1496531                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1245987                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1245987                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       249912                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       249912                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      8512101                       # number of writebacks
+system.cpu.dcache.writebacks::total           8512101                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       311042                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       311042                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1897692                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1897692                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          152                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total          152                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70889                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        70889                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2208886                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2208886                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2208886                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2208886                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5781994                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5781994                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2390100                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2390100                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1466271                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1466271                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1243016                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1243016                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       243840                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       243840                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9525450                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9525450                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     11021981                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     11021981                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33698                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        33698                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.demand_mshr_misses::cpu.data      9415110                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9415110                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     10881381                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     10881381                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33696                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        33696                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67405                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        67405                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  89040002500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  89040002500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  82314078000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  82314078000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  24215113000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  24215113000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  26183606500                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  26183606500                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3424677000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3424677000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        67403                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  94763834000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  94763834000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  88482137000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  88482137000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  25605238500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  25605238500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  26041674000                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  26041674000                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3459340500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3459340500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        82000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        82000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 197537687000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 197537687000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221752800000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 221752800000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6231251500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6231251500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6231251500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6231251500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033149                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033149                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015452                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015452                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.737534                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.737534                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787195                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787195                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.056967                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056967                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 209287645000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 209287645000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 234892883500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 234892883500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6231136500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6231136500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6231136500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6231136500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033098                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033098                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015350                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015350                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.734983                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.734983                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786483                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786483                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.056435                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056435                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028403                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.028403                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032668                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.032668                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15226.468489                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15226.468489                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33849.714876                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33849.714876                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16180.829532                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16180.829532                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21014.349668                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21014.349668                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13703.531643                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13703.531643                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028361                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.028361                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032582                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.032582                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16389.472905                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16389.472905                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37020.265679                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37020.265679                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17462.828154                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17462.828154                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20950.393237                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20950.393237                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14186.927904                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14186.927904                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82000                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20737.885034                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20737.885034                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20119.141922                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20119.141922                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184914.579500                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184914.579500                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92444.944737                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92444.944737                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements          24740790                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.930482                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           432810859                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          24741302                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             17.493455                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       20587192500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.930482                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999864                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999864                       # Average percentage of cache occupancy
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22228.911293                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22228.911293                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21586.679439                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21586.679439                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184922.142094                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184922.142094                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92445.981633                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92445.981633                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements          24547500                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.926335                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           427774095                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          24548012                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             17.426018                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       21430762500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.926335                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999856                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999856                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          308                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          117                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          292                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          126                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         482293482                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        482293482                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    432810859                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       432810859                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     432810859                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        432810859                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    432810859                       # number of overall hits
-system.cpu.icache.overall_hits::total       432810859                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     24741312                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      24741312                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     24741312                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       24741312                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     24741312                       # number of overall misses
-system.cpu.icache.overall_misses::total      24741312                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 329592002500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 329592002500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 329592002500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 329592002500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 329592002500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 329592002500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    457552171                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    457552171                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    457552171                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    457552171                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    457552171                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    457552171                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054073                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.054073                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.054073                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.054073                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.054073                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.054073                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13321.524845                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13321.524845                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13321.524845                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13321.524845                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13321.524845                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13321.524845                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         476870138                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        476870138                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    427774095                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       427774095                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     427774095                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        427774095                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    427774095                       # number of overall hits
+system.cpu.icache.overall_hits::total       427774095                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     24548022                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      24548022                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     24548022                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       24548022                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     24548022                       # number of overall misses
+system.cpu.icache.overall_misses::total      24548022                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 329750158000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 329750158000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 329750158000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 329750158000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 329750158000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 329750158000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    452322117                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    452322117                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    452322117                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    452322117                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    452322117                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    452322117                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054271                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.054271                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.054271                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.054271                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.054271                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.054271                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13432.860619                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13432.860619                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13432.860619                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13432.860619                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13432.860619                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13432.860619                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks     24740790                       # number of writebacks
-system.cpu.icache.writebacks::total          24740790                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24741312                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     24741312                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     24741312                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     24741312                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     24741312                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     24741312                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52293                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total        52293                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52293                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total        52293                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304850691500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 304850691500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304850691500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 304850691500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304850691500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 304850691500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   4087122500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   4087122500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   4087122500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   4087122500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054073                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054073                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054073                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.054073                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054073                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.054073                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12321.524885                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12321.524885                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12321.524885                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12321.524885                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12321.524885                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12321.524885                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 78158.118677                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 78158.118677                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 78158.118677                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 78158.118677                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements          1647378                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65415.989966                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           70152651                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1710758                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            41.006765                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       5897369000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9082.397486                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   468.031396                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   465.228429                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8079.882193                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 47320.450462                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.138586                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.007142                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007099                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.123289                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.722053                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.998169                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          304                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63076                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          301                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          292                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          861                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5993                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55903                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004639                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962463                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        587932179                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       587932179                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       928594                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       259345                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1187939                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks      8619796                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      8619796                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     24737128                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     24737128                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        30047                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        30047                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1665980                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1665980                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24634240                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     24634240                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7256699                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      7256699                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       698207                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       698207                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       928594                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       259345                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     24634240                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      8922679                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        34744858                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       928594                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       259345                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     24634240                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      8922679                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       34744858                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6617                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5620                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        12237                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         4025                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         4025                       # number of UpgradeReq misses
+system.cpu.icache.writebacks::writebacks     24547500                       # number of writebacks
+system.cpu.icache.writebacks::total          24547500                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24548022                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     24548022                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     24548022                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     24548022                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     24548022                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     24548022                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52291                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total        52291                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52291                       # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total        52291                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305202137000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 305202137000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305202137000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 305202137000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305202137000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 305202137000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   4421533000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   4421533000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   4421533000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   4421533000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054271                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054271                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054271                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.054271                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054271                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.054271                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12432.860660                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12432.860660                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12432.860660                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12432.860660                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12432.860660                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12432.860660                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 84556.290757                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 84556.290757                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 84556.290757                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 84556.290757                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements          1591901                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65408.549959                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           69520908                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1655396                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            41.996542                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       6255171000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  9036.958133                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   433.683776                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   402.305370                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7871.756997                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 47663.845683                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.137893                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.006617                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006139                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.120113                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.727293                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.998055                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          271                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63224                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          271                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          790                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5976                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56108                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004135                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.964722                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        582399864                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       582399864                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       921588                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       261482                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1183070                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      8512101                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      8512101                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     24543775                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     24543775                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data        29573                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total        29573                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1660508                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1660508                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24440962                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     24440962                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7164937                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      7164937                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       700668                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       700668                       # number of InvalidateReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker       921588                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker       261482                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst     24440962                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      8825445                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        34449477                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker       921588                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker       261482                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst     24440962                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      8825445                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       34449477                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6273                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5180                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        11453                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         4073                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         4073                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       731868                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       731868                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       107071                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total       107071                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       337287                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       337287                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       547780                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       547780                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         6617                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         5620                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst       107071                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1069155                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1188463                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker         6617                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         5620                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst       107071                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1069155                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1188463                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    582961000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    496565500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1079526500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     72338500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     72338500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_misses::cpu.data       696158                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       696158                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       107059                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total       107059                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       326956                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       326956                       # number of ReadSharedReq misses
+system.cpu.l2cache.InvalidateReq_misses::cpu.data       542348                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       542348                       # number of InvalidateReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker         6273                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker         5180                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst       107059                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1023114                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1141626                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker         6273                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker         5180                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst       107059                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1023114                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1141626                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    939749000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    683365000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1623114000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     72777000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     72777000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        80500                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total        80500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  60704703500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  60704703500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   8853700500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   8853700500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  28854909000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  28854909000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data      1874000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::total      1874000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    582961000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    496565500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   8853700500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  89559612500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  99492839500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    582961000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    496565500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   8853700500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  89559612500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  99492839500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       935211                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       264965                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1200176                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      8619796                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      8619796                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks     24737128                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total     24737128                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        34072                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        34072                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  66999821500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  66999821500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  11524194500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total  11524194500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  37120013000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  37120013000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data      2135500                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::total      2135500                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    939749000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    683365000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  11524194500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 104119834500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 117267143000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    939749000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    683365000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  11524194500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 104119834500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 117267143000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       927861                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       266662                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1194523                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      8512101                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      8512101                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     24543775                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     24543775                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        33646                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        33646                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2397848                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      2397848                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24741311                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     24741311                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7593986                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7593986                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1245987                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1245987                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       935211                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       264965                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     24741311                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9991834                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     35933321                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       935211                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       264965                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     24741311                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9991834                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     35933321                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.007075                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.021210                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.010196                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.118132                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.118132                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      2356666                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      2356666                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24548021                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     24548021                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7491893                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7491893                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1243016                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1243016                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       927861                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       266662                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     24548021                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9848559                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     35591103                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       927861                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       266662                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     24548021                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9848559                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     35591103                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006761                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.019425                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.009588                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.121055                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.121055                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.305219                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.305219                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004328                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004328                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.044415                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.044415                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.439635                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.439635                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.007075                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.021210                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004328                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.107003                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.033074                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.007075                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.021210                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004328                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.107003                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.033074                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88100.498715                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88356.850534                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 88218.231593                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17972.298137                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17972.298137                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.295400                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.295400                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004361                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004361                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043641                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043641                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.436316                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.436316                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006761                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.019425                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004361                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.103885                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.032076                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006761                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.019425                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004361                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.103885                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.032076                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 149808.544556                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 131923.745174                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 141719.549463                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17868.156150                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17868.156150                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82944.880088                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82944.880088                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82689.995424                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82689.995424                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85550.018234                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85550.018234                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data     3.421081                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total     3.421081                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88100.498715                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88356.850534                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82689.995424                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83766.724656                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 83715.554881                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88100.498715                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88356.850534                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82689.995424                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83766.724656                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 83715.554881                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96242.263251                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96242.263251                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107643.397566                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107643.397566                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 113532.135823                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 113532.135823                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data     3.937509                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total     3.937509                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 149808.544556                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 131923.745174                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107643.397566                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101767.578686                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 102719.404604                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 149808.544556                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 131923.745174                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107643.397566                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101767.578686                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 102719.404604                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks      1406063                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1406063                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1356118                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1356118                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
@@ -1132,191 +1134,191 @@ system.cpu.l2cache.demand_mshr_hits::total           24                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6617                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5620                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        12237                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6273                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5180                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        11453                       # number of ReadReq MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            3                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total            3                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4025                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         4025                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4073                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         4073                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       731868                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       731868                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       107068                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total       107068                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       337266                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       337266                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       547780                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       547780                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6617                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5620                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       107068                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1069134                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1188439                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6617                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5620                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       107068                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1069134                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1188439                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52293                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33698                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        85991                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       696158                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       696158                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       107056                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total       107056                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       326935                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       326935                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       542348                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       542348                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6273                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5180                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       107056                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1023093                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1141602                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6273                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5180                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       107056                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1023093                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1141602                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52291                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33696                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        85987                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52293                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67405                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119698                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    516791000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    440365500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    957156500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     76811500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     76811500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52291                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119694                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    877019000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    631565000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1508584000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     77761500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     77761500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        70500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        70500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  53386023001                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  53386023001                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   7782841501                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   7782841501                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  25481161022                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  25481161022                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  11306022501                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  11306022501                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    516791000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    440365500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7782841501                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  78867184023                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  87607182024                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    516791000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    440365500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7782841501                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  78867184023                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  87607182024                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3276571500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5809931000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   9086502500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3276571500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5809931000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9086502500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.007075                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.021210                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010196                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60038241001                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60038241001                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10453433004                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10453433004                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33849413548                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33849413548                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  11199554001                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  11199554001                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    877019000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    631565000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10453433004                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  93887654549                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 105849671553                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    877019000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    631565000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10453433004                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  93887654549                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 105849671553                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3611009000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5809783000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   9420792000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3611009000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5809783000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9420792000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006761                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.019425                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.009588                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.118132                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.118132                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.121055                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.121055                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.305219                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.305219                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004327                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004327                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.044412                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.044412                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.439635                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.439635                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.007075                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.021210                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004327                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.107001                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.033073                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.007075                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.021210                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004327                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.107001                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.033073                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78356.850534                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78218.231593                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19083.602484                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19083.602484                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.295400                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.295400                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004361                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004361                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043639                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043639                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.436316                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.436316                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006761                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.019425                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004361                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.103883                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.032075                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006761                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.019425                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004361                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.103883                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.032075                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 121923.745174                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131719.549463                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19091.946968                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19091.946968                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70500                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72944.879406                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72944.879406                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72690.640537                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72690.640537                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75552.119164                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75552.119164                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20639.713938                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20639.713938                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78356.850534                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72690.640537                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.351916                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73716.178974                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78356.850534                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72690.640537                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.351916                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73716.178974                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62657.937009                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172411.745504                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105668.064100                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62657.937009                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.362436                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 75911.899113                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     72719983                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     36740859                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4284                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1912                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1912                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86242.262534                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86242.262534                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97644.531871                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97644.531871                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103535.606613                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103535.606613                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20650.125014                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20650.125014                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 121923.745174                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97644.531871                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91768.445829                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92720.292670                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 121923.745174                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97644.531871                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91768.445829                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92720.292670                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69056.032587                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172417.586657                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109560.654518                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69056.032587                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.724270                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78707.303624                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests     72021080                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     36381496                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4425                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1940                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1940                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq        1798088                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      34134170                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq        1770978                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      33811680                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33707                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33707                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty     10025859                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     24740790                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2858806                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        34075                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      9868219                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     24547500                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2814706                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        33649                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        34076                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2397848                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2397848                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     24741312                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7596551                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1271756                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1245987                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     74327998                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     33916673                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       673778                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2238495                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total         111156944                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3170201152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1191384986                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2119720                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7481688                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         4371187546                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2188425                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              94133704                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     39520716                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.018595                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.135091                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        33650                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2356666                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2356666                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     24548022                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7494335                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1271849                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1243016                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     73748124                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     33477065                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       672528                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2206986                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total         110104703                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3145459904                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1175323090                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2133296                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7422888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         4330339178                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2114439                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic              90765792                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     39101108                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.018304                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.134047                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           38785811     98.14%     98.14% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             734905      1.86%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           38385418     98.17%     98.17% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             715690      1.83%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       39520716                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    70288980496                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       39101108                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    69634684493                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1482392                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1487890                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   37194713363                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   36904751913                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   15679329987                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   15462672587                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     408839447                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     405908415                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1303303960                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1279140469                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40309                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40309                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40325                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40325                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1333,11 +1335,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230976                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230976                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231008                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231008                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353760                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353792                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1352,102 +1354,102 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334336                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334336                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334464                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334464                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             37793000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492384                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             37691500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               335000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               338000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               16000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25128500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25239000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            36456000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36441500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           569339894                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           569511366                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147736000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147768000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115470                       # number of replacements
-system.iocache.tags.tagsinuse               10.448409                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115486                       # number of replacements
+system.iocache.tags.tagsinuse               10.448155                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115486                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115502                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13140724969000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.519445                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.928964                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.219965                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.433060                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.653026                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13141696144000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.519387                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.928768                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219962                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.433048                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653010                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039749                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039749                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1039893                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039893                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8824                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8861                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8840                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8877                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115488                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115528                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115504                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115544                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115488                       # number of overall misses
-system.iocache.overall_misses::total           115528                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1631024611                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1636110611                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115504                       # number of overall misses
+system.iocache.overall_misses::total           115544                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5085500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   2067712004                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   2072797504                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12739251283                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12739251283                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14370275894                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14375712894                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14370275894                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14375712894                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13276938862                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13276938862                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5436500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15344650866                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15350087366                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5436500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15344650866                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15350087366                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8824                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8861                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8840                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8877                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115488                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115528                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115504                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115544                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115488                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115528                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115504                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115544                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1461,53 +1463,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 184839.597801                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 184641.757251                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 233904.072851                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 233502.028163                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119433.466615                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 119433.466615                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124430.900994                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124434.880670                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124430.900994                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124434.880670                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         31942                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124474.413692                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 124474.413692                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 132849.519203                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 132850.579571                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 132849.519203                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 132850.579571                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         54006                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3389                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3503                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.425199                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    15.417071                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8824                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8861                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8840                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8877                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115488                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115528                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115504                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115544                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115488                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115528                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1189824611                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1193060611                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115504                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115544                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3235500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1625712004                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1628947504                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7399114026                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7399114026                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8588938637                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8592375637                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8588938637                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8592375637                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7936726922                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7936726922                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3436500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9562438926                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9565875426                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3436500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9562438926                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9565875426                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1521,95 +1523,95 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134839.597801                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 134641.757251                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 183904.072851                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 183502.028163                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69368.428204                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69368.428204                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74370.831922                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 74374.832396                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74370.831922                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 74374.832396                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests       3617552                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1792214                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3206                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74408.675111                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74408.675111                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 82788.811868                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 82789.893253                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 82788.811868                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 82789.893253                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests       3510315                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      1740308                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3085                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               85991                       # Transaction distribution
-system.membus.trans_dist::ReadResp             551423                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               85987                       # Transaction distribution
+system.membus.trans_dist::ReadResp             540308                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33707                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33707                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1512694                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           249055                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4641                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1462749                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           243530                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4703                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               7                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            731311                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           731311                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        465432                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        654388                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            695596                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           695596                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        454321                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        648947                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6920                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4683490                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4813146                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237510                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237510                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5050656                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6916                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4528935                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4658587                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237673                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237673                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4896260                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    169337260                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    169507674                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7241152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7241152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               176748826                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3012                       # Total snoops (count)
-system.membus.snoopTraffic                     192320                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           1975472                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.014689                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.120303                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    163142636                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    163313042                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7249536                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7249536                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               170562578                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2899                       # Total snoops (count)
+system.membus.snoopTraffic                     185088                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           1923263                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.016618                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.127834                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 1946455     98.53%     98.53% # Request fanout histogram
-system.membus.snoop_fanout::1                   29017      1.47%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 1891303     98.34%     98.34% # Request fanout histogram
+system.membus.snoop_fanout::1                   31960      1.66%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             1975472                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            99807500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             1923263                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            99811000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               18828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5588000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5612500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9976212567                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9664854495                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6680987810                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6432615655                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44817130                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44921497                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -1652,28 +1654,28 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal
index 5bd114d12..3c88ced61 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal
@@ -32,135 +32,135 @@
 [    0.000000] NR_IRQS:64 nr_irqs:64 0
 [    0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
 [    0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[    0.000031] Console: colour dummy device 80x25
-[    0.000034] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[    0.000036] pid_max: default: 32768 minimum: 301
-[    0.000052] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[    0.000053] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[    0.000228] hw perfevents: no hardware support available
+[    0.000027] Console: colour dummy device 80x25
+[    0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[    0.000032] pid_max: default: 32768 minimum: 301
+[    0.000046] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[    0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[    0.000181] hw perfevents: no hardware support available
 [    1.060097] CPU1: failed to come online
 [    2.080187] CPU2: failed to come online
 [    3.100278] CPU3: failed to come online
-[    3.100282] Brought up 1 CPUs
+[    3.100281] Brought up 1 CPUs
 [    3.100283] SMP: Total of 1 processors activated.
-[    3.100367] devtmpfs: initialized
-[    3.101019] atomic64_test: passed
-[    3.101081] regulator-dummy: no parameters
-[    3.101652] NET: Registered protocol family 16
-[    3.101829] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[    3.101840] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[    3.102554] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[    3.102561] Serial: AMBA PL011 UART driver
-[    3.102830] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[    3.102879] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[    3.103440] console [ttyAMA0] enabled
-[    3.103555] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[    3.103592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[    3.103630] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[    3.103665] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[    3.130723] 3V3: 3300 mV 
-[    3.130781] vgaarb: loaded
-[    3.130844] SCSI subsystem initialized
-[    3.130897] libata version 3.00 loaded.
-[    3.130956] usbcore: registered new interface driver usbfs
-[    3.130977] usbcore: registered new interface driver hub
-[    3.131019] usbcore: registered new device driver usb
-[    3.131051] pps_core: LinuxPPS API ver. 1 registered
-[    3.131061] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[    3.131081] PTP clock support registered
-[    3.131243] Switched to clocksource arch_sys_counter
-[    3.132709] NET: Registered protocol family 2
-[    3.132818] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[    3.132843] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[    3.132874] TCP: Hash tables configured (established 2048 bind 2048)
-[    3.132892] TCP: reno registered
-[    3.132900] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[    3.132916] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[    3.132971] NET: Registered protocol family 1
-[    3.133024] RPC: Registered named UNIX socket transport module.
-[    3.133035] RPC: Registered udp transport module.
-[    3.133043] RPC: Registered tcp transport module.
-[    3.133051] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[    3.133064] PCI: CLS 0 bytes, default 64
-[    3.133270] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[    3.133439] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[    3.135679] fuse init (API version 7.23)
-[    3.135790] msgmni has been set to 469
-[    3.138999] io scheduler noop registered
-[    3.139069] io scheduler cfq registered (default)
-[    3.139634] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[    3.139648] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
-[    3.139659] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[    3.139672] pci_bus 0000:00: root bus resource [bus 00-ff]
-[    3.139682] pci_bus 0000:00: scanning bus
-[    3.139694] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[    3.139709] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[    3.139724] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[    3.139771] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[    3.139784] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]
-[    3.139795] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]
-[    3.139806] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]
-[    3.139818] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]
-[    3.139829] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]
-[    3.139841] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[    3.139883] pci_bus 0000:00: fixups for bus
-[    3.139892] pci_bus 0000:00: bus scan returning with max=00
-[    3.139905] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[    3.139929] pci 0000:00:00.0: fixup irq: got 33
-[    3.139938] pci 0000:00:00.0: assigning IRQ 33
-[    3.139949] pci 0000:00:01.0: fixup irq: got 34
-[    3.139958] pci 0000:00:01.0: assigning IRQ 34
-[    3.139971] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[    3.139985] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[    3.139998] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[    3.140011] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]
-[    3.140023] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]
-[    3.140035] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]
-[    3.140047] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]
-[    3.140059] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]
-[    3.140718] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[    3.141064] ata_piix 0000:00:01.0: version 2.13
-[    3.141076] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[    3.141104] ata_piix 0000:00:01.0: enabling bus mastering
-[    3.141758] scsi0 : ata_piix
-[    3.141889] scsi1 : ata_piix
-[    3.141926] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[    3.141938] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[    3.142070] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[    3.142082] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[    3.142099] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[    3.142111] e1000 0000:00:00.0: enabling bus mastering
-[    3.301279] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[    3.301289] ata1.00: 2096640 sectors, multi 0: LBA 
-[    3.301320] ata1.00: configured for UDMA/33
-[    3.301387] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
-[    3.301528] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[    3.301559] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[    3.301607] sd 0:0:0:0: [sda] Write Protect is off
-[    3.301617] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[    3.301642] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[    3.301803]  sda: sda1
-[    3.301959] sd 0:0:0:0: [sda] Attached SCSI disk
-[    3.421568] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[    3.421582] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[    3.421605] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[    3.421616] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[    3.421640] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[    3.421652] igb: Copyright (c) 2007-2014 Intel Corporation.
-[    3.421739] usbcore: registered new interface driver usb-storage
-[    3.421808] mousedev: PS/2 mouse device common for all mice
-[    3.422005] usbcore: registered new interface driver usbhid
-[    3.422015] usbhid: USB HID core driver
-[    3.422054] TCP: cubic registered
-[    3.422062] NET: Registered protocol family 17
-[    3.422515] VFS: Mounted root (ext2 filesystem) on device 8:1.
-[    3.422556] devtmpfs: mounted
-[    3.422604] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[    3.100354] devtmpfs: initialized
+[    3.100991] atomic64_test: passed
+[    3.101046] regulator-dummy: no parameters
+[    3.101555] NET: Registered protocol family 16
+[    3.101721] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[    3.101732] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[    3.102038] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[    3.102043] Serial: AMBA PL011 UART driver
+[    3.102290] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[    3.102335] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[    3.102901] console [ttyAMA0] enabled
+[    3.103000] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[    3.103038] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[    3.103076] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[    3.103112] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[    3.130703] 3V3: 3300 mV 
+[    3.130755] vgaarb: loaded
+[    3.130815] SCSI subsystem initialized
+[    3.130867] libata version 3.00 loaded.
+[    3.130924] usbcore: registered new interface driver usbfs
+[    3.130945] usbcore: registered new interface driver hub
+[    3.130986] usbcore: registered new device driver usb
+[    3.131018] pps_core: LinuxPPS API ver. 1 registered
+[    3.131027] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[    3.131047] PTP clock support registered
+[    3.131197] Switched to clocksource arch_sys_counter
+[    3.132637] NET: Registered protocol family 2
+[    3.132735] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[    3.132757] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[    3.132784] TCP: Hash tables configured (established 2048 bind 2048)
+[    3.132801] TCP: reno registered
+[    3.132809] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[    3.132824] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[    3.132871] NET: Registered protocol family 1
+[    3.132921] RPC: Registered named UNIX socket transport module.
+[    3.132932] RPC: Registered udp transport module.
+[    3.132940] RPC: Registered tcp transport module.
+[    3.132948] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[    3.132961] PCI: CLS 0 bytes, default 64
+[    3.133158] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[    3.133307] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[    3.135503] fuse init (API version 7.23)
+[    3.135611] msgmni has been set to 469
+[    3.138767] io scheduler noop registered
+[    3.138836] io scheduler cfq registered (default)
+[    3.139309] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[    3.139322] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
+[    3.139334] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[    3.139347] pci_bus 0000:00: root bus resource [bus 00-ff]
+[    3.139357] pci_bus 0000:00: scanning bus
+[    3.139369] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[    3.139383] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[    3.139398] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[    3.139443] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[    3.139455] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]
+[    3.139467] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]
+[    3.139478] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]
+[    3.139489] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]
+[    3.139501] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]
+[    3.139513] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[    3.139555] pci_bus 0000:00: fixups for bus
+[    3.139564] pci_bus 0000:00: bus scan returning with max=00
+[    3.139576] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[    3.139598] pci 0000:00:00.0: fixup irq: got 33
+[    3.139607] pci 0000:00:00.0: assigning IRQ 33
+[    3.139619] pci 0000:00:01.0: fixup irq: got 34
+[    3.139628] pci 0000:00:01.0: assigning IRQ 34
+[    3.139641] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[    3.139654] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[    3.139668] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[    3.139681] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]
+[    3.139693] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]
+[    3.139705] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]
+[    3.139717] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]
+[    3.139729] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]
+[    3.140375] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[    3.140706] ata_piix 0000:00:01.0: version 2.13
+[    3.140717] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[    3.140741] ata_piix 0000:00:01.0: enabling bus mastering
+[    3.141104] scsi0 : ata_piix
+[    3.141497] scsi1 : ata_piix
+[    3.141534] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[    3.141547] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[    3.141673] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[    3.141686] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[    3.141703] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[    3.141715] e1000 0000:00:00.0: enabling bus mastering
+[    3.301229] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[    3.301240] ata1.00: 2096640 sectors, multi 0: LBA 
+[    3.301271] ata1.00: configured for UDMA/33
+[    3.301328] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
+[    3.301469] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[    3.301499] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[    3.301548] sd 0:0:0:0: [sda] Write Protect is off
+[    3.301558] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[    3.301583] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[    3.301736]  sda: sda1
+[    3.301887] sd 0:0:0:0: [sda] Attached SCSI disk
+[    3.421517] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[    3.421531] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[    3.421555] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[    3.421565] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[    3.421589] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[    3.421601] igb: Copyright (c) 2007-2014 Intel Corporation.
+[    3.421690] usbcore: registered new interface driver usb-storage
+[    3.421758] mousedev: PS/2 mouse device common for all mice
+[    3.421951] usbcore: registered new interface driver usbhid
+[    3.421962] usbhid: USB HID core driver
+[    3.421997] TCP: cubic registered
+[    3.422006] NET: Registered protocol family 17
+[    3.422432] VFS: Mounted root (ext2 filesystem) on device 8:1.
+[    3.422472] devtmpfs: mounted
+[    3.422501] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
 
INIT: version 2.88 booting

 Starting udev
-[    3.464675] udevd[607]: starting version 182
+[    3.464513] udevd[607]: starting version 182
 Starting Bootlog daemon: bootlogd.

-[    3.594846] random: dd urandom read with 20 bits of entropy available
+[    3.604760] random: dd urandom read with 21 bits of entropy available
 Populating dev cache

 net.ipv4.conf.default.rp_filter = 1

 net.ipv4.conf.all.rp_filter = 1

@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory

 
INIT: Entering runlevel: 5


 Configuring network interfaces... udhcpc (v1.21.1) started

-[    3.761479] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[    3.771432] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
 Sending discover...

 Sending discover...

 Sending discover...

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
index 72dca03c3..d65c44016 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
@@ -36,7 +36,7 @@ load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM64
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -229,7 +229,7 @@ useIndirect=true
 [system.cpu0.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -591,7 +591,7 @@ pipelined=true
 [system.cpu0.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -723,7 +723,7 @@ port=system.cpu0.toL2Bus.slave[2]
 [system.cpu0.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -948,7 +948,7 @@ useIndirect=true
 [system.cpu1.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1310,7 +1310,7 @@ pipelined=true
 [system.cpu1.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1442,7 +1442,7 @@ port=system.cpu1.toL2Bus.slave[2]
 [system.cpu1.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -1589,7 +1589,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -1635,7 +1635,7 @@ size=1024
 [system.l2c]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1733,27 +1733,27 @@ system=system
 
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -1773,6 +1773,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -1782,7 +1783,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1804,9 +1805,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -2159,7 +2160,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -2472,10 +2473,11 @@ pio=system.iobus.master[21]
 type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
-conf_table_reported=true
+conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -2483,7 +2485,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -2714,6 +2716,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -2721,7 +2724,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr
index ab526e302..d6ed411d1 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr
@@ -11,6 +11,6 @@ warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
 warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
 warn: allocating bonus target for snoop
 warn: allocating bonus target for snoop
+warn: allocating bonus target for snoop
 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
 warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: allocating bonus target for snoop
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout
index 336574573..0d7fb0d1c 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:10:34
-gem5 executing on e108600-lin, pid 12199
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:43:00
+gem5 executing on e108600-lin, pid 17330
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3-dual
 
 Selected 64-bit ARM architecture, updating default disk image...
@@ -15,4 +15,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 47384351300000 because m5_exit instruction encountered
+Exiting @ tick 47384942719000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index 7c01d248f..79f2acec9 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -1,169 +1,169 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.383918                       # Number of seconds simulated
-sim_ticks                                47383917710000                       # Number of ticks simulated
-final_tick                               47383917710000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.384943                       # Number of seconds simulated
+sim_ticks                                47384942719000                       # Number of ticks simulated
+final_tick                               47384942719000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 126839                       # Simulator instruction rate (inst/s)
-host_op_rate                                   149150                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6559041658                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 782584                       # Number of bytes of host memory used
-host_seconds                                  7224.21                       # Real time elapsed on the host
-sim_insts                                   916315151                       # Number of instructions simulated
-sim_ops                                    1077489368                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 146603                       # Simulator instruction rate (inst/s)
+host_op_rate                                   172405                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7419029838                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 776468                       # Number of bytes of host memory used
+host_seconds                                  6386.95                       # Real time elapsed on the host
+sim_insts                                   936348150                       # Number of instructions simulated
+sim_ops                                    1101141201                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker       217728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       211200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          4242016                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         16335944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     21100544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        95616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        61568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3171760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          9979472                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     12170752                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        426688                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             68013288                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      4242016                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3171760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7413776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     84160640                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker       225984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       211072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          4210272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         17875336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     22288384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       132032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        98944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3431264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         10538960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     15414592                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        437696                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             74864536                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      4210272                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3431264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7641536                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     90448704                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          84181224                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         3402                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         3300                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             82234                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            255262                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       329696                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         1494                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker          962                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             49603                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            155942                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       190168                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6667                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1078730                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1315010                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          90469288                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         3531                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         3298                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             81738                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            279315                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       348256                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2063                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1546                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             53657                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            164684                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       240853                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6839                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1185780                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1413261                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1317584                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          4595                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          4457                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               89524                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              344757                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       445310                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2018                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          1299                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               66937                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              210609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       256854                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9005                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1435366                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          89524                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          66937                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             156462                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1776144                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1415835                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          4769                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          4454                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               88853                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              377237                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       470368                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2786                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2088                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               72413                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              222412                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       325306                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9237                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1579922                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          88853                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          72413                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             161265                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1908807                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1776578                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1776144                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         4595                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         4457                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              89524                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             345191                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       445310                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2018                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         1299                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              66937                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             210609                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       256854                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9005                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3211944                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1078730                       # Number of read requests accepted
-system.physmem.writeReqs                      1317584                       # Number of write requests accepted
-system.physmem.readBursts                     1078730                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1317584                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 69010688                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     28032                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  84179968                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  68013288                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               84181224                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      438                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1909241                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1908807                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         4769                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         4454                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              88853                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             377671                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       470368                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2786                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2088                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              72413                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             222412                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       325306                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9237                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3489164                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1185780                       # Number of read requests accepted
+system.physmem.writeReqs                      1415835                       # Number of write requests accepted
+system.physmem.readBursts                     1185780                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1415835                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 75867200                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     22720                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  90467840                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  74864536                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               90469288                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      355                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               67696                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               73149                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               67549                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               71981                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               66956                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               73789                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               64889                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               66635                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               57075                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               82656                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              58467                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              69413                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              60741                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              63810                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              67156                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              66330                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               82175                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               87404                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               82364                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               86039                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               82832                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               88693                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               80795                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               83065                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               76149                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               79916                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              77037                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              82986                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              77147                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              80171                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              84038                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              84501                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               74918                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               82946                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               75146                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               74319                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               73960                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               83356                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               71088                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               75076                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               69225                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               91582                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              63014                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              68676                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              68042                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              71091                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              73017                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              69969                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               88621                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               92960                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               88280                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               90026                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               89701                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               97248                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               87218                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               89230                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               86326                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               88636                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              82100                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              87622                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              86001                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              87485                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              85741                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              86365                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                       50212                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47383916196500                       # Total gap between requests
+system.physmem.numWrRetry                       51113                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47384941205500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
-system.physmem.readPktSize::4                   21334                       # Read request sizes (log2)
+system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1057371                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1164422                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1315010                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    477824                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    264556                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     85571                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     63109                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     41587                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     35911                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     32865                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     30424                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     27932                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      7543                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     3912                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2354                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1437                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1085                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      609                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      513                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      445                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      357                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      146                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       93                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       13                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1413261                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    492558                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    272193                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    123866                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     77106                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     49827                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     41505                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     37948                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     35214                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     31591                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      9310                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     5210                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     3059                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1824                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1397                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      811                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      674                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      576                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      471                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      162                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      110                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -189,136 +189,147 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    22527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    26520                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    36837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    42274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    46464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    50322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    56496                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    66561                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    68608                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    74012                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    78194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    76215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    79218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    90231                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    80845                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    75138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    70175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     5598                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     3927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2866                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2290                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1845                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1368                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1488                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1958                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     2035                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     2146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     2370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     2522                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     2687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     2917                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                     2998                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                     2934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                     3116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                     3382                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                     4014                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                     5428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                    24238                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                   118579                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1002120                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      152.866515                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     102.517170                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     198.697434                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         641919     64.06%     64.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       209293     20.89%     84.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        56817      5.67%     90.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        24891      2.48%     93.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        19538      1.95%     95.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11144      1.11%     96.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7510      0.75%     96.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         6154      0.61%     97.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        24854      2.48%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1002120                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         61846                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        17.434870                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       71.484606                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           61843    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    22656                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    26213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    37414                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    43560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    48703                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    53588                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    59870                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    65839                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    71191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    73927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    78606                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    82389                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    81499                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    83906                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    89741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    97285                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    86545                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    80600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     8679                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     5080                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     3802                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     2902                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     2352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     2103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1842                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1736                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1672                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1659                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1715                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1630                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1838                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1694                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1790                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1915                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1936                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     2089                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     2158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     2578                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     2909                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                     3105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                     3321                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                     3357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                     3394                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                     4009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                     5197                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                     6401                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                    25051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                   120445                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples      1083045                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      153.580618                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     102.695829                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     199.684011                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         694535     64.13%     64.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       223527     20.64%     84.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        61545      5.68%     90.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        27125      2.50%     92.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        21919      2.02%     94.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        12312      1.14%     96.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8465      0.78%     96.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         6818      0.63%     97.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        26799      2.47%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1083045                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         67614                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        17.532168                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       68.484066                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           67610     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           61846                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         61846                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.267535                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.561626                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev      606.950117                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-4095          61844    100.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40960-45055            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::143360-147455            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           61846                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    51075620081                       # Total ticks spent queuing
-system.physmem.totMemAccLat               71293595081                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5391460000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       47367.15                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           67614                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         67614                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.906321                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.453992                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev      533.973047                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-2047          67611    100.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12288-14335            1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43008-45055            1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::129024-131071            1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           67614                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    72498378118                       # Total ticks spent queuing
+system.physmem.totMemAccLat               94725096868                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5927125000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       61158.13                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  66117.15                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.46                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.78                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.44                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.78                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  79908.13                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.60                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.91                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.58                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.91                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.55                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     810741                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    580742                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.19                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  44.15                       # Row buffer hit rate for writes
-system.physmem.avgGap                     19773667.47                       # Average gap between requests
-system.physmem.pageHitRate                      58.13                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 3929423400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2144030625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4310615400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4363418160                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3094887141840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1164748800645                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27408641092500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31683024522570                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.645104                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45596671664426                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1582253140000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    204992820574                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3646603800                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1989714375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4100054400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4159803600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3094887141840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1159320938310                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27413402375250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31681506631575                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.613070                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45604605403923                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1582253140000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    197059081077                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.physmem.avgRdQLen                         1.24                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.94                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     894792                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    621147                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   75.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  43.94                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18213663.90                       # Average gap between requests
+system.physmem.pageHitRate                      58.33                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 4041154320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2147920665                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4361176260                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3775542480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           33222521280.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            42262106220                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             1577144160                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       67404809070                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       44351104800                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       11290594038405                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             11493753562350                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              242.561305                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           47288119152834                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     2641670410                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     14105156000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   47024804557250                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 115497548988                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     80076687506                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 147817098846                       # Time in different power states
+system.physmem_1.actEnergy                 3691794120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1962235110                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4102758240                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3603240720                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           31839581280.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            42875044890                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             1564584000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       59886050220                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       43118785440                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       11295073117425                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             11487733544595                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              242.434260                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           47286801320918                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     2657158504                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13520630000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   47043190241000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 112288389331                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     81956603828                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 131329696337                       # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst          368                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
@@ -345,30 +356,30 @@ system.realview.nvmem.bw_total::cpu0.data            1                       # T
 system.realview.nvmem.bw_total::cpu1.inst            3                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              12                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              139955722                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         92576910                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          6767718                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            98409045                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               61922323                       # Number of BTB hits
+system.cpu0.branchPred.lookups              139745078                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         92256746                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6767345                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            98774130                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               61692324                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            62.923406                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               19026711                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            185987                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        4326684                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           2749366                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses         1577318                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted       397214                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            62.457978                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               19130272                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            187780                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        4236971                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           2716946                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         1520025                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       386103                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -398,86 +409,87 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                   611788                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               611788                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        13108                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        98298                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       292807                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       318981                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2428.828049                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 13543.109769                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       316274     99.15%     99.15% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         2036      0.64%     99.79% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          442      0.14%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143          138      0.04%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679           53      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           29      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       318981                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       326187                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 22022.583671                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18838.451550                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 17664.426007                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       321608     98.60%     98.60% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         3320      1.02%     99.61% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          429      0.13%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          611      0.19%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679          146      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           45      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           21      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                   642249                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               642249                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        14371                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3       105891                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       311173                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       331076                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2394.451727                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 14284.464178                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       328283     99.16%     99.16% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         2041      0.62%     99.77% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          492      0.15%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143          140      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679           44      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           49      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751            5      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::589824-655359           15      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       331076                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       352054                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 21918.096372                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18874.221671                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 17893.290078                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       347548     98.72%     98.72% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071         2975      0.85%     99.57% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          632      0.18%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          594      0.17%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          153      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215          118      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           25      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       326187                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 530119453936                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.586335                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.554664                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 528635854936     99.72%     99.72% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3    807711000      0.15%     99.87% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5    321496500      0.06%     99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7    138249500      0.03%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9    109943500      0.02%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11     58618500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13     20610000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15     26013000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       940000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19        17000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 530119453936                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        98298     88.23%     88.23% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        13108     11.77%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       111406                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       611788                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total       352054                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 539733877528                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.599244                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.552867                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 538149503028     99.71%     99.71% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3    904434000      0.17%     99.87% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5    320975500      0.06%     99.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7    139201000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9    110066000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11     60836000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13     22060500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15     25840500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       959500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19         1500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 539733877528                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K       105891     88.05%     88.05% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        14371     11.95%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       120262                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       642249                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       611788                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       111406                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       642249                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       120262                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       111406                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       723194                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       120262                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       762511                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   102674478                       # DTB read hits
-system.cpu0.dtb.read_misses                    445170                       # DTB read misses
-system.cpu0.dtb.write_hits                   82832935                       # DTB write hits
-system.cpu0.dtb.write_misses                   166618                       # DTB write misses
-system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                   102850435                       # DTB read hits
+system.cpu0.dtb.read_misses                    467880                       # DTB read misses
+system.cpu0.dtb.write_hits                   83320332                       # DTB write hits
+system.cpu0.dtb.write_misses                   174369                       # DTB write misses
+system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              44145                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1062                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   42795                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      479                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  7037                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              45792                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1079                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   42516                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      599                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  7036                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    40072                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               103119648                       # DTB read accesses
-system.cpu0.dtb.write_accesses               82999553                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    38961                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               103318315                       # DTB read accesses
+system.cpu0.dtb.write_accesses               83494701                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        185507413                       # DTB hits
-system.cpu0.dtb.misses                         611788                       # DTB misses
-system.cpu0.dtb.accesses                    186119201                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                        186170767                       # DTB hits
+system.cpu0.dtb.misses                         642249                       # DTB misses
+system.cpu0.dtb.accesses                    186813016                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -507,1182 +519,1177 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    85546                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                85546                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1054                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        59782                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        10366                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        75180                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1322.160149                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  9414.531253                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        74314     98.85%     98.85% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          448      0.60%     99.44% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303          228      0.30%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071          153      0.20%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839            9      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           10      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375            6      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        75180                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        71202                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 26797.709334                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23346.070270                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 22372.473032                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        68772     96.59%     96.59% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071         2000      2.81%     99.40% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607          197      0.28%     99.67% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143          144      0.20%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           55      0.08%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           23      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        71202                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 422744199036                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.876427                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.329334                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    52271860780     12.36%     12.36% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   370441299256     87.63%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       29828500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        1210500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 422744199036                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        59782     98.27%     98.27% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         1054      1.73%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        60836                       # Table walker page sizes translated
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                    84160                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                84160                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1044                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        58792                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        10193                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        73967                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1726.006192                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 15527.215020                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-65535        73402     99.24%     99.24% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-131071          457      0.62%     99.85% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-196607           56      0.08%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-262143           12      0.02%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-327679            7      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-393215            9      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::393216-458751            1      0.00%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::524288-589823            1      0.00%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::589824-655359           22      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        73967                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        70029                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 27234.188693                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23423.171681                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 26401.977199                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        67612     96.55%     96.55% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071         1634      2.33%     98.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          479      0.68%     99.57% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143          184      0.26%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           51      0.07%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           27      0.04%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           16      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            4      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359           21      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        70029                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 423766533036                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.875739                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.330248                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    52705402108     12.44%     12.44% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   371016436928     87.55%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       42131000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        1939000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         624000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 423766533036                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        58792     98.26%     98.26% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         1044      1.74%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        59836                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        85546                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        85546                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        84160                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        84160                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        60836                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        60836                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       146382                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   220474674                       # ITB inst hits
-system.cpu0.itb.inst_misses                     85546                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        59836                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        59836                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       143996                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   220066677                       # ITB inst hits
+system.cpu0.itb.inst_misses                     84160                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              44145                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1062                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   31037                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              45792                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1079                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   30584                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   205838                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   203568                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               220560220                       # ITB inst accesses
-system.cpu0.itb.hits                        220474674                       # DTB hits
-system.cpu0.itb.misses                          85546                       # DTB misses
-system.cpu0.itb.accesses                    220560220                       # DTB accesses
-system.cpu0.numPwrStateTransitions              10840                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         5420                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    8671662092.472324                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   149203914828.202179                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         3833     70.72%     70.72% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         1557     28.73%     99.45% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11           11      0.20%     99.65% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            3      0.06%     99.70% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            1      0.02%     99.72% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            1      0.02%     99.74% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11            1      0.02%     99.76% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows           13      0.24%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 6993554617000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           5420                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   383509168800                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 47000408541200                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       767019929                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               220150837                       # ITB inst accesses
+system.cpu0.itb.hits                        220066677                       # DTB hits
+system.cpu0.itb.misses                          84160                       # DTB misses
+system.cpu0.itb.accesses                    220150837                       # DTB accesses
+system.cpu0.numPwrStateTransitions              10070                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         5035                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    9333517887.918768                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   154504325024.809692                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         3827     76.01%     76.01% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10         1181     23.46%     99.46% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11            7      0.14%     99.60% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.02%     99.62% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            3      0.06%     99.68% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11            1      0.02%     99.70% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            1      0.02%     99.72% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            1      0.02%     99.74% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows           13      0.26%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 6914082505000                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           5035                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   390680153329                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 46994262565671                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       781361530                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          88196996                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     619911097                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  139955722                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          83698400                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    636708825                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               14589342                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2007819                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles              289070                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      6017581                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       759490                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       830550                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                220269194                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              1684756                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  27864                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         742105002                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.977120                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.219124                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          89977379                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     618690334                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  139745078                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          83539542                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    647313928                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               14578052                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   1993554                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles              302966                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      5990682                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       771527                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       852599                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                219863904                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              1701332                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  27447                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         754491661                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.959990                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.215112                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               394679215     53.18%     53.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1               135211877     18.22%     71.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                46727804      6.30%     77.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3               165486106     22.30%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               407421945     54.00%     54.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1               135112889     17.91%     71.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                46679176      6.19%     78.09% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3               165277651     21.91%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           742105002                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.182467                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.808207                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               106471358                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            362106065                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                229306920                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             38969186                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5251473                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19951761                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              2082457                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             641630797                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts             23347252                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5251473                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               142650653                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               53065481                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     241402745                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                231558396                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             68176254                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             624076980                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              6229632                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents             10704846                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                385160                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                931811                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              31501280                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents           11804                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          596222700                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            963956032                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       736577059                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           695179                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            537389975                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                58832686                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          16140854                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      14103711                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 78118251                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           102816112                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           86124751                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          9533509                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         8142362                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 600960924                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           16329392                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                605893488                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued          2751703                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       55206879                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     35882934                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        285911                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    742105002                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.816453                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.065729                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           754491661                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.178848                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.791811                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               107863691                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            373653702                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                228590583                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             39162463                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5221222                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            20030707                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              2107727                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             640747867                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts             23352656                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5221222                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               144093047                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               59069591                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     244366962                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                230957488                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             70783351                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             623359263                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              6158447                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents             11021555                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                440656                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                940490                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              33921586                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents           11494                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          594689945                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            962815337                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       736259751                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           682623                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            536299590                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                58390349                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          16178274                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      14135285                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 78489785                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           102915286                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           86617273                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          9593817                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         8133429                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 600294247                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           16347683                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                605471525                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued          2720884                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       54918264                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     35662191                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        285806                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    754491661                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.802489                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.061507                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          411055814     55.39%     55.39% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          139198751     18.76%     74.15% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2          116841261     15.74%     89.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           67029634      9.03%     98.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            7974397      1.07%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5               5145      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          423297632     56.10%     56.10% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          139867580     18.54%     74.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2          116427415     15.43%     90.07% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           66852551      8.86%     98.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            8040953      1.07%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5               5530      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      742105002                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      754491661                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               62807824     45.43%     45.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 65216      0.05%     45.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                  15839      0.01%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc              32      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead              36880846     26.68%     72.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite             38467267     27.83%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               62202700     45.10%     45.10% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 65869      0.05%     45.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                  12866      0.01%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc              27      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead              36951420     26.79%     71.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite             38701650     28.06%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass               25      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            414236377     68.37%     68.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1540158      0.25%     68.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                80647      0.01%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  9      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   1      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         41778      0.01%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           105913797     17.48%     86.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           84080696     13.88%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass               51      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            413123878     68.23%     68.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1535668      0.25%     68.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                80204      0.01%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  6      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                1      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         45354      0.01%     68.51% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.51% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.51% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.51% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           106103331     17.52%     86.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           84583031     13.97%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             605893488                       # Type of FU issued
-system.cpu0.iq.rate                          0.789932                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                  138237024                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.228154                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        2093764115                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        672208466                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    588253598                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1116590                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            439713                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       411739                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             743434871                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 695616                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         2774549                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             605471525                       # Type of FU issued
+system.cpu0.iq.rate                          0.774893                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                  137934532                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.227813                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        2104985611                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        671273361                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    587796479                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1104514                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            436534                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       408765                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             742719141                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 686865                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         2818576                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     12838296                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        17783                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       152412                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      5562268                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     12827708                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        17934                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       150945                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      5597965                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2788433                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      4754457                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2832815                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      4794177                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5251473                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                7932610                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              1687524                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          617423509                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               5221222                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                8523162                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              2018525                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          616773219                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            102816112                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            86124751                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          13854081                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 62183                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              1552208                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        152412                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       1974984                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      3105212                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5080196                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            597824194                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            102668745                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          7465093                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts            102915286                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            86617273                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13889545                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 69101                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              1866975                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        150945                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       1955799                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      3092868                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             5048667                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            597424685                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            102845914                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          7413191                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       133193                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   185500111                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               112433305                       # Number of branches executed
-system.cpu0.iew.exec_stores                  82831366                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.779412                       # Inst execution rate
-system.cpu0.iew.wb_sent                     589443856                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    588665337                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                287005457                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                470602155                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.767471                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.609869                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       48230515                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       16043481                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4724520                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    732949405                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.766879                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.569816                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       131289                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   186166471                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               112308682                       # Number of branches executed
+system.cpu0.iew.exec_stores                  83320557                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.764594                       # Inst execution rate
+system.cpu0.iew.wb_sent                     588977240                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    588205244                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                286222957                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                469478170                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.752795                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.609662                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       48006701                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       16061877                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4699541                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    745382545                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.753605                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.560188                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    487135616     66.46%     66.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1    127506386     17.40%     83.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     54345658      7.41%     91.27% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     18167389      2.48%     93.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     13030534      1.78%     95.53% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      9013680      1.23%     96.76% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6080548      0.83%     97.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3647046      0.50%     98.09% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     14022548      1.91%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    499589625     67.02%     67.02% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1    127846284     17.15%     84.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     54154407      7.27%     91.44% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     18022208      2.42%     93.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     12958039      1.74%     95.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      8991225      1.21%     96.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      6101110      0.82%     97.62% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3650180      0.49%     98.11% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     14069467      1.89%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    732949405                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           479057822                       # Number of instructions committed
-system.cpu0.commit.committedOps             562083399                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    745382545                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           478330111                       # Number of instructions committed
+system.cpu0.commit.committedOps             561723659                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     170540284                       # Number of memory references committed
-system.cpu0.commit.loads                     89977801                       # Number of loads committed
-system.cpu0.commit.membars                    3918882                       # Number of memory barriers committed
-system.cpu0.commit.branches                 106864519                       # Number of branches committed
-system.cpu0.commit.fp_insts                    404083                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                515735338                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            14196925                       # Number of function calls committed.
+system.cpu0.commit.refs                     171106885                       # Number of memory references committed
+system.cpu0.commit.loads                     90087577                       # Number of loads committed
+system.cpu0.commit.membars                    3940521                       # Number of memory barriers committed
+system.cpu0.commit.branches                 106744395                       # Number of branches committed
+system.cpu0.commit.fp_insts                    400838                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                515553500                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            14275050                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       390151246     69.41%     69.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1292004      0.23%     69.64% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           63609      0.01%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        36256      0.01%     69.66% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.66% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.66% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.66% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       89977801     16.01%     85.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      80562483     14.33%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       389225467     69.29%     69.29% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1288146      0.23%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           63590      0.01%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        39571      0.01%     69.54% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.54% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.54% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.54% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       90087577     16.04%     85.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      81019308     14.42%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        562083399                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             14022548                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1325013729                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1229746140                       # The number of ROB writes
-system.cpu0.timesIdled                         998783                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       24914927                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 94000815527                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  479057822                       # Number of Instructions Simulated
-system.cpu0.committedOps                    562083399                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.601101                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.601101                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.624570                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.624570                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               705670279                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              419695299                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   680997                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  310212                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                130338984                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               131056521                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1328403158                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              16107336                       # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          6279329                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          481.718631                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          157880144                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          6279840                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            25.140791                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       1908955000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   481.718631                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.940857                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.940857                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          218                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        354237308                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       354237308                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     83229187                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       83229187                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     69700757                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      69700757                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       201759                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       201759                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       148045                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       148045                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1863463                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1863463                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1922512                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1922512                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    153077989                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       153077989                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    153279748                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      153279748                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      7047364                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7047364                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      7798246                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      7798246                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       750513                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       750513                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       796040                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       796040                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       285990                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       285990                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       189707                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       189707                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     15641650                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      15641650                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     16392163                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     16392163                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 106587069500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 106587069500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 149276619912                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 149276619912                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  30060531759                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  30060531759                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4170219500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4170219500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4536657500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4536657500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2221500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2221500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 285924221171                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 285924221171                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 285924221171                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 285924221171                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     90276551                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     90276551                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     77499003                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     77499003                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       952272                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       952272                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       944085                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total       944085                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2149453                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2149453                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2112219                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2112219                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    168719639                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    168719639                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    169671911                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    169671911                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.078064                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.078064                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.100624                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.100624                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.788129                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.788129                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.843187                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.843187                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.133052                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.133052                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.089814                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.089814                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.092708                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.092708                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.096611                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.096611                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15124.388282                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15124.388282                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19142.332765                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 19142.332765                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37762.589517                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37762.589517                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14581.696912                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14581.696912                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23914.022677                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23914.022677                       # average StoreCondReq miss latency
+system.cpu0.commit.op_class_0::total        561723659                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             14069467                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1336864700                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1228532736                       # The number of ROB writes
+system.cpu0.timesIdled                        1001309                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       26869869                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 93988523944                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  478330111                       # Number of Instructions Simulated
+system.cpu0.committedOps                    561723659                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.633519                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.633519                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.612175                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.612175                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               705719528                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              419138035                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   669802                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  321532                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                129631161                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               130314957                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1341639409                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              16172326                       # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements          6359267                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          478.495579                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          158196405                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          6359779                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            24.874513                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       2049282000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   478.495579                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.934562                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.934562                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          386                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        355337560                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       355337560                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     83119639                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       83119639                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     70042361                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      70042361                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       205739                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       205739                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       143941                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       143941                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1893040                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1893040                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1948071                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1948071                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    153305941                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       153305941                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    153511680                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      153511680                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      7167523                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      7167523                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      7883078                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      7883078                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       755741                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       755741                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       796292                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       796292                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       289192                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       289192                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       197314                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       197314                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     15846893                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      15846893                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     16602634                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     16602634                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 116616484000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 116616484000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 160918615442                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 160918615442                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  30600076090                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  30600076090                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4458676000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   4458676000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4713253000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4713253000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2519000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2519000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 308135175532                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 308135175532                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 308135175532                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 308135175532                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     90287162                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     90287162                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     77925439                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     77925439                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       961480                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       961480                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       940233                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total       940233                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2182232                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2182232                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2145385                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2145385                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    169152834                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    169152834                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    170114314                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    170114314                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.079386                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.079386                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.101162                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.101162                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.786018                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.786018                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.846909                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.846909                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.132521                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.132521                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.091971                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.091971                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.093684                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.093684                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097597                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.097597                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16270.123444                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 16270.123444                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20413.170521                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 20413.170521                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 38428.209865                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 38428.209865                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15417.701734                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15417.701734                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23887.068328                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23887.068328                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18279.671337                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 18279.671337                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17442.739019                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17442.739019                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      9136124                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets     22955799                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           744485                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         773832                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    12.271737                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    29.665094                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      6279393                       # number of writebacks
-system.cpu0.dcache.writebacks::total          6279393                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3627313                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      3627313                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6268862                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      6268862                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4039                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         4039                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       145852                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       145852                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      9900214                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      9900214                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      9900214                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      9900214                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3420051                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3420051                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1529384                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1529384                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       743716                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       743716                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       792001                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       792001                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       140138                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       140138                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       189707                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       189707                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      5741436                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      5741436                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      6485152                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      6485152                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17085                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17085                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18834                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18834                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        35919                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        35919                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  49260241500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  49260241500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  32250000948                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  32250000948                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16897998500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16897998500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  29124405259                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  29124405259                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1866604500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1866604500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4347004500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4347004500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2167500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2167500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110634647707                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 110634647707                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 127532646207                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 127532646207                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3215151000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3215151000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3215151000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3215151000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037884                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037884                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019734                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019734                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.780991                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.780991                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.838909                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.838909                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.065197                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.065197                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.089814                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.089814                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.034029                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.034029                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.038222                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.038222                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14403.364599                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14403.364599                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21086.921890                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21086.921890                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22721.036659                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22721.036659                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36773.192533                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36773.192533                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13319.759808                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13319.759808                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22914.307327                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22914.307327                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19444.516697                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19444.516697                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18559.415062                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 18559.415062                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      9297521                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets     24817691                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           744023                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         779199                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    12.496282                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    31.850260                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks      6359403                       # number of writebacks
+system.cpu0.dcache.writebacks::total          6359403                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3686639                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      3686639                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6327255                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      6327255                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4271                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         4271                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       148971                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       148971                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data     10018165                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total     10018165                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data     10018165                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total     10018165                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3480884                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3480884                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1555823                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1555823                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       748893                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       748893                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       792021                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       792021                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       140221                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       140221                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       197311                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       197311                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      5828728                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      5828728                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      6577621                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      6577621                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16980                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        16980                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18801                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18801                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        35781                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        35781                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  53164892500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  53164892500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  34944889021                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  34944889021                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  18458336500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  18458336500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  29638184090                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  29638184090                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1982757000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1982757000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4516003000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4516003000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2458000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2458000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 117747965611                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 117747965611                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136206302111                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 136206302111                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3133590500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3133590500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3133590500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3133590500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.038553                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.038553                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019966                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019966                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.778896                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.778896                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.842367                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.842367                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064256                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064256                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.091970                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.091970                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.034458                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.034458                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.038666                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.038666                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15273.388168                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15273.388168                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22460.709876                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22460.709876                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24647.495036                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24647.495036                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 37420.957386                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 37420.957386                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14140.228639                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14140.228639                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22887.740673                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22887.740673                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19269.508135                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19269.508135                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19665.328771                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19665.328771                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188185.601405                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188185.601405                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89511.150088                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89511.150088                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          5960489                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.962298                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          213927686                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          5961001                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            35.887880                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      13033031000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.962298                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999926                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999926                       # Average percentage of cache occupancy
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20201.314182                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20201.314182                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20707.532725                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20707.532725                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184545.965842                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184545.965842                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87576.940276                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87576.940276                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          6086800                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.960315                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          213393241                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          6087312                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            35.055414                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      13476237000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.960315                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999922                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999922                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          166                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          315                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        446443685                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       446443685                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    213927686                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      213927686                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    213927686                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       213927686                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    213927686                       # number of overall hits
-system.cpu0.icache.overall_hits::total      213927686                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6313628                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      6313628                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6313628                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       6313628                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6313628                       # number of overall misses
-system.cpu0.icache.overall_misses::total      6313628                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  68941695345                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  68941695345                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  68941695345                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  68941695345                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  68941695345                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  68941695345                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    220241314                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    220241314                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    220241314                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    220241314                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    220241314                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    220241314                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028667                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.028667                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028667                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.028667                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028667                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.028667                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10919.505448                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10919.505448                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10919.505448                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10919.505448                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10919.505448                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10919.505448                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs     10186888                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          465                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           736848                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              9                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.824952                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets    51.666667                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      5960489                       # number of writebacks
-system.cpu0.icache.writebacks::total          5960489                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       352571                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       352571                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       352571                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       352571                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       352571                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       352571                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5961057                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      5961057                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      5961057                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      5961057                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      5961057                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      5961057                       # number of overall MSHR misses
+system.cpu0.icache.tags.tag_accesses        445759262                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       445759262                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst    213393241                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      213393241                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    213393241                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       213393241                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    213393241                       # number of overall hits
+system.cpu0.icache.overall_hits::total      213393241                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6442715                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      6442715                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6442715                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       6442715                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6442715                       # number of overall misses
+system.cpu0.icache.overall_misses::total      6442715                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  71477790896                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  71477790896                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  71477790896                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  71477790896                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  71477790896                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  71477790896                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    219835956                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    219835956                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    219835956                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    219835956                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    219835956                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    219835956                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029307                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.029307                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029307                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.029307                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029307                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.029307                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11094.358651                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 11094.358651                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11094.358651                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 11094.358651                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11094.358651                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 11094.358651                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs     10557387                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets         2753                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           752829                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets             14                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.023619                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets   196.642857                       # average number of cycles each access was blocked
+system.cpu0.icache.writebacks::writebacks      6086800                       # number of writebacks
+system.cpu0.icache.writebacks::total          6086800                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       355365                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       355365                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       355365                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       355365                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       355365                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       355365                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6087350                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      6087350                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      6087350                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      6087350                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      6087350                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      6087350                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        21293                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        21293                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  62354110053                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  62354110053                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  62354110053                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  62354110053                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  62354110053                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  62354110053                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1885677498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1885677498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1885677498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   1885677498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027066                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027066                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027066                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.027066                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027066                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.027066                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10460.243888                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10460.243888                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10460.243888                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10460.243888                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10460.243888                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10460.243888                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      8592940                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      8600926                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         7220                       # number of redundant prefetches already in prefetch queue
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  64448796094                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  64448796094                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  64448796094                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  64448796094                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  64448796094                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  64448796094                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2027158498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2027158498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2027158498                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   2027158498                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027690                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027690                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027690                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.027690                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027690                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.027690                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10587.332106                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10587.332106                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10587.332106                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10587.332106                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10587.332106                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10587.332106                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      8595677                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      8603285                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         6909                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1116114                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements         2719287                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       15847.951353                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          10783985                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2734787                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            3.943263                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle      2212469000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15472.818870                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    33.262850                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    18.351912                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   323.517722                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.944386                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002030                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001120                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.019746                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.967282                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022          300                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023          111                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15089                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           95                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3           82                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          118                       # Occupied blocks per task id
+system.cpu0.l2cache.prefetcher.pfSpanPage      1123339                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.tags.replacements         2781248                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15839.093178                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          10966307                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2797118                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            3.920574                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle      2357977000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15519.164563                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    33.011471                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    18.049668                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data     0.000001                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   268.867475                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.947215                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002015                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001102                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.000000                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.016410                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.966742                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          337                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           83                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15450                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          131                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          116                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           88                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1           22                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           45                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           12                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           31                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          388                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         2056                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         7291                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3067                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2287                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.018311                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006775                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.920959                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       426577615                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      426577615                       # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       609078                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       186922                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        796000                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks      4110828                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      4110828                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      8127250                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      8127250                       # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data           41                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total           41                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            5                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total            5                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       991441                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       991441                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5365262                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      5365262                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3250561                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      3250561                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       179546                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       179546                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       609078                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       186922                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      5365262                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      4242002                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       10403264                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       609078                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       186922                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      5365262                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      4242002                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      10403264                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        23667                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        12082                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        35749                       # number of ReadReq misses
-system.cpu0.l2cache.WritebackClean_misses::writebacks            2                       # number of WritebackClean misses
-system.cpu0.l2cache.WritebackClean_misses::total            2                       # number of WritebackClean misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       259915                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       259915                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       189699                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       189699                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       286982                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       286982                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       595762                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       595762                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1051075                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total      1051075                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       610539                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       610539                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        23667                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker        12082                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       595762                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1338057                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1969568                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        23667                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker        12082                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       595762                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1338057                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1969568                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    824553000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    534370500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total   1358923500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    956036000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    956036000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    288541500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    288541500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2086500                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2086500                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16444485496                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  16444485496                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  20913606500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  20913606500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  39888753486                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  39888753486                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    293901000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total    293901000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    824553000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    534370500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  20913606500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  56333238982                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  78605768982                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    824553000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    534370500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  20913606500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  56333238982                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  78605768982                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       632745                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       199004                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       831749                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4110828                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total      4110828                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      8127252                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      8127252                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       259956                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       259956                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       189704                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       189704                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1278423                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1278423                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5961024                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      5961024                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4301636                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      4301636                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       790085                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       790085                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       632745                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       199004                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      5961024                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      5580059                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     12372832                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       632745                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       199004                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      5961024                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      5580059                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     12372832                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.037404                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.060712                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.042981                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
-system.cpu0.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999842                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999842                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999974                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999974                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           44                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          205                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1708                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         7197                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4776                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1564                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.020569                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005066                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.942993                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       434183760                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      434183760                       # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       639992                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       185315                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        825307                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks      4159646                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total      4159646                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      8284827                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      8284827                       # number of WritebackClean hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data           23                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total           23                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            2                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       995756                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       995756                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5493946                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      5493946                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3273779                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      3273779                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       166627                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       166627                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       639992                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       185315                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      5493946                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      4269535                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total       10588788                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       639992                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       185315                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      5493946                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      4269535                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      10588788                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        23429                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        11592                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        35021                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       269158                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       269158                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       197304                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       197304                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       301043                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       301043                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       593373                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       593373                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1093007                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total      1093007                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       623543                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       623543                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        23429                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker        11592                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       593373                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1394050                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      2022444                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        23429                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker        11592                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       593373                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1394050                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      2022444                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    862921500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    562577500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total   1425499000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    983366500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    983366500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    308777000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    308777000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2366500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2366500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  18857416997                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  18857416997                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  22027267000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  22027267000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  45190340989                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  45190340989                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    290057500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total    290057500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    862921500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    562577500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22027267000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  64047757986                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  87500523986                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    862921500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    562577500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22027267000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  64047757986                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  87500523986                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       663421                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       196907                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       860328                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4159646                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total      4159646                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      8284827                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      8284827                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       269181                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       269181                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       197306                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       197306                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1296799                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1296799                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6087319                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      6087319                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4366786                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      4366786                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       790170                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       790170                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       663421                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       196907                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      6087319                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      5663585                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     12611232                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       663421                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       196907                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      6087319                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      5663585                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     12611232                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.035315                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.058870                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.040707                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999915                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999915                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999990                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999990                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.224481                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.224481                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.099943                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.099943                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.244343                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.244343                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.772751                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.772751                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.037404                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.060712                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.099943                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.239793                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.159185                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.037404                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.060712                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.099943                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.239793                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.159185                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34839.776905                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 44228.645920                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 38012.909452                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3678.264048                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3678.264048                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1521.049136                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1521.049136                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       695500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       695500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57301.452690                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57301.452690                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35103.961817                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35103.961817                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37950.435017                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37950.435017                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   481.379568                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   481.379568                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34839.776905                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 44228.645920                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35103.961817                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42100.776710                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 39910.157447                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34839.776905                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44228.645920                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35103.961817                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42100.776710                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 39910.157447                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs         1132                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.232143                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.232143                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.097477                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.097477                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.250300                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.250300                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.789125                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.789125                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.035315                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.058870                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.097477                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.246143                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.160368                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.035315                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.058870                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.097477                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.246143                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.160368                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36831.341500                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48531.530366                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 40704.120385                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3653.491629                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3653.491629                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1564.980943                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1564.980943                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       473300                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       473300                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62640.277293                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62640.277293                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37122.125543                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37122.125543                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41344.969418                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41344.969418                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   465.176419                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   465.176419                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36831.341500                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48531.530366                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37122.125543                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45943.659113                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 43264.745024                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36831.341500                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48531.530366                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37122.125543                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45943.659113                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 43264.745024                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs         1347                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs              30                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs              28                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    37.733333                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    48.107143                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches           48307                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks      1757363                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1757363                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker          134                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          356                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total          490                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        18633                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        18633                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5210                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5210                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            3                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::total            3                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker          134                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          356                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        23843                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        24334                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker          134                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          356                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            1                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        23843                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        24334                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        23533                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        11726                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        35259                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            2                       # number of WritebackClean MSHR misses
-system.cpu0.l2cache.WritebackClean_mshr_misses::total            2                       # number of WritebackClean MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       887638                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       887638                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       259915                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       259915                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       189699                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       189699                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       268349                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       268349                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       595761                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       595761                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1045865                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1045865                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       610536                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       610536                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        23533                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        11726                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       595761                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1314214                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      1945234                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        23533                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        11726                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       595761                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1314214                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       887638                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2832872                       # number of overall MSHR misses
+system.cpu0.l2cache.unused_prefetches           49330                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks      1802209                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1802209                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker          136                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          303                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total          439                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        20845                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total        20845                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            2                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         4784                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         4784                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            6                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::total            6                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker          136                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          303                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            2                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data        25629                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total        26070                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker          136                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          303                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            2                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data        25629                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total        26070                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        23293                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        11289                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        34582                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       895757                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       895757                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       269158                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       269158                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       197304                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       197304                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       280198                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       280198                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       593371                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       593371                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1088223                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1088223                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       623537                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       623537                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        23293                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        11289                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       593371                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1368421                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total      1996374                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        23293                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        11289                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       593371                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1368421                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       895757                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total      2892131                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        17085                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        38378                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        18834                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        18834                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        16980                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        38273                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        18801                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        18801                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        35919                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        57212                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    680641500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    457877000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   1138518500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  52792392844                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  52792392844                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4817060992                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4817060992                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2920885493                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2920885493                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1762500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1762500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  12110424498                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  12110424498                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17339026500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17339026500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  33290154486                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  33290154486                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  22238992991                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  22238992991                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    680641500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    457877000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17339026500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  45400578984                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  63878123984                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    680641500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    457877000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17339026500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  45400578984                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  52792392844                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 116670516828                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1725979000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3078004000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4803983000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1725979000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   3078004000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4803983000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.037192                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.058923                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.042391                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
-system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        35781                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        57074                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    720471000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    489799000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   1210270000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  58575065392                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  58575065392                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4984780995                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4984780995                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3032798496                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3032798496                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2000500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2000500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  14111841497                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  14111841497                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  18467014500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  18467014500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  38294410989                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  38294410989                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  22764184995                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  22764184995                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    720471000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    489799000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  18467014500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  52406252486                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  72083536986                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    720471000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    489799000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  18467014500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  52406252486                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  58575065392                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total 130658602378                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1867460000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2997239500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4864699500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1867460000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   2997239500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4864699500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.035110                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.057332                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.040196                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999842                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999842                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999974                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999974                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999915                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999915                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999990                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999990                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.209906                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.209906                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.099943                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.099943                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.243132                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.243132                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.772747                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.772747                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.037192                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.058923                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.099943                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.235520                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.157218                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.037192                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.058923                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.099943                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.235520                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.216069                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.216069                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.097477                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.097477                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.249205                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249205                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.789118                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.789118                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.035110                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.057332                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.097477                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.241617                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.158301                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.035110                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.057332                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.097477                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.241617                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.228959                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 32290.152869                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59475.138338                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18533.216598                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18533.216598                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15397.474383                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15397.474383                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       587500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       587500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45129.381880                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45129.381880                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29103.997241                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29103.997241                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31830.259628                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31830.259628                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36425.359014                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36425.359014                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29103.997241                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34545.803791                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32838.272405                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29103.997241                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34545.803791                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41184.535280                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180158.267486                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125175.439054                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85692.920182                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83968.101098                       # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests     25397703                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     13066663                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1795                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       671473                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       671468                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            5                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq        963728                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     11315166                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        18834                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        18834                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      5872564                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      8129050                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      1348327                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1122615                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp           22                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       466810                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       338240                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       510310                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           74                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          125                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1307620                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1285212                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5961057                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5219350                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       843100                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       790085                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     17925156                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20147173                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       419117                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1337980                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         39829426                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    763317520                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    765224037                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1592032                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      5061960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1535195549                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    5838031                       # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic            119621704                       # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples     19351504                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.054273                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.226556                       # Request fanout histogram
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.229330                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34997.108322                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65391.691488                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18519.906505                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18519.906505                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15371.196205                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15371.196205                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       400100                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       400100                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50363.819503                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50363.819503                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31122.206006                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31122.206006                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35189.856297                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35189.856297                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36508.154280                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36508.154280                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31122.206006                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38296.878290                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36107.230903                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31122.206006                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38296.878290                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45177.276679                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176515.871614                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127105.256970                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83766.230681                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85234.949364                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests     25828303                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     13287358                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1712                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       676521                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       676518                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq        990165                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     11537181                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        18801                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        18801                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5966642                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      8286555                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      1378403                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1136481                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp           14                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       480580                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       352407                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       530357                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           77                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          133                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1327096                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1303956                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6087350                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5339261                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       842479                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       790170                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     18304055                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20435509                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       413815                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1398403                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         40551782                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    779484304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    775974521                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1575256                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      5307368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1562341449                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    5999180                       # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic            122789024                       # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples     19760108                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.053277                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.224586                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          18301249     94.57%     94.57% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           1050250      5.43%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2                 5      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          18707349     94.67%     94.67% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           1052756      5.33%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2                 3      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      19351504                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   25250991712                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      19760108                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   25687014453                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    173970437                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    182391125                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   8969219750                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   9158694684                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   9025116687                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   9158841551                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    220608496                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    217386526                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    706093257                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    735766915                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              128968222                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         85282466                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6518355                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            89675287                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               55364340                       # Number of BTB hits
+system.cpu1.branchPred.lookups              134369829                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         89463085                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6609561                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            94230263                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               58109960                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            61.738682                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               17439644                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            182879                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        4134289                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits           2557852                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses         1576437                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted       401535                       # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.branchPred.BTBHitPct            61.668044                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               17839939                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            183627                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        4347444                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           2695405                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         1652039                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted       417102                       # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1712,96 +1719,86 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                   531460                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               531460                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10155                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        82594                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       244261                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       287199                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2189.199823                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 12408.912934                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-32767       282304     98.30%     98.30% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-65535         2996      1.04%     99.34% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-98303          743      0.26%     99.60% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::98304-131071          602      0.21%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-163839          197      0.07%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::163840-196607          152      0.05%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-229375          103      0.04%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::229376-262143           33      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-294911           16      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::294912-327679           35      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-360447           11      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::425984-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       287199                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       267684                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 20635.114538                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 18133.747768                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 11911.787641                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767       239914     89.63%     89.63% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535        26330      9.84%     99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303          756      0.28%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071          476      0.18%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839           73      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607           24      0.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375           55      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143           22      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911            9      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679            8      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::425984-458751            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       267684                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 465694213496                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.593113                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.550788                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 464589649996     99.76%     99.76% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3    559093500      0.12%     99.88% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5    239052500      0.05%     99.93% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7    120378000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9     87009500      0.02%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11     57335500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13     14978500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15     26310000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       396500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19         9500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 465694213496                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        82595     89.05%     89.05% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        10155     10.95%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        92750                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       531460                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                   561952                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               561952                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11814                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        88087                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       261651                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       300301                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2363.057399                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 13317.227915                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535       298048     99.25%     99.25% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071         1567      0.52%     99.77% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607          436      0.15%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143          167      0.06%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679           36      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215           40      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       300301                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       287935                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 21029.369476                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 18280.568505                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15111.837725                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       285795     99.26%     99.26% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1436      0.50%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          377      0.13%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          181      0.06%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           86      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           29      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           11      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359           16      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       287935                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 466714959496                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.597643                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.555516                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 465490623496     99.74%     99.74% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3    621983000      0.13%     99.87% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5    266845500      0.06%     99.93% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7    131382500      0.03%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9     96036000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11     60845000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13     18797500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15     27878000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       546500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19        22000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 466714959496                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        88088     88.17%     88.17% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        11814     11.83%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        99902                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       561952                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       531460                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        92750                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       561952                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        99902                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        92750                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       624210                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        99902                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       661854                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    93944307                       # DTB read hits
-system.cpu1.dtb.read_misses                    364370                       # DTB read misses
-system.cpu1.dtb.write_hits                   78170381                       # DTB write hits
-system.cpu1.dtb.write_misses                   167090                       # DTB write misses
-system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    97791245                       # DTB read hits
+system.cpu1.dtb.read_misses                    385118                       # DTB read misses
+system.cpu1.dtb.write_hits                   81245431                       # DTB write hits
+system.cpu1.dtb.write_misses                   176834                       # DTB write misses
+system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              44145                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1062                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   34720                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      381                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  5735                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              45792                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1079                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   36850                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      268                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  6109                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    39000                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                94308677                       # DTB read accesses
-system.cpu1.dtb.write_accesses               78337471                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    40755                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                98176363                       # DTB read accesses
+system.cpu1.dtb.write_accesses               81422265                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        172114688                       # DTB hits
-system.cpu1.dtb.misses                         531460                       # DTB misses
-system.cpu1.dtb.accesses                    172646148                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                        179036676                       # DTB hits
+system.cpu1.dtb.misses                         561952                       # DTB misses
+system.cpu1.dtb.accesses                    179598628                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1831,1180 +1828,1166 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                    82381                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                82381                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1018                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        59631                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore         9853                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        72528                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean   882.590172                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  6870.472006                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767        72114     99.43%     99.43% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535          279      0.38%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303           39      0.05%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071           75      0.10%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839            6      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        72528                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        70502                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 24022.878784                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 22243.496704                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 12757.621468                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        63844     90.56%     90.56% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535         6070      8.61%     99.17% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303           93      0.13%     99.30% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071          382      0.54%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839           44      0.06%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           19      0.03%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375           18      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143            8      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        70502                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 379792000076                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.874646                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.331269                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    47625596788     12.54%     12.54% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   332150851288     87.46%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       14331500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3         990000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         230500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 379792000076                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        59631     98.32%     98.32% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         1018      1.68%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        60649                       # Table walker page sizes translated
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                    84407                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                84407                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1027                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        60740                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        10156                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        74251                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1057.238286                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  8622.114888                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-65535        74015     99.68%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-131071          199      0.27%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-196607           18      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-262143           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        74251                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        71923                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 24988.821378                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 22597.090075                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18666.984039                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        70820     98.47%     98.47% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071          715      0.99%     99.46% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          265      0.37%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           63      0.09%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           24      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           16      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            3      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359           10      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        71923                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 410850107648                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.878728                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.326631                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    49848543788     12.13%     12.13% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   360979116860     87.86%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       21177000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        1227500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4          42500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 410850107648                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        60740     98.34%     98.34% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         1027      1.66%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        61767                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        82381                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        82381                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        84407                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        84407                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        60649                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        60649                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       143030                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   201934152                       # ITB inst hits
-system.cpu1.itb.inst_misses                     82381                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        61767                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        61767                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       146174                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   210802915                       # ITB inst hits
+system.cpu1.itb.inst_misses                     84407                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              44145                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1062                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   24569                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              45792                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1079                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   26222                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   202631                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   208943                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               202016533                       # ITB inst accesses
-system.cpu1.itb.hits                        201934152                       # DTB hits
-system.cpu1.itb.misses                          82381                       # DTB misses
-system.cpu1.itb.accesses                    202016533                       # DTB accesses
-system.cpu1.numPwrStateTransitions              26784                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples        13392                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    3512583180.059961                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   88770415671.353104                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         3351     25.02%     25.02% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10        10014     74.78%     99.80% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.01%     99.81% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.81% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.82% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            4      0.03%     99.85% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::3.5e+11-4e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses               210887322                       # ITB inst accesses
+system.cpu1.itb.hits                        210802915                       # DTB hits
+system.cpu1.itb.misses                          84407                       # DTB misses
+system.cpu1.itb.accesses                    210887322                       # DTB accesses
+system.cpu1.numPwrStateTransitions              27667                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples        13834                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    3399006591.183533                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   87524078188.715500                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         3453     24.96%     24.96% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10        10352     74.83%     99.79% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11            5      0.04%     99.83% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            2      0.01%     99.84% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            3      0.02%     99.86% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            2      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::overflows           14      0.10%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 7430623145540                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total          13392                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   343403762637                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 47040513947363                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                       686817572                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value 7390880477084                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total          13834                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON   363085536567                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 47021857182433                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                       726181462                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          87491536                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     569150585                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  128968222                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          75361836                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    564504137                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               14030828                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   1743458                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles              273069                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles      5670150                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       713565                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles       783781                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                201710843                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              1678338                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  26867                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         668195110                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.000138                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.225435                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          86390303                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     594062843                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  134369829                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          78645304                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    601498232                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               14253482                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   1820697                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles              287238                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles      5988786                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       713679                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles       819715                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                210572695                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              1658938                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  27666                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         704645391                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.988963                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.222689                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               348421230     52.14%     52.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1               124504424     18.63%     70.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                42025261      6.29%     77.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3               153244195     22.93%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               370929364     52.64%     52.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1               130277469     18.49%     71.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                43725033      6.21%     77.33% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3               159713525     22.67%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           668195110                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.187777                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.828678                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               102161242                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            311763510                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                215198558                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             34078749                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               4993051                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            18208977                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              2060516                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             590405276                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts             22672761                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               4993051                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               135354794                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               41008219                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     216515907                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                215714387                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             54608752                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             573925738                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts              5865325                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents              9111156                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                235226                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                246551                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              22706071                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents           10845                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          544713354                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            881414288                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       677140554                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           799785                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            489645115                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                55068233                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          14685141                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      12835902                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 68922736                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            94552173                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           81340147                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          8760661                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         7542596                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 552653279                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           14818656                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                556478216                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued          2578197                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       52065959                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     33349277                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        259122                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    668195110                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.832808                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.070079                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           704645391                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.185036                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.818064                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               103020673                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            337373962                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                222407115                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             36734416                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5109225                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            18739170                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              2055775                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             616426802                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts             23026844                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5109225                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               137867421                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               45074504                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     232811775                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                223900939                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             59881527                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             599411621                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts              6042296                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents              9969882                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                242190                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                299313                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              25537080                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents           11262                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          571214843                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            926423560                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       707359605                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           805393                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            514629531                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                56585312                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          15957043                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      14048251                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 73992297                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            98060208                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           84478655                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          8950565                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         7675207                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 576680308                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           16104006                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                581772484                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued          2680133                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       53366771                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     34273904                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        266458                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    704645391                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.825624                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.067009                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          364178661     54.50%     54.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          127786531     19.12%     73.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2          107346035     16.07%     89.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           61539810      9.21%     98.90% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            7340180      1.10%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               3893      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          385934490     54.77%     54.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          135280434     19.20%     73.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2          111501247     15.82%     89.79% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           64231431      9.12%     98.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            7693682      1.09%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               4107      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      668195110                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      704645391                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu               55774345     44.07%     44.07% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 53478      0.04%     44.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                  18362      0.01%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc              15      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead              33579431     26.53%     70.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite             37124892     29.34%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu               58591735     44.23%     44.23% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 49305      0.04%     44.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                  21310      0.02%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc              60      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead              35005485     26.43%     70.71% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite             38791699     29.29%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               35      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            378772554     68.07%     68.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1203453      0.22%     68.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                69506      0.01%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         82169      0.01%     68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            96967073     17.43%     85.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           79383378     14.27%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               36      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            397008075     68.24%     68.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1247296      0.21%     68.46% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                70487      0.01%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         78078      0.01%     68.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           100884939     17.34%     85.82% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           82483526     14.18%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             556478216                       # Type of FU issued
-system.cpu1.iq.rate                          0.810227                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                  126550523                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.227413                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1908944024                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        619142753                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    540109020                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1336236                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            533681                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       496559                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             682200972                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 827732                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         2535076                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             581772484                       # Type of FU issued
+system.cpu1.iq.rate                          0.801139                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                  132459594                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.227683                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        2001993843                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        645760406                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    564750025                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1336243                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            531893                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       495883                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             713403384                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 828658                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         2572358                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     12050927                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        15964                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       139670                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      5367770                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     12226985                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        16460                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       142391                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      5497757                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      2479862                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      3811174                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      2564544                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      4190277                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               4993051                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                6066595                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              1484920                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          567600146                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               5109225                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                6111838                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              1648605                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          592918318                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             94552173                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            81340147                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          12593166                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 61012                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              1366008                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        139670                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       1864288                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2962654                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4826942                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            548760252                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             93936954                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          7198002                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             98060208                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            84478655                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          13792326                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 62841                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              1527139                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        142391                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       1885740                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      3046567                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4932307                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            573876367                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             97784309                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          7346483                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       128211                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   172107181                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               103045741                       # Number of branches executed
-system.cpu1.iew.exec_stores                  78170227                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.798990                       # Inst execution rate
-system.cpu1.iew.wb_sent                     541337937                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    540605579                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                260784878                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                427489689                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.787117                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.610038                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       45375845                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       14559534                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4495992                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    659550921                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.781450                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.574730                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       134004                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   179029158                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               107707763                       # Number of branches executed
+system.cpu1.iew.exec_stores                  81244849                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.790266                       # Inst execution rate
+system.cpu1.iew.wb_sent                     565995055                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    565245908                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                273023556                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                448078183                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.778381                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.609321                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       46535716                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       15837548                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4592045                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    695790390                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.775259                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.568649                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    433210493     65.68%     65.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1    117319741     17.79%     83.47% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     50366969      7.64%     91.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     16989740      2.58%     93.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     12025543      1.82%     95.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      8091474      1.23%     96.73% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5593324      0.85%     97.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3365512      0.51%     98.09% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     12588125      1.91%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    457970279     65.82%     65.82% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1    124243355     17.86%     83.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     52434114      7.54%     91.21% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     17645088      2.54%     93.75% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     12549968      1.80%     95.55% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      8433891      1.21%     96.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5802471      0.83%     97.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3503250      0.50%     98.10% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     13207974      1.90%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    659550921                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           437257329                       # Number of instructions committed
-system.cpu1.commit.committedOps             515405969                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    695790390                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           458018039                       # Number of instructions committed
+system.cpu1.commit.committedOps             539417542                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     158473622                       # Number of memory references committed
-system.cpu1.commit.loads                     82501245                       # Number of loads committed
-system.cpu1.commit.membars                    3568741                       # Number of memory barriers committed
-system.cpu1.commit.branches                  97797753                       # Number of branches committed
-system.cpu1.commit.fp_insts                    487077                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                473223690                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            12865392                       # Number of function calls committed.
+system.cpu1.commit.refs                     164814121                       # Number of memory references committed
+system.cpu1.commit.loads                     85833223                       # Number of loads committed
+system.cpu1.commit.membars                    3719425                       # Number of memory barriers committed
+system.cpu1.commit.branches                 102343051                       # Number of branches committed
+system.cpu1.commit.fp_insts                    486729                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                494686776                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13237013                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       355828768     69.04%     69.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult         973462      0.19%     69.23% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           55201      0.01%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        74874      0.01%     69.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       82501245     16.01%     85.26% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      75972377     14.74%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       373462182     69.23%     69.23% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1014464      0.19%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           55738      0.01%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        70995      0.01%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       85833223     15.91%     85.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      78980898     14.64%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        515405969                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             12588125                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1203797977                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1130170940                       # The number of ROB writes
-system.cpu1.timesIdled                         922689                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       18622462                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 94081017888                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  437257329                       # Number of Instructions Simulated
-system.cpu1.committedOps                    515405969                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.570740                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.570740                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.636643                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.636643                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               647634757                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              384292228                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   785728                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  454696                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                117471222                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               118161265                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1199366647                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              14671382                       # number of misc regfile writes
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements          5153619                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          456.044406                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          148207895                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5154131                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            28.755166                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8517415326000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   456.044406                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.890712                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.890712                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          390                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        328622817                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       328622817                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data     76967758                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       76967758                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     66682281                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      66682281                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       189501                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       189501                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       166829                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       166829                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1726427                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1726427                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1743769                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1743769                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    143816868                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       143816868                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    144006369                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      144006369                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      5978399                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      5978399                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      6727643                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      6727643                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       625948                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       625948                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       458256                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       458256                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       242959                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       242959                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       183921                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       183921                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data     13164298                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total      13164298                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data     13790246                       # number of overall misses
-system.cpu1.dcache.overall_misses::total     13790246                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  87383841500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  87383841500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119886339095                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 119886339095                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  11324190656                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  11324190656                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3328957500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   3328957500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4379371000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4379371000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2907500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2907500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 218594371251                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 218594371251                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 218594371251                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 218594371251                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     82946157                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     82946157                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     73409924                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     73409924                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       815449                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       815449                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       625085                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       625085                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1969386                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1969386                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1927690                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1927690                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    156981166                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    156981166                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    157796615                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    157796615                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.072076                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.072076                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.091645                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.091645                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.767611                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.767611                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.733110                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.733110                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.123368                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.123368                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095410                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095410                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.083859                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.083859                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.087393                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.087393                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14616.595764                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14616.595764                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17819.961478                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 17819.961478                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24711.494571                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24711.494571                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13701.725394                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13701.725394                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23811.152614                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23811.152614                       # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total        539417542                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             13207974                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1264391907                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1180722952                       # The number of ROB writes
+system.cpu1.timesIdled                         944459                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       21536071                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 94043695657                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  458018039                       # Number of Instructions Simulated
+system.cpu1.committedOps                    539417542                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.585487                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.585487                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.630721                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.630721                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               677403787                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              401367044                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   791707                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  438600                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                124889457                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               125620500                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1260290191                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              15974322                       # number of misc regfile writes
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements          5362331                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          456.510727                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          153804268                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5362842                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            28.679620                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8517840775000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   456.510727                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.891623                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.891623                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          382                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        341608540                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       341608540                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data     79940930                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       79940930                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     69078558                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      69078558                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       191831                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       191831                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       170764                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       170764                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1820637                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1820637                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1828950                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1828950                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    149190252                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       149190252                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    149382083                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      149382083                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      6220385                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      6220385                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      7237581                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      7237581                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       689658                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       689658                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       463987                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       463987                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       244543                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       244543                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       192296                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       192296                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data     13921953                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total      13921953                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data     14611611                       # number of overall misses
+system.cpu1.dcache.overall_misses::total     14611611                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  96362388500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  96362388500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 134833660621                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 134833660621                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  11613680644                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  11613680644                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3499456000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   3499456000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4567503000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   4567503000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3019500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3019500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 242809729765                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 242809729765                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 242809729765                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 242809729765                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     86161315                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     86161315                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     76316139                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     76316139                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       881489                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       881489                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       634751                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       634751                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2065180                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      2065180                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2021246                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      2021246                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    163112205                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    163112205                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    163993694                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    163993694                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.072195                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.072195                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.094837                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.094837                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.782378                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.782378                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.730975                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.730975                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.118412                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.118412                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095137                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095137                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.085352                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.085352                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.089099                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.089099                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15491.386546                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15491.386546                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18629.658255                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 18629.658255                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25030.185423                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25030.185423                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14310.186757                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14310.186757                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23752.459750                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23752.459750                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16605.091381                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16605.091381                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15851.375766                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15851.375766                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs      2917967                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets     18895353                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs           374678                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets         668758                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     7.787933                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    28.254395                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks      5153631                       # number of writebacks
-system.cpu1.dcache.writebacks::total          5153631                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3023211                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total      3023211                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5427179                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      5427179                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3743                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total         3743                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       127495                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total       127495                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      8454133                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      8454133                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      8454133                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      8454133                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2955188                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2955188                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1300464                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1300464                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       625861                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       625861                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       454513                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       454513                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       115464                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       115464                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       183920                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       183920                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4710165                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4710165                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5336026                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5336026                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        21232                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        21232                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17440.780741                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 17440.780741                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16617.587873                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 16617.587873                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs      3018250                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets     21738633                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs           378529                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets         731712                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     7.973629                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    29.709275                       # average number of cycles each access was blocked
+system.cpu1.dcache.writebacks::writebacks      5362354                       # number of writebacks
+system.cpu1.dcache.writebacks::total          5362354                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3187456                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total      3187456                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5861363                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      5861363                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3594                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total         3594                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       128092                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total       128092                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      9052413                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      9052413                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      9052413                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      9052413                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3032929                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3032929                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1376218                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1376218                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       689576                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       689576                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       460393                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       460393                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       116451                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       116451                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       192288                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       192288                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4869540                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4869540                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5559116                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5559116                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        21291                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        21291                       # number of ReadReq MSHR uncacheable
 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        19410                       # number of WriteReq MSHR uncacheable
 system.cpu1.dcache.WriteReq_mshr_uncacheable::total        19410                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        40642                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        40642                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  40128990000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  40128990000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  24368462066                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  24368462066                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13718666000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13718666000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  10741056156                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  10741056156                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1514532000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1514532000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4195522000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4195522000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2836500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2836500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  75238508222                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  75238508222                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  88957174222                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  88957174222                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3718611500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3718611500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3718611500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3718611500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035628                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035628                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017715                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017715                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.767505                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.767505                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.727122                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.727122                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058629                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.058629                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095410                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095410                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030005                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.030005                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033816                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.033816                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13579.166537                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13579.166537                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18738.282694                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18738.282694                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21919.669064                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21919.669064                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23632.010869                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23632.010869                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13116.919559                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13116.919559                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22811.668117                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22811.668117                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        40701                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        40701                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  42726170500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  42726170500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26732145261                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26732145261                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16635879000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16635879000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  11021618644                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  11021618644                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1587191500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1587191500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4375287000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4375287000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2947500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2947500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  80479934405                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  80479934405                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  97115813405                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  97115813405                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3797634000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3797634000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3797634000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3797634000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035201                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035201                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018033                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018033                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.782285                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.782285                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.725313                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.725313                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056388                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056388                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095133                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095133                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029854                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.029854                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033898                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.033898                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14087.428522                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14087.428522                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19424.353744                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19424.353744                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24124.794076                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.794076                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23939.587796                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23939.587796                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13629.694034                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13629.694034                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22753.822391                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22753.822391                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15973.645981                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15973.645981                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16671.053369                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16671.053369                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175141.837792                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175141.837792                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91496.764431                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91496.764431                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements          6014648                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          501.532915                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          195349774                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          6015160                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            32.476239                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8517720712000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.532915                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979556                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.979556                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16527.214974                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16527.214974                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17469.650463                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17469.650463                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178368.042835                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178368.042835                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 93305.668165                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 93305.668165                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements          5902862                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          501.529159                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          204324856                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          5903374                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            34.611538                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8518180301500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.529159                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979549                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.979549                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          341                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          243                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           94                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        409423979                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       409423979                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst    195349774                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      195349774                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    195349774                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       195349774                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    195349774                       # number of overall hits
-system.cpu1.icache.overall_hits::total      195349774                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      6354622                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      6354622                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      6354622                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       6354622                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      6354622                       # number of overall misses
-system.cpu1.icache.overall_misses::total      6354622                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  66668444908                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  66668444908                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  66668444908                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  66668444908                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  66668444908                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  66668444908                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    201704396                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    201704396                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    201704396                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    201704396                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    201704396                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    201704396                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.031505                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.031505                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.031505                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.031505                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.031505                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.031505                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10491.331335                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10491.331335                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10491.331335                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10491.331335                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10491.331335                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10491.331335                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs      9555681                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          472                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs           727552                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              4                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.134018                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          118                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks      6014648                       # number of writebacks
-system.cpu1.icache.writebacks::total          6014648                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       339435                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total       339435                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst       339435                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total       339435                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst       339435                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total       339435                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      6015187                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      6015187                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      6015187                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      6015187                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      6015187                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      6015187                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           68                       # number of ReadReq MSHR uncacheable
-system.cpu1.icache.ReadReq_mshr_uncacheable::total           68                       # number of ReadReq MSHR uncacheable
-system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           68                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.overall_mshr_uncacheable_misses::total           68                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  60428904539                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  60428904539                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  60428904539                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  60428904539                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  60428904539                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  60428904539                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6183499                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6183499                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6183499                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      6183499                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.029822                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.029822                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.029822                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.029822                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.029822                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.029822                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10046.055848                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10046.055848                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10046.055848                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10046.055848                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10046.055848                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10046.055848                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90933.808824                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90933.808824                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      6826847                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      6833838                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit         6347                       # number of redundant prefetches already in prefetch queue
+system.cpu1.icache.tags.tag_accesses        427035149                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       427035149                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst    204324856                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      204324856                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    204324856                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       204324856                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    204324856                       # number of overall hits
+system.cpu1.icache.overall_hits::total      204324856                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      6241016                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      6241016                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      6241016                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       6241016                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      6241016                       # number of overall misses
+system.cpu1.icache.overall_misses::total      6241016                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  68483006769                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  68483006769                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  68483006769                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  68483006769                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  68483006769                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  68483006769                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    210565872                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    210565872                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    210565872                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    210565872                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    210565872                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    210565872                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029639                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.029639                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029639                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.029639                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029639                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.029639                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10973.054190                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10973.054190                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10973.054190                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10973.054190                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10973.054190                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10973.054190                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs     10089385                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets          780                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs           729550                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              2                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.829600                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          390                       # average number of cycles each access was blocked
+system.cpu1.icache.writebacks::writebacks      5902862                       # number of writebacks
+system.cpu1.icache.writebacks::total          5902862                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       337611                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total       337611                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst       337611                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total       337611                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst       337611                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total       337611                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5903405                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      5903405                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      5903405                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      5903405                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      5903405                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      5903405                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
+system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
+system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  61792345334                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  61792345334                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  61792345334                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  61792345334                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  61792345334                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  61792345334                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7079498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      7079498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      7079498                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      7079498                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.028036                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.028036                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.028036                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.028036                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.028036                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.028036                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10467.238032                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10467.238032                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10467.238032                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10467.238032                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10467.238032                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 10467.238032                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 105664.149254                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 105664.149254                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      7372835                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      7380898                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit         7290                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       835722                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements         1955228                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       12896.405710                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          10261646                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         1970971                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            5.206391                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage       895622                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.tags.replacements         2111480                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       12950.875249                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          10279593                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2126904                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            4.833125                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.365224                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    35.187602                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    26.957161                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   235.895723                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.768943                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002148                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.001645                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.014398                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.787134                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          398                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           66                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15279                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           11                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          186                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           92                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          100                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           49                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         2171                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         6847                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4119                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1911                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.024292                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004028                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.932556                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       388828691                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      388828691                       # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       536780                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       184573                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        721353                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks      3280399                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total      3280399                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      7886275                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      7886275                       # number of WritebackClean hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data           44                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total           44                       # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       841994                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       841994                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      5485264                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      5485264                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2792582                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2792582                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       201829                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       201829                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       536780                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       184573                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      5485264                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3634576                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        9841193                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       536780                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       184573                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      5485264                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3634576                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       9841193                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        18586                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8726                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        27312                       # number of ReadReq misses
-system.cpu1.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
-system.cpu1.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       218938                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       218938                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       183916                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       183916                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12615.195694                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    33.253837                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    24.384299                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   278.041418                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.769970                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002030                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.001488                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.016970                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.790459                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          414                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023          111                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14899                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           65                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          128                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          114                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          107                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            7                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           89                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            6                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          279                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1377                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5586                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5487                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         2170                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.025269                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.006775                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.909363                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       393006433                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      393006433                       # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       563217                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       188120                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        751337                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3404083                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3404083                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks      7859423                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total      7859423                       # number of WritebackClean hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data           37                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total           37                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            1                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       897837                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       897837                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      5343474                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      5343474                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2865962                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2865962                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       200218                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       200218                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       563217                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       188120                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      5343474                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3763799                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        9858610                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       563217                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       188120                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      5343474                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3763799                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       9858610                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        20588                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9811                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        30399                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       230170                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       230170                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       192283                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       192283                       # number of SCUpgradeReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            4                       # number of SCUpgradeFailReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       248462                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       248462                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       529890                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       529890                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       900142                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       900142                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       250350                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       250350                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        18586                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8726                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       529890                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1148604                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1705806                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        18586                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8726                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       529890                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1148604                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1705806                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    561198500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    279280000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    840478500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    939555000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    939555000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    281624500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    281624500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2725499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2725499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10972899994                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  10972899994                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  18159407000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  18159407000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  31177890486                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  31177890486                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    362314500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total    362314500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    561198500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    279280000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  18159407000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  42150790480                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  61150675980                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    561198500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    279280000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  18159407000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  42150790480                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  61150675980                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       555366                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       193299                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       748665                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3280399                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total      3280399                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks      7886276                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total      7886276                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       218982                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       218982                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       183916                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       183916                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       257129                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       257129                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       559914                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       559914                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       968987                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total       968987                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       258105                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       258105                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        20588                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9811                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       559914                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1226116                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1816429                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        20588                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9811                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       559914                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1226116                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1816429                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    677842000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    364880500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total   1042722500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    983294000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    983294000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    271676000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    271676000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2839500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2839500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  12532259990                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total  12532259990                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  20571950500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  20571950500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  36061918479                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  36061918479                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    340389000                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total    340389000                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    677842000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    364880500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  20571950500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  48594178469                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  70208851469                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    677842000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    364880500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  20571950500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  48594178469                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  70208851469                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       583805                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       197931                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       781736                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3404083                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      3404083                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks      7859423                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total      7859423                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       230207                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       230207                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       192284                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       192284                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1090456                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1090456                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      6015154                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      6015154                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3692724                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3692724                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       452179                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       452179                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       555366                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       193299                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      6015154                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4783180                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     11546999                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       555366                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       193299                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      6015154                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4783180                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     11546999                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.033466                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.045142                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.036481                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
-system.cpu1.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.999799                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999799                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1154966                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1154966                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5903388                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      5903388                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3834949                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3834949                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       458323                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       458323                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       583805                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       197931                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      5903388                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4989915                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     11675039                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       583805                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       197931                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      5903388                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4989915                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     11675039                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.035265                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.049568                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.038887                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.999839                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999839                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999995                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999995                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.227851                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.227851                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.088093                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.088093                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.243761                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.243761                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.553652                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.553652                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.033466                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.045142                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.088093                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.240134                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.147727                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.033466                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.045142                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.088093                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.240134                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.147727                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30194.689551                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 32005.500802                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30773.231547                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4291.420402                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4291.420402                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1531.266991                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1531.266991                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 681374.750000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 681374.750000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44163.292552                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44163.292552                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34270.144747                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34270.144747                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34636.635649                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34636.635649                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1447.231875                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1447.231875                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30194.689551                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 32005.500802                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34270.144747                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36697.408750                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 35848.552520                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30194.689551                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 32005.500802                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34270.144747                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36697.408750                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 35848.552520                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          288                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.222629                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.222629                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.094846                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.094846                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.252673                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.252673                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.563151                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.563151                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.035265                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.049568                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.094846                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.245719                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.155582                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.035265                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.049568                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.094846                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.245719                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.155582                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32924.130561                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37190.959128                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34301.210566                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4272.033714                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4272.033714                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1412.896616                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1412.896616                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       709875                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       709875                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48739.193129                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48739.193129                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36741.268302                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36741.268302                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37216.101433                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37216.101433                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1318.800488                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1318.800488                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32924.130561                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37190.959128                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36741.268302                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39632.611000                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 38652.130895                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32924.130561                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37190.959128                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36741.268302                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39632.611000                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 38652.130895                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs          308                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               5                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs              11                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    57.600000                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           28                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches           40502                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks      1084478                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1084478                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker           75                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          191                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          266                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        10775                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total        10775                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            2                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         4833                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         4833                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            2                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker           75                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          191                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data        15608                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total        15876                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker           75                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          191                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            2                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data        15608                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total        15876                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        18511                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8535                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        27046                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
-system.cpu1.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       693628                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       693628                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       218938                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       218938                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       183916                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       183916                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.unused_prefetches           42085                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks      1170856                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1170856                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker           68                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          195                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total          263                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        13529                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total        13529                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            3                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         4671                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         4671                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            5                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::total            5                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker           68                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          195                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            3                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data        18200                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total        18466                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker           68                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          195                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            3                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data        18200                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total        18466                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        20520                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9616                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        30136                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       763352                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       763352                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       230170                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       230170                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       192283                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       192283                       # number of SCUpgradeReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            4                       # number of SCUpgradeFailReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       237687                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       237687                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       529888                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       529888                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       895309                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       895309                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       250348                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       250348                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        18511                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8535                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       529888                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1132996                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1689930                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        18511                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8535                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       529888                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1132996                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       693628                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2383558                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           68                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        21232                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        21300                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       243600                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       243600                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       559911                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       559911                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       964316                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       964316                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       258100                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       258100                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        20520                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9616                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       559911                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1207916                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1797963                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        20520                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9616                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       559911                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1207916                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       763352                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total      2561315                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        21291                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        21358                       # number of ReadReq MSHR uncacheable
 system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        19410                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        19410                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           68                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        40642                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        40710                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    448702000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    224952500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    673654500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  32672970024                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  32672970024                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4113980492                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4113980492                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2813333996                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2813333996                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2299499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2299499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7950875496                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7950875496                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  14980050000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  14980050000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  25503490486                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  25503490486                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6724179499                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6724179499                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    448702000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    224952500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  14980050000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  33454365982                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  49108070482                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    448702000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    224952500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  14980050000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  33454365982                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  32672970024                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  81781040506                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5673000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3548566000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3554239000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      5673000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3548566000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3554239000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.033331                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.044154                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.036126                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
-system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        40701                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        40768                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    553404000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    304119000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    857523000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  42319154022                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  42319154022                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4307815491                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4307815491                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2930523994                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2930523994                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2407500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2407500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8988147495                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8988147495                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  17212365000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  17212365000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  29935787486                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  29935787486                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6963364497                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6963364497                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    553404000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    304119000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  17212365000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  38923934981                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  56993822981                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    553404000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    304119000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  17212365000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  38923934981                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  42319154022                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  99312977003                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6576000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3627092000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3633668000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      6576000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3627092000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3633668000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.035149                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.048583                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.038550                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.999799                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.999799                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.999839                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.999839                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999995                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999995                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.217970                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.217970                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.088092                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.088092                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.242452                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.242452                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.553648                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.553648                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.033331                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.044154                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.088092                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.236871                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.146352                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.033331                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.044154                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.088092                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.236871                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.210915                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.210915                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.094846                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.094846                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.251455                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.251455                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.563140                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.563140                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.035149                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.048583                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.094846                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.242071                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.154001                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.035149                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.048583                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.094846                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.242071                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.206422                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24907.731273                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 47104.456602                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18790.618769                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18790.618769                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15296.842015                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15296.842015                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574874.750000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574874.750000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33451.032223                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33451.032223                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28270.219367                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28270.219367                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28485.685373                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28485.685373                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26859.329809                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26859.329809                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28270.219367                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29527.346947                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29059.233508                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28270.219367                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29527.346947                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34310.488986                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167132.912585                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166865.680751                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87312.779883                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87306.288381                       # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests     23161545                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11911126                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1586                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       559932                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       559928                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.219384                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28455.103531                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55438.584063                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18715.799153                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18715.799153                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15240.681672                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15240.681672                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       601875                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       601875                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36897.157204                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36897.157204                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30741.251735                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30741.251735                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31043.545359                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31043.545359                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26979.327768                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26979.327768                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30741.251735                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32224.041226                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31699.107813                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30741.251735                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32224.041226                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38774.214418                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170357.991640                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170131.472984                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 89115.549986                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 89130.396389                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests     23401917                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     12050394                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1685                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       583324                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       583320                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            4                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq        858463                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     10650090                       # Transaction distribution
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq        895492                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     10720388                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteReq        19410                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteResp        19410                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      4372034                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      7887876                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      1202832                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       877539                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp           29                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       412195                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       333118                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       458356                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           58                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          125                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1116808                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1095312                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      6015187                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4685876                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       509592                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       452179                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     18045125                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16655613                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       406321                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1179507                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         36286566                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    769908416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    641765745                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1546392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4442928                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1417663481                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    4824103                       # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic             76247568                       # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples     17122714                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.052642                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.223318                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4582624                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      7861129                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      1298468                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       967756                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp           11                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       436519                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       348532                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       480708                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           65                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          133                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1183332                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1160512                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5903405                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4845353                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       522418                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       458323                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     17709789                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17335665                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       416038                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1239832                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         36701324                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    755601072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    668583302                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1583448                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4670440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1430438262                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    5153113                       # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic             82064432                       # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples     17599300                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.053842                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.225707                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          16221347     94.74%     94.74% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            901363      5.26%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          16651717     94.62%     94.62% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            947579      5.38%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 4      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      17122714                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   23027796506                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      17599300                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   23252082447                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    160947650                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    167523282                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   9028759604                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   8861086123                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7641863842                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7965231666                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    213393747                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    218506693                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    624968323                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    656902733                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40315                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40315                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136630                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136630                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47698                       # Packet count per connected master and slave (bytes)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40332                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40332                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136631                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136631                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47650                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -3015,15 +2998,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122580                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231230                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231230                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122584                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231262                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231262                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353890                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47718                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353926                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47670                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -3034,27 +3017,27 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155710                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338936                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338936                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155691                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339064                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7339064                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496732                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36996503                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496841                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36933004                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               325000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               324000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
@@ -3062,77 +3045,77 @@ system.iobus.reqLayer15.occupancy               10500                       # La
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               13000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            24232502                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            24511500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            36410001                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36406001                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           568919799                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           569333352                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92681000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92684000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147926000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147958000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115610                       # number of replacements
-system.iocache.tags.tagsinuse               11.211324                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115627                       # number of replacements
+system.iocache.tags.tagsinuse               11.209625                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115626                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115643                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9155814843000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     7.413268                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     3.798056                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.463329                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.237379                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.700708                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9156281985000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.417323                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.792302                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.463583                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.237019                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.700602                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040892                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040892                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1041036                       # Number of tag accesses
+system.iocache.tags.data_accesses             1041036                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8887                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8924                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8903                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8940                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115615                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115655                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115631                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115671                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115615                       # number of overall misses
-system.iocache.overall_misses::total           115655                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115631                       # number of overall misses
+system.iocache.overall_misses::total           115671                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5200000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1677259553                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1682459553                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1786499757                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1791699757                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12947566246                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12947566246                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13185420595                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13185420595                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5569000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14624825799                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14630394799                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  14971920352                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  14977489352                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5569000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14624825799                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14630394799                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  14971920352                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  14977489352                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8887                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8924                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8903                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8940                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115615                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115655                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115631                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115671                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115615                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115655                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115631                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115671                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -3147,52 +3130,52 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 188731.805221                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 188531.998319                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 200662.670673                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 200413.843065                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121313.678191                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 121313.678191                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123542.281266                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 123542.281266                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       139225                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 126495.920071                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126500.322502                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 129480.159750                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 129483.529597                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       139225                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 126495.920071                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126500.322502                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         33395                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 129480.159750                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 129483.529597                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         39692                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3494                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3537                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.557813                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    11.221939                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks          106693                       # number of writebacks
-system.iocache.writebacks::total               106693                       # number of writebacks
+system.iocache.writebacks::writebacks          106694                       # number of writebacks
+system.iocache.writebacks::total               106694                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8887                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8924                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8903                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8940                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115615                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115655                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115631                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115671                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115615                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115655                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide       115631                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115671                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3350000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1232909553                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1236259553                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1341349757                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1344699757                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7602399187                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7602399187                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7839860905                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7839860905                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3569000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8835308740                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8838877740                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9181210662                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9184779662                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3569000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8835308740                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8838877740                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9181210662                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9184779662                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -3207,664 +3190,658 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138731.805221                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 138531.998319                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 150662.670673                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 150413.843065                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71231.534246                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71231.534246                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73456.458521                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73456.458521                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89225                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.090300                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76424.518957                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 79400.944920                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 79404.342160                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89225                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.090300                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76424.518957                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1575605                       # number of replacements
-system.l2c.tags.tagsinuse                65208.311267                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6750580                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1636875                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.124066                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               3024712500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks    9648.504654                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   430.210636                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   509.722466                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4113.935017                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    22579.924066                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 21373.967512                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    14.667516                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    13.437669                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2580.265558                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2788.873436                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1154.802739                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.147224                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.006564                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.007778                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.062774                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.344542                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.326141                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000224                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000205                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.039372                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.042555                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.017621                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.995000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        10940                       # Occupied blocks per task id
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 79400.944920                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 79404.342160                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                  1712520                       # number of replacements
+system.l2c.tags.tagsinuse                65207.555116                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    7020190                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1774780                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.955527                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               3083323500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   10815.100932                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   305.602667                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   366.195320                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3964.024216                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    19638.791484                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14261.868883                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   151.853339                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   181.379081                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3223.101636                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     5938.767305                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  6360.870252                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.165025                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.004663                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.005588                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.060486                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.299664                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.217619                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002317                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.002768                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.049181                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.090618                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.097059                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.994988                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        11498                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_blocks::1023          249                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        50081                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          103                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          404                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        10423                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::1            5                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          244                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2182                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         3614                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        44004                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.166931                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_blocks::1024        50513                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2         1395                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          577                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         9525                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          246                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          271                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2497                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4893                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        42814                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.175446                       # Percentage of cache occupancy per task id
 system.l2c.tags.occ_task_id_percent::1023     0.003799                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.764175                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 76956529                       # Number of tag accesses
-system.l2c.tags.data_accesses                76956529                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks      2841841                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         2841841                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks            3                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total               3                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data          208782                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data          171973                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total              380755                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data         54097                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data         47819                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total            101916                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            54890                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            53294                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               108184                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        12794                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5104                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       534660                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       628574                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       294599                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        11629                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         5041                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       480238                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       542860                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       283154                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          2798653                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       134880                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       130480                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           265360                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         12794                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          5104                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              534660                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              683464                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       294599                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         11629                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5041                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              480238                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              596154                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       283154                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2906837                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        12794                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         5104                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             534660                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             683464                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       294599                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        11629                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5041                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             480238                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             596154                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       283154                       # number of overall hits
-system.l2c.overall_hits::total                2906837                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         24185                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         25856                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             50041                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          906                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          988                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1894                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          87757                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          47516                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             135273                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3402                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3300                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        61095                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       168033                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       329831                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1494                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker          962                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        49649                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       109122                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       190278                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         917166                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       463890                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       106177                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         570067                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         3402                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         3300                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             61095                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            255790                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       329831                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         1494                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker          962                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             49649                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            156638                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       190278                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1052439                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         3402                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         3300                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            61095                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           255790                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       329831                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         1494                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker          962                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            49649                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           156638                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       190278                       # number of overall misses
-system.l2c.overall_misses::total              1052439                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    155584500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    165207000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    320791500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     10231000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      8907000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total     19138000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   8384405997                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4313472997                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  12697878994                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    311169000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    297359500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   5460514000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  16355884996                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  47369049298                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    141229500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker     92798500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   4383525500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  10640360000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  27539015255                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 112590905549                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data     36778500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data     35261000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total     72039500                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    311169000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    297359500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   5460514000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  24740290993                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  47369049298                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    141229500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker     92798500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   4383525500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  14953832997                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  27539015255                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    125288784543                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    311169000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    297359500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   5460514000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  24740290993                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  47369049298                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    141229500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker     92798500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   4383525500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  14953832997                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  27539015255                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   125288784543                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks      2841841                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      2841841                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks            3                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total            3                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data       232967                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data       197829                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          430796                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        55003                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        48807                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total        103810                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       142647                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       100810                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           243457                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        16196                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         8404                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       595755                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       796607                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       624430                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        13123                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6003                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       529887                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       651982                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       473432                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3715819                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       598770                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       236657                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total       835427                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        16196                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         8404                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          595755                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          939254                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       624430                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        13123                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6003                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          529887                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          752792                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       473432                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             3959276                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        16196                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         8404                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         595755                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         939254                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       624430                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        13123                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6003                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         529887                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         752792                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       473432                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            3959276                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.103813                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.130699                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.116159                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.016472                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.020243                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.018245                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.615204                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.471342                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.555634                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.210052                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.392670                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.102551                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.210936                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.528211                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.113846                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.160253                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.093697                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.167370                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.401912                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.246827                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.774738                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.448654                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.682366                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.210052                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.392670                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.102551                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.272333                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.528211                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.113846                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.160253                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.093697                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.208076                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.401912                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.265816                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.210052                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.392670                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.102551                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.272333                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.528211                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.113846                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.160253                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.093697                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.208076                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.401912                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.265816                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6433.099028                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6389.503403                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6410.573330                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11292.494481                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  9015.182186                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 10104.540655                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95541.164773                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 90779.379514                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 93868.539871                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 91466.490300                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90108.939394                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 89377.428595                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 97337.338475                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 143616.122493                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 94531.124498                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 96464.137214                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 88290.307962                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97508.843313                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 144730.422093                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 122759.571930                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    79.282804                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   332.096405                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total   126.370234                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 91466.490300                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90108.939394                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 89377.428595                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 96721.103221                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143616.122493                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 94531.124498                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 96464.137214                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 88290.307962                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 95467.466368                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 144730.422093                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 119046.124804                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 91466.490300                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90108.939394                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 89377.428595                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 96721.103221                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143616.122493                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 94531.124498                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 96464.137214                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 88290.307962                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 95467.466368                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 144730.422093                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 119046.124804                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              7554                       # number of cycles access was blocked
+system.l2c.tags.occ_task_id_percent::1024     0.770767                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 80570058                       # Number of tag accesses
+system.l2c.tags.data_accesses                80570058                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks      2973062                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2973062                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data          212913                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          179277                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              392190                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         55777                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         49656                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total            105433                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            53324                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            56619                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               109943                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        12274                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4633                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       532793                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       642111                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       285366                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        12502                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         5292                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       506134                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       588825                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       298655                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          2888585                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       133712                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       132940                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           266652                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         12274                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          4633                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              532793                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              695435                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       285366                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         12502                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          5292                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              506134                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              645444                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       298655                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2998528                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        12274                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         4633                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             532793                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             695435                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       285366                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        12502                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         5292                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             506134                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             645444                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       298655                       # number of overall hits
+system.l2c.overall_hits::total                2998528                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         25668                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         25681                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             51349                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          646                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          809                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1455                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          94289                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          48061                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             142350                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3531                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3298                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        60576                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       185593                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       348444                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2063                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1546                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst        53773                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       117277                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       240910                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total        1017011                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       478287                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data       112149                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         590436                       # number of InvalidateReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         3531                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         3298                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             60576                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            279882                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       348444                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         2063                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         1546                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             53773                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            165338                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher       240910                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1159361                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         3531                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         3298                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            60576                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           279882                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       348444                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         2063                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         1546                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            53773                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           165338                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher       240910                       # number of overall misses
+system.l2c.overall_misses::total              1159361                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    172222000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    155225500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    327447500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      9175000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      5803000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total     14978000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  10233917991                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   5260660499                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  15494578490                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    356299000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    337167500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6654556500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  20784674000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  53218202875                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    218154000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    160424000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst   6046329000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data  13882177499                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  36908535986                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total 138566520360                       # number of ReadSharedReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu0.data     31590000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data     32968000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::total     64558000                       # number of InvalidateReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    356299000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    337167500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   6654556500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  31018591991                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  53218202875                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    218154000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    160424000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   6046329000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  19142837998                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  36908535986                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    154061098850                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    356299000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    337167500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   6654556500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  31018591991                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  53218202875                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    218154000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker    160424000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   6046329000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  19142837998                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  36908535986                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   154061098850                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks      2973062                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      2973062                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data       238581                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data       204958                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          443539                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        56423                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        50465                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total        106888                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       147613                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       104680                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           252293                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        15805                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7931                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       593369                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       827704                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       633810                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        14565                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6838                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       559907                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       706102                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       539565                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3905596                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       611999                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       245089                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total       857088                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        15805                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         7931                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          593369                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          975317                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       633810                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        14565                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         6838                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          559907                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          810782                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       539565                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             4157889                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        15805                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         7931                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         593369                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         975317                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       633810                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        14565                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         6838                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         559907                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         810782                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       539565                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4157889                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.107586                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.125299                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.115771                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.011449                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.016031                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.013612                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.638758                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.459123                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.564225                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.223410                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.415837                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.102088                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.224226                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.549761                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.141641                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.226089                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.096039                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.166091                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.446489                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.260398                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.781516                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.457585                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.688886                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.223410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.415837                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.102088                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.286965                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.549761                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.141641                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.226089                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.096039                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.203924                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.446489                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.278834                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.223410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.415837                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.102088                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.286965                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.549761                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.141641                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.226089                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.096039                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.203924                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.446489                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.278834                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6709.599501                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6044.371325                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6376.901205                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14202.786378                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  7173.053152                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 10294.158076                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108537.772073                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109457.990866                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 108848.461468                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100905.975644                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 102233.929654                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109854.670166                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111990.613870                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 105746.000969                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103767.141009                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 112441.727261                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 118370.844232                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 136248.792157                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    66.048210                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   293.966063                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total   109.339539                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100905.975644                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 102233.929654                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 109854.670166                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 110827.391511                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 105746.000969                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103767.141009                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 112441.727261                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 115780.026358                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 132884.493139                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100905.975644                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 102233.929654                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 109854.670166                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 110827.391511                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 105746.000969                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103767.141009                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 112441.727261                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 115780.026358                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 132884.493139                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             11042                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       86                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                      109                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     87.837209                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs    101.302752                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1208317                       # number of writebacks
-system.l2c.writebacks::total                  1208317                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          117                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           19                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          105                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           30                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          271                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            117                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             19                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            105                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             30                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                271                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           117                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            19                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           105                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            30                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               271                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        63698                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        63698                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        24185                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        25856                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        50041                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          906                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          988                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1894                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        87757                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        47516                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        135273                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         3402                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         3300                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        60978                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       168014                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       329831                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1494                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker          962                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        49544                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       109092                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       190278                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       916895                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data       463890                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data       106177                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       570067                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         3402                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         3300                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        60978                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       255771                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       329831                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         1494                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker          962                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        49544                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       156608                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       190278                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1052168                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         3402                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         3300                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        60978                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       255771                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       329831                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         1494                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker          962                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        49544                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       156608                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       190278                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1052168                       # number of overall MSHR misses
+system.l2c.writebacks::writebacks             1306567                       # number of writebacks
+system.l2c.writebacks::total                  1306567                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           94                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data           23                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          174                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           24                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total          315                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst             94                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             23                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst            174                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             24                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                315                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst            94                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            23                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst           174                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data            24                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               315                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks        73117                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total        73117                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        25668                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        25681                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        51349                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          646                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          809                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1455                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        94289                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        48061                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        142350                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         3531                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         3298                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        60482                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       185570                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       348444                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2063                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1546                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        53599                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data       117253                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       240910                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total      1016696                       # number of ReadSharedReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu0.data       478287                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu1.data       112149                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::total       590436                       # number of InvalidateReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker         3531                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker         3298                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        60482                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       279859                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       348444                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker         2063                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker         1546                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        53599                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data       165314                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       240910                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total          1159046                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker         3531                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker         3298                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        60482                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       279859                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       348444                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker         2063                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker         1546                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        53599                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data       165314                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       240910                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total         1159046                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        17085                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           68                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        21230                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        59676                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        18834                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16980                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data        21289                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        59629                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        18801                       # number of WriteReq MSHR uncacheable
 system.l2c.WriteReq_mshr_uncacheable::cpu1.data        19410                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        38244                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        38211                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        35919                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           68                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        40640                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        97920                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    483874498                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    540970500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   1024844998                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     22167999                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     24045000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     46212999                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7506749175                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3838136855                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  11344886030                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    277149000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    264359500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   4841507552                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  14674367202                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  44070592122                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    126288502                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker     83178500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3879884570                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   9547031729                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  25636045664                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 103400404341                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  11548986121                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2199719000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total  13748705121                       # number of InvalidateReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    277149000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    264359500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   4841507552                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  22181116377                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  44070592122                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    126288502                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     83178500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   3879884570                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  13385168584                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  25636045664                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 114745290371                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    277149000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    264359500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   4841507552                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  22181116377                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  44070592122                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    126288502                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     83178500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   3879884570                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  13385168584                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  25636045664                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 114745290371                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1342704500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2770278503                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4446500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3166216503                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   7283646006                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1342704500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2770278503                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4446500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3166216503                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   7283646006                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        35781                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        40699                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        97840                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    520949500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    534002500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   1054952000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     15625500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     19999000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     35624500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   9290880791                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4779832460                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  14070713251                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    320987004                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    304187500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   6041672064                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  18926430190                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  49733607723                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    197523002                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    144964000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   5494647043                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  12706523221                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  34499199531                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total 128369741278                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  11811554063                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2326727500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  14138281563                       # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    320987004                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    304187500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   6041672064                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  28217310981                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  49733607723                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    197523002                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    144964000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   5494647043                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  17486355681                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  34499199531                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 142440454529                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    320987004                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    304187500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   6041672064                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  28217310981                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  49733607723                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    197523002                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    144964000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   5494647043                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  17486355681                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  34499199531                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 142440454529                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1484185500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2691376000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5368000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3243740000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   7424669500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1484185500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2691376000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5368000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3243740000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   7424669500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.103813                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.130699                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.116159                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.016472                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.020243                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.018245                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.615204                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.471342                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.555634                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.210052                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.392670                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.102354                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.210912                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.528211                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.113846                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.160253                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.093499                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.167324                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.401912                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.246754                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.774738                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.448654                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.682366                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.210052                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.392670                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.102354                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.272313                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.528211                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.113846                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.160253                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.093499                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.208036                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.401912                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.265748                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.210052                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.392670                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.102354                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.272313                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.528211                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.113846                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.160253                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.093499                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.208036                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.401912                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.265748                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20007.215133                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20922.435798                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20480.106273                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24467.990066                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24337.044534                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24399.682682                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85540.175428                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80775.672510                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 83866.595921                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 79397.611466                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 87340.145476                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 78311.895891                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87513.582380                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112772.350532                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24895.958354                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20717.471769                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24117.700412                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 79397.611466                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86722.561889                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 78311.895891                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85469.251788                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 109056.054139                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 79397.611466                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86722.561889                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 78311.895891                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85469.251788                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 109056.054139                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162146.824876                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149138.789590                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 122053.187311                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 77125.713494                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77908.870645                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 74383.639767                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests       3980803                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      2353726                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3243                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.107586                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.125299                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.115771                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.011449                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.016031                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.013612                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.638758                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.459123                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.564225                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.223410                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.415837                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.101930                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.224199                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.549761                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.141641                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.226089                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.095728                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.166057                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.446489                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.260318                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.781516                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.457585                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.688886                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.223410                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.415837                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.101930                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.286942                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.549761                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.141641                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.226089                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.095728                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.203895                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.446489                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.278758                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.223410                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.415837                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.101930                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.286942                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.549761                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.141641                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.226089                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.095728                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.203895                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.446489                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.278758                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20295.679445                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20793.680153                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20544.742838                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24188.080495                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24720.642769                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24484.192440                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98536.210915                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99453.454152                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 98845.895687                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99892.068119                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101990.786172                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102513.984272                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108368.427426                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126261.676330                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24695.536494                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20746.752089                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23945.493776                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99892.068119                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100826.884185                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102513.984272                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105776.617110                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 122894.565469                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99892.068119                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100826.884185                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102513.984272                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105776.617110                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 122894.565469                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158502.709069                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152366.950068                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124514.405742                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75218.020737                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 79700.729748                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 75885.828904                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests       4262418                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      2509154                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3063                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               59676                       # Transaction distribution
-system.membus.trans_dist::ReadResp             985495                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38244                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38244                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1315010                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           256715                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           339680                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         271581                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              24                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            147332                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           134542                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        925819                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        674453                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122580                       # Packet count per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               59629                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1085265                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38211                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38211                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1413261                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           284296                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           353595                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         284030                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              23                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            155418                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           141619                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1025636                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        695069                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122584                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25318                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4797896                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4945870                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237932                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237932                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5183802                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155710                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25156                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5185454                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5333270                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238137                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       238137                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5571407                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155691                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          556                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50636                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    144939472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    145146374                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7255040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7255040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               152401414                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           572055                       # Total snoops (count)
-system.membus.snoopTraffic                     191360                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2456788                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.015156                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.122173                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    158067712                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    158274271                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7266112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7266112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               165540383                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           598647                       # Total snoops (count)
+system.membus.snoopTraffic                     181312                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           2611590                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.013385                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.114916                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2419553     98.48%     98.48% # Request fanout histogram
-system.membus.snoop_fanout::1                   37235      1.52%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2576634     98.66%     98.66% # Request fanout histogram
+system.membus.snoop_fanout::1                   34956      1.34%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2456788                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            98064494                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2611590                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            98274995                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               52000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21142497                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            20993495                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9055699898                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9731390131                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5680392120                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6232103011                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           45554532                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           45620246                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -3907,83 +3884,82 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     11893981                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      6468498                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      1904661                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         211231                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       193743                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        17488                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq              59678                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4527289                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38244                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38244                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      4050158                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean            3                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2718586                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          717362                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        373497                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp        1090859                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          125                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          125                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           293033                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          293033                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4468431                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       869390                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp       835427                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9945746                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7459601                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              17405347                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    252717925                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    183230753                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              435948678                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2969827                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                 128627856                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          8396274                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.355668                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.483046                       # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests     12430379                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      6756092                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      1976828                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         231635                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       213178                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        18457                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq              59631                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4752657                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38211                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38211                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      4279629                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2861492                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          742959                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        389463                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1132422                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          133                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          133                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           304770                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          304770                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4693673                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       888953                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp       857088                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10167135                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8009990                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              18177125                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    258318649                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    198738470                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              457057119                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3168754                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                 137382864                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples          8831298                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.353414                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.482382                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                5427479     64.64%     64.64% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                2951307     35.15%     99.79% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  17488      0.21%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                5728650     64.87%     64.87% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                3084191     34.92%     99.79% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  18457      0.21%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            8396274                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         9289434840                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            8831298                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         9716591105                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2606647                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2596400                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4518737086                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4626263938                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3678115853                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3958447661                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    5420                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    5035                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   13392                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                   13834                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal
index cbe8d6472..b30f1e5a4 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal
@@ -33,134 +33,134 @@
 [    0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
 [    0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
 [    0.000015] Console: colour dummy device 80x25
-[    0.000016] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[    0.000017] pid_max: default: 32768 minimum: 301
-[    0.000024] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[    0.000025] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[    0.000098] hw perfevents: no hardware support available
+[    0.000017] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[    0.000018] pid_max: default: 32768 minimum: 301
+[    0.000025] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[    0.000026] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[    0.000102] hw perfevents: no hardware support available
 [    0.060026] CPU1: Booted secondary processor
-[    1.080051] CPU2: failed to come online
-[    2.100096] CPU3: failed to come online
-[    2.100099] Brought up 2 CPUs
-[    2.100099] SMP: Total of 2 processors activated.
-[    2.100138] devtmpfs: initialized
+[    1.080049] CPU2: failed to come online
+[    2.100093] CPU3: failed to come online
+[    2.100095] Brought up 2 CPUs
+[    2.100096] SMP: Total of 2 processors activated.
+[    2.100135] devtmpfs: initialized
 [    2.100443] atomic64_test: passed
-[    2.100470] regulator-dummy: no parameters
-[    2.100693] NET: Registered protocol family 16
-[    2.100775] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[    2.100781] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[    2.100925] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[    2.100928] Serial: AMBA PL011 UART driver
-[    2.101044] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[    2.101067] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[    2.101650] console [ttyAMA0] enabled
-[    2.101714] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[    2.101743] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[    2.101771] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[    2.101798] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[    2.140207] 3V3: 3300 mV 
-[    2.140239] vgaarb: loaded
-[    2.140270] SCSI subsystem initialized
-[    2.140299] libata version 3.00 loaded.
-[    2.140331] usbcore: registered new interface driver usbfs
-[    2.140346] usbcore: registered new interface driver hub
-[    2.140370] usbcore: registered new device driver usb
-[    2.140390] pps_core: LinuxPPS API ver. 1 registered
-[    2.140399] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[    2.140417] PTP clock support registered
-[    2.140503] Switched to clocksource arch_sys_counter
-[    2.141444] NET: Registered protocol family 2
-[    2.141497] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[    2.141512] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[    2.141527] TCP: Hash tables configured (established 2048 bind 2048)
-[    2.141543] TCP: reno registered
-[    2.141550] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[    2.141561] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[    2.141588] NET: Registered protocol family 1
-[    2.141628] RPC: Registered named UNIX socket transport module.
-[    2.141638] RPC: Registered udp transport module.
-[    2.141647] RPC: Registered tcp transport module.
-[    2.141655] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[    2.141667] PCI: CLS 0 bytes, default 64
-[    2.141771] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[    2.141835] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[    2.142859] fuse init (API version 7.23)
-[    2.142916] msgmni has been set to 469
-[    2.143149] io scheduler noop registered
-[    2.143186] io scheduler cfq registered (default)
-[    2.143405] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[    2.143418] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
-[    2.143429] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[    2.143442] pci_bus 0000:00: root bus resource [bus 00-ff]
-[    2.143451] pci_bus 0000:00: scanning bus
-[    2.143461] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[    2.143473] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[    2.143487] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[    2.143514] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[    2.143526] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]
-[    2.143536] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]
-[    2.143547] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]
-[    2.143557] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]
-[    2.143567] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]
-[    2.143578] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[    2.143604] pci_bus 0000:00: fixups for bus
-[    2.143612] pci_bus 0000:00: bus scan returning with max=00
-[    2.143623] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[    2.143640] pci 0000:00:00.0: fixup irq: got 33
-[    2.143648] pci 0000:00:00.0: assigning IRQ 33
-[    2.143658] pci 0000:00:01.0: fixup irq: got 34
-[    2.143666] pci 0000:00:01.0: assigning IRQ 34
-[    2.143676] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[    2.143689] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[    2.143702] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[    2.143715] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]
-[    2.143726] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]
-[    2.143737] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]
-[    2.143748] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]
-[    2.143759] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]
-[    2.144053] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[    2.144214] ata_piix 0000:00:01.0: version 2.13
-[    2.144224] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[    2.144241] ata_piix 0000:00:01.0: enabling bus mastering
-[    2.144410] scsi0 : ata_piix
-[    2.144458] scsi1 : ata_piix
-[    2.144479] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[    2.144492] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[    2.144562] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[    2.144575] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[    2.144587] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[    2.144599] e1000 0000:00:00.0: enabling bus mastering
-[    2.290528] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[    2.290538] ata1.00: 2096640 sectors, multi 0: LBA 
-[    2.290562] ata1.00: configured for UDMA/33
-[    2.290599] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
-[    2.290672] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[    2.290676] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[    2.290693] sd 0:0:0:0: [sda] Write Protect is off
-[    2.290693] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[    2.290701] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[    2.290789]  sda: sda1
-[    2.290864] sd 0:0:0:0: [sda] Attached SCSI disk
-[    2.410776] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[    2.410789] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[    2.410807] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[    2.410817] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[    2.410834] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[    2.410846] igb: Copyright (c) 2007-2014 Intel Corporation.
-[    2.410894] usbcore: registered new interface driver usb-storage
-[    2.410940] mousedev: PS/2 mouse device common for all mice
-[    2.411046] usbcore: registered new interface driver usbhid
-[    2.411056] usbhid: USB HID core driver
-[    2.411079] TCP: cubic registered
-[    2.411086] NET: Registered protocol family 17
-[    2.411358] VFS: Mounted root (ext2 filesystem) on device 8:1.
-[    2.411396] devtmpfs: mounted
-[    2.411414] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[    2.100471] regulator-dummy: no parameters
+[    2.100695] NET: Registered protocol family 16
+[    2.100778] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[    2.100785] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[    2.100927] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[    2.100930] Serial: AMBA PL011 UART driver
+[    2.101048] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[    2.101072] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[    2.101655] console [ttyAMA0] enabled
+[    2.101721] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[    2.101750] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[    2.101779] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[    2.101807] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[    2.140200] 3V3: 3300 mV 
+[    2.140234] vgaarb: loaded
+[    2.140266] SCSI subsystem initialized
+[    2.140287] libata version 3.00 loaded.
+[    2.140319] usbcore: registered new interface driver usbfs
+[    2.140334] usbcore: registered new interface driver hub
+[    2.140351] usbcore: registered new device driver usb
+[    2.140371] pps_core: LinuxPPS API ver. 1 registered
+[    2.140380] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[    2.140398] PTP clock support registered
+[    2.140483] Switched to clocksource arch_sys_counter
+[    2.141317] NET: Registered protocol family 2
+[    2.141370] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[    2.141386] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[    2.141401] TCP: Hash tables configured (established 2048 bind 2048)
+[    2.141417] TCP: reno registered
+[    2.141424] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[    2.141435] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[    2.141463] NET: Registered protocol family 1
+[    2.141503] RPC: Registered named UNIX socket transport module.
+[    2.141513] RPC: Registered udp transport module.
+[    2.141522] RPC: Registered tcp transport module.
+[    2.141530] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[    2.141542] PCI: CLS 0 bytes, default 64
+[    2.141648] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[    2.141718] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[    2.142752] fuse init (API version 7.23)
+[    2.142809] msgmni has been set to 469
+[    2.142890] io scheduler noop registered
+[    2.142925] io scheduler cfq registered (default)
+[    2.143148] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[    2.143161] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
+[    2.143172] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[    2.143184] pci_bus 0000:00: root bus resource [bus 00-ff]
+[    2.143195] pci_bus 0000:00: scanning bus
+[    2.143204] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[    2.143217] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[    2.143231] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[    2.143258] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[    2.143270] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]
+[    2.143280] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]
+[    2.143291] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]
+[    2.143302] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]
+[    2.143312] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]
+[    2.143323] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[    2.143351] pci_bus 0000:00: fixups for bus
+[    2.143359] pci_bus 0000:00: bus scan returning with max=00
+[    2.143371] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[    2.143388] pci 0000:00:00.0: fixup irq: got 33
+[    2.143397] pci 0000:00:00.0: assigning IRQ 33
+[    2.143406] pci 0000:00:01.0: fixup irq: got 34
+[    2.143415] pci 0000:00:01.0: assigning IRQ 34
+[    2.143425] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[    2.143438] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[    2.143451] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[    2.143463] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]
+[    2.143475] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]
+[    2.143486] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]
+[    2.143497] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]
+[    2.143509] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]
+[    2.143798] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[    2.143959] ata_piix 0000:00:01.0: version 2.13
+[    2.143970] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[    2.143987] ata_piix 0000:00:01.0: enabling bus mastering
+[    2.144155] scsi0 : ata_piix
+[    2.144211] scsi1 : ata_piix
+[    2.144232] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[    2.144244] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[    2.144315] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[    2.144327] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[    2.144340] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[    2.144352] e1000 0000:00:00.0: enabling bus mastering
+[    2.300506] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[    2.300516] ata1.00: 2096640 sectors, multi 0: LBA 
+[    2.300541] ata1.00: configured for UDMA/33
+[    2.300579] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
+[    2.300655] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[    2.300670] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[    2.300700] sd 0:0:0:0: [sda] Write Protect is off
+[    2.300709] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[    2.300725] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[    2.300818]  sda: sda1
+[    2.300900] sd 0:0:0:0: [sda] Attached SCSI disk
+[    2.420759] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[    2.420772] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[    2.420790] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[    2.420801] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[    2.420818] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[    2.420830] igb: Copyright (c) 2007-2014 Intel Corporation.
+[    2.420879] usbcore: registered new interface driver usb-storage
+[    2.420923] mousedev: PS/2 mouse device common for all mice
+[    2.421032] usbcore: registered new interface driver usbhid
+[    2.421042] usbhid: USB HID core driver
+[    2.421068] TCP: cubic registered
+[    2.421076] NET: Registered protocol family 17
+[    2.421334] VFS: Mounted root (ext2 filesystem) on device 8:1.
+[    2.421363] devtmpfs: mounted
+[    2.421381] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
 
INIT: version 2.88 booting

 Starting udev
-[    2.447448] udevd[609]: starting version 182
+[    2.457503] udevd[609]: starting version 182
 Starting Bootlog daemon: bootlogd.

-[    2.532422] random: dd urandom read with 18 bits of entropy available
+[    2.532427] random: dd urandom read with 18 bits of entropy available
 Populating dev cache

 net.ipv4.conf.default.rp_filter = 1

 net.ipv4.conf.all.rp_filter = 1

@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory

 
INIT: Entering runlevel: 5


 Configuring network interfaces... udhcpc (v1.21.1) started

-[    2.640730] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[    2.640714] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
 Sending discover...

 Sending discover...

 Sending discover...

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
index b9ad3e9e4..b4ce59a93 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
@@ -36,7 +36,7 @@ load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM64
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -229,7 +229,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -591,7 +591,7 @@ pipelined=true
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -723,7 +723,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -840,7 +840,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -885,7 +885,7 @@ size=1024
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -897,7 +897,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -929,29 +929,36 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -971,6 +978,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -980,7 +988,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1002,9 +1010,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -1357,7 +1365,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -1670,10 +1678,11 @@ pio=system.iobus.master[21]
 type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
-conf_table_reported=true
+conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1681,7 +1690,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -1912,6 +1921,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1919,7 +1929,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout
index 07f342b7e..34f117433 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:10:34
-gem5 executing on e108600-lin, pid 12234
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:05:44
+gem5 executing on e108600-lin, pid 17601
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3
 
 Selected 64-bit ARM architecture, updating default disk image...
@@ -15,4 +15,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 51327142820000 because m5_exit instruction encountered
+Exiting @ tick 51558697863000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
index 7623e0029..2bd86426a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
@@ -1,140 +1,140 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.558015                       # Number of seconds simulated
-sim_ticks                                51558014828000                       # Number of ticks simulated
-final_tick                               51558014828000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.558698                       # Number of seconds simulated
+sim_ticks                                51558697863000                       # Number of ticks simulated
+final_tick                               51558697863000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 133865                       # Simulator instruction rate (inst/s)
-host_op_rate                                   157345                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6235119796                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 696436                       # Number of bytes of host memory used
-host_seconds                                  8268.97                       # Real time elapsed on the host
-sim_insts                                  1106923026                       # Number of instructions simulated
-sim_ops                                    1301083589                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 167711                       # Simulator instruction rate (inst/s)
+host_op_rate                                   197118                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7760882097                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 692228                       # Number of bytes of host memory used
+host_seconds                                  6643.41                       # Real time elapsed on the host
+sim_insts                                  1114173091                       # Number of instructions simulated
+sim_ops                                    1309536110                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker       667968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       559488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           6546400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         112650248                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        429376                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            120853480                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      6546400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6546400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    140957120                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker       691712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       570944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           6573600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         114559048                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        428096                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            122823400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      6573600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6573600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    143392768                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         140977700                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker        10437                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         8742                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             118240                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1760173                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6709                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1904301                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         2202455                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total         143413348                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker        10808                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         8921                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             118665                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1789998                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6689                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1935081                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         2240512                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              2205028                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker          12956                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker          10852                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               126972                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2184922                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8328                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2344029                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          126972                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             126972                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2733952                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              2243085                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker          13416                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker          11074                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               127497                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2221915                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8303                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2382205                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          127497                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             127497                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2781156                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 399                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2734351                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2733952                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker         12956                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker         10852                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              126972                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2185321                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8328                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                5078380                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1904301                       # Number of read requests accepted
-system.physmem.writeReqs                      2205028                       # Number of write requests accepted
-system.physmem.readBursts                     1904301                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    2205028                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                121838144                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     37120                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 140976896                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 120853480                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              140977700                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      580                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                2781555                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2781156                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker         13416                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker         11074                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              127497                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2222314                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8303                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5163760                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1935081                       # Number of read requests accepted
+system.physmem.writeReqs                      2243085                       # Number of write requests accepted
+system.physmem.readBursts                     1935081                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    2243085                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                123796992                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     48192                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 143410368                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 122823400                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              143413348                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      753                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2282                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              114327                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              123692                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              118245                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117057                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              115229                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              125268                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              115683                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              119593                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              115543                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              144676                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             112600                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             120122                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             113965                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             118266                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             113146                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             116309                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              135142                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              141643                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              136917                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              137997                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              135684                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              143871                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              135153                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              138864                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              135935                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              142790                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             134947                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             140191                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             134987                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             137976                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             134592                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             136075                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              114857                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              123887                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              121380                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              115864                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              115150                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              124779                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              116343                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              120532                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              117169                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              147715                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             116324                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             125031                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             116553                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             122187                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             118707                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             117850                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              135590                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              141676                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              140587                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              138605                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              137623                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              144276                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              136529                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              140386                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              138327                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              145050                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             137213                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             144076                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             138694                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             142077                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             140963                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             139115                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         125                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51558013451500                       # Total gap between requests
+system.physmem.numWrRetry                         498                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51558696478500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1883016                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1913796                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                2202455                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1140639                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    689076                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     48103                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     20384                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       609                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       486                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       633                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       498                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1348                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       388                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      416                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      194                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      189                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      133                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      126                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                2240512                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1142122                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    697940                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     62817                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     25850                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       642                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       477                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       602                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       504                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      1020                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       655                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      347                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      302                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      225                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      166                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      132                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                      123                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      108                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      105                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      111                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      107                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                       90                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       64                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       79                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -160,170 +160,167 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    30482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    38490                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    83702                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   117171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   125843                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   130438                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   133004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   138248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   140822                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   137539                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   142466                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   143357                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   133954                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   146358                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   136372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   127299                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   130102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   120942                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     4373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     3466                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2325                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2247                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     2028                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1875                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1659                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1545                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1535                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1393                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1321                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1242                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     1055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                     1049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      833                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      758                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      761                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      745                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      477                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      365                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       933198                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      281.628105                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     167.352526                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     309.404332                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         371108     39.77%     39.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       233427     25.01%     64.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        88383      9.47%     74.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        51664      5.54%     79.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        37413      4.01%     83.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        26389      2.83%     86.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        21045      2.26%     88.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        17945      1.92%     90.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        85824      9.20%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         933198                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples        116229                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        16.379053                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       52.340079                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511          116223     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            4      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    28657                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    36011                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    84715                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                   118224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                   127097                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   131612                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   133869                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   139104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   141132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   137785                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   140939                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   143104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   134560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   133279                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   134737                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   146876                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   129080                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   132587                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     6051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     4346                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     3556                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     3116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     2816                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     2568                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     2532                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     2407                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     2309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     2163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     2226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     2215                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1932                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1857                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1851                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1676                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1672                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1609                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1636                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1695                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1783                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                     1764                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                     1945                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                     1548                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                     1284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                     1590                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                     2274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                     1415                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      702                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                     1141                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       951139                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      280.933676                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     167.585937                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     307.458614                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         376624     39.60%     39.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       238014     25.02%     64.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        91172      9.59%     74.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        53576      5.63%     79.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        39458      4.15%     83.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        27371      2.88%     86.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        21519      2.26%     89.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        17750      1.87%     90.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        85655      9.01%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         951139                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples        118362                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        16.342416                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       51.876252                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511          118357    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total          116229                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples        116228                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.951965                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.478061                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       17.079115                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31          111884     96.26%     96.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47            1770      1.52%     97.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63             397      0.34%     98.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79             626      0.54%     98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95             488      0.42%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111            246      0.21%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127           362      0.31%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143           120      0.10%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            64      0.06%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175            59      0.05%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            51      0.04%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            11      0.01%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223            17      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239            10      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255            37      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271            24      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287            14      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             3      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             6      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             5      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             4      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             4      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::608-623             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::624-639             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::752-767             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::768-783             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::976-991             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total          116228                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    42075497859                       # Total ticks spent queuing
-system.physmem.totMemAccLat               77770266609                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9518605000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       22101.71                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total          118362                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples        118362                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.931642                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.417353                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       17.979781                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-31           114164     96.45%     96.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-63            1862      1.57%     98.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-95            1234      1.04%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-127            621      0.52%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-159           196      0.17%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-191           102      0.09%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-223            42      0.04%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-255            35      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-287            40      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-319            18      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-351             4      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-383            11      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-415             4      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::448-479             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-511             7      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-543             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::576-607             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::608-639             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::736-767             4      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::768-799             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::864-895             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::960-991             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1024-1055            1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total          118362                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    71570448504                       # Total ticks spent queuing
+system.physmem.totMemAccLat              107839098504                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9671640000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       37000.16                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  40851.71                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.36                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.73                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.34                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.73                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  55750.16                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.40                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.78                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.38                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.78                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.62                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1533744                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1639539                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.57                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.43                       # Row buffer hit rate for writes
-system.physmem.avgGap                     12546577.18                       # Average gap between requests
-system.physmem.pageHitRate                      77.27                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 3530119320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1926156375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7402894200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               7162084800                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3367518529440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1313077918185                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29782982922000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34483600624320                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.831109                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49545451951432                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1721635240000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    290927248568                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3524804640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1923256500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7446082800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               7111728720                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3367518529440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1314046606680                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29782133195250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34483704204030                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.833118                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49544014933949                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1721635240000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    292364518051                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.69                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1560611                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1663363                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.68                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.23                       # Row buffer hit rate for writes
+system.physmem.avgGap                     12340030.64                       # Average gap between requests
+system.physmem.pageHitRate                      77.22                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3363189900                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1787570235                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6802934880                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               5821719840                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           51899586960.000015                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            51612190140                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             3200334720                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy      101759183310                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       76295730720                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       12252381205680                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             12554961718635                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              243.508122                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           51437094541003                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     5396479999                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     22052840000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   51015251458000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 198686963242                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     94153955748                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 223156166011                       # Time in different power states
+system.physmem_1.actEnergy                 3427956840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1822002270                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7008167040                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5875188300                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           53218604400.000015                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            52383682290                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             3161186880                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy      106497624090                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       77662512480                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       12248740584255                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             12559836053265                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              243.602662                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           51435493097538                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     5216830750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     22612324000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   50999709861500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 202245988185                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     95365744212                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 233547114353                       # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           420                       # Number of bytes read from this memory
@@ -340,30 +337,30 @@ system.realview.nvmem.bw_inst_read::total            7                       # I
 system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               290131106                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         198353835                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          13679752                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            208494226                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               130534623                       # Number of BTB hits
+system.cpu.branchPred.lookups               292003156                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         199825428                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          13707860                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            209782047                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               131422635                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             62.608268                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                37597374                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             402079                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         8125236                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            6045082                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses          2080154                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       800698                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             62.647227                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                37743675                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             403344                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         8164760                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            6089475                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          2075285                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       798713                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -393,88 +390,90 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                   1423094                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong               1423094                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        30587                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       273540                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       668841                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       754253                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  2502.822660                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 16371.142747                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535       747574     99.11%     99.11% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071         4739      0.63%     99.74% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607          871      0.12%     99.86% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143          433      0.06%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679          327      0.04%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215           64      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751          235      0.03%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::458752-524287            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::655360-720895            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       754253                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       795185                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 25800.017606                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 21033.129871                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 18337.040091                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       776690     97.67%     97.67% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071        15553      1.96%     99.63% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         1840      0.23%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          558      0.07%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          320      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215          153      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751           44      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287           19      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       795185                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 1040609044948                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.747004                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.517062                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  1036648437448     99.62%     99.62% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    2501393000      0.24%     99.86% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     710900000      0.07%     99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     286069000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     201203000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    121106500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     48982500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     87667500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      3189000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::18-19        41500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::20-21        55500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 1040609044948                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        273541     89.94%     89.94% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         30587     10.06%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       304128                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data      1423094                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                   1433016                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong               1433016                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        32195                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       277777                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       671696                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       761320                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  2826.976830                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 21785.764506                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535       754204     99.07%     99.07% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071         4652      0.61%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607          981      0.13%     99.81% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143          445      0.06%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679          347      0.05%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215           34      0.00%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751          244      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::458752-524287           36      0.00%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::524288-589823           13      0.00%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359          353      0.05%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::655360-720895            7      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::786432-851967            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::917504-983039            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       761320                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       803371                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 26077.733077                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 21137.704877                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 20668.738137                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-131071       799705     99.54%     99.54% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-262143         2825      0.35%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-393215          589      0.07%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-524287          118      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-655359          123      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-786431            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::786432-917503            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::1.17965e+06-1.31072e+06            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       803371                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 1075651264316                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.736998                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.521821                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  1071482592816     99.61%     99.61% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    2636080000      0.25%     99.86% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     763976000      0.07%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     297116500      0.03%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     205516000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    123566500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     47691000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     91565500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      3134000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::18-19         3000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::20-21        23000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 1075651264316                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        277778     89.61%     89.61% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         32195     10.39%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       309973                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data      1433016                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total      1423094                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       304128                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total      1433016                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       309973                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       304128                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1727222                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       309973                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1742989                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    217549636                       # DTB read hits
-system.cpu.dtb.read_misses                    1002675                       # DTB read misses
-system.cpu.dtb.write_hits                   192429615                       # DTB write hits
-system.cpu.dtb.write_misses                    420419                       # DTB write misses
+system.cpu.dtb.read_hits                    218874380                       # DTB read hits
+system.cpu.dtb.read_misses                    1009020                       # DTB read misses
+system.cpu.dtb.write_hits                   193682033                       # DTB write hits
+system.cpu.dtb.write_misses                    423996                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               63275                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1203                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    84838                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       110                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  16158                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid               63704                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1209                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    89021                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       108                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  17262                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     86326                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                218552311                       # DTB read accesses
-system.cpu.dtb.write_accesses               192850034                       # DTB write accesses
+system.cpu.dtb.perms_faults                     85593                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                219883400                       # DTB read accesses
+system.cpu.dtb.write_accesses               194106029                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         409979251                       # DTB hits
-system.cpu.dtb.misses                         1423094                       # DTB misses
-system.cpu.dtb.accesses                     411402345                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                         412556413                       # DTB hits
+system.cpu.dtb.misses                         1433016                       # DTB misses
+system.cpu.dtb.accesses                     413989429                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -504,231 +503,234 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                    177767                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                177767                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1532                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       128663                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        19966                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       157801                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1393.783943                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  9971.559116                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       155663     98.65%     98.65% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535         1042      0.66%     99.31% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303          672      0.43%     99.73% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071          333      0.21%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839           30      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           26      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375           15      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::294912-327679            7      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::327680-360447            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       157801                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       150161                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 28501.914612                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 23015.105793                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 23459.229673                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       144112     95.97%     95.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071         5152      3.43%     99.40% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607          475      0.32%     99.72% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143          255      0.17%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679           99      0.07%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           55      0.04%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       150161                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 911756921068                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.951043                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.216068                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     44693483152      4.90%      4.90% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    867007398416     95.09%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        55571500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          466000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4            2000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 911756921068                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        128663     98.82%     98.82% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1532      1.18%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       130195                       # Table walker page sizes translated
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                    178466                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                178466                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1508                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       129505                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        20095                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       158371                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1754.443680                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 17709.281636                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-65535       157140     99.22%     99.22% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-131071         1047      0.66%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-196607           42      0.03%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-262143           30      0.02%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-327679           14      0.01%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-393215            7      0.00%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::393216-458751            1      0.00%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::458752-524287            1      0.00%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::524288-589823           40      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::589824-655359           48      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       158371                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       151108                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 29265.005824                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23190.077140                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 30431.733671                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       145001     95.96%     95.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         5046      3.34%     99.30% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607          391      0.26%     99.56% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143          366      0.24%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679          100      0.07%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           51      0.03%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           20      0.01%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            8      0.01%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823            6      0.00%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359           85      0.06%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::655360-720895            8      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::720896-786431           24      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::983040-1.04858e+06            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       151108                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 912439402568                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.949255                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.219812                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     46367810152      5.08%      5.08% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    866006867916     94.91%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        63907500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          568000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4          249000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 912439402568                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        129505     98.85%     98.85% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1508      1.15%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       131013                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       177767                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       177767                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       178466                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       178466                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       130195                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       130195                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       307962                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    462600046                       # ITB inst hits
-system.cpu.itb.inst_misses                     177767                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       131013                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       131013                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       309479                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    465485773                       # ITB inst hits
+system.cpu.itb.inst_misses                     178466                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               63275                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1203                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    58185                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               63704                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1209                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    62647                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    440221                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    443320                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                462777813                       # ITB inst accesses
-system.cpu.itb.hits                         462600046                       # DTB hits
-system.cpu.itb.misses                          177767                       # DTB misses
-system.cpu.itb.accesses                     462777813                       # DTB accesses
-system.cpu.numPwrStateTransitions               34262                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples         17131                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     2947433272.666569                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    58590018858.186401                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows         7811     45.60%     45.60% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         9284     54.19%     99.79% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.82% # Distribution of time spent in the clock gated state
+system.cpu.itb.inst_accesses                465664239                       # ITB inst accesses
+system.cpu.itb.hits                         465485773                       # DTB hits
+system.cpu.itb.misses                          178466                       # DTB misses
+system.cpu.itb.accesses                     465664239                       # DTB accesses
+system.cpu.numPwrStateTransitions               34324                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples         17162                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     2940404395.507225                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    58760863847.973442                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows         7839     45.68%     45.68% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10         9288     54.12%     99.80% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+10-1e+11            4      0.02%     99.82% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            4      0.02%     99.84% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.85% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.86% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            2      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+11-5.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::9.5e+11-1e+12            1      0.01%     99.89% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            2      0.01%     99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::9.5e+11-1e+12            1      0.01%     99.90% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::overflows           18      0.10%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 1988780762168                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total           17131                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    1065535433949                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50492479394051                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       2131080190                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::max_value 1988780801904                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total           17162                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    1095477627305                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50463220235695                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       2190964579                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          789533395                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1294232501                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   290131106                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          174177079                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                    1253396684                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                29442936                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    4521296                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                28032                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles      11449142                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1221670                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          685                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 462141962                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6901101                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   52491                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         2074872372                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.731015                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.142682                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          794033282                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1302230220                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   292003156                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          175255785                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                    1304336456                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                29502488                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    4651258                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                26755                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles      11711903                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1225327                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles         1089                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 465024484                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6899822                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   52313                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         2130737314                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.716190                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.134027                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1354023092     65.26%     65.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                279633538     13.48%     78.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 86518146      4.17%     82.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                354697596     17.09%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1403414987     65.87%     65.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                283475853     13.30%     79.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 89003023      4.18%     83.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                354843451     16.65%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           2074872372                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.136143                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.607313                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                615922756                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             835719938                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 532432043                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              80077312                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               10720323                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             41258933                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               4059445                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1407827153                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              33008479                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               10720323                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                679035070                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                79966926                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      552687037                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 549603762                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             202859254                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1383638167                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               8109162                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               7348509                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 966276                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1094350                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents              119568064                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            22725                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1333397174                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2200696007                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1641425227                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1433031                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1254726296                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 78670875                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           43643507                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       39180007                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 166278031                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            222554034                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           196867138                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12635283                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11114743                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1330840515                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            43953891                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1360477402                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           4212137                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        73710813                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     41934009                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         368799                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    2074872372                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.655692                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.916068                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           2130737314                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.133276                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.594364                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                615599644                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             888388322                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 542818505                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              73189293                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               10741550                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             41458105                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               4067803                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1416661162                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              33069720                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               10741550                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                678370602                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                94749069                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      569457122                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 557397759                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             220021212                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1392357267                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               8139910                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               7467928                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 990269                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1135391                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents              140197147                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            22858                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1342242693                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2216016664                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1651872272                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1433815                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1263306379                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 78936311                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           44081382                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       39609601                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 160762582                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            223936207                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           198122558                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12861166                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11120462                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1339067750                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            44403277                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1369076757                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           4228585                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        73934913                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     42101353                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         368543                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    2130737314                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.642537                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.913709                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0          1226409345     59.11%     59.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           451307165     21.75%     80.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           291780533     14.06%     94.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            95920964      4.62%     99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             9425546      0.45%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               28819      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0          1278640571     60.01%     60.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           452467629     21.24%     81.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           292658965     13.74%     94.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            96618652      4.53%     99.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            10322243      0.48%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               29254      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      2074872372                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      2130737314                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                73561900     34.17%     34.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  90692      0.04%     34.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26794      0.01%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              484      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               57931960     26.91%     61.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              83660297     38.86%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                74049078     33.84%     33.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  90108      0.04%     33.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26756      0.01%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              482      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               59033401     26.97%     60.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              85651168     39.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                57      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             939889673     69.09%     69.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2936613      0.22%     69.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                130878      0.01%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                55      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             945875031     69.09%     69.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2941932      0.21%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                129428      0.01%     69.31% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                 372      0.00%     69.31% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.31% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.31% # Type of FU issued
@@ -751,100 +753,100 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.31% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.31% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.31% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         112363      0.01%     69.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         112221      0.01%     69.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            222587367     16.36%     85.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           194820033     14.32%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            223931934     16.36%     85.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           196085738     14.32%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1360477402                       # Type of FU issued
-system.cpu.iq.rate                           0.638398                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   215272127                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.158233                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5012901497                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1447776434                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1338315649                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2409942                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             914537                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       885572                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1574233532                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1515940                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          5717597                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1369076757                       # Type of FU issued
+system.cpu.iq.rate                           0.624874                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   218850993                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.159853                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5089559021                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1456673430                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1346855595                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2411384                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             915419                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       886368                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1586411072                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1516623                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5720273                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     17343387                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        24124                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       187368                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      7978529                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     17413416                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        22608                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       184689                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      8002869                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      3596780                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1680866                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      3613750                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       2051788                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               10720323                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                12040487                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               4569260                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1375079942                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               10741550                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                13180703                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               5272349                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1383757283                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             222554034                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            196867138                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           38644291                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 177419                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               4207009                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         187368                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4048268                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      6103351                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             10151619                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1346834094                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             217554512                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          12249639                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             223936207                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            198122558                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           39070088                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 183909                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               4898355                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         184689                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4057329                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      6115164                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             10172493                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1355379185                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             218880930                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          12294353                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        285536                       # number of nop insts executed
-system.cpu.iew.exec_refs                    409993947                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                255680172                       # Number of branches executed
-system.cpu.iew.exec_stores                  192439435                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.631996                       # Inst execution rate
-system.cpu.iew.wb_sent                     1340240150                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1339201221                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 574929948                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 943031378                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.628414                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.609662                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        62850702                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        43585092                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9678607                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   2060674246                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.631387                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.270689                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        286256                       # number of nop insts executed
+system.cpu.iew.exec_refs                    412572980                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                257403074                       # Number of branches executed
+system.cpu.iew.exec_stores                  193692050                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.618622                       # Inst execution rate
+system.cpu.iew.wb_sent                     1348783541                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1347741963                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 576070929                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 948341211                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.615136                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.607451                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        63015193                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        44034734                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           9698166                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   2116507295                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.618725                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.263721                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1383412740     67.13%     67.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    394991247     19.17%     86.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    150433823      7.30%     93.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     44582057      2.16%     95.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     36156812      1.75%     97.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     18175173      0.88%     98.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     10964042      0.53%     98.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      5475656      0.27%     99.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     16482696      0.80%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1435626131     67.83%     67.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    397528537     18.78%     86.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    150810671      7.13%     93.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     44606790      2.11%     95.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     36101901      1.71%     97.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     18021060      0.85%     98.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     11293216      0.53%     98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      5858251      0.28%     99.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     16660738      0.79%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   2060674246                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts           1106923026                       # Number of instructions committed
-system.cpu.commit.committedOps             1301083589                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   2116507295                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts           1114173091                       # Number of instructions committed
+system.cpu.commit.committedOps             1309536110                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      394099255                       # Number of memory references committed
-system.cpu.commit.loads                     205210646                       # Number of loads committed
-system.cpu.commit.membars                     9122435                       # Number of memory barriers committed
-system.cpu.commit.branches                  247396089                       # Number of branches committed
-system.cpu.commit.fp_insts                     873905                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1189215854                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             30973786                       # Number of function calls committed.
+system.cpu.commit.refs                      396642479                       # Number of memory references committed
+system.cpu.commit.loads                     206522790                       # Number of loads committed
+system.cpu.commit.membars                     9192719                       # Number of memory barriers committed
+system.cpu.commit.branches                  249090207                       # Number of branches committed
+system.cpu.commit.fp_insts                     874521                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1196753296                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             31104441                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        904226715     69.50%     69.50% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2546778      0.20%     69.69% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           104952      0.01%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        910131481     69.50%     69.50% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2552727      0.19%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           103687      0.01%     69.70% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.70% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.70% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.70% # Class of committed instruction
@@ -867,577 +869,581 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.70% #
 system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.70% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.70% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.70% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc       105847      0.01%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       105694      0.01%     69.71% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.71% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.71% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       205210646     15.77%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      188888609     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       206522790     15.77%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      190119689     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1301083589                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              16482696                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3398675710                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2741957858                       # The number of ROB writes
-system.cpu.timesIdled                         9058128                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        56207818                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 100984949503                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                  1106923026                       # Number of Instructions Simulated
-system.cpu.committedOps                    1301083589                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.925229                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.925229                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.519419                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.519419                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1599627417                       # number of integer regfile reads
-system.cpu.int_regfile_writes               942915680                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1421408                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   762380                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 312164706                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                313034766                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              3414318389                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               44468731                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements          13662519                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.983620                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           361203380                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          13663031                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             26.436548                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1659288500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.983620                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999968                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
+system.cpu.commit.op_class_0::total        1309536110                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              16660738                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3462896243                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2759222856                       # The number of ROB writes
+system.cpu.timesIdled                         9103079                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        60227265                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 100926431181                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                  1114173091                       # Number of Instructions Simulated
+system.cpu.committedOps                    1309536110                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.966449                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.966449                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.508531                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.508531                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1609897597                       # number of integer regfile reads
+system.cpu.int_regfile_writes               948614350                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1422281                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   763660                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 314738541                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                315610902                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              3478507383                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               44953668                       # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements          13773933                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.982218                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           363424605                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          13774445                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             26.383974                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1801582500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.982218                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999965                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999965                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          395                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          379                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1599492126                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1599492126                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    186946586                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       186946586                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    163344159                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      163344159                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       463383                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        463383                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       333988                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       333988                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      4793284                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      4793284                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      5278947                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      5278947                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     350624733                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        350624733                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    351088116                       # number of overall hits
-system.cpu.dcache.overall_hits::total       351088116                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     12788061                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      12788061                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     18648516                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     18648516                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      2041461                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      2041461                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1270506                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1270506                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       548369                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       548369                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            9                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            9                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     32707083                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       32707083                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     34748544                       # number of overall misses
-system.cpu.dcache.overall_misses::total      34748544                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 205827865000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 205827865000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1003464059741                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1003464059741                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  29968640002                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  29968640002                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   8933513500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   8933513500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       300500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       300500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 1239260564743                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 1239260564743                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 1239260564743                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 1239260564743                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    199734647                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    199734647                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    181992675                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    181992675                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      2504844                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      2504844                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1604494                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1604494                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      5341653                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      5341653                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      5278956                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      5278956                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    383331816                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    383331816                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    385836660                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    385836660                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.064025                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.064025                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.102468                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.102468                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.815005                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.815005                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791842                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.791842                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.102659                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.102659                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.085323                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.085323                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.090060                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.090060                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16095.314606                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16095.314606                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53809.325082                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53809.325082                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23587.956296                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23587.956296                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16291.062223                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16291.062223                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33388.888889                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33388.888889                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37889.669487                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37889.669487                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35663.668807                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35663.668807                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     24419954                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses        1609792532                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1609792532                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    188105539                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       188105539                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    164299305                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      164299305                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       464298                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        464298                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       335039                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       335039                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      4843113                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4843113                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      5333928                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      5333928                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     352739883                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        352739883                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    353204181                       # number of overall hits
+system.cpu.dcache.overall_hits::total       353204181                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     12867394                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      12867394                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     18868212                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     18868212                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      2064415                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      2064415                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1270711                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1270711                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       552556                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       552556                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            8                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            8                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data     33006317                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       33006317                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     35070732                       # number of overall misses
+system.cpu.dcache.overall_misses::total      35070732                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 226129752000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 226129752000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1113756894884                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1113756894884                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  30103485720                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  30103485720                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   9429427500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   9429427500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       286500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       286500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 1369990132604                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 1369990132604                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 1369990132604                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 1369990132604                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    200972933                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    200972933                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    183167517                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    183167517                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      2528713                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      2528713                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1605750                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1605750                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      5395669                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      5395669                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      5333936                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      5333936                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    385746200                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    385746200                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    388274913                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    388274913                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.064026                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.064026                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.103011                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.103011                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.816390                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.816390                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791350                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.791350                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.102407                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.102407                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.085565                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.085565                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.090324                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.090324                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17573.857768                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17573.857768                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59028.216075                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59028.216075                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23690.269243                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23690.269243                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17065.107428                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17065.107428                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35812.500000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35812.500000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41506.907075                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41506.907075                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39063.630967                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39063.630967                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     29294390                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           2093623                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           2113869                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.663969                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    13.858186                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks     10319802                       # number of writebacks
-system.cpu.dcache.writebacks::total          10319802                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5736139                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      5736139                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data     15576096                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total     15576096                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         6849                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total         6849                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       265006                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       265006                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     21319084                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     21319084                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     21319084                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     21319084                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7051922                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7051922                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      3072420                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      3072420                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      2034687                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      2034687                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1263657                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1263657                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       283363                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       283363                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            9                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            9                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data     11387999                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total     11387999                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     13422686                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     13422686                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks     10422476                       # number of writebacks
+system.cpu.dcache.writebacks::total          10422476                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5755479                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      5755479                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data     15769683                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total     15769683                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         6881                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         6881                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       266620                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       266620                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     21532043                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     21532043                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     21532043                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     21532043                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7111915                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7111915                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      3098529                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      3098529                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      2057605                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      2057605                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1263830                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1263830                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       285936                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       285936                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            8                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            8                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data     11474274                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total     11474274                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     13531879                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     13531879                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33692                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33692                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33703                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33703                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67395                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67395                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110827450000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 110827450000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 147154305213                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 147154305213                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  32559356000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  32559356000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  28426038502                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  28426038502                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   4117736500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   4117736500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       291500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       291500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286407793715                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 286407793715                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318967149715                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 318967149715                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6225596500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6225596500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6225596500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6225596500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035306                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035306                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.016882                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.016882                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.812301                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.812301                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787574                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787574                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.053048                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.053048                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029708                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.029708                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034789                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.034789                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15715.921135                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15715.921135                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47895.243884                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47895.243884                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16002.144802                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16002.144802                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22495.058787                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22495.058787                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14531.666096                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14531.666096                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32388.888889                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32388.888889                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25149.966532                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25149.966532                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23763.287744                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23763.287744                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184779.665796                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184779.665796                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92374.753320                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92374.753320                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements          16891256                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.956016                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           444441322                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          16891768                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             26.311119                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       13164566500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.956016                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999914                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999914                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 120215948500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 120215948500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 164231979720                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 164231979720                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  35080858000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  35080858000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  28539216720                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  28539216720                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   4259524000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   4259524000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       278500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       278500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 312987144940                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 312987144940                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 348068002940                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 348068002940                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6225685500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6225685500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6225685500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6225685500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035387                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035387                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.016916                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.016916                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.813697                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.813697                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787065                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787065                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.052994                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.052994                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029746                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.029746                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034851                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.034851                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16903.456875                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16903.456875                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53003.208852                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53003.208852                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17049.364674                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17049.364674                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22581.531314                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22581.531314                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14896.774103                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14896.774103                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34812.500000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34812.500000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27277.293966                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 27277.293966                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25722.074735                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25722.074735                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184782.307373                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184782.307373                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92376.073893                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92376.073893                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements          16962264                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.953467                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           447249112                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          16962776                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             26.366505                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       13767456500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.953467                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999909                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999909                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          112                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         479012658                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        479012658                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    444441322                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       444441322                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     444441322                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        444441322                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    444441322                       # number of overall hits
-system.cpu.icache.overall_hits::total       444441322                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     17679342                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      17679342                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     17679342                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       17679342                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     17679342                       # number of overall misses
-system.cpu.icache.overall_misses::total      17679342                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 234300237389                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 234300237389                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 234300237389                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 234300237389                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 234300237389                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 234300237389                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    462120664                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    462120664                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    462120664                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    462120664                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    462120664                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    462120664                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.038257                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.038257                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.038257                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.038257                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.038257                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.038257                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13252.769101                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13252.769101                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13252.769101                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13252.769101                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13252.769101                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13252.769101                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        16371                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         481966186                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        481966186                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    447249112                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       447249112                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     447249112                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        447249112                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    447249112                       # number of overall hits
+system.cpu.icache.overall_hits::total       447249112                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     17754074                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      17754074                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     17754074                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       17754074                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     17754074                       # number of overall misses
+system.cpu.icache.overall_misses::total      17754074                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 238230546873                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 238230546873                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 238230546873                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 238230546873                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 238230546873                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 238230546873                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    465003186                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    465003186                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    465003186                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    465003186                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    465003186                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    465003186                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.038181                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.038181                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.038181                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.038181                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.038181                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.038181                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13418.359463                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13418.359463                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13418.359463                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13418.359463                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13418.359463                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13418.359463                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        22063                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1212                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1484                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    13.507426                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    14.867251                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks     16891256                       # number of writebacks
-system.cpu.icache.writebacks::total          16891256                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       787348                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       787348                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       787348                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       787348                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       787348                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       787348                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     16891994                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     16891994                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     16891994                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     16891994                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     16891994                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     16891994                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     16962264                       # number of writebacks
+system.cpu.icache.writebacks::total          16962264                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       791074                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       791074                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       791074                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total       791074                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst       791074                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total       791074                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     16963000                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     16963000                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     16963000                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     16963000                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     16963000                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     16963000                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210691534398                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 210691534398                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210691534398                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 210691534398                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210691534398                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 210691534398                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1610722500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1610722500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1610722500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   1610722500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.036553                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.036553                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.036553                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.036553                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.036553                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.036553                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12472.863440                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12472.863440                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12472.863440                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12472.863440                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12472.863440                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12472.863440                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75642.082277                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75642.082277                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75642.082277                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75642.082277                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements          2372905                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65457.290128                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           58959202                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          2435994                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            24.203345                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       2520974000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9397.889077                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   196.572797                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   228.214718                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6628.882550                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 49005.730985                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.143400                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.002999                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.003482                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.101149                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.747768                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.998799                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          222                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        62867                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          222                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          376                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1017                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5588                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55850                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003387                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.959274                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        505094110                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       505094110                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker      1274032                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       302472                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1576504                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks     10319802                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total     10319802                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     16888637                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     16888637                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        38922                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        38922                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            5                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            5                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1712070                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1712070                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     16794801                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     16794801                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      8925946                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      8925946                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       673558                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       673558                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker      1274032                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       302472                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     16794801                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data     10638016                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        29009321                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker      1274032                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       302472                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     16794801                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data     10638016                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       29009321                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker        10437                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         8742                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        19179                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         4078                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         4078                       # number of UpgradeReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 214024505887                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 214024505887                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 214024505887                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 214024505887                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 214024505887                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 214024505887                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1752662500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1752662500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1752662500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   1752662500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.036479                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.036479                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.036479                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.036479                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.036479                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.036479                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12617.137646                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12617.137646                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12617.137646                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12617.137646                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12617.137646                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12617.137646                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82307.809712                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82307.809712                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82307.809712                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82307.809712                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements          2409655                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65438.820576                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           59303582                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          2471799                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            23.992073                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       2677802000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  9434.053113                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   385.411867                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   416.493163                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6670.865899                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 48531.996533                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.143952                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005881                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006355                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.101789                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.740539                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.998517                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          284                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        61860                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          284                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          304                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1041                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5649                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54812                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004333                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.943909                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        508249108                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       508249108                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker      1295823                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       305430                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1601253                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks     10422476                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total     10422476                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     16959660                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     16959660                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data        39331                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total        39331                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            4                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total            4                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1728598                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1728598                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     16865372                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     16865372                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      8990828                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      8990828                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       668361                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       668361                       # number of InvalidateReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker      1295823                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker       305430                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst     16865372                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data     10719426                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        29186051                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker      1295823                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker       305430                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst     16865372                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data     10719426                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       29186051                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker        10808                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         8922                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        19730                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         4027                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         4027                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            4                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            4                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data      1333352                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total      1333352                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        96984                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        96984                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       428025                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       428025                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       590099                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       590099                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker        10437                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         8742                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        96984                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1761377                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1877540                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker        10437                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         8742                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        96984                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1761377                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1877540                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    936727000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    780169000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1716896000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     73235500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     73235500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       191000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total       191000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123861773500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 123861773500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   8301693500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   8301693500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  38723437000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  38723437000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data       483000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::total       483000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    936727000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    780169000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   8301693500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 162585210500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 172603800000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    936727000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    780169000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   8301693500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 162585210500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 172603800000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker      1284469                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       311214                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1595683                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks     10319802                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total     10319802                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks     16888637                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total     16888637                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        43000                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        43000                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            9                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            9                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      3045422                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      3045422                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     16891785                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     16891785                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      9353971                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      9353971                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1263657                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1263657                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker      1284469                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       311214                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     16891785                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data     12399393                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     30886861                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker      1284469                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       311214                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     16891785                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data     12399393                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     30886861                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.008126                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.028090                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.012019                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.094837                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.094837                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.444444                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.444444                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.437822                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.437822                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005741                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005741                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.045759                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.045759                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.466977                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.466977                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.008126                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.028090                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005741                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.142053                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.060788                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.008126                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.028090                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005741                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.142053                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.060788                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89750.598831                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89243.765729                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 89519.578706                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17958.680726                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17958.680726                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        47750                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        47750                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92895.029595                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92895.029595                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85598.588427                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85598.588427                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90470.035629                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90470.035629                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data     0.818507                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total     0.818507                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89750.598831                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89243.765729                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85598.588427                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92305.741758                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 91930.824377                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89750.598831                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89243.765729                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85598.588427                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92305.741758                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 91930.824377                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_misses::cpu.data      1343031                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total      1343031                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        97409                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        97409                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       448173                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       448173                       # number of ReadSharedReq misses
+system.cpu.l2cache.InvalidateReq_misses::cpu.data       595469                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       595469                       # number of InvalidateReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker        10808                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker         8922                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        97409                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1791204                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1908343                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker        10808                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker         8922                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        97409                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1791204                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1908343                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker   1486458000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    980532000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2466990000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     73290500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     73290500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       192000                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::total       192000                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 140749219500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 140749219500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  10783493000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total  10783493000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  49949086500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  49949086500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data       569000                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::total       569000                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker   1486458000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    980532000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  10783493000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 190698306000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 203948789000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker   1486458000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    980532000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  10783493000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 190698306000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 203948789000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker      1306631                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       314352                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1620983                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks     10422476                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total     10422476                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     16959660                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     16959660                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        43358                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        43358                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            8                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total            8                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      3071629                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      3071629                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     16962781                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     16962781                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      9439001                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      9439001                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1263830                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1263830                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker      1306631                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       314352                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     16962781                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data     12510630                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     31094394                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker      1306631                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       314352                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     16962781                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data     12510630                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     31094394                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.008272                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.028382                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.012172                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.092878                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.092878                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.437237                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.437237                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005743                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005743                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.047481                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.047481                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.471162                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.471162                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.008272                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.028382                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005743                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.143175                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.061373                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.008272                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.028382                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005743                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.143175                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.061373                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137533.123612                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 109900.470746                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 125037.506336                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18199.776509                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18199.776509                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        48000                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        48000                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104799.680350                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104799.680350                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110703.251240                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110703.251240                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 111450.458863                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 111450.458863                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data     0.955549                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total     0.955549                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137533.123612                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 109900.470746                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110703.251240                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106463.756222                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 106872.186499                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137533.123612                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 109900.470746                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110703.251240                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106463.756222                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 106872.186499                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks      2095825                       # number of writebacks
-system.cpu.l2cache.writebacks::total          2095825                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      2133882                       # number of writebacks
+system.cpu.l2cache.writebacks::total          2133882                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.itb.walker            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           22                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.itb.walker            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker        10437                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         8742                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        19179                       # number of ReadReq MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            3                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            3                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4078                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         4078                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::total           22                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker        10808                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         8921                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        19729                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4027                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         4027                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            4                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            4                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data      1333352                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total      1333352                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        96984                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        96984                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       428004                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       428004                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       590099                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       590099                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker        10437                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         8742                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        96984                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1761356                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1877519                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker        10437                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         8742                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        96984                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1761356                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1877519                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data      1343031                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total      1343031                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        97409                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        97409                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       448152                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       448152                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       595469                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       595469                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker        10808                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         8921                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        97409                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1791183                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1908321                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker        10808                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         8921                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        97409                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1791183                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1908321                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33692                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54986                       # number of ReadReq MSHR uncacheable
@@ -1446,156 +1452,156 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33703
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67395                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88689                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    832356501                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    692749000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1525105501                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     77850000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     77850000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       181500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       181500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110528159195                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110528159195                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   7331831049                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   7331831049                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  34442081593                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  34442081593                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  12207320002                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  12207320002                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    832356501                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    692749000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7331831049                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144970240788                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 153827177338                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    832356501                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    692749000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7331831049                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144970240788                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 153827177338                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1344547500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5804287500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   7148835000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1344547500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5804287500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   7148835000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.008126                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.028090                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.012019                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1378378000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    891304000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2269682000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     76822000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     76822000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       182500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       182500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127318887048                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127318887048                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   9809383542                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   9809383542                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  45465885070                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  45465885070                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  12316948002                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  12316948002                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker   1378378000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    891304000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   9809383542                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 172784772118                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 184863837660                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker   1378378000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    891304000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   9809383542                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 172784772118                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 184863837660                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1486487500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5804372500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   7290860000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1486487500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5804372500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   7290860000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.008272                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.028379                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.012171                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.094837                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.094837                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.444444                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.444444                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.437822                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.437822                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005741                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005741                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.045756                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.045756                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.466977                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.466977                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.008126                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.028090                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005741                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.142052                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060787                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.008126                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.028090                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005741                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.142052                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060787                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79243.765729                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79519.552688                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19090.240314                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19090.240314                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        45375                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        45375                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82894.958867                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82894.958867                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75598.356935                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75598.356935                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80471.401186                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80471.401186                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.901693                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.901693                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79243.765729                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75598.356935                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82306.041929                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81931.089559                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79243.765729                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75598.356935                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82306.041929                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81931.089559                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63142.082277                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172274.946575                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130011.912123                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63142.082277                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86123.414200                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 80605.655718                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     62084255                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     31529230                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3455                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2096                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2096                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.092878                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.092878                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.437237                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.437237                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005743                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005743                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.047479                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.047479                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.471162                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.471162                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.008272                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.028379                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005743                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.143173                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.061372                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.008272                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.028379                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005743                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.143173                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.061372                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99910.772335                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115042.931725                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19076.732059                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19076.732059                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        45625                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        45625                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94799.663632                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94799.663632                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100703.051484                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100703.051484                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101451.929412                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101451.929412                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20684.448732                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20684.448732                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99910.772335                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100703.051484                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96464.053153                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96872.506072                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99910.772335                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100703.051484                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96464.053153                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96872.506072                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69807.809712                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.469429                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.842324                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69807.809712                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.675421                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.038077                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests     62444778                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     31707340                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3433                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2080                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2080                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq        2242102                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      28488845                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq        2265526                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      28668320                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33703                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33703                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty     12415627                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     16891256                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      3619797                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43003                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            9                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43012                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      3045422                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      3045422                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     16891994                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      9356331                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1295806                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1263657                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50717623                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     41210208                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       777423                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3005376                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          95710630                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   2162455328                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1454268658                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2489712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side     10275752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         3629489450                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2999840                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic             138927432                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     35281285                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.026592                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.160887                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty     12556358                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     16962264                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      3627230                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43361                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            8                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43369                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      3071629                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      3071629                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     16963000                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      9441368                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1296315                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1263830                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50930633                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     41545171                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       782892                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3048631                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          96307327                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   2171543584                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1467959922                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2514816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side     10453048                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         3652471370                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     3035082                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic             141349672                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     35524572                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.026277                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.159958                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           34343098     97.34%     97.34% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             938187      2.66%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           34591090     97.37%     97.37% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             933482      2.63%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       35281285                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    58941748976                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       35524572                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    59309730487                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1470395                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1500879                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   25369728010                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   25476019939                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   19308156079                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   19475244130                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     466604190                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     468898263                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1721722349                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1742663628                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40300                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40300                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40311                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40311                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1612,11 +1618,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230958                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230958                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230980                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230980                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353742                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353764                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1631,16 +1637,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334264                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334264                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334352                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334352                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492184                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             41887500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             41893500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               337000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               344000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
@@ -1654,79 +1660,79 @@ system.iobus.reqLayer14.occupancy                9500                       # La
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               14000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25106500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25183500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            36500500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36499000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           568968673                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           569168088                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147718000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147740000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115465                       # number of replacements
-system.iocache.tags.tagsinuse               10.450543                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115471                       # number of replacements
+system.iocache.tags.tagsinuse               10.450359                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115481                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115487                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13091229344000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     5.877255                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     4.573288                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.367328                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.285830                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.653159                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13091904207000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.527977                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.922382                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.220499                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.432649                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653147                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039668                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039668                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1039767                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039767                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8815                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8852                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8826                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8863                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115479                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115519                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115490                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115530                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115479                       # number of overall misses
-system.iocache.overall_misses::total           115519                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1629675592                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1634761592                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115490                       # number of overall misses
+system.iocache.overall_misses::total           115530                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5085500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1926111562                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1931197062                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12811525081                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12811525081                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14441200673                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14446637673                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14441200673                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14446637673                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13315765026                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13315765026                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5436500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15241876588                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15247313088                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5436500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15241876588                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15247313088                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8815                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8852                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8826                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8863                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115479                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115519                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115490                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115530                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115479                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115519                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115490                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115530                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1740,53 +1746,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 184875.279864                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 184677.089019                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 218231.538862                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 217894.286585                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120111.050411                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 120111.050411                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125054.777691                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125058.541651                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125054.777691                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125058.541651                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         32070                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124838.418079                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 124838.418079                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 131975.725933                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 131977.088964                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 131975.725933                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 131977.088964                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         47583                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3415                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3458                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.390922                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    13.760266                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8815                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8852                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8826                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8863                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115479                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115519                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115490                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115530                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115479                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115519                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1188925592                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1192161592                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115490                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115530                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3235500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1484811562                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1488047062                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7471582182                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7471582182                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8660507774                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8663944774                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8660507774                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8663944774                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7975666597                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7975666597                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3436500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9460478159                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9463914659                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3436500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9460478159                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9463914659                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1800,95 +1806,95 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134875.279864                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 134677.089019                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168231.538862                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 167894.286585                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70047.834152                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70047.834152                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74996.386997                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75000.171175                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74996.386997                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75000.171175                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests       5074419                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      2524015                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3002                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74773.743690                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74773.743690                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 81915.994103                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 81917.377815                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 81915.994103                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 81917.377815                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests       5147706                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      2561464                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3010                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               54986                       # Transaction distribution
-system.membus.trans_dist::ReadResp             608005                       # Transaction distribution
+system.membus.trans_dist::ReadResp             629139                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33703                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33703                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      2202455                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           284620                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4643                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      2240512                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           283345                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4596                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1332798                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1332798                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        553019                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        696755                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1342476                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1342476                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        574153                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        702122                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6900                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6767333                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      6896995                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237693                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237693                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                7134688                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6871030                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      7000692                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237690                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237690                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                7238382                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          420                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13800                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    254577484                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    254747538                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7253696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7253696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               262001234                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2809                       # Total snoops (count)
-system.membus.snoopTraffic                     179264                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2675908                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.013150                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.113918                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    258984332                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    259154386                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7252416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7252416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               266406802                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2841                       # Total snoops (count)
+system.membus.snoopTraffic                     181312                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           2712040                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.013104                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.113719                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2640719     98.68%     98.68% # Request fanout histogram
-system.membus.snoop_fanout::1                   35189      1.32%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2676502     98.69%     98.69% # Request fanout histogram
+system.membus.snoop_fanout::1                   35538      1.31%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2675908                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           103923000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2712040                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           104012000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               32500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5620000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5608000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         14223305475                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         14521699612                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        10050154677                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        10216122095                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44814659                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44869281                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -1931,30 +1937,30 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000                       # Cumulative time (in ticks) in various power states
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    17131                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    17162                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal
index 3c0eb417b..b157c1f08 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal
@@ -31,136 +31,136 @@
 [    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
 [    0.000000] NR_IRQS:64 nr_irqs:64 0
 [    0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
-[    0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[    0.000021] Console: colour dummy device 80x25
-[    0.000024] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[    0.000025] pid_max: default: 32768 minimum: 301
-[    0.000036] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[    0.000037] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[    0.000147] hw perfevents: no hardware support available
-[    1.060066] CPU1: failed to come online
-[    2.080127] CPU2: failed to come online
+[    0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[    0.000019] Console: colour dummy device 80x25
+[    0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[    0.000022] pid_max: default: 32768 minimum: 301
+[    0.000032] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[    0.000033] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[    0.000120] hw perfevents: no hardware support available
+[    1.060065] CPU1: failed to come online
+[    2.080126] CPU2: failed to come online
 [    3.100188] CPU3: failed to come online
-[    3.100191] Brought up 1 CPUs
-[    3.100192] SMP: Total of 1 processors activated.
-[    3.100247] devtmpfs: initialized
-[    3.100685] atomic64_test: passed
-[    3.100727] regulator-dummy: no parameters
-[    3.101141] NET: Registered protocol family 16
-[    3.101262] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[    3.101271] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[    3.101633] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[    3.101638] Serial: AMBA PL011 UART driver
-[    3.101817] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[    3.101850] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[    3.102416] console [ttyAMA0] enabled
-[    3.102495] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[    3.102526] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[    3.102557] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[    3.102587] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[    3.130494] 3V3: 3300 mV 
-[    3.130534] vgaarb: loaded
-[    3.130580] SCSI subsystem initialized
-[    3.130617] libata version 3.00 loaded.
-[    3.130659] usbcore: registered new interface driver usbfs
-[    3.130676] usbcore: registered new interface driver hub
-[    3.130707] usbcore: registered new device driver usb
-[    3.130732] pps_core: LinuxPPS API ver. 1 registered
-[    3.130740] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[    3.130759] PTP clock support registered
-[    3.130873] Switched to clocksource arch_sys_counter
-[    3.131846] NET: Registered protocol family 2
-[    3.131920] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[    3.131938] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[    3.131960] TCP: Hash tables configured (established 2048 bind 2048)
-[    3.131975] TCP: reno registered
-[    3.131982] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[    3.131997] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[    3.132036] NET: Registered protocol family 1
-[    3.132085] RPC: Registered named UNIX socket transport module.
-[    3.132095] RPC: Registered udp transport module.
-[    3.132103] RPC: Registered tcp transport module.
-[    3.132111] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[    3.132123] PCI: CLS 0 bytes, default 64
-[    3.132266] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[    3.132363] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[    3.133901] fuse init (API version 7.23)
-[    3.133978] msgmni has been set to 469
-[    3.136097] io scheduler noop registered
-[    3.136147] io scheduler cfq registered (default)
-[    3.136516] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[    3.136528] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
-[    3.136540] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[    3.136552] pci_bus 0000:00: root bus resource [bus 00-ff]
-[    3.136562] pci_bus 0000:00: scanning bus
-[    3.136573] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[    3.136586] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[    3.136600] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[    3.136636] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[    3.136647] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]
-[    3.136658] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]
-[    3.136669] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]
-[    3.136679] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]
-[    3.136690] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]
-[    3.136701] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[    3.136734] pci_bus 0000:00: fixups for bus
-[    3.136742] pci_bus 0000:00: bus scan returning with max=00
-[    3.136755] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[    3.136774] pci 0000:00:00.0: fixup irq: got 33
-[    3.136782] pci 0000:00:00.0: assigning IRQ 33
-[    3.136793] pci 0000:00:01.0: fixup irq: got 34
-[    3.136801] pci 0000:00:01.0: assigning IRQ 34
-[    3.136812] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[    3.136825] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[    3.136838] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[    3.136851] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]
-[    3.136862] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]
-[    3.136874] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]
-[    3.136885] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]
-[    3.136896] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]
-[    3.137335] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[    3.137572] ata_piix 0000:00:01.0: version 2.13
-[    3.137583] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[    3.137604] ata_piix 0000:00:01.0: enabling bus mastering
-[    3.137866] scsi0 : ata_piix
-[    3.137956] scsi1 : ata_piix
-[    3.137984] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[    3.137996] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[    3.138093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[    3.138105] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[    3.138120] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[    3.138131] e1000 0000:00:00.0: enabling bus mastering
-[    3.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[    3.290909] ata1.00: 2096640 sectors, multi 0: LBA 
-[    3.290935] ata1.00: configured for UDMA/33
-[    3.290984] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
-[    3.291086] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[    3.291109] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[    3.291146] sd 0:0:0:0: [sda] Write Protect is off
-[    3.291155] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[    3.291174] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[    3.291287]  sda: sda1
-[    3.291392] sd 0:0:0:0: [sda] Attached SCSI disk
-[    3.411166] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[    3.411179] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[    3.411199] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[    3.411209] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[    3.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[    3.411240] igb: Copyright (c) 2007-2014 Intel Corporation.
-[    3.411304] usbcore: registered new interface driver usb-storage
-[    3.411354] mousedev: PS/2 mouse device common for all mice
-[    3.411491] usbcore: registered new interface driver usbhid
-[    3.411501] usbhid: USB HID core driver
-[    3.411531] TCP: cubic registered
-[    3.411538] NET: Registered protocol family 17
-[    3.411866] VFS: Mounted root (ext2 filesystem) on device 8:1.
-[    3.411900] devtmpfs: mounted
-[    3.411930] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[    3.100190] Brought up 1 CPUs
+[    3.100191] SMP: Total of 1 processors activated.
+[    3.100238] devtmpfs: initialized
+[    3.100663] atomic64_test: passed
+[    3.100701] regulator-dummy: no parameters
+[    3.101063] NET: Registered protocol family 16
+[    3.101179] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[    3.101187] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[    3.101343] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[    3.101347] Serial: AMBA PL011 UART driver
+[    3.101513] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[    3.101543] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[    3.102115] console [ttyAMA0] enabled
+[    3.102184] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[    3.102216] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[    3.102248] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[    3.102278] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[    3.130478] 3V3: 3300 mV 
+[    3.130515] vgaarb: loaded
+[    3.130558] SCSI subsystem initialized
+[    3.130595] libata version 3.00 loaded.
+[    3.130635] usbcore: registered new interface driver usbfs
+[    3.130652] usbcore: registered new interface driver hub
+[    3.130683] usbcore: registered new device driver usb
+[    3.130706] pps_core: LinuxPPS API ver. 1 registered
+[    3.130716] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[    3.130734] PTP clock support registered
+[    3.130840] Switched to clocksource arch_sys_counter
+[    3.131799] NET: Registered protocol family 2
+[    3.131866] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[    3.131883] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[    3.131902] TCP: Hash tables configured (established 2048 bind 2048)
+[    3.131917] TCP: reno registered
+[    3.131924] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[    3.131937] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[    3.131972] NET: Registered protocol family 1
+[    3.132017] RPC: Registered named UNIX socket transport module.
+[    3.132028] RPC: Registered udp transport module.
+[    3.132036] RPC: Registered tcp transport module.
+[    3.132044] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[    3.132057] PCI: CLS 0 bytes, default 64
+[    3.132193] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[    3.132284] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[    3.133790] fuse init (API version 7.23)
+[    3.133866] msgmni has been set to 469
+[    3.135967] io scheduler noop registered
+[    3.136016] io scheduler cfq registered (default)
+[    3.136336] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[    3.136349] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
+[    3.136360] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[    3.136373] pci_bus 0000:00: root bus resource [bus 00-ff]
+[    3.136383] pci_bus 0000:00: scanning bus
+[    3.136393] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[    3.136406] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[    3.136420] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[    3.136454] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[    3.136466] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]
+[    3.136477] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]
+[    3.136488] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]
+[    3.136499] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]
+[    3.136510] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]
+[    3.136521] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[    3.136554] pci_bus 0000:00: fixups for bus
+[    3.136562] pci_bus 0000:00: bus scan returning with max=00
+[    3.136574] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[    3.136592] pci 0000:00:00.0: fixup irq: got 33
+[    3.136601] pci 0000:00:00.0: assigning IRQ 33
+[    3.136611] pci 0000:00:01.0: fixup irq: got 34
+[    3.136620] pci 0000:00:01.0: assigning IRQ 34
+[    3.136631] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[    3.136644] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[    3.136657] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[    3.136670] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]
+[    3.136682] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]
+[    3.136693] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]
+[    3.136705] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]
+[    3.136716] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]
+[    3.137147] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[    3.137373] ata_piix 0000:00:01.0: version 2.13
+[    3.137384] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[    3.137403] ata_piix 0000:00:01.0: enabling bus mastering
+[    3.137653] scsi0 : ata_piix
+[    3.137740] scsi1 : ata_piix
+[    3.137768] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[    3.137780] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[    3.137872] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[    3.137884] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[    3.137899] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[    3.137911] e1000 0000:00:00.0: enabling bus mastering
+[    3.290863] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[    3.290873] ata1.00: 2096640 sectors, multi 0: LBA 
+[    3.290899] ata1.00: configured for UDMA/33
+[    3.290941] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
+[    3.291042] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[    3.291065] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[    3.291102] sd 0:0:0:0: [sda] Write Protect is off
+[    3.291112] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[    3.291131] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[    3.291239]  sda: sda1
+[    3.291342] sd 0:0:0:0: [sda] Attached SCSI disk
+[    3.411129] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[    3.411142] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[    3.411163] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[    3.411173] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[    3.411193] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[    3.411205] igb: Copyright (c) 2007-2014 Intel Corporation.
+[    3.411268] usbcore: registered new interface driver usb-storage
+[    3.411318] mousedev: PS/2 mouse device common for all mice
+[    3.411454] usbcore: registered new interface driver usbhid
+[    3.411464] usbhid: USB HID core driver
+[    3.411492] TCP: cubic registered
+[    3.411499] NET: Registered protocol family 17
+[    3.411807] VFS: Mounted root (ext2 filesystem) on device 8:1.
+[    3.411840] devtmpfs: mounted
+[    3.411860] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
 
INIT: version 2.88 booting

 Starting udev
-[    3.450359] udevd[607]: starting version 182
+[    3.450256] udevd[607]: starting version 182
 Starting Bootlog daemon: bootlogd.

-[    3.543431] random: dd urandom read with 19 bits of entropy available
+[    3.603394] random: dd urandom read with 21 bits of entropy available
 Populating dev cache

 net.ipv4.conf.default.rp_filter = 1

 net.ipv4.conf.all.rp_filter = 1

@@ -168,8 +168,8 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory
 Mon Jan 27 08:00:00 UTC 2014

 hwclock: can't open '/dev/misc/rtc': No such file or directory

 
INIT: Entering runlevel: 5


-Configuring network interfaces... [    3.671103] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
-udhcpc (v1.21.1) started

+Configuring network interfaces... udhcpc (v1.21.1) started

+[    3.741068] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
 Sending discover...

 Sending discover...

 Sending discover...

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
index 2a00a6a90..9e59e49a8 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
@@ -36,7 +36,7 @@ load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM64
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -153,7 +153,7 @@ icache_port=system.cpu0.icache.cpu_side
 [system.cpu0.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -250,7 +250,7 @@ port=system.cpu0.toL2Bus.slave[3]
 [system.cpu0.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -310,7 +310,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -382,7 +382,7 @@ port=system.cpu0.toL2Bus.slave[2]
 [system.cpu0.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -531,7 +531,7 @@ icache_port=system.cpu1.icache.cpu_side
 [system.cpu1.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -628,7 +628,7 @@ port=system.cpu1.toL2Bus.slave[3]
 [system.cpu1.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -688,7 +688,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -760,7 +760,7 @@ port=system.cpu1.toL2Bus.slave[2]
 [system.cpu1.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -907,7 +907,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -953,7 +953,7 @@ size=1024
 [system.l2c]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1051,27 +1051,27 @@ system=system
 
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -1091,6 +1091,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -1100,7 +1101,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1122,9 +1123,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -1477,7 +1478,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -1790,10 +1791,11 @@ pio=system.iobus.master[21]
 type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
-conf_table_reported=true
+conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1801,7 +1803,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -2032,6 +2034,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -2039,7 +2042,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
index c648cad5f..7bd8ed2ad 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:41:50
-gem5 executing on e108600-lin, pid 23131
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:42:59
+gem5 executing on e108600-lin, pid 17314
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
 
 Selected 64-bit ARM architecture, updating default disk image...
@@ -15,4 +15,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 47403574916500 because m5_exit instruction encountered
+Exiting @ tick 47405012960500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
index c73396a86..68cea9e8f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
@@ -1,169 +1,169 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.374315                       # Number of seconds simulated
-sim_ticks                                47374315410500                       # Number of ticks simulated
-final_tick                               47374315410500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.405013                       # Number of seconds simulated
+sim_ticks                                47405012960500                       # Number of ticks simulated
+final_tick                               47405012960500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 573964                       # Simulator instruction rate (inst/s)
-host_op_rate                                   675116                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            30496109280                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 762100                       # Number of bytes of host memory used
-host_seconds                                  1553.45                       # Real time elapsed on the host
-sim_insts                                   891626325                       # Number of instructions simulated
-sim_ops                                    1048762579                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 480061                       # Simulator instruction rate (inst/s)
+host_op_rate                                   564722                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            25874318289                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 758156                       # Number of bytes of host memory used
+host_seconds                                  1832.13                       # Real time elapsed on the host
+sim_insts                                   879531552                       # Number of instructions simulated
+sim_ops                                    1034641707                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker       107264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       103104                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3762996                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         12951880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     13484096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       112000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       117056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2426936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         10199632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     12856576                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        431488                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             56553028                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3762996                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2426936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6189932                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     74832448                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker       107584                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       111616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3269620                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         13856200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     15427200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       122176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       126272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2852024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          9626320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     10834112                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        432576                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             56765700                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3269620                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2852024                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6121644                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     74832256                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          74853032                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1676                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1611                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             99204                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            202386                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       210689                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         1750                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         1829                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             38009                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            159382                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       200884                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6742                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                924162                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1169257                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          74852840                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1681                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1744                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             91495                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            216516                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       241050                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1909                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1973                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             44651                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            150424                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       169283                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6759                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                927485                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1169254                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1171831                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2264                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2176                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               79431                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              273395                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       284629                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2364                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2471                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               51229                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              215299                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       271383                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9108                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1193749                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          79431                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          51229                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             130660                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1579600                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1171828                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2269                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2355                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               68972                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              292294                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       325434                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2577                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2664                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               60163                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              203065                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       228544                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9125                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1197462                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          68972                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          60163                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             129135                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1578573                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1580034                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1579600                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2264                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2176                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              79431                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             273829                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       284629                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2364                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2471                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              51229                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             215299                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       271383                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9108                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2773783                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        924162                       # Number of read requests accepted
-system.physmem.writeReqs                      1171831                       # Number of write requests accepted
-system.physmem.readBursts                      924162                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1171831                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 59123712                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     22656                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  74852544                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  56553028                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               74853032                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      354                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2245                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1579007                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1578573                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2269                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2355                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              68972                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             292728                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       325434                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2577                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2664                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              60163                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             203066                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       228544                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9125                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2776469                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        927485                       # Number of read requests accepted
+system.physmem.writeReqs                      1171828                       # Number of write requests accepted
+system.physmem.readBursts                      927485                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1171828                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 59337472                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21568                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  74850880                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  56765700                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               74852840                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      337                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2262                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               54791                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               60963                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               51680                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               61600                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               56399                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               67623                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               62592                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               58195                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               51047                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               95684                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              47816                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              53141                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              48535                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              54663                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              49130                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              49949                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               71660                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               78743                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               71851                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               78616                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               73485                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               81529                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               75635                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               74455                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               70456                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               72917                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              67611                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              70918                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              67621                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              71486                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              70570                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              72018                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               53188                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               58555                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               49548                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               58849                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               61060                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               64213                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               58593                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               62574                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               53530                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               96457                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              50033                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              57571                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              47029                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              51615                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              49510                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              54823                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               69378                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               74382                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               69427                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               75087                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               76532                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               78990                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               75385                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               77589                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               70916                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               76207                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              70858                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              75862                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              66596                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              70423                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              68869                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              73044                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          85                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47374312061000                       # Total gap between requests
+system.physmem.numWrRetry                         516                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47405009605000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  880937                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  884260                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1169257                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    656925                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     77551                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     38628                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     33370                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     28745                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     25204                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     22090                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     18063                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     15811                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2611                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1283                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      912                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      744                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      565                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      402                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      317                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      250                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      187                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       88                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       59                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1169254                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    645919                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     88942                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     42222                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     33520                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     28634                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     25074                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     21962                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     18312                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     15502                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2962                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1110                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      816                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      608                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      446                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      314                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      249                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      195                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      169                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      100                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       79                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -189,173 +189,184 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    29578                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    37673                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    49096                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    55472                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    61395                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    64054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    66659                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    68456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    71033                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    71567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    75072                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    77359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    72847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    72784                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    77929                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    71715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    66943                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    64345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2561                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1329                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      960                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      633                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      524                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      522                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      453                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      332                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      426                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      313                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      299                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      349                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      308                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      252                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      259                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       927168                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      144.500035                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      98.409552                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     191.008164                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         615708     66.41%     66.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       189300     20.42%     86.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        44500      4.80%     91.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20695      2.23%     93.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        14869      1.60%     95.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         9173      0.99%     96.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         6380      0.69%     97.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5518      0.60%     97.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        21025      2.27%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         927168                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         60983                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        15.148533                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      130.608088                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          60979     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    28620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    36458                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    48218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    54653                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    60726                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    63711                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    65994                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    67665                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    70176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    70363                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    73600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    75174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    72029                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    70698                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    71278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    75021                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    68576                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    65669                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3787                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2027                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1477                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      975                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1013                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      865                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      814                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      756                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      763                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      695                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      747                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      648                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      743                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      716                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      785                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      937                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      852                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      551                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      928                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                     1380                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                     1236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      535                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                     1170                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       929017                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      144.440810                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      98.331936                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     191.352121                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         617371     66.45%     66.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       189527     20.40%     86.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        44674      4.81%     91.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20356      2.19%     93.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        14838      1.60%     95.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         9142      0.98%     96.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         6196      0.67%     97.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5371      0.58%     97.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        21542      2.32%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         929017                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         60832                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        15.240992                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      130.606668                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          60830    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60983                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         60983                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.178640                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.436589                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.785486                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           49393     80.99%     80.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            4571      7.50%     88.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            2800      4.59%     93.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            1776      2.91%     95.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35            1006      1.65%     97.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             308      0.51%     98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             149      0.24%     98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             125      0.20%     98.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              64      0.10%     98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              38      0.06%     98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              29      0.05%     98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              41      0.07%     98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             435      0.71%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              54      0.09%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              52      0.09%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              40      0.07%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              33      0.05%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               5      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               5      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             5      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            14      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             3      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             4      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             9      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           60832                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         60832                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.225819                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.418138                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        8.471341                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           49295     81.03%     81.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            4521      7.43%     88.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27            2878      4.73%     93.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31            1749      2.88%     96.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35            1023      1.68%     97.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             226      0.37%     98.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              91      0.15%     98.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             113      0.19%     98.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              47      0.08%     98.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              23      0.04%     98.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              10      0.02%     98.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              42      0.07%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             494      0.81%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              82      0.13%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              51      0.08%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              57      0.09%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              26      0.04%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.00%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               4      0.01%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.00%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             5      0.01%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             4      0.01%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            14      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.00%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.00%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            21      0.03%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             3      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143            13      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             4      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             3      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             2      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::212-215             1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::240-243             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60983                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    30413749694                       # Total ticks spent queuing
-system.physmem.totMemAccLat               47735149694                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4619040000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       32922.15                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           60832                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    46218732203                       # Total ticks spent queuing
+system.physmem.totMemAccLat               63602757203                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4635740000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       49850.44                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  51672.15                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  68600.44                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.25                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.58                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.19                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.20                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.58                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.27                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     683627                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    482581                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.00                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  41.26                       # Row buffer hit rate for writes
-system.physmem.avgGap                     22602323.61                       # Average gap between requests
-system.physmem.pageHitRate                      55.71                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 3700302480                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2019014250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3695975400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3926705040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3094259578800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1192499073090                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27378533808750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31678634457810                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.688048                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45546210437205                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1581932300000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    246167130795                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3308936400                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1805471250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3509181000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3651784560                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3094259578800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1178425765395                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27390878815500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31675839532905                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.629051                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45566794873385                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1581932300000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    225582219115                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.physmem.avgRdQLen                         1.15                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.09                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     685692                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    481982                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   73.96                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.21                       # Row buffer hit rate for writes
+system.physmem.avgGap                     22581201.38                       # Average gap between requests
+system.physmem.pageHitRate                      55.69                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3446827860                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1832028660                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3331381200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3115139400                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           41510941680.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            46501533090                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             2234866560                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       80625696300                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       57761558880                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       11279719224960                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             11520096687780                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              243.014314                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           47297174723637                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     3911587994                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     17636282000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   46969945639000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 150420602883                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     86288423369                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 176810425254                       # Time in different power states
+system.physmem_1.actEnergy                 3186367800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1693590855                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3288455520                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               2989885500                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           39461117280.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            47361781080                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             2153404320                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       72224847060                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       55366694400                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       11285008491285                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             11512750460370                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              242.859346                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           47295506898407                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     3731843770                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     16766470000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   46992934432500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 144184093324                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     89007700573                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 158388420333                       # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
@@ -382,17 +393,17 @@ system.realview.nvmem.bw_total::cpu0.data            1                       # T
 system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
+system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -422,73 +433,71 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                   101108                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               101108                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         9051                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        76906                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore           14                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       101094                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         101094    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       101094                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        85971                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 24170.842493                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 22339.898543                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 14600.032387                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767        76182     88.61%     88.61% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535         8727     10.15%     98.76% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-98303          200      0.23%     99.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-131071          718      0.84%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839           29      0.03%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607           15      0.02%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-229375           34      0.04%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::229376-262143           15      0.02%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-294911           12      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::294912-327679           19      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-360447           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::360448-393215            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        85971                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples   -250064880                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.334382                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.471774                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0     -166447796     66.56%     66.56% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1      -83617084     33.44%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total   -250064880                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        76906     89.47%     89.47% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M         9051     10.53%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        85957                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       101108                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                   110745                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               110745                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10295                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        84545                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore           22                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       110723                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean     0.234820                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev    78.136585                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047       110722    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       110723                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        94862                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 23879.314162                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 22054.085361                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 16759.177694                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535        93763     98.84%     98.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          840      0.89%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          113      0.12%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           60      0.06%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           52      0.05%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           15      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751            1      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359           13      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        94862                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  -2682325288                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     2.121047                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     3007013124   -112.10%   -112.10% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    -5689338412    212.10%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  -2682325288                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        84546     89.14%     89.14% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        10295     10.86%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        94841                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       110745                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       101108                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        85957                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       110745                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        94841                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        85957                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       187065                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        94841                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       205586                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    84046306                       # DTB read hits
-system.cpu0.dtb.read_misses                     73432                       # DTB read misses
-system.cpu0.dtb.write_hits                   77237834                       # DTB write hits
-system.cpu0.dtb.write_misses                    27676                       # DTB write misses
+system.cpu0.dtb.read_hits                    86849149                       # DTB read hits
+system.cpu0.dtb.read_misses                     83538                       # DTB read misses
+system.cpu0.dtb.write_hits                   78785461                       # DTB write hits
+system.cpu0.dtb.write_misses                    27207                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              41711                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   35922                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              41059                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   37555                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4635                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  4746                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9711                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                84119738                       # DTB read accesses
-system.cpu0.dtb.write_accesses               77265510                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     9443                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                86932687                       # DTB read accesses
+system.cpu0.dtb.write_accesses               78812668                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        161284140                       # DTB hits
-system.cpu0.dtb.misses                         101108                       # DTB misses
-system.cpu0.dtb.accesses                    161385248                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                        165634610                       # DTB hits
+system.cpu0.dtb.misses                         110745                       # DTB misses
+system.cpu0.dtb.accesses                    165745355                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -518,763 +527,759 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    58460                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                58460                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          540                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        52669                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        58460                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          58460    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        58460                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        53209                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 26190.982728                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 24044.890366                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 17871.734437                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767        47169     88.65%     88.65% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535         4943      9.29%     97.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303           65      0.12%     98.06% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071          859      1.61%     99.67% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839           39      0.07%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607           17      0.03%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375           47      0.09%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143           13      0.02%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911           25      0.05%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679           20      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        53209                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples   -282313796                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     -282313796    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total   -282313796                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        52669     98.99%     98.99% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          540      1.01%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        53209                       # Table walker page sizes translated
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                    57780                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                57780                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          572                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        51544                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        57780                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          57780    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        57780                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        52116                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 25803.102694                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23425.328726                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 22386.426518                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        51056     97.97%     97.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071          692      1.33%     99.29% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          219      0.42%     99.71% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           60      0.12%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           50      0.10%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           14      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751            4      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359           14      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::655360-720895            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        52116                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples     14842204                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0       14842204    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total     14842204                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        51544     98.90%     98.90% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          572      1.10%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        52116                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        58460                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        58460                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        57780                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        57780                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        53209                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        53209                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       111669                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   449335815                       # ITB inst hits
-system.cpu0.itb.inst_misses                     58460                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52116                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52116                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       109896                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   463942995                       # ITB inst hits
+system.cpu0.itb.inst_misses                     57780                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              41711                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   24946                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              41059                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   26477                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               449394275                       # ITB inst accesses
-system.cpu0.itb.hits                        449335815                       # DTB hits
-system.cpu0.itb.misses                          58460                       # DTB misses
-system.cpu0.itb.accesses                    449394275                       # DTB accesses
-system.cpu0.numPwrStateTransitions               8624                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         4312                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    10857440365.954313                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   156382311444.961365                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         3059     70.94%     70.94% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         1229     28.50%     99.44% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            2      0.05%     99.49% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            2      0.05%     99.54% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            2      0.05%     99.58% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11            1      0.02%     99.61% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.02%     99.63% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11            1      0.02%     99.65% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11            1      0.02%     99.68% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows           14      0.32%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses               464000775                       # ITB inst accesses
+system.cpu0.itb.hits                        463942995                       # DTB hits
+system.cpu0.itb.misses                          57780                       # DTB misses
+system.cpu0.itb.accesses                    464000775                       # DTB accesses
+system.cpu0.numPwrStateTransitions               8984                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         4492                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    10426010818.709705                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   169261679723.888153                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         3260     72.57%     72.57% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10         1205     26.83%     99.40% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11            8      0.18%     99.58% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.02%     99.60% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            2      0.04%     99.64% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            2      0.04%     99.69% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            1      0.02%     99.71% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.02%     99.73% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows           12      0.27%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 7470353528320                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           4312                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   557032552505                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 46817282857995                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                     94748630821                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 7033293863000                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           4492                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   571372362856                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 46833640597644                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                     94810025915                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    4312                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  449083110                       # Number of instructions committed
-system.cpu0.committedOps                    528384419                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            485390643                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                507449                       # Number of float alu accesses
-system.cpu0.num_func_calls                   26866500                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     68160489                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   485390643                       # number of integer instructions
-system.cpu0.num_fp_insts                       507449                       # number of float instructions
-system.cpu0.num_int_register_reads          703891240                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         384865941                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              816779                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             435492                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           117650799                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          117386896                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    161276211                       # number of memory refs
-system.cpu0.num_load_insts                   84042257                       # Number of load instructions
-system.cpu0.num_store_insts                  77233954                       # Number of store instructions
-system.cpu0.num_idle_cycles              93634565715.988022                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1114065105.011976                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.011758                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.988242                       # Percentage of idle cycles
-system.cpu0.Branches                        100200450                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                366086093     69.25%     69.25% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1185979      0.22%     69.47% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    59083      0.01%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                 21      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             72839      0.01%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::MemRead                84042257     15.90%     85.39% # Class of executed instruction
-system.cpu0.op_class::MemWrite               77233954     14.61%    100.00% # Class of executed instruction
+system.cpu0.kern.inst.quiesce                    4492                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  463690677                       # Number of instructions committed
+system.cpu0.committedOps                    544305781                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            499985272                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                430429                       # Number of float alu accesses
+system.cpu0.num_func_calls                   27825312                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     70353837                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   499985272                       # number of integer instructions
+system.cpu0.num_fp_insts                       430429                       # number of float instructions
+system.cpu0.num_int_register_reads          725660016                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         396645033                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              713342                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             322808                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           121489824                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          121106505                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    165624912                       # number of memory refs
+system.cpu0.num_load_insts                   86844124                       # Number of load instructions
+system.cpu0.num_store_insts                  78780788                       # Number of store instructions
+system.cpu0.num_idle_cycles              93667281189.358337                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1142744725.641658                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.012053                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.987947                       # Percentage of idle cycles
+system.cpu0.Branches                        103560532                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                377679680     69.35%     69.35% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1190205      0.22%     69.57% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    61578      0.01%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             44848      0.01%     69.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.59% # Class of executed instruction
+system.cpu0.op_class::MemRead                86844124     15.95%     85.53% # Class of executed instruction
+system.cpu0.op_class::MemWrite               78780788     14.47%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 528680248                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          5566798                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          502.671926                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          155470196                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5567308                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.925560                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       4031081000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   502.671926                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.981781                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.981781                       # Average percentage of cache occupancy
+system.cpu0.op_class::total                 544601223                       # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements          5731745                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          479.859189                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          159669170                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5732255                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.854513                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       4328406000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   479.859189                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.937225                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.937225                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          419                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           31                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          452                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        328131694                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       328131694                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     78275725                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       78275725                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     72837974                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      72837974                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       200143                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       200143                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       232092                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       232092                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1764306                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1764306                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1721538                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1721538                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    151345791                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       151345791                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    151545934                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      151545934                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2974115                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      2974115                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1412109                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1412109                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       649854                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       649854                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       801670                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       801670                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       161158                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       161158                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       202775                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       202775                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      5187894                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       5187894                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5837748                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      5837748                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  44497648000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  44497648000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  28844482000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  28844482000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  25694293000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  25694293000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2462602000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2462602000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4821620000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4821620000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2416000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2416000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  99036423000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  99036423000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  99036423000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  99036423000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     81249840                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     81249840                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     74250083                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     74250083                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       849997                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       849997                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1033762                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1033762                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1925464                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      1925464                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1924313                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1924313                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    156533685                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    156533685                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    157383682                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    157383682                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036605                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.036605                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.019018                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.019018                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.764537                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.764537                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.775488                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.775488                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.083698                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.083698                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.105375                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.105375                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.033142                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.033142                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.037092                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.037092                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14961.643380                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14961.643380                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20426.526564                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 20426.526564                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32050.959871                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32050.959871                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15280.668661                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15280.668661                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23778.177783                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23778.177783                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses        337018109                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       337018109                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     80850678                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       80850678                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     74290365                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      74290365                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       206988                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       206988                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       237888                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       237888                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1848102                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1848102                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1813975                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1813975                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    155378931                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       155378931                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    155585919                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      155585919                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3109712                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3109712                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1421405                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1421405                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       649654                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       649654                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       796576                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       796576                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       167654                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       167654                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       200528                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       200528                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      5327693                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       5327693                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      5977347                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      5977347                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  48841831500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  48841831500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  30112535000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  30112535000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  25700725500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  25700725500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2575322000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2575322000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4758884500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4758884500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2246000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2246000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 104655092000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 104655092000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 104655092000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 104655092000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     83960390                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     83960390                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     75711770                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     75711770                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       856642                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       856642                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1034464                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1034464                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2015756                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2015756                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2014503                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2014503                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    160706624                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    160706624                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    161563266                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    161563266                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.037038                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.037038                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018774                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.018774                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.758373                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.758373                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.770037                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.770037                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.083172                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.083172                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.099542                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.099542                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.033152                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.033152                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.036997                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.036997                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15706.223438                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15706.223438                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21185.049300                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 21185.049300                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32263.996781                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32263.996781                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15360.933828                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15360.933828                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23731.770626                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23731.770626                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19089.908738                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19089.908738                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16964.833528                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16964.833528                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19643.604089                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19643.604089                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17508.619125                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 17508.619125                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      5566798                       # number of writebacks
-system.cpu0.dcache.writebacks::total          5566798                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        29633                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        29633                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21518                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21518                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        45711                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        45711                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        51151                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        51151                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        51151                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        51151                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2944482                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2944482                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1390591                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1390591                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       648168                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       648168                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       801670                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       801670                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       115447                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       115447                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       202775                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       202775                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      5136743                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      5136743                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5784911                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5784911                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        21025                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        21025                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        22388                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        22388                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        43413                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        43413                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  40085054500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  40085054500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  26946583500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  26946583500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14957704500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14957704500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  24892623000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24892623000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1575244000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1575244000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4618898000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4618898000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2363000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2363000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  91924261000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  91924261000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 106881965500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 106881965500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3989550000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3989550000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3989550000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3989550000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036240                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036240                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018728                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018728                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.762553                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.762553                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.775488                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.775488                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059958                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059958                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.105375                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.105375                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.032816                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.032816                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.036757                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.036757                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13613.618456                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13613.618456                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19377.792248                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19377.792248                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23076.894416                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23076.894416                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31050.959871                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31050.959871                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13644.737412                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13644.737412                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22778.439157                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22778.439157                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      5731745                       # number of writebacks
+system.cpu0.dcache.writebacks::total          5731745                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        26385                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        26385                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21245                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        21245                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        44162                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        44162                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        47630                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        47630                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        47630                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        47630                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3083327                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3083327                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1400160                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1400160                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       648080                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       648080                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       796576                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       796576                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       123492                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       123492                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       200528                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       200528                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      5280063                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      5280063                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5928143                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5928143                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16381                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        16381                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        17694                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        17694                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34075                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34075                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  44323294000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  44323294000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  28148510000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  28148510000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14944693500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14944693500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  24904149500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24904149500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1681387500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1681387500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4558410500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4558410500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2192000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2192000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  97375953500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  97375953500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112320647000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 112320647000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3040589500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3040589500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3040589500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3040589500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036724                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036724                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018493                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018493                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.756535                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.756535                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.770037                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.770037                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061263                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.061263                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.099542                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.099542                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.032855                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.032855                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.036692                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.036692                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14375.151906                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14375.151906                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20103.780996                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20103.780996                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23059.951703                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23059.951703                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31263.996781                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31263.996781                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13615.355651                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13615.355651                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22732.039915                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22732.039915                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17895.437050                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17895.437050                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18475.991333                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18475.991333                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189752.675386                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189752.675386                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91897.588280                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91897.588280                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          5174135                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.907744                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          444161163                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          5174647                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            85.834099                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      30089682000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.907744                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999820                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999820                       # Average percentage of cache occupancy
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18442.195387                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18442.195387                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.020509                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.020509                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185616.842684                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185616.842684                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89232.267058                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89232.267058                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          4959559                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.903947                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          458982923                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          4960071                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            92.535555                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      30768955000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.903947                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999812                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999812                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          265                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          186                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          421                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        903846282                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       903846282                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    444161163                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      444161163                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    444161163                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       444161163                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    444161163                       # number of overall hits
-system.cpu0.icache.overall_hits::total      444161163                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5174652                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      5174652                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5174652                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       5174652                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5174652                       # number of overall misses
-system.cpu0.icache.overall_misses::total      5174652                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  55704586500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  55704586500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  55704586500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  55704586500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  55704586500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  55704586500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    449335815                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    449335815                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    449335815                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    449335815                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    449335815                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    449335815                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011516                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.011516                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011516                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.011516                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011516                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.011516                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10764.895205                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10764.895205                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10764.895205                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10764.895205                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10764.895205                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10764.895205                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        932846061                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       932846061                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst    458982923                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      458982923                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    458982923                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       458982923                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    458982923                       # number of overall hits
+system.cpu0.icache.overall_hits::total      458982923                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      4960072                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      4960072                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      4960072                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       4960072                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      4960072                       # number of overall misses
+system.cpu0.icache.overall_misses::total      4960072                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  54306348500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  54306348500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  54306348500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  54306348500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  54306348500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  54306348500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    463942995                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    463942995                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    463942995                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    463942995                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    463942995                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    463942995                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010691                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.010691                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010691                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.010691                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010691                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.010691                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10948.701652                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10948.701652                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10948.701652                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10948.701652                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10948.701652                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10948.701652                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      5174135                       # number of writebacks
-system.cpu0.icache.writebacks::total          5174135                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5174652                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      5174652                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      5174652                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      5174652                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      5174652                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      5174652                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      4959559                       # number of writebacks
+system.cpu0.icache.writebacks::total          4959559                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4960072                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      4960072                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      4960072                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      4960072                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      4960072                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      4960072                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  53117260500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  53117260500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  53117260500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  53117260500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  53117260500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  53117260500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3819470000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3819470000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3819470000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   3819470000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011516                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011516                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011516                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.011516                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011516                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.011516                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10264.895205                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10264.895205                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10264.895205                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10264.895205                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10264.895205                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10264.895205                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7568346                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7568354                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit            7                       # number of redundant prefetches already in prefetch queue
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  51826313000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  51826313000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  51826313000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  51826313000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  51826313000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  51826313000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4116534000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4116534000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4116534000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   4116534000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010691                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010691                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010691                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.010691                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010691                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.010691                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10448.701753                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10448.701753                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10448.701753                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10448.701753                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10448.701753                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10448.701753                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7732053                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7732077                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit           21                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       981182                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements         2342884                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       15723.839714                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           9135802                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2358598                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            3.873404                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle      5100393500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15407.459260                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    38.158261                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    27.135006                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   251.087187                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.940397                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002329                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001656                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.015325                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.959707                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022          345                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           72                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15297                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           19                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          130                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          167                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           29                       # Occupied blocks per task id
+system.cpu0.l2cache.prefetcher.pfSpanPage      1019171                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.tags.replacements         2286879                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15893.622807                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           9162734                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2302009                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            3.980321                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle      5406430500                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15603.896064                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    29.949034                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    16.856945                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   242.920764                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.952386                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.001828                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001029                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.014827                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.970070                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          306                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           67                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14757                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          100                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          139                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           67                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           18                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           53                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1333                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5696                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7896                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          254                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.021057                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004395                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.933655                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       370311903                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      370311903                       # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       225709                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       148168                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        373877                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks      3696575                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      3696575                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      7043197                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      7043197                       # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       878685                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       878685                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4695575                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      4695575                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2752703                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      2752703                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       216682                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       216682                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       225709                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       148168                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      4695575                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3631388                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        8700840                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       225709                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       148168                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      4695575                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3631388                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       8700840                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        18676                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        10607                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        29283                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       251664                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       251664                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       202763                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       202763                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           12                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total           12                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       278535                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       278535                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       479077                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       479077                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       955394                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       955394                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       582714                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       582714                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        18676                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker        10607                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       479077                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1233929                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1742289                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        18676                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker        10607                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       479077                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1233929                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1742289                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    564732000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    371950000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total    936682000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    916815500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    916815500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    321936500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    321936500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2282499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2282499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  12626438998                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  12626438998                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  17151939500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  17151939500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  33121351500                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  33121351500                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    399249500                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total    399249500                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    564732000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    371950000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  17151939500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  45747790498                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  63836411998                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    564732000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    371950000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  17151939500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  45747790498                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  63836411998                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       244385                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       158775                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       403160                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3696575                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total      3696575                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      7043197                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      7043197                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       251664                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       251664                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       202763                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       202763                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           12                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           12                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1157220                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1157220                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5174652                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      5174652                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3708097                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      3708097                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       799396                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       799396                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       244385                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       158775                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      5174652                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      4865317                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     10443129                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       244385                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       158775                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      5174652                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      4865317                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     10443129                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.076420                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.066805                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.072634                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           42                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4608                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         8403                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1616                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.018677                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004089                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.900696                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       368793343                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      368793343                       # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       252482                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       146217                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        398699                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks      3794669                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total      3794669                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      6895627                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      6895627                       # number of WritebackClean hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       932984                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       932984                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4503327                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      4503327                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2919116                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      2919116                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       217183                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       217183                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       252482                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       146217                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      4503327                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      3852100                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        8754126                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       252482                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       146217                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      4503327                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3852100                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       8754126                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        17757                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8990                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        26747                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       236502                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       236502                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       200518                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       200518                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           10                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total           10                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       248602                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       248602                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       456745                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       456745                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       935783                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       935783                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       577322                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       577322                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        17757                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8990                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       456745                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1184385                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      1667877                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        17757                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8990                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       456745                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1184385                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      1667877                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    557104000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    362043000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total    919147000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    930109500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    930109500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    320714500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    320714500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2109497                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2109497                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  13818048499                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  13818048499                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  17338170000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  17338170000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  36151090000                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  36151090000                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    305279500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total    305279500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    557104000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    362043000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  17338170000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  49969138499                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  68226455499                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    557104000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    362043000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  17338170000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  49969138499                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  68226455499                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       270239                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       155207                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       425446                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3794669                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total      3794669                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      6895627                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      6895627                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       236502                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       236502                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       200518                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       200518                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           10                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           10                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1181586                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1181586                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      4960072                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      4960072                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3854899                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      3854899                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       794505                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       794505                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       270239                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       155207                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      4960072                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      5036485                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     10422003                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       270239                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       155207                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      4960072                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      5036485                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     10422003                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.065709                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.057923                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.062868                       # miss rate for ReadReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.240693                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.240693                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.092581                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.092581                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.257651                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.257651                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.728943                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.728943                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.076420                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.066805                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.092581                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.253617                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.166836                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.076420                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.066805                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.092581                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.253617                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.166836                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30238.380810                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35066.465542                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31987.228085                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3643.014098                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3643.014098                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1587.747765                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1587.747765                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 190208.250000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 190208.250000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45331.606434                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45331.606434                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35802.051653                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35802.051653                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34667.740744                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34667.740744                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   685.155153                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   685.155153                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30238.380810                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35066.465542                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35802.051653                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37074.896933                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 36639.393349                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30238.380810                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35066.465542                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35802.051653                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37074.896933                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 36639.393349                       # average overall miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.210397                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.210397                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.092084                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.092084                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.242752                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.242752                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.726644                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.726644                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.065709                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.057923                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.092084                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.235161                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.160034                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.065709                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.057923                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.092084                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.235161                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.160034                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31373.768091                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 40271.746385                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34364.489475                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3932.776467                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3932.776467                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1599.429976                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1599.429976                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 210949.700000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 210949.700000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55583.014211                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55583.014211                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37960.284185                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37960.284185                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38631.915733                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38631.915733                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   528.785496                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   528.785496                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31373.768091                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 40271.746385                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37960.284185                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42189.945414                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 40906.167241                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31373.768091                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 40271.746385                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37960.284185                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42189.945414                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 40906.167241                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches           41508                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks      1560695                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1560695                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5412                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         5412                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          417                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          417                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5829                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         5829                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5829                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         5829                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        18676                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        10607                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        29283                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       726457                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       726457                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       251664                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       251664                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       202763                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       202763                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           12                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           12                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       273123                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       273123                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       479077                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       479077                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       954977                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       954977                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       582714                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       582714                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        18676                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        10607                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       479077                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1228100                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      1736460                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        18676                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        10607                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       479077                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1228100                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       726457                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2462917                       # number of overall MSHR misses
+system.cpu0.l2cache.unused_prefetches           38115                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks      1518116                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1518116                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         6419                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         6419                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          459                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          459                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6878                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         6878                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6878                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         6878                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        17757                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8990                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        26747                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       749864                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       749864                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       236502                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       236502                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       200518                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       200518                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           10                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           10                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       242183                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       242183                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       456745                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       456745                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       935324                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       935324                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       577322                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       577322                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        17757                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8990                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       456745                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1177507                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total      1660999                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        17757                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8990                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       456745                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1177507                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       749864                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total      2410863                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        21025                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        64150                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        22388                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        22388                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        16381                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        59506                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        17694                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        17694                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        43413                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        86538                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    452676000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    308308000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    760984000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  31463015041                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  31463015041                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4662148500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4662148500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3097020500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3097020500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1964499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1964499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10454677998                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10454677998                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  14277477500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  14277477500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  27353907000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  27353907000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  18732640000                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  18732640000                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    452676000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    308308000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  14277477500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  37808584998                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  52847046498                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    452676000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    308308000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  14277477500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  37808584998                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  31463015041                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  84310061539                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3496032500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3820807000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7316839500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3496032500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   3820807000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7316839500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.076420                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.066805                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.072634                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        34075                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        77200                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    450562000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    308103000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    758665000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  37032584946                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  37032584946                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4392780000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4392780000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3053423000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3053423000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1785497                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1785497                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  11646133999                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  11646133999                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  14597700000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  14597700000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  30480683500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  30480683500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  18786696000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  18786696000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    450562000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    308103000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  14597700000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  42126817499                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  57483182499                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    450562000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    308103000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  14597700000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  42126817499                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  37032584946                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  94515767445                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3793096500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2909184500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6702281000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3793096500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   2909184500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6702281000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.065709                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.057923                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.062868                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
@@ -1283,123 +1288,124 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.236016                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.236016                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.092581                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.092581                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.257538                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.257538                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.728943                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.728943                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.076420                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.066805                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.092581                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.252419                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.166278                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.076420                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.066805                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.092581                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.252419                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.204964                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.204964                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.092084                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.092084                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.242633                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.242633                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.726644                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.726644                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.065709                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.057923                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.092084                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.233795                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.159374                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.065709                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.057923                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.092084                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.233795                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.235841                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25987.228085                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43310.223511                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18525.289672                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18525.289672                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15274.090934                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15274.090934                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 163708.250000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 163708.250000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38278.277545                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38278.277545                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29802.051653                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29802.051653                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28643.524399                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28643.524399                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32147.228314                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32147.228314                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29802.051653                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30786.242975                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30433.782810                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29802.051653                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30786.242975                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34231.791627                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181726.848989                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114058.293063                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 88010.665008                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 84550.596270                       # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests     22270826                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11431607                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1159                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       634641                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       634635                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq        532548                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      9516927                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        22389                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        22388                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      5262772                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      7044356                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      1133181                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       892107                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       438346                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       371201                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       524392                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           61                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          102                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1190804                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1167926                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5174652                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4606140                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       845268                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       799396                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     15609689                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18074319                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       333482                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       538074                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         34555564                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    662494868                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    674962485                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1270200                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1955080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1340682633                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    5171785                       # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic            107950516                       # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples     16772894                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.051983                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.221994                       # Request fanout histogram
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.231324                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28364.489475                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49385.735208                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18573.965548                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18573.965548                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15227.675321                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15227.675321                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178549.700000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178549.700000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48088.156473                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48088.156473                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31960.284185                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31960.284185                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32588.368843                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32588.368843                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32541.105310                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32541.105310                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31960.284185                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35776.277762                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34607.596091                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31960.284185                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35776.277762                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39204.122111                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177595.049142                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112632.020300                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85375.920763                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86817.111399                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests     22159208                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11368269                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1008                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       619514                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       619512                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            2                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq        553426                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      9465318                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        17695                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        17694                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5316723                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      6896635                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      1098455                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       916448                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       433150                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       369627                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       506111                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           59                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          103                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1214944                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1192020                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      4960072                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4756139                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       842201                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       794505                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     14965952                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18512478                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       327835                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       591529                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         34397794                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    635028820                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    696134983                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1241656                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2161912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1334567371                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    5130075                       # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic            104832276                       # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples     16684270                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.051566                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.221149                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          15900995     94.80%     94.80% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            871893      5.20%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2                 6      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          15823936     94.84%     94.84% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            860332      5.16%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2                 2      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      16772894                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   22046960997                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      16684270                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   21945410994                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    203834159                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    195855793                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   7805103000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   7483231500                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   7957435977                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   8196031021                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    174707000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    172628000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    293689000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    321290000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1429,75 +1435,71 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                   113512                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               113512                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10824                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        86665                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore           27                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       113485                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.290787                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev    77.918264                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-2047       113483    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::6144-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       113485                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        97516                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23769.576275                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 22071.904189                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 14608.572728                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767        88342     90.59%     90.59% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535         8042      8.25%     98.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303          147      0.15%     98.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071          810      0.83%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839           21      0.02%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607           18      0.02%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375           45      0.05%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143           20      0.02%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911           17      0.02%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679           36      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-425983            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::425984-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        97516                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples     14762172                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean   194.841712                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    -2861524688 -19384.17% -19384.17% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1     2876286860  19484.17%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total     14762172                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        86666     88.90%     88.90% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        10824     11.10%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        97490                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       113512                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                    99152                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong                99152                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         8586                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        75770                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            4                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        99148                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.080687                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev    25.406685                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-511        99147    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::7680-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        99148                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        84360                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 24513.021574                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 22367.425597                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 18734.439703                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535        83116     98.53%     98.53% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071          940      1.11%     99.64% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          161      0.19%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           58      0.07%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           36      0.04%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           23      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751            6      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359           16      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        84360                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples    407519048                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     2.490877                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     -607560648   -149.09%   -149.09% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1     1015079696    249.09%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total    407519048                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        75770     89.82%     89.82% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         8586     10.18%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        84356                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        99152                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       113512                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        97490                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        99152                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        84356                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        97490                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       211002                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        84356                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       183508                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    83873503                       # DTB read hits
-system.cpu1.dtb.read_misses                     85876                       # DTB read misses
-system.cpu1.dtb.write_hits                   75393075                       # DTB write hits
-system.cpu1.dtb.write_misses                    27636                       # DTB write misses
+system.cpu1.dtb.read_hits                    78885011                       # DTB read hits
+system.cpu1.dtb.read_misses                     72039                       # DTB read misses
+system.cpu1.dtb.write_hits                   71761800                       # DTB write hits
+system.cpu1.dtb.write_misses                    27113                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              41711                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   39012                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              41059                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   36637                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  3907                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  3802                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    10199                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                83959379                       # DTB read accesses
-system.cpu1.dtb.write_accesses               75420711                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    10123                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                78957050                       # DTB read accesses
+system.cpu1.dtb.write_accesses               71788913                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        159266578                       # DTB hits
-system.cpu1.dtb.misses                         113512                       # DTB misses
-system.cpu1.dtb.accesses                    159380090                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                        150646811                       # DTB hits
+system.cpu1.dtb.misses                          99152                       # DTB misses
+system.cpu1.dtb.accesses                    150745963                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1527,759 +1529,759 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                    59776                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                59776                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          674                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        53293                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        59776                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          59776    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        59776                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        53967                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 25622.306224                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23504.254601                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18586.945639                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        52820     97.87%     97.87% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071          977      1.81%     99.68% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607           34      0.06%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           58      0.11%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           61      0.11%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           10      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        53967                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  -1314622148                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    -1314622148    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  -1314622148                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        53293     98.75%     98.75% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          674      1.25%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        53967                       # Table walker page sizes translated
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                    58316                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                58316                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          626                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        52495                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        58316                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          58316    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        58316                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        53121                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 27183.693831                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24219.790403                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 26514.333195                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        51734     97.39%     97.39% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071          949      1.79%     99.18% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          242      0.46%     99.63% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           79      0.15%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           53      0.10%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           14      0.03%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            9      0.02%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            5      0.01%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359           33      0.06%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::655360-720895            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        53121                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   -615394148                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     -615394148    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   -615394148                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        52495     98.82%     98.82% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          626      1.18%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        53121                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        59776                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        59776                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        58316                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        58316                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        53967                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        53967                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       113743                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   442849873                       # ITB inst hits
-system.cpu1.itb.inst_misses                     59776                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        53121                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        53121                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       111437                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   416140593                       # ITB inst hits
+system.cpu1.itb.inst_misses                     58316                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              41711                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   27503                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              41059                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   25699                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               442909649                       # ITB inst accesses
-system.cpu1.itb.hits                        442849873                       # DTB hits
-system.cpu1.itb.misses                          59776                       # DTB misses
-system.cpu1.itb.accesses                    442909649                       # DTB accesses
-system.cpu1.numPwrStateTransitions              28574                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples        14287                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    3279405691.982362                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   123453533761.994095                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         4140     28.98%     28.98% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10        10126     70.88%     99.85% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            7      0.05%     99.90% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.91% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.92% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.92% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11            1      0.01%     99.93% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows           10      0.07%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses               416198909                       # ITB inst accesses
+system.cpu1.itb.hits                        416140593                       # DTB hits
+system.cpu1.itb.misses                          58316                       # DTB misses
+system.cpu1.itb.accesses                    416198909                       # DTB accesses
+system.cpu1.numPwrStateTransitions              28692                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples        14346                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    3269284130.341071                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   86001867955.202789                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         3953     27.55%     27.55% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10        10364     72.24%     99.80% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.83% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            3      0.02%     99.86% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows           14      0.10%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 11813601970000                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total          14287                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   521446289148                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 46852869121352                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                     94748630821                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value 7510077904252                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total          14346                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON   503862826627                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 46901150133873                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                     94810025921                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   14287                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  442543215                       # Number of instructions committed
-system.cpu1.committedOps                    520378160                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            478315040                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                404780                       # Number of float alu accesses
-system.cpu1.num_func_calls                   26483096                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     67217461                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   478315040                       # number of integer instructions
-system.cpu1.num_fp_insts                       404780                       # number of float instructions
-system.cpu1.num_int_register_reads          696723237                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         379679857                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              664337                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             317564                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           114632172                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          114267384                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    159256484                       # number of memory refs
-system.cpu1.num_load_insts                   83870110                       # Number of load instructions
-system.cpu1.num_store_insts                  75386374                       # Number of store instructions
-system.cpu1.num_idle_cycles              93705738242.702026                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1042892578.297978                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.011007                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.988993                       # Percentage of idle cycles
-system.cpu1.Branches                         98643380                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                360264761     69.19%     69.19% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1062033      0.20%     69.39% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    60918      0.01%     69.41% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             40731      0.01%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::MemRead                83870110     16.11%     85.52% # Class of executed instruction
-system.cpu1.op_class::MemWrite               75386374     14.48%    100.00% # Class of executed instruction
+system.cpu1.kern.inst.quiesce                   14346                       # number of quiesce instructions executed
+system.cpu1.committedInsts                  415840875                       # Number of instructions committed
+system.cpu1.committedOps                    490335926                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            450775425                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                467875                       # Number of float alu accesses
+system.cpu1.num_func_calls                   24835210                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     63203882                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   450775425                       # number of integer instructions
+system.cpu1.num_fp_insts                       467875                       # number of float instructions
+system.cpu1.num_int_register_reads          655878523                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         357644258                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              746575                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             415812                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           107608929                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          107374492                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    150638767                       # number of memory refs
+system.cpu1.num_load_insts                   78882725                       # Number of load instructions
+system.cpu1.num_store_insts                  71756042                       # Number of store instructions
+system.cpu1.num_idle_cycles              93802300267.744019                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1007725653.255979                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.010629                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.989371                       # Percentage of idle cycles
+system.cpu1.Branches                         92635099                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                338840052     69.06%     69.06% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1031473      0.21%     69.27% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    58381      0.01%     69.28% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             67037      0.01%     69.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.30% # Class of executed instruction
+system.cpu1.op_class::MemRead                78882725     16.08%     85.37% # Class of executed instruction
+system.cpu1.op_class::MemWrite               71756042     14.63%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 520684927                       # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements          5203972                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          424.411021                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          153866536                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5204484                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            29.564225                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8378899013000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   424.411021                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.828928                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.828928                       # Average percentage of cache occupancy
+system.cpu1.op_class::total                 490635753                       # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements          4949273                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          456.328608                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          145491110                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          4949785                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            29.393420                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8379669141000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   456.328608                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.891267                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.891267                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          153                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          310                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          415                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           36                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        323742508                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       323742508                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data     78110378                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       78110378                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     71558729                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      71558729                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       177304                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       177304                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data        95899                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total        95899                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1773602                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1773602                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1738086                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1738086                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    149765006                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       149765006                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    149942310                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      149942310                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      2993339                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      2993339                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1322577                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1322577                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       630415                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       630415                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       446111                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       446111                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       170906                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       170906                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       205163                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       205163                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      4762027                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       4762027                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      5392442                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      5392442                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  43487315000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  43487315000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  24009342500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  24009342500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  10785817000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  10785817000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2544188500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2544188500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4864957000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4864957000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2180500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2180500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  78282474500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  78282474500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  78282474500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  78282474500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     81103717                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     81103717                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     72881306                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     72881306                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       807719                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       807719                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       542010                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       542010                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1944508                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1944508                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1943249                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1943249                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    154527033                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    154527033                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    155334752                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    155334752                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036908                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.036908                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018147                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.018147                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.780488                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.780488                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.823068                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.823068                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.087892                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.087892                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.105577                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105577                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.030817                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.030817                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.034715                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.034715                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14528.028733                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14528.028733                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18153.455338                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18153.455338                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24177.428936                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24177.428936                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14886.478532                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14886.478532                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23712.643118                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23712.643118                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.tag_accesses        306227498                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       306227498                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data     73475131                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       73475131                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     68103188                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      68103188                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       168046                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       168046                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data        87192                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total        87192                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1644934                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1644934                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1602204                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1602204                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    141665511                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       141665511                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    141833557                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      141833557                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      2804863                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      2804863                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1292961                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1292961                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       609189                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       609189                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       443031                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       443031                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       160663                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       160663                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       202242                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       202242                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      4540855                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       4540855                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      5150044                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      5150044                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  42649111500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  42649111500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  25017964000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  25017964000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  10518897000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  10518897000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2505987000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2505987000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4791659000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   4791659000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2159000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2159000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  78185972500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  78185972500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  78185972500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  78185972500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     76279994                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     76279994                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     69396149                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     69396149                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       777235                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       777235                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       530223                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       530223                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1805597                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1805597                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1804446                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1804446                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    146206366                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    146206366                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    146983601                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    146983601                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036771                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.036771                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018632                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.018632                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.783790                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.783790                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.835556                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.835556                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.088981                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.088981                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.112080                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.112080                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031058                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.031058                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035038                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.035038                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.416985                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.416985                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19349.357019                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 19349.357019                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23743.027012                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23743.027012                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15597.785427                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15597.785427                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23692.699835                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23692.699835                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16438.897658                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16438.897658                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14517.073063                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14517.073063                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17218.337185                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 17218.337185                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15181.612526                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15181.612526                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks      5203972                       # number of writebacks
-system.cpu1.dcache.writebacks::total          5203972                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        14156                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        14156                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          216                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total          216                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44175                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44175                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        14372                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        14372                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        14372                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        14372                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2979183                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2979183                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1322361                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1322361                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       630415                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       630415                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       446111                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       446111                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       126731                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       126731                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       205163                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       205163                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4747655                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4747655                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5378070                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5378070                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        17577                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        17577                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        16125                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        16125                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        33702                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        33702                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  39805955500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  39805955500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  22681350000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  22681350000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12330973000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12330973000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  10339706000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  10339706000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1686365000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1686365000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4659843000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4659843000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2131500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2131500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  72827011500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  72827011500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  85157984500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  85157984500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2978895500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2978895500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2978895500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2978895500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036733                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036733                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018144                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018144                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.780488                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.780488                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.823068                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.823068                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.065174                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.065174                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.105577                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105577                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030724                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.030724                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034622                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.034622                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.366354                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13361.366354                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17152.161929                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17152.161929                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19560.088196                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19560.088196                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23177.428936                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23177.428936                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13306.649517                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13306.649517                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22712.881952                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22712.881952                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      4949273                       # number of writebacks
+system.cpu1.dcache.writebacks::total          4949273                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18154                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        18154                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          423                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total          423                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        43805                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        43805                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        18577                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        18577                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        18577                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        18577                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2786709                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2786709                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1292538                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1292538                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       609189                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       609189                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       443031                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       443031                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       116858                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       116858                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       202242                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       202242                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4522278                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4522278                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5131467                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5131467                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        22203                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        22203                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        20755                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        20755                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        42958                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        42958                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38628648000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38628648000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  23695979500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  23695979500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13886318000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13886318000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  10075866000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  10075866000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1623112500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1623112500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4589466000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4589466000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2110000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2110000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  72400493500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  72400493500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  86286811500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  86286811500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3923399500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3923399500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3923399500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3923399500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036533                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036533                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018626                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018626                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.783790                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.783790                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.835556                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.835556                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064720                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.064720                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.112080                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.112080                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030931                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.030931                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034912                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.034912                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13861.744445                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13861.744445                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18332.907427                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18332.907427                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22794.761560                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22794.761560                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22743.027012                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22743.027012                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13889.613890                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13889.613890                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22692.942119                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22692.942119                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15339.575327                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15339.575327                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15834.301989                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15834.301989                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169476.901633                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169476.901633                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.279568                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 88389.279568                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements          4895837                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          496.209399                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          437953524                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          4896349                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            89.444916                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8378871626000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.209399                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969159                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.969159                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16009.739671                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16009.739671                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16815.232662                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16815.232662                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176705.828041                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176705.828041                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91331.055915                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91331.055915                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements          4981311                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          496.212019                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          411158765                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          4981823                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            82.531789                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8379594860000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.212019                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969164                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.969164                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          324                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          314                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          140                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        890596095                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       890596095                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst    437953524                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      437953524                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    437953524                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       437953524                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    437953524                       # number of overall hits
-system.cpu1.icache.overall_hits::total      437953524                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      4896349                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      4896349                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      4896349                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       4896349                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      4896349                       # number of overall misses
-system.cpu1.icache.overall_misses::total      4896349                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  51444170000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  51444170000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  51444170000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  51444170000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  51444170000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  51444170000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    442849873                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    442849873                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    442849873                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    442849873                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    442849873                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    442849873                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011056                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.011056                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011056                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.011056                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011056                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.011056                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10506.638722                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10506.638722                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10506.638722                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10506.638722                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10506.638722                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10506.638722                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        837263014                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       837263014                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst    411158765                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      411158765                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    411158765                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       411158765                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    411158765                       # number of overall hits
+system.cpu1.icache.overall_hits::total      411158765                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      4981828                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      4981828                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      4981828                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       4981828                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      4981828                       # number of overall misses
+system.cpu1.icache.overall_misses::total      4981828                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  54111358000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  54111358000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  54111358000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  54111358000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  54111358000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  54111358000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    416140593                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    416140593                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    416140593                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    416140593                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    416140593                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    416140593                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011972                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.011972                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011972                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.011972                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011972                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.011972                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10861.747535                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10861.747535                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10861.747535                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10861.747535                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10861.747535                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10861.747535                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks      4895837                       # number of writebacks
-system.cpu1.icache.writebacks::total          4895837                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4896349                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      4896349                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      4896349                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      4896349                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      4896349                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      4896349                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks      4981311                       # number of writebacks
+system.cpu1.icache.writebacks::total          4981311                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4981828                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      4981828                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      4981828                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      4981828                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      4981828                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      4981828                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  48995995500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  48995995500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  48995995500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  48995995500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  48995995500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  48995995500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10402000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10402000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10402000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     10402000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011056                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011056                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011056                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.011056                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011056                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.011056                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10006.638722                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10006.638722                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10006.638722                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10006.638722                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10006.638722                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10006.638722                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94563.636364                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94563.636364                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7252070                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7252079                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit            8                       # number of redundant prefetches already in prefetch queue
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  51620444000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  51620444000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  51620444000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  51620444000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  51620444000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  51620444000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10472000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10472000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10472000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     10472000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011972                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011972                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011972                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.011972                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011972                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.011972                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10361.747535                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10361.747535                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10361.747535                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10361.747535                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10361.747535                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 10361.747535                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        95200                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total        95200                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst        95200                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total        95200                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      6872416                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      6872436                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           18                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       909185                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements         1859788                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13078.836793                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           8983696                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         1875537                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            4.789933                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage       852028                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.tags.replacements         1861043                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       12976.163549                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           8767962                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         1876890                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            4.671537                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12823.617935                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    17.493162                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    11.479573                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   226.246124                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.782692                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001068                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000701                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.013809                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.798269                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          286                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           54                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15409                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          107                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          144                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           23                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           39                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          868                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         6435                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         7258                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          673                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.017456                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003296                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.940491                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       348956442                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      348956442                       # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       258658                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       151547                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        410205                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks      3266667                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total      3266667                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      6832390                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      6832390                       # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       881671                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       881671                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4452144                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      4452144                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2841120                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2841120                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       192152                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       192152                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       258658                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       151547                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4452144                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3722791                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        8585140                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       258658                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       151547                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4452144                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3722791                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       8585140                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        18381                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9249                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        27630                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       207506                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       207506                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       205160                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       205160                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12709.863020                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    27.854479                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    23.050365                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   215.395684                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.775748                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001700                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.001407                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.013147                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.792002                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          377                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           55                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15415                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            6                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          137                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           69                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          165                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           25                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1400                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5858                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4122                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3918                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.023010                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003357                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.940857                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       342605185                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      342605185                       # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       220532                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       147847                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        368379                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3122709                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3122709                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks      6807120                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total      6807120                       # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       835381                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       835381                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4529100                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      4529100                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2623579                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2623579                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       191618                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       191618                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       220532                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       147847                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      4529100                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3458960                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        8356439                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       220532                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       147847                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      4529100                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3458960                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       8356439                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        17957                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        10279                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        28236                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       208369                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       208369                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       202239                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       202239                       # number of SCUpgradeReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            3                       # number of SCUpgradeFailReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       235234                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       235234                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       444205                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       444205                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       895209                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       895209                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       252043                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       252043                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        18381                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9249                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       444205                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1130443                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1602278                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        18381                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9249                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       444205                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1130443                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1602278                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    560546000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    349476500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    910022500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    940760500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    940760500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    308144500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    308144500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2058000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2058000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   9879714999                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   9879714999                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  14896666000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  14896666000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  29710253000                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  29710253000                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    322403500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total    322403500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    560546000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    349476500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  14896666000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  39589967999                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  55396656499                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    560546000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    349476500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  14896666000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  39589967999                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  55396656499                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       277039                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       160796                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       437835                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3266667                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total      3266667                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks      6832390                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total      6832390                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       207506                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       207506                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       205160                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       205160                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       250965                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       250965                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       452728                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       452728                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       889177                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total       889177                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       249433                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       249433                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        17957                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker        10279                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       452728                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1140142                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1621106                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        17957                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker        10279                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       452728                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1140142                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1621106                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    590137500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    422641500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total   1012779000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    875652500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    875652500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    333590500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    333590500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2035999                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2035999                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  11238175000                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total  11238175000                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  16933068500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  16933068500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  31773824000                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  31773824000                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    403814500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total    403814500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    590137500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    422641500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  16933068500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  43011999000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  60957846500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    590137500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    422641500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  16933068500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  43011999000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  60957846500                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       238489                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       158126                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       396615                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3122709                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      3122709                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks      6807120                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total      6807120                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       208369                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       208369                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       202239                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       202239                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1116905                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1116905                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4896349                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      4896349                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3736329                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3736329                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       444195                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       444195                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       277039                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       160796                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      4896349                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4853234                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     10187418                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       277039                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       160796                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      4896349                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4853234                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     10187418                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.066348                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.057520                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.063106                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1086346                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1086346                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4981828                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      4981828                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3512756                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3512756                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       441051                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       441051                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       238489                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       158126                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      4981828                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4599102                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total      9977545                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       238489                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       158126                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      4981828                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4599102                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total      9977545                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.075295                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.065005                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.071192                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.210612                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.210612                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.090722                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.090722                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.239596                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.239596                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.567415                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.567415                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.066348                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.057520                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.090722                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.232926                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.157280                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.066348                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.057520                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.090722                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.232926                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.157280                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30495.946902                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37785.328144                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32936.029678                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4533.654449                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4533.654449                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1501.971632                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1501.971632                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       686000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       686000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41999.519623                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41999.519623                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33535.565786                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33535.565786                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 33188.063346                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 33188.063346                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1279.160699                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1279.160699                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30495.946902                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37785.328144                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33535.565786                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35021.640188                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 34573.686026                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30495.946902                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37785.328144                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33535.565786                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35021.640188                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 34573.686026                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.231018                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.231018                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.090876                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.090876                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.253128                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.253128                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.565542                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.565542                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.075295                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.065005                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.090876                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.247905                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.162475                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.075295                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.065005                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.090876                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.247905                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.162475                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32863.924932                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41116.986088                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 35868.359541                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4202.412547                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4202.412547                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1649.486499                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1649.486499                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 678666.333333                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 678666.333333                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44779.849780                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44779.849780                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37402.300057                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37402.300057                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35733.969727                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35733.969727                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1618.929733                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1618.929733                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32863.924932                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41116.986088                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37402.300057                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37725.124590                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 37602.628391                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32863.924932                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41116.986088                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37402.300057                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37725.124590                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 37602.628391                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches           39888                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks      1080406                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1080406                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         5355                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         5355                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          314                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          314                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            2                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         5669                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         5669                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         5669                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         5669                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        18381                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9249                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        27630                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       700284                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       700284                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       207506                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       207506                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       205160                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       205160                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.unused_prefetches           38928                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks      1071108                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1071108                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         4423                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         4423                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          417                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          417                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4840                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         4840                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4840                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         4840                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        17957                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        10279                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        28236                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       666851                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       666851                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       208369                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       208369                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       202239                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       202239                       # number of SCUpgradeReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       229879                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       229879                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       444205                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       444205                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       894895                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       894895                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       252041                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       252041                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        18381                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9249                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       444205                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1124774                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1596609                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        18381                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9249                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       444205                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1124774                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       700284                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2296893                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       246542                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       246542                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       452728                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       452728                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       888760                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       888760                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       249433                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       249433                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        17957                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        10279                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       452728                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1135302                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1616266                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        17957                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        10279                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       452728                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1135302                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       666851                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total      2283117                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        17577                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17687                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        16125                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        16125                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        22203                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        22313                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        20755                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        20755                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        33702                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        33812                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    450260000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    293982500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    744242500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  29274832519                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  29274832519                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   3856981999                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   3856981999                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3119783996                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3119783996                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1764000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1764000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7964098999                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7964098999                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  12231436000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  12231436000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  24307582500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  24307582500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6863337500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6863337500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    450260000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    293982500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  12231436000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  32271681499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  45247359999                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    450260000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    293982500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  12231436000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  32271681499                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  29274832519                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  74522192518                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9577000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2837977500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2847554500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9577000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2837977500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2847554500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.066348                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.057520                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.063106                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        42958                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        43068                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    482395500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    360967500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    843363000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  27800562984                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  27800562984                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   3852073000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   3852073000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3071337500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3071337500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1741999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1741999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   9224946500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   9224946500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  14216700500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  14216700500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  26383538000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  26383538000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6621907000                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6621907000                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    482395500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    360967500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  14216700500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  35608484500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  50668548000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    482395500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    360967500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  14216700500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  35608484500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  27800562984                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  78469110984                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9647000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3745274000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3754921000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9647000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3745274000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3754921000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.075295                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.065005                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.071192                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
@@ -2288,128 +2290,129 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.205818                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.205818                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.090722                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.090722                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.239512                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.239512                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.567411                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.567411                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.066348                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.057520                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.090722                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.231758                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.156724                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.066348                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.057520                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.090722                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.231758                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.226946                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.226946                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.090876                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.090876                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.253009                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.253009                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.565542                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.565542                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.075295                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.065005                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.090876                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.246853                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.161990                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.075295                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.065005                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.090876                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.246853                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.225464                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26936.029678                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41804.228740                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18587.327591                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18587.327591                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15206.589959                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15206.589959                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       588000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       588000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34644.743535                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34644.743535                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27535.565786                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27535.565786                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27162.496717                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27162.496717                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27231.035824                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27231.035824                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27535.565786                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28691.702955                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28339.662371                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27535.565786                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28691.702955                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32444.781937                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161459.720089                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160997.031718                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 84207.984689                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 84217.274932                       # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests     20954555                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10760929                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          751                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       564007                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       564007                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.228826                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29868.359541                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41689.317380                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18486.785462                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18486.785462                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15186.672699                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15186.672699                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 580666.333333                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 580666.333333                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37417.342684                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37417.342684                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31402.300057                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31402.300057                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29685.784689                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29685.784689                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26547.838498                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26547.838498                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31402.300057                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31364.768581                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31349.139312                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31402.300057                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31364.768581                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34369.290310                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        87700                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168683.241003                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168284.004840                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst        87700                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87184.552353                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87185.868859                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests     20600525                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10578683                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          754                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       558580                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       558580                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq        525208                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      9244496                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        16125                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        16125                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      4351848                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      6833141                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      1083593                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       850253                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       408331                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       372440                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       477174                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           56                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          102                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1146242                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1123232                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4896349                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4644090                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       493781                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       444195                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14688755                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16849115                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       339302                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       606054                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         32483226                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    626700344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    649733422                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1286368                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      2216312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1279936446                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    4601099                       # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic             75959664                       # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples     15521649                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.052382                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.222797                       # Request fanout histogram
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq        484798                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      9068801                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        20755                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        20755                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4199993                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      6807874                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      1098101                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       809012                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       385894                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       368515                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       474989                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           57                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          103                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1114310                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1093127                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4981828                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4385137                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       490192                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       441051                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14945187                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16097398                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       332311                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       526789                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         31901685                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    637641336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    617397659                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1265008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1907912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1258211915                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    4504290                       # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic             75632944                       # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples     15215883                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.052359                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.222750                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          14708591     94.76%     94.76% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            813058      5.24%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          14419192     94.76%     94.76% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            796691      5.24%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      15521649                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   20731667993                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      15215883                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   20375325498                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    171895510                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    176794994                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   7344633500                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   7472852000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7734220026                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7357432377                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    178506000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    174185000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    329015998                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    288300000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40399                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40399                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136980                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136980                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47798                       # Packet count per connected master and slave (bytes)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40355                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40355                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136628                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136628                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47782                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2420,15 +2423,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122940                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231738                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231738                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122664                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231222                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231222                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354758                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47818                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353966                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47802                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2439,23 +2442,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155955                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355304                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7355304                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155794                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338904                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338904                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7513345                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             37010502                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496784                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36982500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                12500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               320500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               322500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                 8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -2469,75 +2472,75 @@ system.iobus.reqLayer16.occupancy               14000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            26741000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            26451500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            37418500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            37417000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           570750713                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           569427501                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92947000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92767000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148178000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147918000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115853                       # number of replacements
-system.iocache.tags.tagsinuse               11.245503                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115615                       # number of replacements
+system.iocache.tags.tagsinuse               11.298649                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115869                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115631                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9136243501000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.839816                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.405687                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.239988                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.462855                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.702844                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9136560427000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.416178                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.882471                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.463511                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.242654                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706166                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1043178                       # Number of tag accesses
-system.iocache.tags.data_accesses             1043178                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1040856                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040856                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8885                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8922                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8883                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8920                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide       106984                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106984                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115869                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115909                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115611                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115651                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115869                       # number of overall misses
-system.iocache.overall_misses::total           115909                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5278000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1633593087                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1638871087                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115611                       # number of overall misses
+system.iocache.overall_misses::total           115651                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5193500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1828649003                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1833842503                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12911092626                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12911092626                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5647000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14544685713                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14550332713                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5647000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14544685713                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14550332713                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13346157998                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13346157998                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5562500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15174807001                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15180369501                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5562500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15174807001                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15180369501                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8885                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8922                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8883                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8920                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115869                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115909                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115611                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115651                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115869                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115909                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115611                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115651                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2551,53 +2554,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142648.648649                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 183859.660889                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 183688.756669                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140364.864865                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 205859.394686                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 205587.724552                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120682.463041                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 120682.463041                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       141175                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125526.980582                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125532.380687                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       141175                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125526.980582                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125532.380687                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         31750                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125048.328442                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125048.328442                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 139062.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 131257.466859                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 131260.166371                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 139062.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 131257.466859                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 131260.166371                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         41899                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3454                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3535                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.192241                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    11.852617                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks          106953                       # number of writebacks
-system.iocache.writebacks::total               106953                       # number of writebacks
+system.iocache.writebacks::writebacks          106702                       # number of writebacks
+system.iocache.writebacks::total               106702                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8885                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8922                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8883                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8920                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide       106984                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total       106984                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115869                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115909                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115611                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115651                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115869                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115909                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3428000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1189343087                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1192771087                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115611                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115651                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3343500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1384499003                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1387842503                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7553188799                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7553188799                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3647000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8742531886                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8746178886                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3647000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8742531886                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8746178886                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8000796585                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8000796585                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3562500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9385295588                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9388858088                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3562500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9385295588                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9388858088                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2611,662 +2614,659 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92648.648649                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133859.660889                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 133688.756669                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90364.864865                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 155859.394686                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 155587.724552                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70601.106698                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70601.106698                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        91175                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75451.862759                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75457.288787                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        91175                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75451.862759                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75457.288787                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1378015                       # number of replacements
-system.l2c.tags.tagsinuse                64998.786153                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6107230                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1440978                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.238253                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               9552186500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   11716.268844                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   133.184810                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   146.917074                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4004.381376                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    14231.433494                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  7902.194687                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   315.518093                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   369.695425                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2763.350410                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    11175.503416                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12240.338524                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.178776                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002032                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.002242                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.061102                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.217154                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.120578                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004814                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.005641                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.042165                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.170525                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.186773                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.991803                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        12060                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          189                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        50714                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::0           60                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1          153                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2         1009                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         1115                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         9723                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          184                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          163                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1849                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         9563                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        39124                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.184021                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.002884                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.773834                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 69629880                       # Number of tag accesses
-system.l2c.tags.data_accesses                69629880                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks      2641101                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         2641101                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data          213424                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data          155298                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total              368722                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data         50511                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data         50527                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total            101038                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            63650                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            48993                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               112643                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        10681                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5935                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       422841                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       567260                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       276728                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         9775                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4116                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       406188                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       512398                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       278781                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          2494703                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       136557                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       120325                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           256882                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         10681                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          5935                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              422841                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              630910                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       276728                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          9775                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4116                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              406188                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              561391                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       278781                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2607346                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        10681                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         5935                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             422841                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             630910                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       276728                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         9775                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4116                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             406188                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             561391                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       278781                       # number of overall hits
-system.l2c.overall_hits::total                2607346                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         24497                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         25507                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             50004                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          796                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          825                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1621                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          72583                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          52296                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             124879                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1676                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1611                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        56236                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       130395                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       210895                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1750                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1829                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        38017                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       107679                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       200910                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         750998                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       430773                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       119101                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         549874                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1676                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1611                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             56236                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            202978                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       210895                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         1750                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         1829                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             38017                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            159975                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       200910                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                875877                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1676                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1611                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            56236                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           202978                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       210895                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         1750                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         1829                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            38017                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           159975                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       200910                       # number of overall misses
-system.l2c.overall_misses::total               875877                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    177641500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    151031500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    328673000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      8353500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      8021500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total     16375000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   6466021500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4532203999                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  10998225499                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    151916500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    149670500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   4848581000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  11828995999                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  26350487356                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    157377000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    162435000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3283945500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data   9698473500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  24221293566                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  80853175921                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data     43381500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data     30876500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total     74258000                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    151916500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    149670500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   4848581000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  18295017499                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  26350487356                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    157377000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    162435000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   3283945500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  14230677499                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  24221293566                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     91851401420                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    151916500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    149670500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   4848581000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  18295017499                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  26350487356                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    157377000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    162435000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   3283945500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  14230677499                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  24221293566                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    91851401420                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks      2641101                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      2641101                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data       237921                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data       180805                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          418726                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        51307                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        51352                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total        102659                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       136233                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       101289                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           237522                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        12357                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7546                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       479077                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       697655                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       487623                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        11525                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5945                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       444205                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       620077                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       479691                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3245701                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       567330                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       239426                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total       806756                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        12357                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         7546                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          479077                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          833888                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       487623                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        11525                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         5945                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          444205                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          721366                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       479691                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             3483223                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        12357                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         7546                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         479077                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         833888                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       487623                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        11525                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         5945                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         444205                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         721366                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       479691                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            3483223                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.102963                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.141075                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.119419                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.015514                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.016066                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.015790                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.532786                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.516305                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.525758                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.135632                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.213491                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.117384                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.186905                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.432496                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.151844                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.307653                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.085584                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.173654                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.418832                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.231382                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.759299                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.497444                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.681587                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.135632                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.213491                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.117384                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.243412                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.432496                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.151844                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.307653                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.085584                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.221767                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.418832                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.251456                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.135632                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.213491                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.117384                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.243412                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.432496                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.151844                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.307653                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.085584                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.221767                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.418832                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.251456                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  7251.561416                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5921.178500                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6572.934165                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 10494.346734                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  9723.030303                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 10101.789019                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89084.517036                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 86664.448505                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 88071.056775                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90642.303103                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92905.338299                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86218.454371                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90716.637900                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89929.714286                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88810.825588                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86380.974301                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90068.383807                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 107660.973692                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   100.706172                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   259.246354                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total   135.045483                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90642.303103                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92905.338299                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 86218.454371                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 90133.007020                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89929.714286                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88810.825588                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 86380.974301                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 88955.633687                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 104867.922574                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90642.303103                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92905.338299                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 86218.454371                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 90133.007020                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89929.714286                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88810.825588                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 86380.974301                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 88955.633687                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 104867.922574                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               424                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74964.363475                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74964.363475                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89062.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 81179.953361                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 81182.679683                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89062.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 81179.953361                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 81182.679683                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                  1376932                       # number of replacements
+system.l2c.tags.tagsinuse                65061.419917                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5975056                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1437120                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.157660                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               9858759500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   11843.449139                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   304.799159                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   356.696004                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3585.763677                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    19085.445505                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14223.146945                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   128.223998                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   149.509582                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3193.954857                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     6240.562219                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  5949.868833                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.180717                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.004651                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.005443                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.054714                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.291221                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.217028                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.001957                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.002281                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.048736                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.095223                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.090788                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.992758                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        11266                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          259                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        48663                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          152                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          297                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        10816                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          259                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          888                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4525                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        43209                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.171906                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003952                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.742538                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 68586261                       # Number of tag accesses
+system.l2c.tags.data_accesses                68586261                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks      2589224                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2589224                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data          191644                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          164185                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              355829                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         48914                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         48173                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             97087                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            47737                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            58567                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               106304                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         9201                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         3860                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       408160                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       537157                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       271610                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        10477                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         5555                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       408048                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       521656                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       272486                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          2448210                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       124551                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       127410                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           251961                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          9201                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          3860                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              408160                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              584894                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       271610                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         10477                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          5555                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              408048                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              580223                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       272486                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2554514                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         9201                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         3860                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             408160                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             584894                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       271610                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        10477                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         5555                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             408048                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             580223                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       272486                       # number of overall hits
+system.l2c.overall_hits::total                2554514                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         24439                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         23204                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             47643                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          628                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          554                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1182                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          75730                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          50449                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             126179                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1681                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1744                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        48585                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       141383                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       241091                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1909                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1973                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst        44680                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       100605                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       169474                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         753125                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       440725                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data       106525                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         547250                       # number of InvalidateReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         1681                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         1744                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             48585                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            217113                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       241091                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         1909                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         1973                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             44680                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            151054                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher       169474                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                879304                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         1681                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         1744                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            48585                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           217113                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       241091                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         1909                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         1973                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            44680                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           151054                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher       169474                       # number of overall misses
+system.l2c.overall_misses::total               879304                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    162640000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    138377500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    301017500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      7502500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      7047000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total     14549500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   8218459999                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   5520286999                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  13738746998                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    167721500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    180518500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   5556413500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  15487743000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  32099260605                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    194137000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    210753000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst   5171670000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data  11743795000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  22852256906                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  93664269011                       # number of ReadSharedReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu0.data     42596000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data     33301500                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::total     75897500                       # number of InvalidateReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    167721500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    180518500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   5556413500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  23706202999                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  32099260605                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    194137000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    210753000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   5171670000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  17264081999                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  22852256906                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    107403016009                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    167721500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    180518500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   5556413500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  23706202999                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  32099260605                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    194137000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker    210753000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   5171670000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  17264081999                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  22852256906                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   107403016009                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks      2589224                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      2589224                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data       216083                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data       187389                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          403472                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        49542                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        48727                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         98269                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       123467                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       109016                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           232483                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        10882                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         5604                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       456745                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       678540                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       512701                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        12386                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7528                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       452728                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       622261                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       441960                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3201335                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       565276                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       233935                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total       799211                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        10882                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         5604                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          456745                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          802007                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       512701                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        12386                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7528                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          452728                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          731277                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       441960                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             3433818                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        10882                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         5604                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         456745                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         802007                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       512701                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        12386                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7528                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         452728                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         731277                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       441960                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            3433818                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.113100                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.123828                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.118083                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.012676                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.011369                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.012028                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.613362                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.462767                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.542745                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.154475                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.311206                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.106372                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.208364                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.470237                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.154126                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.262088                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.098691                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.161677                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.383460                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.235253                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.779663                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.455362                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.684738                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.154475                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.311206                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.106372                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.270712                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.470237                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.154126                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.262088                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.098691                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.206562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.383460                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.256072                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.154475                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.311206                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.106372                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.270712                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.470237                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.154126                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.262088                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.098691                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.206562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.383460                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.256072                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6654.936781                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5963.519221                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6318.189451                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11946.656051                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12720.216606                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 12309.221658                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108523.174422                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109423.120359                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 108882.991607                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 99774.836407                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 103508.314220                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 114364.793661                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 109544.591641                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 101695.652174                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 106818.550431                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 115749.104745                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116731.723075                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 124367.494122                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    96.649838                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   312.616757                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total   138.688899                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 99774.836407                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 103508.314220                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 114364.793661                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 109188.316678                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 101695.652174                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 106818.550431                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 115749.104745                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 114290.796662                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 122145.487805                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 99774.836407                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 103508.314220                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 114364.793661                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 109188.316678                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 101695.652174                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 106818.550431                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 115749.104745                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 114290.796662                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 122145.487805                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               340                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        5                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       16                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     84.800000                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     21.250000                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1062304                       # number of writebacks
-system.l2c.writebacks::total                  1062304                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          133                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           64                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           89                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           16                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          302                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            133                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             64                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             89                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             16                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                302                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           133                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            64                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            89                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            16                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               302                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        54771                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        54771                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        24497                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        25507                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        50004                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          796                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          825                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1621                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        72583                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        52296                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        124879                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1676                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1611                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        56103                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       130331                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       210895                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1750                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1829                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        37928                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       107663                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       200910                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       750696                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data       430773                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data       119101                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       549874                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         1676                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         1611                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        56103                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       202914                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       210895                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         1750                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         1829                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        37928                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       159959                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       200910                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           875575                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         1676                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         1611                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        56103                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       202914                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       210895                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         1750                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         1829                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        37928                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       159959                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       200910                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          875575                       # number of overall MSHR misses
+system.l2c.writebacks::writebacks             1062552                       # number of writebacks
+system.l2c.writebacks::total                  1062552                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          178                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data           32                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          123                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           57                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total          390                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst            178                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             32                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst            123                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             57                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                390                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst           178                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            32                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst           123                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data            57                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               390                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks        55381                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total        55381                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        24439                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        23204                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        47643                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          628                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          554                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1182                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        75730                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        50449                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        126179                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1681                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1744                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        48407                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       141351                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       241091                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1909                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1973                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        44557                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data       100548                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       169474                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       752735                       # number of ReadSharedReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu0.data       440725                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu1.data       106525                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::total       547250                       # number of InvalidateReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker         1681                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker         1744                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        48407                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       217081                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       241091                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker         1909                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker         1973                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        44557                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data       150997                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       169474                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           878914                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker         1681                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker         1744                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        48407                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       217081                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       241091                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker         1909                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker         1973                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        44557                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data       150997                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       169474                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          878914                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        21025                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16381                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17575                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        81835                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        22388                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        16125                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        38513                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data        22201                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        81817                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        17694                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data        20755                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        38449                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        43413                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        34075                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        33700                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total       120348                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    503126000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    519991500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   1023117500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     19775000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     20085500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     39860500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5740155074                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4009215058                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   9749370132                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    135154504                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    133557506                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   4277568054                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  10520997188                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  24241323314                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    139876501                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    144145000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   2898586521                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   8620097178                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  22212057363                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  73323363129                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   8575090000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2366625500                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total  10941715500                       # number of InvalidateReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    135154504                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    133557506                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   4277568054                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  16261152262                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  24241323314                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    139876501                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    144145000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   2898586521                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  12629312236                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  22212057363                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  83072733261                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    135154504                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    133557506                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   4277568054                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  16261152262                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  24241323314                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    139876501                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    144145000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   2898586521                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  12629312236                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  22212057363                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  83072733261                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2719782000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3442200004                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7595500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2521551501                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   8691129005                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2719782000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3442200004                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7595500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2521551501                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   8691129005                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        42956                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       120266                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    494587500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    479394000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    973981500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     15163500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     13789000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     28952500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7461135548                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5015765562                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  12476901110                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    150911500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    163078500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   5057062528                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  14070826165                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  29688205910                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    175047000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    191021503                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   4714685544                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  10733108269                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  21157302360                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  86101249279                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   8759971500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2141412000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  10901383500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    150911500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    163078500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   5057062528                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  21531961713                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  29688205910                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    175047000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    191021503                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   4714685544                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  15748873831                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  21157302360                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  98578150389                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    150911500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    163078500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   5057062528                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  21531961713                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  29688205910                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    175047000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    191021503                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   4714685544                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  15748873831                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  21157302360                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  98578150389                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3016846000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2614209002                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7665500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3345576000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   8984296502                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3016846000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2614209002                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7665500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3345576000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   8984296502                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.102963                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.141075                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.119419                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.015514                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.016066                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.015790                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.532786                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.516305                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.525758                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.135632                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.213491                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.117106                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.186813                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.432496                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.151844                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.307653                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.085384                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.173628                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.418832                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.231289                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.759299                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.497444                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.681587                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.135632                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.213491                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.117106                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.243335                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.432496                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.151844                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.307653                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.085384                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.221745                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.418832                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.251369                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.135632                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.213491                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.117106                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.243335                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.432496                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.151844                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.307653                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.085384                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.221745                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.418832                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.251369                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20538.269992                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20386.227310                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20460.713143                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24842.964824                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24346.060606                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24590.067859                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79084.015183                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76663.895097                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 78070.533332                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76244.907652                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80725.208799                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76423.394880                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80065.548777                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97673.842846                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19906.284749                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19870.744158                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19898.586767                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76244.907652                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80138.148487                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76423.394880                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78953.433292                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 94877.918238                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76244.907652                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80138.148487                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76423.394880                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78953.433292                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 94877.918238                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163719.381879                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        69050                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143473.769616                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106203.079428                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 79289.613802                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst        69050                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74823.486677                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 72216.646766                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests       3586859                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      2135577                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3113                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.113100                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.123828                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.118083                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.012676                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.011369                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.012028                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.613362                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.462767                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.542745                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.154475                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.311206                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.105983                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.208316                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.470237                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.154126                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.262088                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.098419                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.161585                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383460                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.235132                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.779663                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.455362                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.684738                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.154475                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.311206                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.105983                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.270672                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.470237                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.154126                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.262088                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.098419                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.206484                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383460                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.255958                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.154475                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.311206                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.105983                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.270672                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.470237                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.154126                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.262088                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.098419                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.206484                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383460                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.255958                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20237.632473                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20659.972419                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20443.328506                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24145.700637                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24889.891697                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24494.500846                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98522.851552                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99422.497215                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 98882.548681                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104469.653728                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99545.289138                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 105812.454698                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106746.113985                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114384.543404                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19876.275455                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20102.436048                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19920.298767                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104469.653728                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99188.605696                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 105812.454698                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 104299.249859                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 112159.039894                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104469.653728                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99188.605696                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 105812.454698                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 104299.249859                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 112159.039894                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159587.876320                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150694.833566                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109809.654497                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76719.266383                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77883.788062                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 74703.544659                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests       3576184                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      2127782                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3085                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               81835                       # Transaction distribution
-system.membus.trans_dist::ReadResp             841453                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38513                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38513                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1169257                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           224172                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           330190                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         306798                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              21                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            142313                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           124217                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        759618                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        654423                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122940                       # Packet count per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               81817                       # Transaction distribution
+system.membus.trans_dist::ReadResp             843472                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38449                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38449                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1169254                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           223620                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           320332                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         305580                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            143723                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           125482                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        761655                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        651499                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122664                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26066                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4320804                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4469902                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238504                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       238504                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4708406                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155955                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26178                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4313500                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4462434                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238025                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       238025                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4700459                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155794                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    124129580                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    124337871                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7276480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7276480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               131614351                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           603280                       # Total snoops (count)
-system.membus.snoopTraffic                     185472                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2313692                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.013382                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.114902                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52356                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    124357036                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    124565390                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7261504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7261504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               131826894                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           595046                       # Total snoops (count)
+system.membus.snoopTraffic                     184128                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           2303059                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.014256                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.118544                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2282731     98.66%     98.66% # Request fanout histogram
-system.membus.snoop_fanout::1                   30961      1.34%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2270227     98.57%     98.57% # Request fanout histogram
+system.membus.snoop_fanout::1                   32832      1.43%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2313692                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           101576998                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2303059                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           101257500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21542999                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21679000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8037178912                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8033203938                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4828786098                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         4846349578                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           45456460                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           45469982                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -3309,78 +3309,78 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     10929949                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      5951808                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      1800454                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         181173                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       166358                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        14815                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq              81837                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4119674                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38513                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38513                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      3703405                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2363493                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          695815                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        407836                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp        1103651                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          102                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          102                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           294367                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          294367                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4038548                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       834564                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp       806756                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8843715                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7139942                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              15983657                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    216752505                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    175713942                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              392466447                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2839573                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                 122328784                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          7769609                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.368989                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.486467                       # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests     10759482                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      5851735                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      1766751                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         181547                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       166860                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        14687                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq              81819                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4062742                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38449                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38449                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      3651776                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2342209                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          672985                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        402667                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1075652                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          103                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          103                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           288170                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          288170                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      3981632                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       828938                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp       799211                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8607895                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7128520                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              15736415                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    211923339                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    174059331                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              385982670                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2818319                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                 121467536                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples          7671705                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.367658                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.486122                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                4917524     63.29%     63.29% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                2837270     36.52%     99.81% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  14815      0.19%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                4865825     63.43%     63.43% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                2791193     36.38%     99.81% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  14687      0.19%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            7769609                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         8597464366                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            7671705                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         8456586164                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2599172                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2556167                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4012155776                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        3921212144                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3555978029                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3534160915                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal
index 8a6e02412..1ab2ced54 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal
@@ -32,135 +32,135 @@
 [    0.000000] NR_IRQS:64 nr_irqs:64 0
 [    0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
 [    0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[    0.000027] Console: colour dummy device 80x25
-[    0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[    0.000032] pid_max: default: 32768 minimum: 301
-[    0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[    0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[    0.000186] hw perfevents: no hardware support available
-[    0.060051] CPU1: Booted secondary processor
-[    1.080095] CPU2: failed to come online
-[    2.100183] CPU3: failed to come online
-[    2.100186] Brought up 2 CPUs
-[    2.100188] SMP: Total of 2 processors activated.
-[    2.100259] devtmpfs: initialized
-[    2.100898] atomic64_test: passed
-[    2.100952] regulator-dummy: no parameters
-[    2.101389] NET: Registered protocol family 16
-[    2.101557] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[    2.101563] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[    2.102363] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[    2.102366] Serial: AMBA PL011 UART driver
-[    2.102592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[    2.102637] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[    2.103214] console [ttyAMA0] enabled
-[    2.103383] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[    2.103459] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[    2.103535] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[    2.103603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[    2.130362] 3V3: 3300 mV 
-[    2.130420] vgaarb: loaded
-[    2.130477] SCSI subsystem initialized
-[    2.130513] libata version 3.00 loaded.
-[    2.130567] usbcore: registered new interface driver usbfs
-[    2.130587] usbcore: registered new interface driver hub
-[    2.130614] usbcore: registered new device driver usb
-[    2.130645] pps_core: LinuxPPS API ver. 1 registered
-[    2.130654] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[    2.130674] PTP clock support registered
-[    2.130822] Switched to clocksource arch_sys_counter
-[    2.132478] NET: Registered protocol family 2
-[    2.132574] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[    2.132593] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[    2.132613] TCP: Hash tables configured (established 2048 bind 2048)
-[    2.132642] TCP: reno registered
-[    2.132649] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[    2.132663] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[    2.132704] NET: Registered protocol family 1
-[    2.132763] RPC: Registered named UNIX socket transport module.
-[    2.132774] RPC: Registered udp transport module.
-[    2.132782] RPC: Registered tcp transport module.
-[    2.132791] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[    2.132804] PCI: CLS 0 bytes, default 64
-[    2.133012] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[    2.133128] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[    2.135205] fuse init (API version 7.23)
-[    2.135350] msgmni has been set to 469
-[    2.135656] io scheduler noop registered
-[    2.135718] io scheduler cfq registered (default)
-[    2.136286] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[    2.136300] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
-[    2.136311] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[    2.136324] pci_bus 0000:00: root bus resource [bus 00-ff]
-[    2.136335] pci_bus 0000:00: scanning bus
-[    2.136346] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[    2.136360] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[    2.136375] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[    2.136416] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[    2.136429] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]
-[    2.136440] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]
-[    2.136452] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]
-[    2.136463] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]
-[    2.136474] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]
-[    2.136486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[    2.136527] pci_bus 0000:00: fixups for bus
-[    2.136536] pci_bus 0000:00: bus scan returning with max=00
-[    2.136548] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[    2.136569] pci 0000:00:00.0: fixup irq: got 33
-[    2.136578] pci 0000:00:00.0: assigning IRQ 33
-[    2.136589] pci 0000:00:01.0: fixup irq: got 34
-[    2.136598] pci 0000:00:01.0: assigning IRQ 34
-[    2.136609] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[    2.136623] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[    2.136636] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[    2.136650] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]
-[    2.136662] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]
-[    2.136674] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]
-[    2.136686] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]
-[    2.136698] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]
-[    2.137491] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[    2.137826] ata_piix 0000:00:01.0: version 2.13
-[    2.137837] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[    2.137864] ata_piix 0000:00:01.0: enabling bus mastering
-[    2.138204] scsi0 : ata_piix
-[    2.138329] scsi1 : ata_piix
-[    2.138380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[    2.138393] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[    2.138543] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[    2.138556] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[    2.138573] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[    2.138585] e1000 0000:00:00.0: enabling bus mastering
-[    2.280852] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[    2.280862] ata1.00: 2096640 sectors, multi 0: LBA 
-[    2.280892] ata1.00: configured for UDMA/33
-[    2.280951] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
-[    2.281082] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[    2.281116] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[    2.281160] sd 0:0:0:0: [sda] Write Protect is off
-[    2.281170] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[    2.281192] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[    2.281337]  sda: sda1
-[    2.281470] sd 0:0:0:0: [sda] Attached SCSI disk
-[    2.401164] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[    2.401177] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[    2.401211] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[    2.401224] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[    2.401253] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[    2.401268] igb: Copyright (c) 2007-2014 Intel Corporation.
-[    2.401414] usbcore: registered new interface driver usb-storage
-[    2.401486] mousedev: PS/2 mouse device common for all mice
-[    2.401677] usbcore: registered new interface driver usbhid
-[    2.401687] usbhid: USB HID core driver
-[    2.401726] TCP: cubic registered
-[    2.401734] NET: Registered protocol family 17
-[    2.402177] VFS: Mounted root (ext2 filesystem) on device 8:1.
-[    2.402215] devtmpfs: mounted
-[    2.402270] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[    0.000029] Console: colour dummy device 80x25
+[    0.000031] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[    0.000033] pid_max: default: 32768 minimum: 301
+[    0.000047] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[    0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[    0.000190] hw perfevents: no hardware support available
+[    0.060052] CPU1: Booted secondary processor
+[    1.080092] CPU2: failed to come online
+[    2.100178] CPU3: failed to come online
+[    2.100181] Brought up 2 CPUs
+[    2.100182] SMP: Total of 2 processors activated.
+[    2.100254] devtmpfs: initialized
+[    2.100899] atomic64_test: passed
+[    2.100953] regulator-dummy: no parameters
+[    2.101395] NET: Registered protocol family 16
+[    2.101565] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[    2.101572] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[    2.102371] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[    2.102374] Serial: AMBA PL011 UART driver
+[    2.102603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[    2.102648] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[    2.103226] console [ttyAMA0] enabled
+[    2.103397] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[    2.103474] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[    2.103550] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[    2.103618] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[    2.130484] 3V3: 3300 mV 
+[    2.130542] vgaarb: loaded
+[    2.130598] SCSI subsystem initialized
+[    2.130640] libata version 3.00 loaded.
+[    2.130696] usbcore: registered new interface driver usbfs
+[    2.130716] usbcore: registered new interface driver hub
+[    2.130745] usbcore: registered new device driver usb
+[    2.130775] pps_core: LinuxPPS API ver. 1 registered
+[    2.130785] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[    2.130805] PTP clock support registered
+[    2.130963] Switched to clocksource arch_sys_counter
+[    2.132610] NET: Registered protocol family 2
+[    2.132708] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[    2.132728] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[    2.132748] TCP: Hash tables configured (established 2048 bind 2048)
+[    2.132775] TCP: reno registered
+[    2.132782] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[    2.132796] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[    2.132838] NET: Registered protocol family 1
+[    2.132904] RPC: Registered named UNIX socket transport module.
+[    2.132915] RPC: Registered udp transport module.
+[    2.132923] RPC: Registered tcp transport module.
+[    2.132932] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[    2.132945] PCI: CLS 0 bytes, default 64
+[    2.133141] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[    2.133256] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[    2.135328] fuse init (API version 7.23)
+[    2.135440] msgmni has been set to 469
+[    2.135797] io scheduler noop registered
+[    2.135862] io scheduler cfq registered (default)
+[    2.136433] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[    2.136447] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
+[    2.136458] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[    2.136472] pci_bus 0000:00: root bus resource [bus 00-ff]
+[    2.136482] pci_bus 0000:00: scanning bus
+[    2.136494] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[    2.136508] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[    2.136523] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[    2.136564] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[    2.136577] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]
+[    2.136588] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]
+[    2.136600] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]
+[    2.136611] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]
+[    2.136622] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]
+[    2.136634] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[    2.136675] pci_bus 0000:00: fixups for bus
+[    2.136684] pci_bus 0000:00: bus scan returning with max=00
+[    2.136697] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[    2.136718] pci 0000:00:00.0: fixup irq: got 33
+[    2.136727] pci 0000:00:00.0: assigning IRQ 33
+[    2.136739] pci 0000:00:01.0: fixup irq: got 34
+[    2.136748] pci 0000:00:01.0: assigning IRQ 34
+[    2.136760] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[    2.136773] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[    2.136787] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[    2.136801] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]
+[    2.136813] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]
+[    2.136825] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]
+[    2.136837] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]
+[    2.136849] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]
+[    2.137426] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[    2.137740] ata_piix 0000:00:01.0: version 2.13
+[    2.137750] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[    2.137778] ata_piix 0000:00:01.0: enabling bus mastering
+[    2.138110] scsi0 : ata_piix
+[    2.138200] scsi1 : ata_piix
+[    2.138235] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[    2.138247] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[    2.138381] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[    2.138393] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[    2.138410] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[    2.138423] e1000 0000:00:00.0: enabling bus mastering
+[    2.290984] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[    2.290994] ata1.00: 2096640 sectors, multi 0: LBA 
+[    2.291024] ata1.00: configured for UDMA/33
+[    2.291083] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
+[    2.291212] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[    2.291226] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[    2.291255] sd 0:0:0:0: [sda] Write Protect is off
+[    2.291265] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[    2.291288] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[    2.291434]  sda: sda1
+[    2.291570] sd 0:0:0:0: [sda] Attached SCSI disk
+[    2.411274] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[    2.411288] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[    2.411313] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[    2.411324] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[    2.411348] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[    2.411360] igb: Copyright (c) 2007-2014 Intel Corporation.
+[    2.411448] usbcore: registered new interface driver usb-storage
+[    2.411534] mousedev: PS/2 mouse device common for all mice
+[    2.411744] usbcore: registered new interface driver usbhid
+[    2.411754] usbhid: USB HID core driver
+[    2.411794] TCP: cubic registered
+[    2.411802] NET: Registered protocol family 17
+[    2.412301] VFS: Mounted root (ext2 filesystem) on device 8:1.
+[    2.412341] devtmpfs: mounted
+[    2.412395] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
 
INIT: version 2.88 booting

 Starting udev
-[    2.442337] udevd[608]: starting version 182
+[    2.452586] udevd[609]: starting version 182
 Starting Bootlog daemon: bootlogd.

-[    2.533997] random: dd urandom read with 18 bits of entropy available
+[    2.534161] random: dd urandom read with 18 bits of entropy available
 Populating dev cache

 net.ipv4.conf.default.rp_filter = 1

 net.ipv4.conf.all.rp_filter = 1

@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory

 
INIT: Entering runlevel: 5


 Configuring network interfaces... udhcpc (v1.21.1) started

-[    2.671053] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[    2.671190] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
 Sending discover...

 Sending discover...

 Sending discover...

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
index ebadfb41e..d16508053 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
@@ -36,7 +36,7 @@ load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM64
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -153,7 +153,7 @@ icache_port=system.cpu.icache.cpu_side
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -250,7 +250,7 @@ port=system.cpu.toL2Bus.slave[3]
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -310,7 +310,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -382,7 +382,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -499,7 +499,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -544,7 +544,7 @@ size=1024
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -556,7 +556,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -588,29 +588,36 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -630,6 +637,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -639,7 +647,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -661,9 +669,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -1016,7 +1024,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -1329,10 +1337,11 @@ pio=system.iobus.master[21]
 type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
-conf_table_reported=true
+conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1340,7 +1349,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -1571,6 +1580,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1578,7 +1588,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
index ad2b5e63e..b93a4d4b7 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 15:07:38
-gem5 executing on e108600-lin, pid 24412
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:50:54
+gem5 executing on e108600-lin, pid 17458
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing
 
 Selected 64-bit ARM architecture, updating default disk image...
@@ -15,4 +15,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 51759347706500 because m5_exit instruction encountered
+Exiting @ tick 51821888787500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
index db63d86a7..39817260d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
@@ -1,139 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.820895                       # Number of seconds simulated
-sim_ticks                                51820894502500                       # Number of ticks simulated
-final_tick                               51820894502500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.821889                       # Number of seconds simulated
+sim_ticks                                51821888787500                       # Number of ticks simulated
+final_tick                               51821888787500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 612269                       # Simulator instruction rate (inst/s)
-host_op_rate                                   719485                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            35448799247                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 680056                       # Number of bytes of host memory used
-host_seconds                                  1461.85                       # Real time elapsed on the host
-sim_insts                                   895045967                       # Number of instructions simulated
-sim_ops                                    1051780871                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 515124                       # Simulator instruction rate (inst/s)
+host_op_rate                                   605315                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            31054928912                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 676612                       # Number of bytes of host memory used
+host_seconds                                  1668.72                       # Real time elapsed on the host
+sim_insts                                   859596485                       # Number of instructions simulated
+sim_ops                                    1010098639                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker       268032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       256704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5200500                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          51306824                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        409600                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             57441660                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5200500                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5200500                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     78712256                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker       216448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       219200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5035380                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          42867656                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        394432                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             48733116                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5035380                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5035380                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     69868992                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          78732836                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         4188                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         4011                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             121665                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             801682                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6400                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                937946                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1229879                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          69889572                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3382                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         3425                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             119085                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             669820                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6163                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                801875                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1091703                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1232452                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           5172                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           4954                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               100355                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               990080                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7904                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1108465                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          100355                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             100355                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1518929                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1094276                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           4177                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           4230                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                97167                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               827211                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7611                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  940396                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           97167                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              97167                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1348253                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 397                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1519326                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1518929                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          5172                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          4954                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              100355                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              990477                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7904                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2627791                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        937946                       # Number of read requests accepted
-system.physmem.writeReqs                      1232452                       # Number of write requests accepted
-system.physmem.readBursts                      937946                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1232452                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 59993856                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     34688                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  78731584                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  57441660                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               78732836                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      542                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1348650                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1348253                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          4177                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          4230                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               97167                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              827609                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7611                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2289046                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        801875                       # Number of read requests accepted
+system.physmem.writeReqs                      1094276                       # Number of write requests accepted
+system.physmem.readBursts                      801875                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1094276                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 51277952                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     42048                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  69886912                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  48733116                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               69889572                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      657                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2265                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               58989                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               58919                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               58679                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               55735                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               54249                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               59544                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               52586                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               53926                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               52975                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              101116                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              56481                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              59298                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              53072                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              58564                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              50527                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              52744                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               76908                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               78477                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               80133                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               78953                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               75778                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               80212                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               72590                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               74527                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               74121                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               79665                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              76241                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              79585                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              74881                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              79432                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              73606                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              75072                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               50164                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               52640                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               46199                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               47700                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               47678                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               54947                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               45482                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               44174                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               47146                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               89983                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              47048                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              49101                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              43837                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              45399                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              43891                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              45829                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               68109                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               72083                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               69263                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               69948                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               67942                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               73995                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               66206                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65273                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               68509                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               70672                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              68078                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              68626                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64922                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              66812                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              65438                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              66107                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          41                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51820891581500                       # Total gap between requests
+system.physmem.numWrRetry                         528                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51821885925500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  894830                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  758759                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1229879                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    903506                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     28089                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       425                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       344                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       490                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       475                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       651                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       467                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1235                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       309                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      395                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      169                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      183                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      135                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      109                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      107                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       97                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       93                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       74                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       51                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1091703                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    767795                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     27710                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       516                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       322                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       453                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       438                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       573                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       470                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       924                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       568                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      268                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      279                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      181                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      146                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      120                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      106                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      101                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       79                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       70                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -160,154 +160,185 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    33600                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    39104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    67316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    70490                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    74148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    71564                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    70236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    72767                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    75611                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    72543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    77682                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    76300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    72201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    70498                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    70723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    68261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    67880                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    67043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      865                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      625                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      521                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      296                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      368                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      354                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      334                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      397                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      259                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      230                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      255                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      128                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       563432                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      246.214486                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     148.153142                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     287.290760                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         250076     44.38%     44.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       147098     26.11%     70.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        49891      8.85%     79.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        26994      4.79%     84.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18337      3.25%     87.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11939      2.12%     89.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8931      1.59%     91.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7653      1.36%     92.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        42513      7.55%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         563432                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         66023                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        14.197810                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      125.335088                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          66020    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    30627                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    34869                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    57710                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    61714                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    64549                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    61650                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    60651                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    63213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    64819                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    63587                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    67440                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    65819                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    60766                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    60977                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    60110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    59233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    58775                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2370                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1929                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1663                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1421                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1048                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      853                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      823                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      783                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      742                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      685                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      731                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      732                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      794                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      858                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      921                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      715                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      761                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      715                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      977                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                     1097                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                     1188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                     1099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      664                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                     1235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                     2021                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                     1432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      593                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                     1157                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       494449                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      245.049629                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     147.402723                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     288.016754                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         219085     44.31%     44.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       131738     26.64%     70.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        43693      8.84%     79.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        22796      4.61%     84.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        15362      3.11%     87.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         9595      1.94%     89.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7428      1.50%     90.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5929      1.20%     92.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        38823      7.85%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         494449                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         57195                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        14.008130                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      134.294281                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          57192     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           66023                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         66023                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.632613                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.082710                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.894597                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           62853     95.20%     95.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31            1132      1.71%     96.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39            1165      1.76%     98.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47             145      0.22%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55              61      0.09%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              50      0.08%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71             451      0.68%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              71      0.11%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              27      0.04%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               7      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103              4      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            11      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             4      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            20      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             9      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             4      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             4      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           66023                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    12434281516                       # Total ticks spent queuing
-system.physmem.totMemAccLat               30010606516                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4687020000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13264.59                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           57195                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         57195                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.092281                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.359425                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        8.356307                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           44576     77.94%     77.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            9441     16.51%     94.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             730      1.28%     95.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             284      0.50%     96.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             871      1.52%     97.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             293      0.51%     98.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              48      0.08%     98.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              36      0.06%     98.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              15      0.03%     98.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              17      0.03%     98.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              14      0.02%     98.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              33      0.06%     98.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             518      0.91%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              69      0.12%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              50      0.09%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              58      0.10%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              36      0.06%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.01%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               3      0.01%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.00%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             5      0.01%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.00%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            17      0.03%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             4      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.00%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             2      0.00%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             5      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            20      0.03%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             6      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143            11      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             4      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             3      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             5      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           57195                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    29399013585                       # Total ticks spent queuing
+system.physmem.totMemAccLat               44421851085                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4006090000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       36692.90                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32014.59                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.16                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.11                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.52                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  55442.90                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           0.99                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.35                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        0.94                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.35                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.96                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     702833                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    901319                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.98                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.27                       # Row buffer hit rate for writes
-system.physmem.avgGap                     23876216.06                       # Average gap between requests
-system.physmem.pageHitRate                      74.01                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2165373000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1181503125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3530451600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4001905440                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3384688532160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1300349435715                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29951875881000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34647793082040                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.606693                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49827060150280                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1730413360000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    263420580720                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2094172920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1142653875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3781260600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3969667440                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3384688532160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1299689474040                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29952454794750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34647820555785                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.607223                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49827979372630                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1730413360000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    262496082370                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.physmem.avgWrQLen                        24.42                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     600273                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    798478                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   74.92                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.12                       # Row buffer hit rate for writes
+system.physmem.avgGap                     27330041.71                       # Average gap between requests
+system.physmem.pageHitRate                      73.88                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1812881700                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  963565680                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                2777345760                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               2885715180                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           48801801360.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            38319920670                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             3025839840                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       94040362440                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       72590911200                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       12330316288695                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             12595556394525                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              243.054753                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           51729925726993                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     5744734750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     20754236000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   51334657894500                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 189038733198                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     65464048007                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 206229141045                       # Time in different power states
+system.physmem_1.actEnergy                 1717491300                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  912868275                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                2943350760                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               2814436080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           46544843280.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            38176673400                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             2758502400                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       87988375470                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       69794301120                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       12334956932460                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             12588629106345                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              242.921078                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           51730316233255                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     5091528742                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     19793960000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   51356223942250                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 181755962683                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     66066776003                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 192956617822                       # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -324,9 +355,9 @@ system.realview.nvmem.bw_inst_read::total            2                       # I
 system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
@@ -334,7 +365,7 @@ system.cf0.dma_write_full_pages                  1666                       # Nu
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -364,69 +395,74 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                    214264                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                214264                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        17030                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       164948                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore           21                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       214243                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean     0.140028                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev    46.737844                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-2047       214241    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                    195978                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                195978                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        13491                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       152311                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore           20                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       195958                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean     0.153094                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev    48.869782                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-2047       195956    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::16384-18431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       214243                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       181999                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 24181.814186                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 20419.578200                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 15522.698406                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       180089     98.95%     98.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         1633      0.90%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607          118      0.06%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143           77      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679           52      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           23      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       181999                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples   4819875556                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     1.150179                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0      -723841796    -15.02%    -15.02% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::1      5543717352    115.02%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total   4819875556                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        164949     90.64%     90.64% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         17030      9.36%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       181979                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       214264                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkWaitTime::total       195958                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       165822                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 23748.733582                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 19720.854851                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 19654.042010                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       164137     98.98%     98.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         1390      0.84%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607           75      0.05%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143           54      0.03%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679           79      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           19      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751            7      0.00%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287            4      0.00%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359           53      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       165822                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples  -2782551036                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.846086                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.360866                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0      -428273296     15.39%     15.39% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::1     -2354277740     84.61%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total  -2782551036                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        152312     91.86%     91.86% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         13491      8.14%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       165803                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       195978                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       214264                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       181979                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       195978                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       165803                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       181979                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       396243                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       165803                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       361781                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    168009449                       # DTB read hits
-system.cpu.dtb.read_misses                     157878                       # DTB read misses
-system.cpu.dtb.write_hits                   152852610                       # DTB write hits
-system.cpu.dtb.write_misses                     56386                       # DTB write misses
+system.cpu.dtb.read_hits                    161602593                       # DTB read hits
+system.cpu.dtb.read_misses                     145506                       # DTB read misses
+system.cpu.dtb.write_hits                   146806893                       # DTB write hits
+system.cpu.dtb.write_misses                     50472                       # DTB write misses
 system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               43022                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1067                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    75936                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb_mva_asid               40242                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1033                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    72949                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   8201                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   7287                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     19949                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                168167327                       # DTB read accesses
-system.cpu.dtb.write_accesses               152908996                       # DTB write accesses
+system.cpu.dtb.perms_faults                     19275                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                161748099                       # DTB read accesses
+system.cpu.dtb.write_accesses               146857365                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         320862059                       # DTB hits
-system.cpu.dtb.misses                          214264                       # DTB misses
-system.cpu.dtb.accesses                     321076323                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                         308409486                       # DTB hits
+system.cpu.dtb.misses                          195978                       # DTB misses
+system.cpu.dtb.accesses                     308605464                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -456,674 +492,671 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                    122945                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                122945                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                    120718                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                120718                       # Table walker walks initiated with long descriptors
 system.cpu.itb.walker.walksLongTerminationLevel::Level2         1119                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       110624                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples       122945                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          122945    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       122945                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       111743                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 27331.219853                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 23493.082733                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 18310.002732                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       109587     98.07%     98.07% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071         1865      1.67%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607          133      0.12%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           84      0.08%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679           40      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           22      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       111743                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples   -850328296                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0      -850328296    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total   -850328296                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        110624     99.00%     99.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1119      1.00%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       111743                       # Table walker page sizes translated
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       108838                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       120718                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          120718    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       120718                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       109957                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 27485.576180                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23297.926209                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 24382.701456                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       107960     98.18%     98.18% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         1664      1.51%     99.70% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607           68      0.06%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143           86      0.08%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           74      0.07%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           23      0.02%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751            5      0.00%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359           76      0.07%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       109957                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples   -556629296                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      -556629296    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total   -556629296                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        108838     98.98%     98.98% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1119      1.02%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       109957                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       122945                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       122945                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       120718                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       120718                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       111743                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       111743                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       234688                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    895597591                       # ITB inst hits
-system.cpu.itb.inst_misses                     122945                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       109957                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       109957                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       230675                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    860126625                       # ITB inst hits
+system.cpu.itb.inst_misses                     120718                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               43022                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1067                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    53957                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               40242                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1033                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    52157                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                895720536                       # ITB inst accesses
-system.cpu.itb.hits                         895597591                       # DTB hits
-system.cpu.itb.misses                          122945                       # DTB misses
-system.cpu.itb.accesses                     895720536                       # DTB accesses
-system.cpu.numPwrStateTransitions               32698                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples         16349                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     3072754762.549147                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    59826711358.002258                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows         7060     43.18%     43.18% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         9253     56.60%     99.78% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+10-1e+11            6      0.04%     99.82% # Distribution of time spent in the clock gated state
+system.cpu.itb.inst_accesses                860247343                       # ITB inst accesses
+system.cpu.itb.hits                         860126625                       # DTB hits
+system.cpu.itb.misses                          120718                       # DTB misses
+system.cpu.itb.accesses                     860247343                       # DTB accesses
+system.cpu.numPwrStateTransitions               32322                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples         16161                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     3111677574.020791                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    60407510991.245888                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows         6870     42.51%     42.51% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10         9256     57.27%     99.78% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.81% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            3      0.02%     99.83% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.85% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+11-5.5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::6.5e+11-7e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            2      0.01%     99.86% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::7.5e+11-8e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 1988775178432                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total           16349                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    1584426889584                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50236467612916                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                     103641789005                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::max_value 1988775138696                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total           16161                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    1534067513750                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50287821273750                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                     103643777575                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16349                       # number of quiesce instructions executed
-system.cpu.committedInsts                   895045967                       # Number of instructions committed
-system.cpu.committedOps                    1051780871                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             965574423                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 894989                       # Number of float alu accesses
-system.cpu.num_func_calls                    52935800                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    136802593                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    965574423                       # number of integer instructions
-system.cpu.num_fp_insts                        894989                       # number of float instructions
-system.cpu.num_int_register_reads          1409614532                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          766141547                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              1442074                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              760100                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            235678872                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           235085086                       # number of times the CC registers were written
-system.cpu.num_mem_refs                     320845878                       # number of memory refs
-system.cpu.num_load_insts                   168002679                       # Number of load instructions
-system.cpu.num_store_insts                  152843199                       # Number of store instructions
-system.cpu.num_idle_cycles               100472935225.830063                       # Number of idle cycles
-system.cpu.num_busy_cycles               3168853779.169939                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.030575                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.969425                       # Percentage of idle cycles
-system.cpu.Branches                         199903261                       # Number of branches fetched
+system.cpu.kern.inst.quiesce                    16161                       # number of quiesce instructions executed
+system.cpu.committedInsts                   859596485                       # Number of instructions committed
+system.cpu.committedOps                    1010098639                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             927989339                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 896850                       # Number of float alu accesses
+system.cpu.num_func_calls                    51273640                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    130821573                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    927989339                       # number of integer instructions
+system.cpu.num_fp_insts                        896850                       # number of float instructions
+system.cpu.num_int_register_reads          1348541336                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          735865236                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              1446705                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              758956                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads            224361660                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           223761478                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     308390268                       # number of memory refs
+system.cpu.num_load_insts                   161593947                       # Number of load instructions
+system.cpu.num_store_insts                  146796321                       # Number of store instructions
+system.cpu.num_idle_cycles               100575642547.498062                       # Number of idle cycles
+system.cpu.num_busy_cycles               3068135027.501941                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.029603                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.970397                       # Percentage of idle cycles
+system.cpu.Branches                         191892206                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 729096517     69.28%     69.28% # Class of executed instruction
-system.cpu.op_class::IntMult                  2224980      0.21%     69.49% # Class of executed instruction
-system.cpu.op_class::IntDiv                     97778      0.01%     69.50% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   8      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.50% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc             110423      0.01%     69.51% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     69.51% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.51% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.51% # Class of executed instruction
-system.cpu.op_class::MemRead                168002679     15.96%     85.48% # Class of executed instruction
-system.cpu.op_class::MemWrite               152843199     14.52%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 699904687     69.25%     69.25% # Class of executed instruction
+system.cpu.op_class::IntMult                  2167959      0.21%     69.47% # Class of executed instruction
+system.cpu.op_class::IntDiv                     97409      0.01%     69.48% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   8      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc             111537      0.01%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::MemRead                161593947     15.99%     85.48% # Class of executed instruction
+system.cpu.op_class::MemWrite               146796321     14.52%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 1052375619                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements          10244350                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.965651                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           310416272                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          10244862                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             30.299703                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        3504161500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.965651                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999933                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999933                       # Average percentage of cache occupancy
+system.cpu.op_class::total                 1010671903                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           9712865                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.962733                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           298498000                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9713377                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             30.730610                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        3801165500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.962733                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999927                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999927                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          392                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           71                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          418                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1293353364                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1293353364                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    156944978                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       156944978                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    145025968                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      145025968                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       395817                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        395817                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       335163                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       335163                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3689072                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3689072                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3994801                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3994801                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     302306109                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        302306109                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    302701926                       # number of overall hits
-system.cpu.dcache.overall_hits::total       302701926                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      5326710                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       5326710                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2212553                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2212553                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1311764                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1311764                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1232866                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1232866                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       307422                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       307422                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            3                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            3                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      8772129                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        8772129                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     10083893                       # number of overall misses
-system.cpu.dcache.overall_misses::total      10083893                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  84631439000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  84631439000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  66820707500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  66820707500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  25293878500                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  25293878500                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4522600000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   4522600000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       197000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       197000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 176746025000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 176746025000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 176746025000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 176746025000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    162271688                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    162271688                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    147238521                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    147238521                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1707581                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1707581                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1568029                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1568029                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3996494                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3996494                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3994804                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3994804                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    311078238                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    311078238                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    312785819                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    312785819                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032826                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.032826                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015027                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015027                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.768200                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.768200                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786252                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.786252                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.076923                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.076923                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.tags.tag_accesses        1243014374                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1243014374                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    151150245                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       151150245                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    139360023                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      139360023                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       383359                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        383359                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       333234                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       333234                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3475622                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3475622                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3766718                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3766718                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     290843502                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        290843502                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    291226861                       # number of overall hits
+system.cpu.dcache.overall_hits::total       291226861                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      5063029                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       5063029                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2070213                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2070213                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1203887                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1203887                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1226147                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1226147                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       292765                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       292765                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      8359389                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        8359389                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9563276                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9563276                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  86479051000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  86479051000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  64029512000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  64029512000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  24965286000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  24965286000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4461300000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   4461300000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       167500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 175473849000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 175473849000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 175473849000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 175473849000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    156213274                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    156213274                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    141430236                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    141430236                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1587246                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1587246                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1559381                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1559381                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3768387                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3768387                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3766720                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3766720                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    299202891                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    299202891                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    300790137                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    300790137                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032411                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.032411                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014638                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.014638                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.758475                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.758475                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786304                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.786304                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.077690                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.077690                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.028199                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.028199                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.032239                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.032239                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15888.125879                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15888.125879                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30200.726265                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30200.726265                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20516.324159                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20516.324159                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14711.373942                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14711.373942                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 65666.666667                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 65666.666667                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 20148.589356                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 20148.589356                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17527.558553                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17527.558553                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.027939                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.027939                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.031794                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.031794                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17080.496873                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17080.496873                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30928.948857                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30928.948857                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20360.760985                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20360.760985                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15238.501870                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15238.501870                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83750                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83750                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20991.229024                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20991.229024                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 18348.717427                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 18348.717427                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      7906430                       # number of writebacks
-system.cpu.dcache.writebacks::total           7906430                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21920                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        21920                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21246                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        21246                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70972                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        70972                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        43166                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        43166                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        43166                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        43166                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5304790                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5304790                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2191307                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2191307                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1309953                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1309953                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1232866                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1232866                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       236450                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       236450                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            3                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      8728963                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      8728963                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     10038916                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     10038916                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks      7498102                       # number of writebacks
+system.cpu.dcache.writebacks::total           7498102                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21612                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        21612                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21289                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        21289                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70591                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        70591                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        42901                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        42901                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        42901                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        42901                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5041417                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5041417                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2048924                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2048924                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1203533                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1203533                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1226147                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1226147                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       222174                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       222174                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      8316488                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      8316488                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9520021                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9520021                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33706                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33706                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33710                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67416                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67416                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  78748278500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  78748278500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  63964841000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  63964841000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  21083631000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  21083631000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  24061012500                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  24061012500                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3160913500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3160913500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       194000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       194000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 166774132000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 166774132000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187857763000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 187857763000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6233075000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6233075000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6233075000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6233075000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032691                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032691                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014883                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014883                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.767140                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.767140                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786252                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786252                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.059164                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.059164                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  80551413000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  80551413000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  61232027000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  61232027000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  21569596000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  21569596000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  23739139000                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  23739139000                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3061958500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3061958500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       165500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       165500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165522579000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 165522579000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187092175000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 187092175000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6232858000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6232858000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6232858000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6232858000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032273                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032273                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014487                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014487                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.758252                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.758252                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786304                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786304                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.058957                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.058957                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028060                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.028060                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032095                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.032095                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14844.749462                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14844.749462                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29190.269095                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29190.269095                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16094.952262                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16094.952262                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19516.324159                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19516.324159                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13368.211038                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13368.211038                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 64666.666667                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 64666.666667                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19105.835596                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19105.835596                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18712.952972                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18712.952972                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184924.790838                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184924.790838                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92456.909339                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92456.909339                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements          13792548                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.891104                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           881804526                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          13793060                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             63.931030                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       31603903500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.891104                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999787                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999787                       # Average percentage of cache occupancy
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027795                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.027795                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031650                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031650                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15977.931006                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15977.931006                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29884.967427                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29884.967427                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17921.898278                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17921.898278                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19360.760985                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19360.760985                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13781.803901                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13781.803901                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82750                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82750                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19902.942083                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19902.942083                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19652.496040                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19652.496040                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184918.352816                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.352816                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92453.690519                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92453.690519                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements          13489644                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.886684                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           846636464                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          13490156                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             62.759576                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       32464202500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.886684                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999779                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999779                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          243                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          200                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          276                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          169                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         909390656                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        909390656                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    881804526                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       881804526                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     881804526                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        881804526                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    881804526                       # number of overall hits
-system.cpu.icache.overall_hits::total       881804526                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     13793065                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      13793065                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     13793065                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       13793065                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     13793065                       # number of overall misses
-system.cpu.icache.overall_misses::total      13793065                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 185289814000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 185289814000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 185289814000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 185289814000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 185289814000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 185289814000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    895597591                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    895597591                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    895597591                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    895597591                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    895597591                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    895597591                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015401                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.015401                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.015401                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.015401                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.015401                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.015401                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13433.548961                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13433.548961                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13433.548961                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13433.548961                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13433.548961                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13433.548961                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         873616786                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        873616786                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    846636464                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       846636464                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     846636464                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        846636464                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    846636464                       # number of overall hits
+system.cpu.icache.overall_hits::total       846636464                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     13490161                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      13490161                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     13490161                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       13490161                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     13490161                       # number of overall misses
+system.cpu.icache.overall_misses::total      13490161                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 183617881000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 183617881000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 183617881000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 183617881000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 183617881000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 183617881000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    860126625                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    860126625                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    860126625                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    860126625                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    860126625                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    860126625                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015684                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.015684                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.015684                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.015684                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.015684                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.015684                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13611.244595                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13611.244595                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13611.244595                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13611.244595                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13611.244595                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13611.244595                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks     13792548                       # number of writebacks
-system.cpu.icache.writebacks::total          13792548                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13793065                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     13793065                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     13793065                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     13793065                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     13793065                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     13793065                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     13489644                       # number of writebacks
+system.cpu.icache.writebacks::total          13489644                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13490161                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     13490161                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     13490161                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     13490161                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     13490161                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     13490161                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171496749000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 171496749000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171496749000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 171496749000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171496749000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 171496749000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   3263374000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   3263374000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   3263374000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   3263374000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.015401                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.015401                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.015401                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.015401                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.015401                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.015401                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12433.548961                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12433.548961                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12433.548961                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12433.548961                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12433.548961                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12433.548961                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75672.440580                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75672.440580                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75672.440580                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75672.440580                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements          1308215                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65291.954914                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           46007809                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1371583                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            33.543584                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       6631976500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 10023.392915                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   424.218871                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   466.075042                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6280.682260                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 48097.585826                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.152945                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.006473                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007112                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.095836                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.733911                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996276                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          271                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63097                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          271                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          779                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5781                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56275                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004135                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962784                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        391701839                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       391701839                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       351291                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       234298                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         585589                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks      7906430                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      7906430                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     13790970                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     13790970                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        26514                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        26514                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1636834                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1636834                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     13714488                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     13714488                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6572328                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6572328                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       722608                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       722608                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       351291                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       234298                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     13714488                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      8209162                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        22509239                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       351291                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       234298                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     13714488                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      8209162                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       22509239                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         4188                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         4011                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         8199                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         3956                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         3956                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       524003                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       524003                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        78577                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        78577                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       278865                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       278865                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       510258                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       510258                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         4188                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         4011                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        78577                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       802868                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        889644                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker         4188                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         4011                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        78577                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       802868                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       889644                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    360029500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    354230500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    714260000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     69357500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     69357500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       189500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total       189500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  43047428500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  43047428500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   6529692000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   6529692000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  23627731000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  23627731000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data       478000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::total       478000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    360029500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    354230500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   6529692000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  66675159500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  73919111500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    360029500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    354230500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   6529692000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  66675159500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  73919111500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       355479                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       238309                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       593788                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      7906430                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      7906430                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks     13790970                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total     13790970                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        30470                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        30470                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            3                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            3                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2160837                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      2160837                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     13793065                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     13793065                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6851193                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      6851193                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1232866                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1232866                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       355479                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       238309                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     13793065                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9012030                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     23398883                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       355479                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       238309                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     13793065                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9012030                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     23398883                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.011781                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.016831                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.013808                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.129833                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.129833                       # miss rate for UpgradeReq accesses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170127720000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 170127720000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170127720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 170127720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170127720000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 170127720000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   3557271000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   3557271000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   3557271000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   3557271000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.015684                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.015684                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.015684                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.015684                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.015684                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.015684                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12611.244595                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12611.244595                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12611.244595                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12611.244595                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12611.244595                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12611.244595                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82487.443478                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82487.443478                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82487.443478                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82487.443478                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements          1158676                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65394.159072                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           44435371                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1220446                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            36.409125                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       6958052500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 10890.998401                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   465.362855                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   539.855564                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6670.163394                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 46827.778856                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.166183                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.007101                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.008238                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.101779                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.714535                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997836                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          278                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        61492                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          278                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          199                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          829                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5790                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54645                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004242                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.938293                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        377782006                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       377782006                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       307317                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       227975                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         535292                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      7498102                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      7498102                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     13488047                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     13488047                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data        24835                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total        24835                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1605264                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1605264                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     13414164                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     13414164                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6210983                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6210983                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       729246                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       729246                       # number of InvalidateReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker       307317                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker       227975                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst     13414164                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      7816247                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        21765703                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker       307317                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker       227975                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst     13414164                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      7816247                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       21765703                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3382                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3425                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         6807                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         3962                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         3962                       # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       414863                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       414863                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        75997                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        75997                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       256141                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       256141                       # number of ReadSharedReq misses
+system.cpu.l2cache.InvalidateReq_misses::cpu.data       496901                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       496901                       # number of InvalidateReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker         3382                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker         3425                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        75997                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       671004                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        753808                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker         3382                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker         3425                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        75997                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       671004                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       753808                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    458444500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    422573500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    881018000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     69853000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     69853000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162500                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162500                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  40877442000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  40877442000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   8773195000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   8773195000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  30189333000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  30189333000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data       454500                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::total       454500                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    458444500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    422573500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   8773195000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  71066775000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  80720988000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    458444500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    422573500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   8773195000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  71066775000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  80720988000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       310699                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       231400                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       542099                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      7498102                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      7498102                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     13488047                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     13488047                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        28797                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        28797                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      2020127                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      2020127                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     13490161                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     13490161                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6467124                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      6467124                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1226147                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1226147                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       310699                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       231400                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     13490161                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      8487251                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     22519511                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       310699                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       231400                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     13490161                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      8487251                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     22519511                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.010885                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.014801                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.012557                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.137584                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.137584                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.242500                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.242500                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005697                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005697                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.040703                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.040703                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.413880                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.413880                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.011781                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.016831                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005697                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.089088                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.038021                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.011781                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.016831                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005697                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.089088                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.038021                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85966.929322                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88314.759412                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 87115.501890                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17532.229525                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17532.229525                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 63166.666667                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 63166.666667                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82151.110776                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82151.110776                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83099.278415                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83099.278415                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84728.205404                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84728.205404                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data     0.936781                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total     0.936781                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85966.929322                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88314.759412                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83099.278415                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83046.228645                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 83088.416827                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85966.929322                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88314.759412                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83099.278415                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83046.228645                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 83088.416827                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.205365                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.205365                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005634                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005634                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.039607                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.039607                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.405254                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.405254                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.010885                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.014801                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005634                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.079060                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.033474                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.010885                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.014801                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005634                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.079060                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.033474                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 135554.257836                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 123379.124088                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 129428.235640                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17630.742049                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17630.742049                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81250                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81250                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98532.387800                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98532.387800                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 115441.333211                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 115441.333211                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 117862.165760                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 117862.165760                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data     0.914669                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total     0.914669                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135554.257836                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 123379.124088                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 115441.333211                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105911.104852                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 107084.281409                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135554.257836                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 123379.124088                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 115441.333211                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105911.104852                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 107084.281409                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks      1123249                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1123249                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         4188                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4011                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         8199                       # number of ReadReq MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         3956                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         3956                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       524003                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       524003                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        78577                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        78577                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       278865                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       278865                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       510258                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       510258                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         4188                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         4011                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        78577                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       802868                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       889644                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         4188                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         4011                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        78577                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       802868                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       889644                       # number of overall MSHR misses
+system.cpu.l2cache.writebacks::writebacks       985073                       # number of writebacks
+system.cpu.l2cache.writebacks::total           985073                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3382                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3425                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         6807                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         3962                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         3962                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       414863                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       414863                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        75997                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        75997                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       256141                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       256141                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       496901                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       496901                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3382                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3425                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        75997                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       671004                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       753808                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3382                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3425                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        75997                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       671004                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       753808                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33706                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        76831                       # number of ReadReq MSHR uncacheable
@@ -1132,156 +1165,154 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33710
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67416                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total       110541                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    318149500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    314120500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    632270000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     75426500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     75426500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       159500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       159500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  37807398500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  37807398500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   5743922000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   5743922000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  20839044573                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  20839044573                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data   9521744500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total   9521744500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    318149500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    314120500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5743922000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  58646443073                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  65022635073                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    318149500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    314120500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5743922000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  58646443073                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  65022635073                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2724311500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5810947000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8535258500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2724311500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5810947000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   8535258500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.011781                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.016831                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013808                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.129833                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.129833                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    424624500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    388323500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    812948000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     75436500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     75436500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       142500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       142500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  36728812000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  36728812000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   8013225000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   8013225000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  27627908030                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  27627908030                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data   9273801000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total   9273801000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    424624500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    388323500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8013225000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  64356720030                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  73182893030                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    424624500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    388323500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8013225000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  64356720030                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  73182893030                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3018208500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5810725000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8828933500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3018208500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5810725000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   8828933500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.010885                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.014801                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.012557                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.137584                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.137584                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.242500                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.242500                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005697                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005697                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.040703                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.040703                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.413880                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.413880                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.011781                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.016831                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005697                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.089088                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.038021                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.011781                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.016831                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005697                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.089088                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.038021                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78314.759412                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77115.501890                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19066.354904                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19066.354904                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53166.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72151.110776                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72151.110776                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73099.278415                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73099.278415                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74728.074778                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74728.074778                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18660.647163                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18660.647163                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78314.759412                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73099.278415                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73046.183274                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73088.375882                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78314.759412                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73099.278415                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73046.183274                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73088.375882                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63172.440580                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172400.967187                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111091.336830                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63172.440580                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86195.369052                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 77213.509015                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     48633709                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     24595755                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.205365                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.205365                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005634                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005634                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.039607                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.039607                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.405254                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.405254                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.010885                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.014801                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005634                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.079060                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.033474                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.010885                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.014801                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005634                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.079060                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.033474                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 113379.124088                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 119428.235640                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19040.005048                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19040.005048                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        71250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        71250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88532.387800                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88532.387800                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 105441.333211                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 105441.333211                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 107862.107316                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 107862.107316                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18663.276991                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18663.276991                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 113379.124088                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 105441.333211                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95911.082542                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 97084.261549                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 113379.124088                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 105441.333211                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95911.082542                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 97084.261549                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69987.443478                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172394.380822                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114913.687184                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69987.443478                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86192.076065                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 79870.215576                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests     46934872                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     23731321                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1745                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2030                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2030                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1965                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1965                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq        1068832                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      21713957                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq        1010835                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      20969000                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33710                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33710                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      9029679                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     13792548                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2522886                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        30473                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        30476                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2160837                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2160837                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     13793065                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6853863                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1261524                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1232866                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41464928                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     30930790                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       605749                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       980040                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          73981507                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1765651732                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1083027398                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      1906472                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2843832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2853429434                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1738629                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              75129128                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     26510522                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.020074                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.140252                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8483175                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     13489644                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2388366                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        28800                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        28802                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2020127                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2020127                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     13490161                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6470086                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1256693                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1226147                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     40556216                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29332974                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       592159                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       883944                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          71365293                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1726880020                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1023309382                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      1851200                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2485592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2754526194                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1584975                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic              66236232                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     25469090                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.019778                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.139236                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           25978363     97.99%     97.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             532159      2.01%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           24965367     98.02%     98.02% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             503723      1.98%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       26510522                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    46319770000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       25469090                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    44744307000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1608386                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1625890                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   20732722500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   20278366500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14200291468                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13408934951                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     367440000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     360759000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     624561000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     573245000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40312                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40312                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40346                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40346                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1298,11 +1329,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230982                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230982                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231050                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231050                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353766                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353834                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1317,16 +1348,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334360                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334360                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334632                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334632                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492280                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             42148500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492552                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             42150000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               320500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               321500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
@@ -1344,75 +1375,75 @@ system.iobus.reqLayer16.occupancy               17000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25722000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25714500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            38610500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            38601500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           568931558                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           569287162                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147742000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147810000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115472                       # number of replacements
-system.iocache.tags.tagsinuse               10.457340                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115506                       # number of replacements
+system.iocache.tags.tagsinuse               10.457104                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115488                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115522                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13153794616000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.511175                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.946165                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.219448                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.434135                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.653584                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13154766855000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.510739                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.946366                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219421                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.434148                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653569                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039776                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039776                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1040082                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040082                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8827                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8864                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8861                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8898                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115491                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115531                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115525                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115565                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115491                       # number of overall misses
-system.iocache.overall_misses::total           115531                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1606262152                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1611348152                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115525                       # number of overall misses
+system.iocache.overall_misses::total           115565                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5086500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   2019214145                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   2024300645                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12771737406                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12771737406                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14377999558                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14383436558                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14377999558                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14383436558                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13409527517                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13409527517                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5437500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15428741662                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15434179162                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5437500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15428741662                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15434179162                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8827                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8864                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8861                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8898                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115491                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115531                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115525                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115565                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115491                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115531                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115525                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115565                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1426,53 +1457,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 181971.468449                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 181785.666968                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 227876.554001                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 227500.634412                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119738.031632                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 119738.031632                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124494.545532                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124498.503068                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124494.545532                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124498.503068                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         31144                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125717.463408                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125717.463408                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 133553.271257                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 133554.096500                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 133553.271257                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 133554.096500                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         51750                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3368                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3356                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.247031                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    15.420143                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8827                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8864                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8861                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8898                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115491                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115531                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115525                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115565                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115491                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115531                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1164912152                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1168148152                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115525                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115565                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1576164145                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1579400645                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7431704095                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7431704095                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8596616247                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8600053247                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8596616247                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8600053247                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8069228353                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8069228353                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3437500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9645392498                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9648829998                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3437500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9645392498                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9648829998                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1486,95 +1517,95 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131971.468449                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 131785.666968                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177876.554001                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 177500.634412                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69673.967740                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69673.967740                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74435.378055                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 74439.356078                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74435.378055                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 74439.356078                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests       2941993                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1455813                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3308                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75650.907082                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75650.907082                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 83491.819935                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 83492.666447                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 83491.819935                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 83492.666447                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests       2643885                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      1308749                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3600                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               76831                       # Transaction distribution
-system.membus.trans_dist::ReadResp             451336                       # Transaction distribution
+system.membus.trans_dist::ReadResp             424674                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1229879                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           192681                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4527                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1091703                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           181416                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4530                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            523443                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           523443                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        374505                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        616914                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            414305                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           414305                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        347843                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        603558                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3690757                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3820461                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237403                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237403                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4057864                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3256260                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3385964                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237234                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237234                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                3623198                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    128940576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    129110426                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7233920                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7233920                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               136344346                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3126                       # Total snoops (count)
-system.membus.snoopTraffic                     199552                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           1629933                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.019638                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.138754                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    111403936                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    111573786                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7218752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7218752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               118792538                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3397                       # Total snoops (count)
+system.membus.snoopTraffic                     216896                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           1480779                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.023089                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.150185                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 1597924     98.04%     98.04% # Request fanout histogram
-system.membus.snoop_fanout::1                   32009      1.96%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 1446590     97.69%     97.69% # Request fanout histogram
+system.membus.snoop_fanout::1                   34189      2.31%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             1629933                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           106906500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             1480779                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           106893000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5804000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5820500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8036011189                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7180364209                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4923968289                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         4203282304                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44661763                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44877398                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -1617,28 +1648,28 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal
index 0cb0b7645..42937e8d5 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal
@@ -32,135 +32,135 @@
 [    0.000000] NR_IRQS:64 nr_irqs:64 0
 [    0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
 [    0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[    0.000044] Console: colour dummy device 80x25
-[    0.000048] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[    0.000050] pid_max: default: 32768 minimum: 301
-[    0.000073] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[    0.000075] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[    0.000316] hw perfevents: no hardware support available
-[    1.060136] CPU1: failed to come online
-[    2.080267] CPU2: failed to come online
-[    3.100398] CPU3: failed to come online
-[    3.100403] Brought up 1 CPUs
-[    3.100405] SMP: Total of 1 processors activated.
-[    3.100517] devtmpfs: initialized
-[    3.101614] atomic64_test: passed
-[    3.101697] regulator-dummy: no parameters
-[    3.102519] NET: Registered protocol family 16
-[    3.102798] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[    3.102809] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[    3.104232] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[    3.104240] Serial: AMBA PL011 UART driver
-[    3.104622] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[    3.104693] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[    3.105277] console [ttyAMA0] enabled
-[    3.105422] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[    3.105471] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[    3.105522] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[    3.105568] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[    3.130937] 3V3: 3300 mV 
-[    3.131019] vgaarb: loaded
-[    3.131116] SCSI subsystem initialized
-[    3.131186] libata version 3.00 loaded.
-[    3.131272] usbcore: registered new interface driver usbfs
-[    3.131299] usbcore: registered new interface driver hub
-[    3.131354] usbcore: registered new device driver usb
-[    3.131399] pps_core: LinuxPPS API ver. 1 registered
-[    3.131409] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[    3.131433] PTP clock support registered
-[    3.131670] Switched to clocksource arch_sys_counter
-[    3.133769] NET: Registered protocol family 2
-[    3.133932] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[    3.133964] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[    3.134004] TCP: Hash tables configured (established 2048 bind 2048)
-[    3.134042] TCP: reno registered
-[    3.134050] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[    3.134070] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[    3.134144] NET: Registered protocol family 1
-[    3.134216] RPC: Registered named UNIX socket transport module.
-[    3.134227] RPC: Registered udp transport module.
-[    3.134236] RPC: Registered tcp transport module.
-[    3.134245] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[    3.134259] PCI: CLS 0 bytes, default 64
-[    3.134575] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[    3.134796] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[    3.138336] fuse init (API version 7.23)
-[    3.138502] msgmni has been set to 469
-[    3.143073] io scheduler noop registered
-[    3.143173] io scheduler cfq registered (default)
-[    3.144095] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[    3.144109] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
-[    3.144122] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[    3.144136] pci_bus 0000:00: root bus resource [bus 00-ff]
-[    3.144147] pci_bus 0000:00: scanning bus
-[    3.144161] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[    3.144177] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[    3.144195] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[    3.144258] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[    3.144272] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]
-[    3.144285] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]
-[    3.144297] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]
-[    3.144310] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]
-[    3.144322] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]
-[    3.144336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[    3.144395] pci_bus 0000:00: fixups for bus
-[    3.144405] pci_bus 0000:00: bus scan returning with max=00
-[    3.144419] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[    3.144446] pci 0000:00:00.0: fixup irq: got 33
-[    3.144456] pci 0000:00:00.0: assigning IRQ 33
-[    3.144470] pci 0000:00:01.0: fixup irq: got 34
-[    3.144480] pci 0000:00:01.0: assigning IRQ 34
-[    3.144494] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[    3.144509] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[    3.144524] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[    3.144538] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]
-[    3.144552] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]
-[    3.144565] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]
-[    3.144578] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]
-[    3.144591] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]
-[    3.145478] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[    3.146000] ata_piix 0000:00:01.0: version 2.13
-[    3.146012] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[    3.146049] ata_piix 0000:00:01.0: enabling bus mastering
-[    3.146644] scsi0 : ata_piix
-[    3.146827] scsi1 : ata_piix
-[    3.146881] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[    3.146894] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[    3.147093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[    3.147106] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[    3.147129] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[    3.147142] e1000 0000:00:00.0: enabling bus mastering
-[    3.301707] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[    3.301718] ata1.00: 2096640 sectors, multi 0: LBA 
-[    3.301753] ata1.00: configured for UDMA/33
-[    3.301838] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
-[    3.302037] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[    3.302073] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[    3.302130] sd 0:0:0:0: [sda] Write Protect is off
-[    3.302141] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[    3.302170] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[    3.302373]  sda: sda1
-[    3.302577] sd 0:0:0:0: [sda] Attached SCSI disk
-[    3.422032] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[    3.422047] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[    3.422076] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[    3.422087] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[    3.422118] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[    3.422131] igb: Copyright (c) 2007-2014 Intel Corporation.
-[    3.422262] usbcore: registered new interface driver usb-storage
-[    3.422357] mousedev: PS/2 mouse device common for all mice
-[    3.422646] usbcore: registered new interface driver usbhid
-[    3.422657] usbhid: USB HID core driver
-[    3.422710] TCP: cubic registered
-[    3.422720] NET: Registered protocol family 17
-[    3.423338] VFS: Mounted root (ext2 filesystem) on device 8:1.
-[    3.423384] devtmpfs: mounted
-[    3.423472] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[    0.000040] Console: colour dummy device 80x25
+[    0.000043] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[    0.000046] pid_max: default: 32768 minimum: 301
+[    0.000066] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[    0.000069] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[    0.000252] hw perfevents: no hardware support available
+[    1.060135] CPU1: failed to come online
+[    2.080266] CPU2: failed to come online
+[    3.100397] CPU3: failed to come online
+[    3.100402] Brought up 1 CPUs
+[    3.100404] SMP: Total of 1 processors activated.
+[    3.100503] devtmpfs: initialized
+[    3.101571] atomic64_test: passed
+[    3.101646] regulator-dummy: no parameters
+[    3.102401] NET: Registered protocol family 16
+[    3.102664] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[    3.102675] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[    3.103283] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[    3.103290] Serial: AMBA PL011 UART driver
+[    3.103646] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[    3.103712] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[    3.104302] console [ttyAMA0] enabled
+[    3.104405] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[    3.104456] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[    3.104507] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[    3.104554] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[    3.131002] 3V3: 3300 mV 
+[    3.131076] vgaarb: loaded
+[    3.131168] SCSI subsystem initialized
+[    3.131239] libata version 3.00 loaded.
+[    3.131320] usbcore: registered new interface driver usbfs
+[    3.131346] usbcore: registered new interface driver hub
+[    3.131401] usbcore: registered new device driver usb
+[    3.131444] pps_core: LinuxPPS API ver. 1 registered
+[    3.131455] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[    3.131477] PTP clock support registered
+[    3.131699] Switched to clocksource arch_sys_counter
+[    3.133732] NET: Registered protocol family 2
+[    3.133887] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[    3.133915] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[    3.133949] TCP: Hash tables configured (established 2048 bind 2048)
+[    3.133976] TCP: reno registered
+[    3.133984] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[    3.134003] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[    3.134067] NET: Registered protocol family 1
+[    3.134134] RPC: Registered named UNIX socket transport module.
+[    3.134145] RPC: Registered udp transport module.
+[    3.134154] RPC: Registered tcp transport module.
+[    3.134163] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[    3.134177] PCI: CLS 0 bytes, default 64
+[    3.134494] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[    3.134701] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[    3.138130] fuse init (API version 7.23)
+[    3.138291] msgmni has been set to 469
+[    3.142786] io scheduler noop registered
+[    3.142885] io scheduler cfq registered (default)
+[    3.143673] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[    3.143688] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
+[    3.143701] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[    3.143715] pci_bus 0000:00: root bus resource [bus 00-ff]
+[    3.143727] pci_bus 0000:00: scanning bus
+[    3.143740] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[    3.143755] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[    3.143773] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[    3.143833] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[    3.143848] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]
+[    3.143860] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]
+[    3.143873] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]
+[    3.143886] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]
+[    3.143899] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]
+[    3.143912] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[    3.143970] pci_bus 0000:00: fixups for bus
+[    3.143980] pci_bus 0000:00: bus scan returning with max=00
+[    3.143994] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[    3.144020] pci 0000:00:00.0: fixup irq: got 33
+[    3.144030] pci 0000:00:00.0: assigning IRQ 33
+[    3.144044] pci 0000:00:01.0: fixup irq: got 34
+[    3.144054] pci 0000:00:01.0: assigning IRQ 34
+[    3.144070] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[    3.144084] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[    3.144099] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[    3.144114] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]
+[    3.144127] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]
+[    3.144141] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]
+[    3.144154] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]
+[    3.144168] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]
+[    3.145036] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[    3.145534] ata_piix 0000:00:01.0: version 2.13
+[    3.145546] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[    3.145577] ata_piix 0000:00:01.0: enabling bus mastering
+[    3.146149] scsi0 : ata_piix
+[    3.146327] scsi1 : ata_piix
+[    3.146380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[    3.146394] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[    3.146583] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[    3.146596] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[    3.146618] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[    3.146632] e1000 0000:00:00.0: enabling bus mastering
+[    3.301733] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[    3.301744] ata1.00: 2096640 sectors, multi 0: LBA 
+[    3.301779] ata1.00: configured for UDMA/33
+[    3.301852] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5
+[    3.302048] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[    3.302084] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[    3.302142] sd 0:0:0:0: [sda] Write Protect is off
+[    3.302153] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[    3.302182] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[    3.302382]  sda: sda1
+[    3.302584] sd 0:0:0:0: [sda] Attached SCSI disk
+[    3.422057] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[    3.422072] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[    3.422102] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[    3.422113] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[    3.422144] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[    3.422157] igb: Copyright (c) 2007-2014 Intel Corporation.
+[    3.422289] usbcore: registered new interface driver usb-storage
+[    3.422380] mousedev: PS/2 mouse device common for all mice
+[    3.422670] usbcore: registered new interface driver usbhid
+[    3.422681] usbhid: USB HID core driver
+[    3.422731] TCP: cubic registered
+[    3.422741] NET: Registered protocol family 17
+[    3.423331] VFS: Mounted root (ext2 filesystem) on device 8:1.
+[    3.423377] devtmpfs: mounted
+[    3.423427] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
 
INIT: version 2.88 booting

 Starting udev
-[    3.470435] udevd[607]: starting version 182
+[    3.470296] udevd[607]: starting version 182
 Starting Bootlog daemon: bootlogd.

-[    3.596617] random: dd urandom read with 22 bits of entropy available
+[    3.606651] random: dd urandom read with 20 bits of entropy available
 Populating dev cache

 net.ipv4.conf.default.rp_filter = 1

 net.ipv4.conf.all.rp_filter = 1

@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory

 
INIT: Entering runlevel: 5


 Configuring network interfaces... udhcpc (v1.21.1) started

-[    3.791906] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[    3.801935] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
 Sending discover...

 Sending discover...

 Sending discover...

diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
index 20272ec5e..459e4731f 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
@@ -151,7 +151,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -631,7 +631,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -691,7 +691,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -880,6 +880,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -891,7 +892,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -899,29 +900,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -941,6 +949,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:268435455
+range=0:268435455:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -972,9 +981,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
index 1a3679afb..06eacea30 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 15:03:02
-gem5 executing on e108600-lin, pid 24162
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:43:02
+gem5 executing on e108600-lin, pid 17345
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -26,4 +26,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 62408957500 because target called exit()
+Exiting @ tick 62552970500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
index 2d36751f4..38958d98d 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.062421                       # Number of seconds simulated
-sim_ticks                                 62420912500                       # Number of ticks simulated
-final_tick                                62420912500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.062553                       # Number of seconds simulated
+sim_ticks                                 62552970500                       # Number of ticks simulated
+final_tick                                62552970500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 255603                       # Simulator instruction rate (inst/s)
-host_op_rate                                   256876                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              176097831                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 405340                       # Number of bytes of host memory used
-host_seconds                                   354.47                       # Real time elapsed on the host
+host_inst_rate                                 185964                       # Simulator instruction rate (inst/s)
+host_op_rate                                   186891                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              128391357                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 403424                       # Number of bytes of host memory used
+host_seconds                                   487.21                       # Real time elapsed on the host
 sim_insts                                    90602850                       # Number of instructions simulated
 sim_ops                                      91054081                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             49472                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            947264                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               996736                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           49472                       # Nu
 system.physmem.num_reads::cpu.inst                773                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14801                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                 15574                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               792555                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             15175427                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15967982                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          792555                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             792555                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              792555                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            15175427                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               15967982                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               790882                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             15143390                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15934271                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          790882                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             790882                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              790882                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            15143390                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               15934271                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                         15574                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                       15574                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     62420817500                       # Total gap between requests
+system.physmem.totGap                     62552869500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,8 +91,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     15458                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       110                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     15454                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       114                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -188,28 +188,28 @@ system.physmem.wrQLenPdf::61                        0                       # Wh
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples         1540                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      645.984416                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     440.038624                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     401.127365                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            251     16.30%     16.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          179     11.62%     27.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           84      5.45%     33.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           75      4.87%     38.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           76      4.94%     43.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           73      4.74%     47.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           57      3.70%     51.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           48      3.12%     54.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          697     45.26%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      646.524675                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     437.476336                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     402.605762                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            259     16.82%     16.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          178     11.56%     28.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           79      5.13%     33.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           62      4.03%     37.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           82      5.32%     42.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           81      5.26%     48.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           41      2.66%     50.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           66      4.29%     55.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          692     44.94%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total           1540                       # Bytes accessed per row activation
-system.physmem.totQLat                       72080000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 364092500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                      211081250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 503093750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     77870000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4628.23                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       13553.44                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23378.23                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.97                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32303.44                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          15.93                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       15.97                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       15.93                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.12                       # Data bus utilization in percentage
@@ -217,48 +217,58 @@ system.physmem.busUtilRead                       0.12                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14024                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      14027                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.05                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   90.07                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      4008014.48                       # Average gap between requests
-system.physmem.pageHitRate                      90.05                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    6335280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3456750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  63648000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      4016493.48                       # Average gap between requests
+system.physmem.pageHitRate                      90.07                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    6047580                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3202980                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  58533720                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4076616960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2557911195                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            35205114000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41913082185                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.524455                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    58558754750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2084160000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1773814250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5292000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2887500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  57462600                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           210821520.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy              136599930                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                8776800                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy         736788270                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy         212075520                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        14428808400                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              15801654720                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              252.612376                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime            62230500750                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE        9906000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF        89372000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    60062510500                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN    552254250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       223131000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN   1615796750                       # Time in different power states
+system.physmem_1.actEnergy                    4998000                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2641320                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  52664640                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4076616960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2600892900                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            35167410750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41910562710                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.484088                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    58497118250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2084160000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1836331750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                20808241                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          17115627                       # Number of conditional branches predicted
+system.physmem_1.refreshEnergy           256919520.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy              136420380                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               13274400                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy         827381220                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy         248160000                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        14377425165                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              15919954335                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              254.503567                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime            62217855000                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE       20713000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       109118000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    59758396500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN    646214750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       203977250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN   1814551000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                20808248                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          17115636                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            756798                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8965661                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 8840824                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups              8965663                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 8840828                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.607610                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             98.607632                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                   61995                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups           26211                       # Number of indirect predictor lookups.
@@ -266,7 +276,7 @@ system.cpu.branchPred.indirectHits              24795                       # Nu
 system.cpu.branchPred.indirectMisses             1416                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted          665                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -296,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -326,7 +336,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -356,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -387,16 +397,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     62420912500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        124841825                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        125105941                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    90602850                       # Number of instructions committed
 system.cpu.committedOps                      91054081                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2182225                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2182224                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.377902                       # CPI: cycles per instruction
-system.cpu.ipc                               0.725741                       # IPC: instructions per cycle
+system.cpu.cpi                               1.380817                       # CPI: cycles per instruction
+system.cpu.ipc                               0.724209                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu                63822829     70.09%     70.09% # Class of committed instruction
 system.cpu.op_class_0::IntMult                  10474      0.01%     70.10% # Class of committed instruction
@@ -432,60 +442,60 @@ system.cpu.op_class_0::MemWrite               4744844      5.21%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                 91054081                       # Class of committed instruction
-system.cpu.tickCycles                       110516273                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        14325552                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                       110521627                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        14584314                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            946101                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3621.404220                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26274921                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3621.108293                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26274912                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            950197                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.652077                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       20706654500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3621.404220                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.884132                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.884132                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs             27.652068                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       20754063500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3621.108293                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.884060                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.884060                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          242                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2205                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1649                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          232                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2202                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1662                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          55461265                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         55461265                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     21605938                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21605938                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4660701                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4660701                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          55461283                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         55461283                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     21605963                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21605963                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4660667                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4660667                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          508                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           508                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      26266639                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26266639                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26267147                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26267147                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       906329                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        906329                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        74280                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        74280                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      26266630                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26266630                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26267138                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26267138                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       906313                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        906313                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        74314                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        74314                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            4                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            4                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       980609                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         980609                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       980613                       # number of overall misses
-system.cpu.dcache.overall_misses::total        980613                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11804222500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11804222500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2566012000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2566012000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  14370234500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14370234500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  14370234500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14370234500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22512267                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22512267                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       980627                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         980627                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       980631                       # number of overall misses
+system.cpu.dcache.overall_misses::total        980631                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11831745500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11831745500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2760211000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2760211000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  14591956500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14591956500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  14591956500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14591956500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22512276                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22512276                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          512                       # number of SoftPFReq accesses(hits+misses)
@@ -494,28 +504,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     27247248                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     27247248                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     27247760                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     27247760                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     27247257                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27247257                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     27247769                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27247769                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040259                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.040259                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015687                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015687                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015695                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015695                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.007812                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.007812                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.035989                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.035989                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.035990                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.035990                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.035989                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.035989                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13024.213613                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13024.213613                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34545.126548                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34545.126548                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.397930                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14654.397930                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.338154                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14654.338154                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13054.811638                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13054.811638                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.543801                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.543801                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14880.231219                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14880.231219                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14880.170523                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14880.170523                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -524,14 +534,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.writebacks::writebacks       943282                       # number of writebacks
 system.cpu.dcache.writebacks::total            943282                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2899                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         2899                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27516                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        27516                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        30415                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        30415                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        30415                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        30415                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2883                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         2883                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27550                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        27550                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        30433                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        30433                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        30433                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        30433                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903430                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       903430                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46764                       # number of WriteReq MSHR misses
@@ -542,16 +552,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       950194
 system.cpu.dcache.demand_mshr_misses::total       950194                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       950197                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       950197                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10862380000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10862380000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1495373500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1495373500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       158000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       158000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12357753500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12357753500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12357911500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12357911500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10889954000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10889954000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1596188500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1596188500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       170000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       170000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12486142500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12486142500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12486312500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12486312500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040131                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040131                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009876                       # mshr miss rate for WriteReq accesses
@@ -562,71 +572,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034873
 system.cpu.dcache.demand_mshr_miss_rate::total     0.034873                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034872                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.034872                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.488261                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.488261                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31977.022924                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31977.022924                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52666.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52666.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13005.505718                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13005.505718                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13005.630938                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13005.630938                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12054.009719                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12054.009719                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.847917                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.847917                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.624441                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.624441                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.761863                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.761863                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 5                       # number of replacements
-system.cpu.icache.tags.tagsinuse           689.589449                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27835051                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           689.568004                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27835083                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               801                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          34750.375780                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          34750.415730                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   689.589449                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.336714                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.336714                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   689.568004                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.336703                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.336703                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          796                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          740                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.388672                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          55672505                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         55672505                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     27835051                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27835051                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27835051                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27835051                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27835051                       # number of overall hits
-system.cpu.icache.overall_hits::total        27835051                       # number of overall hits
+system.cpu.icache.tags.tag_accesses          55672569                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         55672569                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     27835083                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27835083                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27835083                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27835083                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27835083                       # number of overall hits
+system.cpu.icache.overall_hits::total        27835083                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          801                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           801                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          801                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            801                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          801                       # number of overall misses
 system.cpu.icache.overall_misses::total           801                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     60780500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     60780500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     60780500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     60780500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     60780500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     60780500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27835852                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27835852                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27835852                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27835852                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27835852                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27835852                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     71410000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     71410000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     71410000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     71410000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     71410000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     71410000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27835884                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27835884                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27835884                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27835884                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27835884                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27835884                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000029                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000029                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75880.774032                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75880.774032                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75880.774032                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75880.774032                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75880.774032                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75880.774032                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.061174                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 89151.061174                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.061174                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 89151.061174                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.061174                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 89151.061174                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -641,36 +651,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          801
 system.cpu.icache.demand_mshr_misses::total          801                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          801                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          801                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     59979500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     59979500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     59979500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     59979500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     59979500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     59979500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     70609000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     70609000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     70609000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     70609000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     70609000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     70609000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000029                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74880.774032                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74880.774032                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74880.774032                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 74880.774032                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74880.774032                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 74880.774032                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.061174                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.061174                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.061174                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.061174                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.061174                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.061174                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        11312.672856                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        11307.978899                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1881373                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs            15574                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs           120.802170                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.593915                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 10638.078941                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020587                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.324648                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.345235                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.572897                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.406002                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020586                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.324506                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.345092                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        15574                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
@@ -680,7 +690,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15454
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.475281                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         15191206                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        15191206                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks       943282                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       943282                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks            4                       # number of WritebackClean hits
@@ -709,18 +719,18 @@ system.cpu.l2cache.demand_misses::total         15581                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          774                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        14807                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        15581                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1081439500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1081439500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     58471000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     58471000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     21652500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     21652500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     58471000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1103092000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1161563000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     58471000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1103092000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1161563000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1182252000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1182252000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     69100500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     69100500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     49237000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     49237000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     69100500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1231489000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1300589500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     69100500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1231489000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1300589500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks       943282                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total       943282                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks            4                       # number of WritebackClean accesses(hits+misses)
@@ -749,18 +759,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.016384                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.966292                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015583                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.016384                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74356.401265                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74356.401265                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75543.927649                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75543.927649                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82328.897338                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82328.897338                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75543.927649                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74498.007699                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74549.964701                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75543.927649                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74498.007699                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74549.964701                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.953795                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.953795                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.131783                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.131783                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.131783                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.379348                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 83472.787369                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.131783                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.379348                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 83472.787369                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -789,18 +799,18 @@ system.cpu.l2cache.demand_mshr_misses::total        15574
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          773                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14801                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        15574                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    935999500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    935999500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     50673500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     50673500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     18685500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     18685500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     50673500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    954685000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1005358500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     50673500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    954685000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1005358500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1036812000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1036812000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     61297000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     61297000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     46234000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     46234000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     61297000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1083046000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1144343000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     61297000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1083046000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1144343000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311008                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311008                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.965044                       # mshr miss rate for ReadCleanReq accesses
@@ -813,25 +823,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.016376
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965044                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015577                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.016376                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64356.401265                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64356.401265                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65554.333765                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65554.333765                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72706.225681                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72706.225681                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65554.333765                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64501.385042                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64553.647104                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65554.333765                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64501.385042                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64553.647104                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.953795                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.953795                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79297.542044                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79297.542044                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79297.542044                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.839605                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.783485                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79297.542044                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.839605                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.783485                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      1897104                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       946122                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          150                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp        904234                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       943282                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            5                       # Transaction distribution
@@ -871,7 +881,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  62420912500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp               1030                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14544                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            14544                       # Transaction distribution
@@ -892,9 +902,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total               15574                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            21795000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            21777000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           82138750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           82137500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index 9dfbe1ac3..afbdccd37 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -172,7 +172,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -534,7 +534,7 @@ pipelined=true
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -813,6 +813,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -824,7 +825,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -832,29 +833,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -874,6 +882,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:268435455
+range=0:268435455:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -905,9 +914,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index e215a7e6c..07887a4ce 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:10:34
-gem5 executing on e108600-lin, pid 12217
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:52:57
+gem5 executing on e108600-lin, pid 17480
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -26,4 +26,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 58199030500 because target called exit()
+Exiting @ tick 58675371500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index a9bdce95d..3b8f7cb56 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,117 +1,117 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.058328                       # Number of seconds simulated
-sim_ticks                                 58328364500                       # Number of ticks simulated
-final_tick                                58328364500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.058675                       # Number of seconds simulated
+sim_ticks                                 58675371500                       # Number of ticks simulated
+final_tick                                58675371500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 135523                       # Simulator instruction rate (inst/s)
-host_op_rate                                   136198                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               87259482                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 492508                       # Number of bytes of host memory used
-host_seconds                                   668.45                       # Real time elapsed on the host
+host_inst_rate                                 111966                       # Simulator instruction rate (inst/s)
+host_op_rate                                   112523                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               72520515                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 490592                       # Number of bytes of host memory used
+host_seconds                                   809.09                       # Real time elapsed on the host
 sim_insts                                    90589799                       # Number of instructions simulated
 sim_ops                                      91041030                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             44736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            218752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       921408                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1184896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            218240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       923072                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1186048                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        44736                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           44736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks         5696                       # Number of bytes written to this memory
-system.physmem.bytes_written::total              5696                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks         6656                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              6656                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                699                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               3418                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        14397                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 18514                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks              89                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                   89                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               766968                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3750354                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     15796911                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                20314233                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          766968                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             766968                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks             97654                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                  97654                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks             97654                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              766968                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3750354                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     15796911                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               20411887                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         18515                       # Number of read requests accepted
-system.physmem.writeReqs                           89                       # Number of write requests accepted
-system.physmem.readBursts                       18515                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                         89                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1179904                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      5056                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                      4480                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1184960                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                   5696                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       79                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       2                       # Number of DRAM write bursts merged with an existing one
+system.physmem.num_reads::cpu.data               3410                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        14423                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 18532                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             104                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  104                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               762432                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3719448                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     15731848                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                20213728                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          762432                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             762432                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            113438                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 113438                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            113438                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              762432                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3719448                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     15731848                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               20327166                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         18533                       # Number of read requests accepted
+system.physmem.writeReqs                          104                       # Number of write requests accepted
+system.physmem.readBursts                       18533                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        104                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1180480                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      5632                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                      4608                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1186112                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                   6656                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       88                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       3                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                3247                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                3245                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 921                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 949                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 952                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                1031                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                1061                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1117                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1095                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                1097                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1065                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1118                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1097                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                1096                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                1024                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                932                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                902                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                896                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               1399                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                904                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                904                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                895                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               1401                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                903                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   2                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   1                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   2                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                   9                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                  10                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                   8                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                   2                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                   3                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                   3                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                  12                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                  10                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                  15                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                   1                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                  3                       # Per bank write bursts
+system.physmem.perBankWrBursts::10                  1                       # Per bank write bursts
 system.physmem.perBankWrBursts::11                  3                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  2                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                  9                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                 13                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                  6                       # Per bank write bursts
+system.physmem.perBankWrBursts::12                  5                       # Per bank write bursts
+system.physmem.perBankWrBursts::13                 12                       # Per bank write bursts
+system.physmem.perBankWrBursts::14                  7                       # Per bank write bursts
+system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     58328356000                       # Total gap between requests
+system.physmem.totGap                     58675363000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   18515                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   18533                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                     89                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     13470                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2526                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       477                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    104                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     12556                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      3396                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       496                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                       410                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       307                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       301                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       310                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       283                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       292                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        60                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       314                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       300                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       298                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       296                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       280                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        99                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
@@ -149,20 +149,20 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                        5                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::29                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        4                       # What write queue length does an incoming req see
@@ -198,102 +198,109 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         3107                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      380.704216                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     201.847183                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     402.867268                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           1088     35.02%     35.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          865     27.84%     62.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           94      3.03%     65.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           72      2.32%     68.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           65      2.09%     70.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           68      2.19%     72.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           56      1.80%     74.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           51      1.64%     75.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          748     24.07%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           3107                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples         2974                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      397.815736                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     217.392167                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     406.651837                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            841     28.28%     28.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          992     33.36%     61.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           92      3.09%     64.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           59      1.98%     66.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           59      1.98%     68.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           62      2.08%     70.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           53      1.78%     72.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           59      1.98%     74.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          757     25.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           2974                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples             4                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean             4608                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean     1496.681558                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     7484.705695                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511               1     25.00%     25.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            1     25.00%     50.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean             4542                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean     1434.998534                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     7438.956513                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511               2     50.00%     50.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1536-2047            1     25.00%     75.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::15360-15871            1     25.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total               4                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples             4                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.500000                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.477704                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev               1                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                  1     25.00%     25.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                  3     75.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean               18                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.000000                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                  4    100.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total               4                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      204802662                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 550477662                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     92180000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11108.84                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                      819558662                       # Total ticks spent queuing
+system.physmem.totMemAccLat                1165402412                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     92225000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       44432.57                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29858.84                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          20.23                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  63182.57                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          20.12                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.08                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       20.32                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.10                       # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       20.21                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.11                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.16                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.16                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.38                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      15382                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                        10                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.43                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  11.49                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3135258.87                       # Average gap between requests
-system.physmem.pageHitRate                      83.10                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   17803800                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    9714375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  81876600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                   162000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3809622960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             6575109030                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            29228595750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              39722884515                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              681.036990                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    48583441495                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1947660000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      7795971005                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5609520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3060750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  61760400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                   187920                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3809622960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2425538385                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            32868570000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              39174349935                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.632528                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    54671634140                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1947660000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1708703360                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                28233990                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          23266525                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            835401                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11829630                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                11747896                       # Number of BTB hits
+system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        17.01                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      15523                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                        12                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   84.16                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  11.88                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3148326.61                       # Average gap between requests
+system.physmem.pageHitRate                      83.76                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   15986460                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    8481825                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  75141360                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                   224460                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           1848222480.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy              457291620                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy               99494880                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy        3995273070                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        3179264640                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        10079734425                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              19762775190                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              336.815504                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime            57405272063                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      196297250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       786242000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    40364411250                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN   8279321820                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       287560187                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN   8761538993                       # Time in different power states
+system.physmem_1.actEnergy                    5305020                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2804505                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  56548800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                   151380                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           250773120.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy              129702360                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               13640160                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy         769421340                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy         250623360                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        13483521390                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              14962606875                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              255.006594                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime            58353889098                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE       22210250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       106530000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    56015166500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN    652672389                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       191421152                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN   1687371209                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                28234010                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23266490                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            835433                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11829728                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                11748003                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.309074                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   74550                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             99.309156                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   74546                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 96                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups           27225                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits              25478                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses             1747                       # Number of indirect misses.
+system.cpu.branchPred.indirectLookups           27219                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              25475                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             1744                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted          245                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -323,7 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -353,7 +360,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -383,7 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -414,84 +421,84 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     58328364500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        116656730                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     58675371500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        117350744                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles             746133                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      134907690                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    28233990                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11847924                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     115018036                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1674227                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  853                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles          829                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  32275439                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   555                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          116602964                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.162155                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.318550                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles             746331                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      134908246                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    28234010                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11848024                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     115699810                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1674291                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  849                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          926                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  32275670                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   568                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          117285061                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.155401                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.317679                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 59067374     50.66%     50.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 13933709     11.95%     62.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9228635      7.91%     70.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 34373246     29.48%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 59749210     50.94%     50.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 13933958     11.88%     62.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9228354      7.87%     70.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 34373539     29.31%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            116602964                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.242026                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.156450                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8835100                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              64368120                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  33012562                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9561783                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 825399                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4097891                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 11814                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              114395515                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               1985251                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 825399                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15271601                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                50089085                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         110009                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  35409630                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              14897240                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              110872720                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               1412183                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              11133547                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1231881                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1645196                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 486344                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           129945840                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             483153679                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        119447461                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               433                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            117285061                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.240595                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.149616                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8835265                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              65049836                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  33012809                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9561722                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 825429                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4097911                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 11817                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              114395758                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               1985288                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 825429                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15272092                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                50298480                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         112986                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  35409562                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              15366512                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              110872789                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               1412207                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              11133815                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1555614                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2094363                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 506230                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           129945991                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             483154289                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        119447702                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               431                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             107312919                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 22632921                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 22633072                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts               4409                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts           4401                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  21513680                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26805319                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5347286                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads            522469                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           256366                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  109667529                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                  21514760                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26805262                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5347320                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads            521988                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           256188                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  109667585                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                8283                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 101366370                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1074686                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        18634782                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     41671490                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                 101366888                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1074694                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        18634838                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     41670017                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             65                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     116602964                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.869329                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.988911                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     117285061                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.864278                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.988233                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            54969091     47.14%     47.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            31363076     26.90%     74.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            22007447     18.87%     92.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7065313      6.06%     98.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1197724      1.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            55650042     47.45%     47.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            31364266     26.74%     74.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22008003     18.76%     92.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7064697      6.02%     98.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1197740      1.02%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                 313      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -499,9 +506,9 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       116602964                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       117285061                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9783594     48.67%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9783493     48.67%     48.67% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                     50      0.00%     48.67% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.67% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.67% # attempts to use FU when none available
@@ -530,12 +537,12 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.67% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.67% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.67% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9615674     47.83%     96.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                702930      3.50%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9615894     47.83%     96.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                702925      3.50%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              71970691     71.00%     71.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              71970995     71.00%     71.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                10697      0.01%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.01% # Type of FU issued
@@ -560,86 +567,86 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.01% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               2      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt              54      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc            125      0.00%     71.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            124      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24337594     24.01%     95.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5047205      4.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24337772     24.01%     95.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5047242      4.98%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              101366370                       # Type of FU issued
-system.cpu.iq.rate                           0.868929                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    20102261                       # FU busy when requested
+system.cpu.iq.FU_type_0::total              101366888                       # Type of FU issued
+system.cpu.iq.rate                           0.863794                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    20102375                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.198313                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          340512191                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         128311283                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     99607990                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 460                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                628                       # Number of floating instruction queue writes
+system.cpu.iq.int_inst_queue_reads          341195448                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         128311397                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     99608403                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 458                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                626                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses          113                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              121468392                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     239                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           288047                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              121469025                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     238                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           288057                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4329408                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4329351                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses         1498                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation         1351                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       602442                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores       602476                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads         7583                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        130712                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked        130798                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 825399                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 8206553                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                706266                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           109688634                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 825429                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 8290686                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                768265                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           109688691                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26805319                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              5347286                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts              26805262                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5347320                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts               4395                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 180569                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                362078                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents                 180386                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                424316                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents           1351                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         435086                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       412401                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               847487                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             100109489                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23802993                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1256881                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect         435090                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       412415                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               847505                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             100109953                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23803133                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1256935                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         12822                       # number of nop insts executed
-system.cpu.iew.exec_refs                     28718621                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 20621294                       # Number of branches executed
-system.cpu.iew.exec_stores                    4915628                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.858154                       # Inst execution rate
-system.cpu.iew.wb_sent                       99693258                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      99608103                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  59691284                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95529167                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.853856                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.624849                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        17363279                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                         12823                       # number of nop insts executed
+system.cpu.iew.exec_refs                     28718801                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 20621332                       # Number of branches executed
+system.cpu.iew.exec_stores                    4915668                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.853083                       # Inst execution rate
+system.cpu.iew.wb_sent                       99693665                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      99608516                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  59691499                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95528314                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.848810                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.624857                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        17363350                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            823687                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    113915056                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.799312                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.736114                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            823717                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    114597116                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.794554                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.732042                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     77490817     68.03%     68.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     18611366     16.34%     84.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      7154135      6.28%     90.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      3469454      3.05%     93.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1644903      1.44%     95.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       541342      0.48%     95.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       703110      0.62%     96.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       178773      0.16%     96.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4121156      3.62%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     78173194     68.22%     68.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     18611100     16.24%     84.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      7154015      6.24%     90.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3469592      3.03%     93.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1644807      1.44%     95.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       541237      0.47%     95.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       703127      0.61%     96.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       178794      0.16%     96.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4121250      3.60%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    113915056                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    114597116                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             90602408                       # Number of instructions committed
 system.cpu.commit.committedOps               91053639                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -685,80 +692,80 @@ system.cpu.commit.op_class_0::MemWrite        4744844      5.21%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91053639                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               4121156                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    218205084                       # The number of ROB reads
-system.cpu.rob.rob_writes                   219522331                       # The number of ROB writes
-system.cpu.timesIdled                             576                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           53766                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               4121250                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    218887121                       # The number of ROB reads
+system.cpu.rob.rob_writes                   219522508                       # The number of ROB writes
+system.cpu.timesIdled                             581                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           65683                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    90589799                       # Number of Instructions Simulated
 system.cpu.committedOps                      91041030                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.287747                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.287747                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.776550                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.776550                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                108097252                       # number of integer regfile reads
-system.cpu.int_regfile_writes                58691902                       # number of integer regfile writes
+system.cpu.cpi                               1.295408                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.295408                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.771958                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.771958                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                108097860                       # number of integer regfile reads
+system.cpu.int_regfile_writes                58692141                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                       93                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 369002875                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 58686679                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                28409649                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                 369004584                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 58686965                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                28409767                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           5470636                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.779483                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            18249262                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           5471148                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              3.335545                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          36545500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.779483                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999569                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999569                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           5470621                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.769293                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            18249382                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           5471133                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              3.335576                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          38111500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.769293                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999549                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999549                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          335                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          177                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          338                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          174                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          61906894                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         61906894                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     13887138                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13887138                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4353836                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4353836                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          61907171                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         61907171                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     13887260                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13887260                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4353834                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4353834                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          522                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           522                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3873                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3873                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      18240974                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18240974                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     18241496                       # number of overall hits
-system.cpu.dcache.overall_hits::total        18241496                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9587451                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9587451                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       381145                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       381145                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      18241094                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18241094                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18241616                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18241616                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9587475                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9587475                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       381147                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       381147                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            7                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            7                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data           14                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total           14                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      9968596                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9968596                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9968603                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9968603                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  88929958000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  88929958000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   4000514273                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   4000514273                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       284000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       284000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  92930472273                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  92930472273                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  92930472273                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  92930472273                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23474589                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23474589                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9968622                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9968622                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9968629                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9968629                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  89371349000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  89371349000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4092576700                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4092576700                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       302000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       302000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  93463925700                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  93463925700                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  93463925700                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  93463925700                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23474735                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23474735                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          529                       # number of SoftPFReq accesses(hits+misses)
@@ -767,474 +774,475 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28209570                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28209570                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28210099                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28210099                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408418                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.408418                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     28209716                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28209716                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28210245                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28210245                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408417                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.408417                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080496                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.080496                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003602                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003602                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.353376                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.353376                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.353370                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.353370                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9275.662322                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  9275.662322                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10496.042905                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10496.042905                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20285.714286                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20285.714286                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9322.323051                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9322.323051                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9322.316504                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9322.316504                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       330469                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       108734                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            121517                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           12838                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.719529                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     8.469699                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      5470636                       # number of writebacks
-system.cpu.dcache.writebacks::total           5470636                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4338792                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4338792                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158657                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       158657                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_miss_rate::cpu.data     0.353375                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.353375                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.353369                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.353369                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9321.677397                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  9321.677397                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10737.528303                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10737.528303                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  9375.811993                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  9375.811993                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  9375.805409                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  9375.805409                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       331977                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       129797                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            121610                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           12840                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.729850                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    10.108801                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks      5470621                       # number of writebacks
+system.cpu.dcache.writebacks::total           5470621                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4338830                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4338830                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158660                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       158660                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           14                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total           14                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4497449                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4497449                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4497449                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4497449                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248659                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5248659                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222488                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       222488                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4497490                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4497490                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4497490                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4497490                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248645                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5248645                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222487                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       222487                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      5471147                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      5471147                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      5471151                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      5471151                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43429617000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  43429617000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2285050165                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2285050165                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       217500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       217500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45714667165                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  45714667165                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45714884665                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  45714884665                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223589                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223589                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      5471132                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      5471132                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      5471136                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      5471136                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43817219500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  43817219500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2296823105                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2296823105                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       235500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       235500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  46114042605                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  46114042605                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  46114278105                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  46114278105                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223587                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223587                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046988                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046988                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.007561                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.007561                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193946                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.193946                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193943                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.193943                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8274.421524                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8274.421524                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.442294                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.442294                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        54375                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        54375                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8355.591097                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  8355.591097                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8355.624742                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  8355.624742                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements               447                       # number of replacements
-system.cpu.icache.tags.tagsinuse           427.481000                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            32274286                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               904                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          35701.643805                       # Average number of references to valid blocks.
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193945                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.193945                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193941                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.193941                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8348.291702                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8348.291702                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10323.403637                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10323.403637                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        58875                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        58875                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8428.610862                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  8428.610862                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8428.647744                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  8428.647744                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements               448                       # number of replacements
+system.cpu.icache.tags.tagsinuse           427.600534                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            32274508                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               906                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          35623.077263                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   427.481000                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.834924                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.834924                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          457                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   427.600534                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.835157                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.835157                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          458                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           19                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          335                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.892578                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          64551760                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         64551760                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     32274286                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        32274286                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      32274286                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         32274286                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     32274286                       # number of overall hits
-system.cpu.icache.overall_hits::total        32274286                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1142                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1142                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1142                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1142                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1142                       # number of overall misses
-system.cpu.icache.overall_misses::total          1142                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     61976480                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     61976480                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     61976480                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     61976480                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     61976480                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     61976480                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     32275428                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     32275428                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     32275428                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     32275428                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     32275428                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     32275428                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000035                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000035                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000035                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000035                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000035                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000035                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54270.122592                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54270.122592                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54270.122592                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54270.122592                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54270.122592                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54270.122592                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        19008                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          148                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               219                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    86.794521                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    29.600000                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks          447                       # number of writebacks
-system.cpu.icache.writebacks::total               447                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          237                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          237                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          237                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          237                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          237                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          237                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          905                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          905                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          905                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          905                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          905                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          905                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50842984                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     50842984                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50842984                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     50842984                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50842984                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     50842984                       # number of overall MSHR miss cycles
+system.cpu.icache.tags.occ_task_id_percent::1024     0.894531                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          64552224                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         64552224                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     32274508                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        32274508                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      32274508                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         32274508                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     32274508                       # number of overall hits
+system.cpu.icache.overall_hits::total        32274508                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1151                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1151                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1151                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1151                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1151                       # number of overall misses
+system.cpu.icache.overall_misses::total          1151                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     79113980                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     79113980                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     79113980                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     79113980                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     79113980                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     79113980                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     32275659                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     32275659                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     32275659                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     32275659                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     32275659                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     32275659                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000036                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000036                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000036                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000036                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000036                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000036                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68734.995656                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68734.995656                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68734.995656                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68734.995656                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68734.995656                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68734.995656                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        21173                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          759                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               225                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               6                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    94.102222                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets   126.500000                       # average number of cycles each access was blocked
+system.cpu.icache.writebacks::writebacks          448                       # number of writebacks
+system.cpu.icache.writebacks::total               448                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          244                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          244                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          244                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          244                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          244                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          244                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          907                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          907                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          907                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          907                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          907                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          907                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     60405484                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     60405484                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     60405484                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     60405484                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     60405484                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     60405484                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000028                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56180.092818                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56180.092818                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56180.092818                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 56180.092818                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56180.092818                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 56180.092818                       # average overall mshr miss latency
-system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.prefetcher.num_hwpf_issued      4982437                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      5296601                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit       273114                       # number of redundant prefetches already in prefetch queue
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66599.210584                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66599.210584                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66599.210584                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66599.210584                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66599.210584                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66599.210584                       # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.prefetcher.num_hwpf_issued      4988856                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      5295771                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit       266816                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage     14074231                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements              123                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        11197.361342                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5291777                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            14677                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           360.548954                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage     14074045                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements              140                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        11212.925557                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5291618                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            14696                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           360.071992                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 11137.339599                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    60.021743                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.679769                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.003663                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.683433                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022           61                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        14493                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 11154.278216                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    58.647341                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.680803                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.003580                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.684383                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022           60                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        14496                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4           50                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          466                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3478                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9594                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          118                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          837                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.003723                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.884583                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        180526187                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       180526187                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks      5457780                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      5457780                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        10426                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        10426                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       226022                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       226022                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          204                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total          204                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5241527                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      5241527                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          204                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      5467549                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         5467753                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          204                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      5467549                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        5467753                       # number of overall hits
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4           49                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          477                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3389                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9672                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          119                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          839                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.003662                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.884766                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        180525801                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       180525801                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks      5457281                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      5457281                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        10913                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        10913                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       226015                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       226015                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          206                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total          206                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5241513                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      5241513                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          206                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      5467528                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         5467734                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          206                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      5467528                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        5467734                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            3                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            3                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          499                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          499                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data          505                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          505                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          701                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total          701                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data         3100                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total         3100                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          701                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         3599                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          4300                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         3605                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          4306                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          701                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         3599                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         4300                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        64500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total        64500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     41467500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     41467500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     48564000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     48564000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    228575500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total    228575500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     48564000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    270043000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    318607000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     48564000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    270043000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    318607000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      5457780                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      5457780                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        10426                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        10426                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.data         3605                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         4306                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        63500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total        63500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     64129500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     64129500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     58109500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     58109500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    616309000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total    616309000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     58109500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    680438500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    738548000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     58109500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    680438500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    738548000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      5457281                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      5457281                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        10913                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        10913                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data            3                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total            3                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       226521                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       226521                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          905                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          905                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      5244627                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      5244627                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          905                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      5471148                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      5472053                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          905                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      5471148                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      5472053                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       226520                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       226520                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          907                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          907                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      5244613                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      5244613                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          907                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      5471133                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      5472040                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          907                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      5471133                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      5472040                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002203                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.002203                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.774586                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.774586                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002229                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.002229                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.772878                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.772878                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000591                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000591                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.774586                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.000658                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.000786                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.774586                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.000658                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.000786                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        21500                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        21500                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83101.202405                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83101.202405                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 69278.174037                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 69278.174037                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73734.032258                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73734.032258                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69278.174037                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75032.786885                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74094.651163                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69278.174037                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75032.786885                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74094.651163                       # average overall miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.772878                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.000659                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.000787                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.772878                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.000659                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.000787                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21166.666667                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21166.666667                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 126989.108911                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 126989.108911                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82895.149786                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82895.149786                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198809.354839                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198809.354839                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82895.149786                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188748.543689                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 171516.024152                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82895.149786                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188748.543689                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 171516.024152                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks           89                       # number of writebacks
-system.cpu.l2cache.writebacks::total               89                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          158                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total          158                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.unused_prefetches                3                       # number of HardPF blocks evicted w/o reference
+system.cpu.l2cache.writebacks::writebacks          104                       # number of writebacks
+system.cpu.l2cache.writebacks::total              104                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          162                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total          162                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           22                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           32                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           32                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          180                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          181                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data          194                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          195                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          180                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          181                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       316573                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       316573                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data          194                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total          195                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       316848                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       316848                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            3                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            3                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          341                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          341                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          343                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          343                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          700                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total          700                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         3078                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total         3078                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         3068                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total         3068                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          700                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         3419                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         4119                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3411                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         4111                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          700                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         3419                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       316573                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       320692                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    866631987                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    866631987                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        46500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        46500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     32627500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     32627500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     44309000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     44309000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    208942500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    208942500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     44309000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    241570000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    285879000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     44309000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    241570000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    866631987                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1152510987                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data         3411                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       316848                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       320959                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher   1079223443                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total   1079223443                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        45500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        45500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     45646000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     45646000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     53848500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     53848500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    589212500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    589212500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     53848500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    634858500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    688707000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     53848500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    634858500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher   1079223443                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1767930443                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001505                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001505                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.773481                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.773481                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000587                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000587                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.773481                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000625                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.000753                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.773481                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000625                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001514                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001514                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.771775                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.771775                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000585                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000585                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.771775                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000623                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.000751                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.771775                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000623                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.058605                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2737.542327                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  2737.542327                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        15500                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        15500                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95681.818182                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95681.818182                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63298.571429                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63298.571429                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67882.553606                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67882.553606                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63298.571429                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70655.162328                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69404.952658                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63298.571429                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70655.162328                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2737.542327                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total  3593.825187                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     10943139                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      5471099                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2877                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops       302176                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops       302175                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.058654                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3406.123577                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  3406.123577                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15166.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15166.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 133078.717201                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 133078.717201                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76926.428571                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76926.428571                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192051.010430                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192051.010430                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76926.428571                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 186120.932278                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167527.852104                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76926.428571                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 186120.932278                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3406.123577                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total  5508.275023                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests     10943112                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      5471085                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2875                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       302425                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops       302424                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp       5245531                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      5457869                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        13303                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict           34                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       318447                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp       5245519                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      5457385                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        13788                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict           36                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       318720                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFResp            4                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq            3                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       226521                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       226521                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          905                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244627                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2256                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16412942                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          16415198                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        86464                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    700274432                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          700360896                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      318574                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic                  5952                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      5790626                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.052683                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.223400                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq       226520                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       226520                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          907                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244613                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2261                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16412897                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          16415158                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        86656                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    700272512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          700359168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      318864                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                  6912                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      5790903                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.052723                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.223481                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            5485560     94.73%     94.73% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             305065      5.27%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            5485590     94.73%     94.73% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             305312      5.27%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5790626                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10942652515                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization         18.8                       # Layer utilization (%)
+system.cpu.toL2Bus.snoop_fanout::total        5790903                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    10942625015                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization         18.6                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy         6019                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1357497                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1360996                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    8206727492                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization         14.1                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests         18642                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests         3008                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.respLayer1.occupancy    8206704493                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization         14.0                       # Layer utilization (%)
+system.membus.snoop_filter.tot_requests         18677                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests         3023                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  58328364500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp              18174                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty           89                       # Transaction distribution
-system.membus.trans_dist::CleanEvict               34                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED  58675371500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp              18190                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty          104                       # Transaction distribution
+system.membus.trans_dist::CleanEvict               36                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                4                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               340                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              340                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         18175                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        37156                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  37156                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1190592                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1190592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq               342                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              342                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         18191                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        37209                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  37209                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1192704                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1192704                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples             18519                       # Request fanout histogram
+system.membus.snoop_fanout::samples             18537                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   18519    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   18537    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               18519                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            29524488                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               18537                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            29625930                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           97237655                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           97326818                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index fa42af61f..e54b7db9f 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -179,7 +179,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -552,7 +552,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -756,6 +756,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -767,7 +768,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -775,29 +776,36 @@ width=16
 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -817,6 +825,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:268435455
+range=0:268435455:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -848,9 +857,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index e1bfb6d2d..9e929c5a5 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:18
-gem5 executing on e108600-lin, pid 18558
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:08:11
+gem5 executing on e108600-lin, pid 17630
 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -21,11 +21,11 @@ active arcs                : 1905
 simplex iterations         : 1502
 info: Increasing stack size by one page.
 flow value                 : 4990014995
+info: Increasing stack size by one page.
 new implicit arcs          : 23867
 active arcs                : 25772
-info: Increasing stack size by one page.
 simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 65986743500 because target called exit()
+Exiting @ tick 66079350000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 1e87ba0e2..dac7009e5 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,80 +1,80 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.065554                       # Number of seconds simulated
-sim_ticks                                 65553895500                       # Number of ticks simulated
-final_tick                                65553895500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.066079                       # Number of seconds simulated
+sim_ticks                                 66079350000                       # Number of ticks simulated
+final_tick                                66079350000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 122580                       # Simulator instruction rate (inst/s)
-host_op_rate                                   215844                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               50862026                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 417260                       # Number of bytes of host memory used
-host_seconds                                  1288.86                       # Real time elapsed on the host
+host_inst_rate                                 104457                       # Simulator instruction rate (inst/s)
+host_op_rate                                   183932                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               43689609                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 414668                       # Number of bytes of host memory used
+host_seconds                                  1512.47                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst             69632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1890944                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1960576                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        69632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           69632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        17920                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             17920                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1088                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              29546                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 30634                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             280                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  280                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1062210                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             28845639                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                29907849                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1062210                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1062210                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            273363                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 273363                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            273363                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1062210                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            28845639                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               30181212                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         30634                       # Number of read requests accepted
-system.physmem.writeReqs                          280                       # Number of write requests accepted
-system.physmem.readBursts                       30634                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        280                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1951616                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8960                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                     16000                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1960576                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  17920                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      140                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst             69696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1892800                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1962496                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        69696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           69696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        19520                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             19520                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1089                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              29575                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 30664                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             305                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  305                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1054732                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             28644350                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                29699081                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1054732                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1054732                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            295402                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 295402                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            295402                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1054732                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            28644350                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               29994484                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         30664                       # Number of read requests accepted
+system.physmem.writeReqs                          305                       # Number of write requests accepted
+system.physmem.readBursts                       30664                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        305                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1952768                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9728                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                     18368                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1962496                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  19520                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      152                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1938                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                2083                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1940                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                2080                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                2040                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1941                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                2041                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1918                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1976                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1947                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                2062                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1911                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1975                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                1870                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                1951                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                1940                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                1941                       # Per bank write bursts
 system.physmem.perBankRdBursts::10               1805                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               1794                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               1792                       # Per bank write bursts
 system.physmem.perBankRdBursts::13               1799                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               1827                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               1826                       # Per bank write bursts
 system.physmem.perBankRdBursts::15               1779                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                  10                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                 107                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                  31                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                  25                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                  39                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                  13                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                  16                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                  26                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                 125                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                  27                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                  24                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                  54                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                   3                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                  18                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                   1                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                   5                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                   6                       # Per bank write bursts
 system.physmem.perBankWrBursts::10                  3                       # Per bank write bursts
 system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
@@ -83,28 +83,28 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     65553697500                       # Total gap between requests
+system.physmem.totGap                     66079146500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   30634                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   30664                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    280                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     29978                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       404                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        85                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        22                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    305                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     29931                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       435                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        98                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -147,24 +147,24 @@ system.physmem.wrQLenPdf::13                        1                       # Wh
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::15                       14                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::16                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
@@ -194,335 +194,347 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         2859                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      687.860091                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     477.665686                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     399.129385                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            441     15.42%     15.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          263      9.20%     24.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          134      4.69%     29.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          136      4.76%     34.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          118      4.13%     38.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          116      4.06%     42.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           85      2.97%     45.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           96      3.36%     48.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         1470     51.42%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           2859                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples            14                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2173.928571                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       21.222071                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     8074.812153                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023             13     92.86%     92.86% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::29696-30719            1      7.14%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total              14                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples            14                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.857143                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.849200                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.534522                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                  1      7.14%      7.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                 13     92.86%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total              14                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      136299000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 708061500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    152470000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4469.70                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         2875                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      685.122783                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     477.283945                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     398.354531                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            431     14.99%     14.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          281      9.77%     24.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          140      4.87%     29.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          134      4.66%     34.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          130      4.52%     38.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          125      4.35%     43.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           77      2.68%     45.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           84      2.92%     48.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         1473     51.23%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           2875                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples            16                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      1904.687500                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       23.337942                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     7552.888425                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023             15     93.75%     93.75% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::29696-30719            1      6.25%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total              16                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples            16                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.937500                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.900644                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.181454                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                  3     18.75%     18.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 10     62.50%     81.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  1      6.25%     87.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  2     12.50%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total              16                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      407578000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 979678000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    152560000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13357.96                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23219.70                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          29.77                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.24                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       29.91                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.27                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32107.96                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          29.55                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.28                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       29.70                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.30                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.23                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.23                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        11.62                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      27721                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                       161                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.91                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  57.50                       # Row buffer hit rate for writes
-system.physmem.avgGap                      2120518.13                       # Average gap between requests
-system.physmem.pageHitRate                      90.60                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   11740680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    6406125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 123169800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                  1568160                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4281566640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3052855305                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            36653676000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              44130982710                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              673.213820                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    60959756000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2188940000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      2404016500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    9873360                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    5387250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 114558600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                    51840                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4281566640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3230070300                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            36498224250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              44139732240                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              673.347293                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    60700713000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2188940000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      2663059500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                40360668                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          40360668                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1392637                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             26664097                       # Number of BTB lookups
+system.physmem.avgWrQLen                        15.50                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      27718                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                       199                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.84                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  65.25                       # Row buffer hit rate for writes
+system.physmem.avgGap                      2133719.09                       # Average gap between requests
+system.physmem.pageHitRate                      90.59                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   11095560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    5886045                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 112990500                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                  1451160                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           311007840.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy              261882510                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy               17017920                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy         979925760                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy         266852640                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        15064489440                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              17032599375                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              257.759790                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime            65460562250                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE       23034750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       131986000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    62616842500                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN    694916500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       463599750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN   2148970500                       # Time in different power states
+system.physmem_1.actEnergy                    9481920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    5024580                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 104865180                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                    46980                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           381691440.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy              255809160                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               19980960                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy        1151008410                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy         399268320                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        14907041175                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              17234823375                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              260.820111                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime            65463256000                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE       30077000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       162078000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    61901089500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN   1039749000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       422083750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN   2524272750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                40670761                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          40670761                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1447235                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             26704882                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 5988252                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              86625                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups        26664097                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits           21157452                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses          5506645                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       511906                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.usedRAS                 6058055                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              92918                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        26704882                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           21174798                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          5530084                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       547932                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     65553895500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        131107792                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     66079350000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        132158701                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           30523578                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      219647427                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    40360668                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           27145704                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      98945290                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2900833                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        518                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 6239                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        114030                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           50                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          156                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  29742559                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                352958                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                      20                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          131040277                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.949675                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.407509                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           30720551                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      221310466                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    40670761                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           27232853                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      99729501                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3011659                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        476                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 6367                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        115460                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           59                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          223                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  29905952                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                367398                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                      15                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          132078466                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.949325                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.409240                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 65532629     50.01%     50.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4015050      3.06%     53.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3611452      2.76%     55.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  6110552      4.66%     60.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  7743592      5.91%     66.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5553299      4.24%     70.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3377797      2.58%     73.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2818268      2.15%     75.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 32277638     24.63%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 66113924     50.06%     50.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4057337      3.07%     53.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3620378      2.74%     55.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6125698      4.64%     60.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  7769884      5.88%     66.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5562288      4.21%     70.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3378570      2.56%     73.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2898316      2.19%     75.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 32552071     24.65%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            131040277                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.307843                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.675319                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 15257836                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              64260169                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  40205069                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9866787                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1450416                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              361840570                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                1450416                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 20789312                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                11161609                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          17754                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  44252475                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              53368711                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              352352816                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 16475                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 802883                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               46797603                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4838735                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           354809982                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             933969547                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        575070468                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             25233                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            132078466                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.307742                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.674581                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 15424627                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              64723504                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  40539404                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9885102                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1505829                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              364367574                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                1505829                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 20975204                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11377644                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          18396                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  44575622                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              53625771                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              354569179                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 16511                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 791289                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               46695905                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                5223216                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           357047318                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             939748965                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        578695140                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             22535                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 75597235                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                487                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            488                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  64661942                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            112312024                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            38476139                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          51587404                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9144280                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  343861767                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                4715                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 317818488                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            169830                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        65674018                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    101673382                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           4270                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     131040277                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.425350                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.164581                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 77834571                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                494                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            495                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  64563941                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            112883257                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            38651230                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          51754424                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9024100                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  345545955                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                4258                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 318634973                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            172634                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        67357749                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    104786759                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           3813                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     132078466                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.412467                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.166876                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            35194225     26.86%     26.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            20112862     15.35%     42.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            17093441     13.04%     55.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            17641161     13.46%     68.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            15328111     11.70%     80.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            12869587      9.82%     90.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             6689257      5.10%     95.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             4093724      3.12%     98.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             2017909      1.54%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            36007190     27.26%     27.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            20156467     15.26%     42.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            17165000     13.00%     55.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            17631185     13.35%     68.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            15357300     11.63%     80.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            12905365      9.77%     90.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             6726655      5.09%     95.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             4095436      3.10%     98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2033868      1.54%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       131040277                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       132078466                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  366862      8.95%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                3538662     86.29%     95.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                195200      4.76%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  366214      8.93%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                3544036     86.42%     95.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                190508      4.65%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33340      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             181791277     57.20%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                11724      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                   408      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 305      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     57.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            101272470     31.86%     89.08% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            34708964     10.92%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             182328648     57.22%     57.23% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                11540      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                   353      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 275      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            101489755     31.85%     89.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34771062     10.91%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              317818488                       # Type of FU issued
-system.cpu.iq.rate                           2.424101                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     4100724                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012903                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          770927721                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         409562927                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    313648272                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               20086                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              38326                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         4607                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              321877132                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    8740                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         57541030                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              318634973                       # Type of FU issued
+system.cpu.iq.rate                           2.411003                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     4100758                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012870                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          773602517                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         412934380                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    314305089                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               19287                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              34996                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         4478                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              322693854                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    8537                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         57471685                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     21532639                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        67356                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        63407                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      7036387                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     22103872                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        67270                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        64283                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      7211478                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3908                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        141249                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3969                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        140998                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1450416                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 8045146                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               3020269                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           343866482                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            122594                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             112312024                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             38476139                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1910                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3213                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3025719                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          63407                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         529775                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      1033204                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1562979                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             315414153                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             100518036                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2404335                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1505829                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 8247421                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3042364                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           345550213                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            133191                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             112883257                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             38651230                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1745                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   2963                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3048582                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          64283                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         545574                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1082259                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1627833                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             316133024                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             100718075                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2501949                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    134824639                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 32104448                       # Number of branches executed
-system.cpu.iew.exec_stores                   34306603                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.405762                       # Inst execution rate
-system.cpu.iew.wb_sent                      314286106                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     313652879                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 237682188                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 343423954                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       2.392328                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.692096                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        65797430                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                    135067596                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 32155475                       # Number of branches executed
+system.cpu.iew.exec_stores                   34349521                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.392071                       # Inst execution rate
+system.cpu.iew.wb_sent                      314966910                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     314309567                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 238188610                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 344086280                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       2.378274                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.692235                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        67483313                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1399141                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    121633848                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.287130                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.051606                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1453904                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    122408865                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.272650                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.045643                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     56556051     46.50%     46.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     16464352     13.54%     60.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     11233282      9.24%     69.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8748892      7.19%     76.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2045691      1.68%     78.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1756798      1.44%     79.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       927336      0.76%     80.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       727466      0.60%     80.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     23173980     19.05%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     57244612     46.77%     46.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     16526306     13.50%     60.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     11253907      9.19%     69.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8747083      7.15%     76.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2074138      1.69%     78.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1764583      1.44%     79.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       930878      0.76%     80.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       726504      0.59%     81.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     23140854     18.90%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    121633848                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    122408865                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
 system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -568,466 +580,466 @@ system.cpu.commit.op_class_0::MemWrite       31439752     11.30%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              23173980                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    442449762                       # The number of ROB reads
-system.cpu.rob.rob_writes                   697455131                       # The number of ROB writes
-system.cpu.timesIdled                             919                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           67515                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              23140854                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    444943788                       # The number of ROB reads
+system.cpu.rob.rob_writes                   701094607                       # The number of ROB writes
+system.cpu.timesIdled                             892                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           80235                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
 system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.829856                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.829856                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.205028                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.205028                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                502814986                       # number of integer regfile reads
-system.cpu.int_regfile_writes               247784196                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      4396                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      732                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 109093589                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 65488596                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               201890594                       # number of misc regfile reads
+system.cpu.cpi                               0.836508                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.836508                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.195446                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.195446                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                503639899                       # number of integer regfile reads
+system.cpu.int_regfile_writes               248370602                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      4288                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      677                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 109192725                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 65564647                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               202344104                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           2073601                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4068.108072                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            71473739                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2077697                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             34.400463                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       21041764500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4068.108072                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993190                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993190                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           2073334                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4067.317880                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            71743454                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2077430                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             34.534715                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       21320595500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4067.317880                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.992998                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.992998                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          507                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3433                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          156                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          505                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3441                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         150601371                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        150601371                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     40127755                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        40127755                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31345984                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31345984                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      71473739                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         71473739                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     71473739                       # number of overall hits
-system.cpu.dcache.overall_hits::total        71473739                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2694330                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2694330                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        93768                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        93768                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2788098                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2788098                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2788098                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2788098                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  32345718500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  32345718500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2982305493                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2982305493                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35328023993                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35328023993                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35328023993                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35328023993                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     42822085                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     42822085                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         151138894                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        151138894                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     40397499                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        40397499                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31345955                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31345955                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      71743454                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         71743454                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     71743454                       # number of overall hits
+system.cpu.dcache.overall_hits::total        71743454                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2693481                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2693481                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        93797                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        93797                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2787278                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2787278                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2787278                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2787278                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  32417345000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  32417345000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3182155993                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3182155993                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35599500993                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35599500993                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35599500993                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35599500993                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     43090980                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     43090980                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     74261837                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     74261837                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     74261837                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     74261837                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.062919                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.062919                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002982                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.002982                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037544                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037544                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037544                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037544                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12005.106464                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 12005.106464                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31805.152003                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31805.152003                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12671.012279                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12671.012279                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12671.012279                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12671.012279                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       218790                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          393                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             43059                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     74530732                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     74530732                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     74530732                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     74530732                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.062507                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.062507                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002983                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.002983                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037398                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037398                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037398                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037398                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12035.483079                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12035.483079                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33925.989029                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33925.989029                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12772.138622                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12772.138622                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12772.138622                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12772.138622                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       219409                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          385                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             43429                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.081168                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    98.250000                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      2067196                       # number of writebacks
-system.cpu.dcache.writebacks::total           2067196                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       698496                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       698496                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11905                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        11905                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       710401                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       710401                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       710401                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       710401                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1995834                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1995834                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        81863                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        81863                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2077697                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2077697                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2077697                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2077697                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24223051500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24223051500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2825101993                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2825101993                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27048153493                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  27048153493                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27048153493                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  27048153493                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046608                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046608                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.052131                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    96.250000                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks      2066585                       # number of writebacks
+system.cpu.dcache.writebacks::total           2066585                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       697929                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       697929                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11919                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        11919                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       709848                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       709848                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       709848                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       709848                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1995552                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1995552                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        81878                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        81878                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2077430                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2077430                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2077430                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2077430                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24266554500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24266554500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3024734993                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3024734993                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27291289493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  27291289493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27291289493                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  27291289493                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046310                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046310                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002604                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027978                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.027978                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027978                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027978                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.806718                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.806718                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34510.120482                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34510.120482                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13018.333998                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13018.333998                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13018.333998                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13018.333998                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements                91                       # number of replacements
-system.cpu.icache.tags.tagsinuse           875.979350                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            29741086                       # Total number of references to valid blocks.
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027873                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.027873                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027873                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027873                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12160.321806                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12160.321806                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36941.974560                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36941.974560                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13137.044085                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13137.044085                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13137.044085                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13137.044085                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements                94                       # number of replacements
+system.cpu.icache.tags.tagsinuse           871.416193                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            29904477                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              1117                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          26625.860340                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          26772.136974                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   875.979350                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.427724                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.427724                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1026                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           29                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           35                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          914                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.500977                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          59486235                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         59486235                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     29741086                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        29741086                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      29741086                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         29741086                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     29741086                       # number of overall hits
-system.cpu.icache.overall_hits::total        29741086                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1473                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1473                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1473                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1473                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1473                       # number of overall misses
-system.cpu.icache.overall_misses::total          1473                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    110309999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    110309999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    110309999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    110309999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    110309999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    110309999                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     29742559                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     29742559                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     29742559                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     29742559                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     29742559                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     29742559                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000050                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000050                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000050                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000050                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000050                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000050                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74887.983028                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 74887.983028                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 74887.983028                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 74887.983028                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 74887.983028                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 74887.983028                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1013                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   871.416193                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.425496                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.425496                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1023                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           37                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          905                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.499512                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          59813021                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         59813021                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     29904477                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        29904477                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      29904477                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         29904477                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     29904477                       # number of overall hits
+system.cpu.icache.overall_hits::total        29904477                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1475                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1475                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1475                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1475                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1475                       # number of overall misses
+system.cpu.icache.overall_misses::total          1475                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    154630499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    154630499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    154630499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    154630499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    154630499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    154630499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     29905952                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     29905952                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     29905952                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     29905952                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     29905952                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     29905952                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000049                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000049                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000049                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000049                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000049                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000049                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 104834.236610                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 104834.236610                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 104834.236610                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 104834.236610                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 104834.236610                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 104834.236610                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         3285                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                13                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    77.923077                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          219                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks           91                       # number of writebacks
-system.cpu.icache.writebacks::total                91                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          356                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          356                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          356                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          356                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          356                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          356                       # number of overall MSHR hits
+system.cpu.icache.writebacks::writebacks           94                       # number of writebacks
+system.cpu.icache.writebacks::total                94                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          358                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          358                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          358                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          358                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          358                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          358                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1117                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total         1117                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst         1117                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total         1117                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         1117                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         1117                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     86959999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     86959999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     86959999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     86959999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     86959999                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     86959999                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000038                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000038                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000038                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000038                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000038                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000038                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77851.386750                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77851.386750                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77851.386750                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 77851.386750                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77851.386750                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 77851.386750                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements              663                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        21665.639104                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4121840                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            30651                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           134.476526                       # Average number of references to valid blocks.
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    115157499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    115157499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    115157499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    115157499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    115157499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    115157499                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000037                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000037                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000037                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 103095.343778                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 103095.343778                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 103095.343778                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 103095.343778                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 103095.343778                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 103095.343778                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements              694                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        21600.967235                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4121275                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            30681                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           134.326619                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     2.943755                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   711.855926                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 20950.839423                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000090                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.021724                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.639369                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.661183                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29988                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks     3.261837                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   710.389241                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 20887.316157                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000100                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.021679                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.637430                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.659209                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29987                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          166                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          187                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3           56                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29650                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.915161                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         33250579                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        33250579                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks      2067196                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      2067196                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks           91                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total           91                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        52900                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        52900                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           29                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           29                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1995251                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1995251                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           29                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2048151                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2048180                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           29                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2048151                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2048180                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data        28989                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        28989                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1088                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         1088                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          557                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          557                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1088                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        29546                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         30634                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1088                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        29546                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        30634                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2146396500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   2146396500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     84962000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     84962000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     42143000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     42143000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     84962000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   2188539500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   2273501500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     84962000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   2188539500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   2273501500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      2067196                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      2067196                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks           91                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total           91                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        81889                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        81889                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29627                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.915131                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         33246329                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        33246329                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2066585                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2066585                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks           94                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total           94                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        52930                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        52930                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           28                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           28                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1994925                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1994925                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           28                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2047855                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2047883                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           28                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2047855                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2047883                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data        28997                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        28997                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1089                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         1089                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          578                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          578                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1089                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        29575                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         30664                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1089                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        29575                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        30664                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2345855500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2345855500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    113174000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    113174000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     87677000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     87677000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    113174000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   2433532500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   2546706500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    113174000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   2433532500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   2546706500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2066585                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2066585                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks           94                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total           94                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        81927                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        81927                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1117                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::total         1117                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1995808                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1995808                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1995503                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1995503                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst         1117                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2077697                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2078814                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2077430                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2078547                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst         1117                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2077697                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2078814                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.354004                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.354004                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.974038                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.974038                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000279                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000279                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.974038                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.014221                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.014736                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.974038                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.014221                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.014736                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74041.757218                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74041.757218                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78090.073529                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78090.073529                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75660.682226                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75660.682226                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78090.073529                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74072.277127                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74214.973559                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78090.073529                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74072.277127                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74214.973559                       # average overall miss latency
+system.cpu.l2cache.overall_accesses::cpu.data      2077430                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2078547                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.353937                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.353937                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.974933                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.974933                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000290                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000290                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.974933                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.014236                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.014753                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.974933                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.014236                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.014753                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80899.937925                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80899.937925                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103924.701561                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103924.701561                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 151690.311419                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 151690.311419                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103924.701561                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82283.431953                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 83051.999087                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103924.701561                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82283.431953                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 83051.999087                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks          280                       # number of writebacks
-system.cpu.l2cache.writebacks::total              280                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28989                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        28989                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1088                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1088                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          557                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          557                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1088                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        29546                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        30634                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1088                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        29546                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        30634                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1856506500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1856506500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     74082000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     74082000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     36573000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     36573000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     74082000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1893079500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1967161500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     74082000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1893079500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1967161500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.354004                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.354004                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.974038                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.974038                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000279                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000279                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.974038                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014221                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014736                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.974038                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014221                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.014736                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64041.757218                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64041.757218                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68090.073529                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68090.073529                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65660.682226                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65660.682226                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68090.073529                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64072.277127                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64214.973559                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68090.073529                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64072.277127                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64214.973559                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      4152506                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2073696                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests           15                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.l2cache.writebacks::writebacks          305                       # number of writebacks
+system.cpu.l2cache.writebacks::total              305                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28997                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        28997                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1089                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1089                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          578                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          578                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1089                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        29575                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        30664                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1089                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        29575                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        30664                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2055885500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2055885500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    102284000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    102284000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     81897000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     81897000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    102284000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   2137782500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   2240066500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    102284000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   2137782500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   2240066500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.353937                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.353937                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.974933                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.974933                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000290                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000290                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.974933                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014236                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.014753                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.974933                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014236                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.014753                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70899.937925                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70899.937925                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93924.701561                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93924.701561                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 141690.311419                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 141690.311419                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93924.701561                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72283.431953                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73051.999087                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93924.701561                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72283.431953                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73051.999087                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      4151975                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2073430                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests           19                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops          331                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops          331                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp       1996925                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      2067476                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean           91                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         6788                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        81889                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        81889                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp       1996620                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2066890                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean           94                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         7138                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        81927                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        81927                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq         1117                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1995808                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2325                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6228995                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6231320                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265273152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          265350464                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                         663                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic                 17920                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      2079477                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000168                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.012972                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1995503                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2328                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6228194                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6230522                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77504                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265216960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          265294464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         694                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                 19520                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      2079241                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000169                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.013010                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2079127     99.98%     99.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                350      0.02%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2078889     99.98%     99.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                352      0.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2079477                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4143540000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2079241                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4142666500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          6.3                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1675999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3116545500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          4.8                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests         30966                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests          332                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.respLayer1.occupancy    3116145000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          4.7                       # Layer utilization (%)
+system.membus.snoop_filter.tot_requests         31027                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests          363                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp               1645                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty          280                       # Transaction distribution
-system.membus.trans_dist::CleanEvict               52                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             28989                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            28989                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          1645                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61600                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61600                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  61600                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1978496                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1978496                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1978496                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED  66079350000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp               1667                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty          305                       # Transaction distribution
+system.membus.trans_dist::CleanEvict               58                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             28997                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            28997                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          1667                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61691                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61691                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  61691                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1982016                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1982016                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1982016                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples             30634                       # Request fanout histogram
+system.membus.snoop_fanout::samples             30664                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   30634    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   30664    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               30634                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            43502500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               30664                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            43847500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          161439750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          161573250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
index d14e71c27..4a417985d 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
@@ -149,7 +149,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -583,7 +583,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -643,7 +643,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -760,6 +760,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -779,29 +780,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -821,6 +829,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -852,9 +861,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout
index 48ddcf72a..8606e90c7 100755
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:28
-gem5 executing on e108600-lin, pid 4298
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:45
+gem5 executing on e108600-lin, pid 28069
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/alpha/tru64/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -69,4 +69,4 @@ Echoing of input sentence turned on.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 417309765500 because target called exit()
+Exiting @ tick 422342506500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
index eadbc59cf..ddf2151ed 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,70 +1,70 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.417806                       # Number of seconds simulated
-sim_ticks                                417805983500                       # Number of ticks simulated
-final_tick                               417805983500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.422343                       # Number of seconds simulated
+sim_ticks                                422342506500                       # Number of ticks simulated
+final_tick                               422342506500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 243916                       # Simulator instruction rate (inst/s)
-host_op_rate                                   243916                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              166545939                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 257728                       # Number of bytes of host memory used
-host_seconds                                  2508.65                       # Real time elapsed on the host
+host_inst_rate                                 265332                       # Simulator instruction rate (inst/s)
+host_op_rate                                   265332                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              183135937                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 256400                       # Number of bytes of host memory used
+host_seconds                                  2306.17                       # Real time elapsed on the host
 sim_insts                                   611901617                       # Number of instructions simulated
 sim_ops                                     611901617                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 417805983500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 422342506500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            156672                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24196352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24353024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24196288                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24352960                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       156672                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          156672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18839232                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18839232                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks     18839168                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18839168                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst               2448                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             378068                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                380516                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          294363                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               294363                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               374987                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             57912890                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                58287878                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          374987                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             374987                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45090862                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45090862                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45090862                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              374987                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            57912890                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              103378740                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        380516                       # Number of read requests accepted
-system.physmem.writeReqs                       294363                       # Number of write requests accepted
-system.physmem.readBursts                      380516                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     294363                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24332224                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     20800                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18837888                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24353024                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18839232                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      325                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::cpu.data             378067                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                380515                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          294362                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               294362                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               370960                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             57290677                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                57661636                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          370960                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             370960                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          44606374                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               44606374                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          44606374                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              370960                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            57290677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              102268011                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        380515                       # Number of read requests accepted
+system.physmem.writeReqs                       294362                       # Number of write requests accepted
+system.physmem.readBursts                      380515                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     294362                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24331840                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21120                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18837824                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24352960                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18839168                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      330                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               23763                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               23178                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               23759                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               23180                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               23498                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24610                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25501                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23627                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               23703                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               23985                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23235                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24625                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25498                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23629                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               23701                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               23987                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23227                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               24022                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24757                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              22829                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23792                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              24451                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              22759                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              22481                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24752                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              22836                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23786                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              24450                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              22762                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              22473                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               17837                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               17476                       # Per bank write bursts
 system.physmem.perBankWrBursts::2               17996                       # Per bank write bursts
@@ -75,32 +75,32 @@ system.physmem.perBankWrBursts::6               18825                       # Pe
 system.physmem.perBankWrBursts::7               18731                       # Per bank write bursts
 system.physmem.perBankWrBursts::8               18487                       # Per bank write bursts
 system.physmem.perBankWrBursts::9               18977                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              19289                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              18103                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              19288                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18104                       # Per bank write bursts
 system.physmem.perBankWrBursts::12              18331                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18779                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18778                       # Per bank write bursts
 system.physmem.perBankWrBursts::14              17209                       # Per bank write bursts
 system.physmem.perBankWrBursts::15              17155                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    417805895500                       # Total gap between requests
+system.physmem.totGap                    422342412500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  380516                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  380515                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 294363                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    379108                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1078                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         5                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 294362                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    379040                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1139                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    17466                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17517                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17510                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17512                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17513                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17553                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17513                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17517                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17531                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17517                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17512                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17507                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6479                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6849                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    17525                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17563                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17563                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17562                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17561                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17562                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17562                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17561                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17568                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17565                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17567                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17575                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17580                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17569                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17569                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
@@ -194,101 +194,112 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       138680                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      311.287453                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     185.207223                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.580337                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          47172     34.01%     34.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        38791     27.97%     61.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13255      9.56%     71.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         8020      5.78%     77.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5116      3.69%     81.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3846      2.77%     83.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3216      2.32%     86.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2646      1.91%     88.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16618     11.98%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         138680                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17507                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.716228                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       18.015056                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      232.517715                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17502     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       138956                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      310.667780                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     185.031528                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     328.663803                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          47467     34.16%     34.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        38428     27.65%     61.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13549      9.75%     71.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         8124      5.85%     77.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5242      3.77%     81.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3828      2.75%     83.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3157      2.27%     86.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2628      1.89%     88.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16533     11.90%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         138956                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17561                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.649109                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       17.965863                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      233.199678                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17556     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            2      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::7168-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17507                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17507                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.812818                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.784450                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.984212                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              10318     58.94%     58.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                249      1.42%     60.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               6843     39.09%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 94      0.54%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  2      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17507                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4112094750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11240676000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1900955000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10815.87                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           17561                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17561                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.761061                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.733847                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.964147                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              10711     60.99%     60.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                371      2.11%     63.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               6450     36.73%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 26      0.15%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17561                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8688901500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               15817370250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1900925000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       22854.40                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29565.87                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          58.24                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          45.09                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       58.29                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       45.09                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  41604.40                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          57.61                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          44.60                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       57.66                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       44.61                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.81                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.80                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.45                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.35                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.26                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     314275                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    221571                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.66                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.27                       # Row buffer hit rate for writes
-system.physmem.avgGap                       619082.67                       # Average gap between requests
-system.physmem.pageHitRate                      79.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  534363480                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  291567375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1496445600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                959027040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            27288821040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            62100331785                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           196207614000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             288878170320                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              691.422544                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   325857976500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13951340000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     77993346000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  513853200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  280376250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1468724400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                948101760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            27288821040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            59269027500                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           198691214250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             288460118400                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              690.421947                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   330008811500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13951340000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     73843223000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 417805983500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               124433678                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          87996740                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6213240                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             71713362                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                67453030                       # Number of BTB hits
+system.physmem.avgWrQLen                        20.60                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     314590                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    220977                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.75                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.07                       # Row buffer hit rate for writes
+system.physmem.avgGap                       625806.50                       # Average gap between requests
+system.physmem.pageHitRate                      79.40                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  505526280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  268693590                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1370001780                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                772622640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           11362849680.000002                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             8093551410                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              616183200                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       31552584270                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       13412815680                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        73287717855                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             141246410115                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              334.435695                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           402979630750                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      931134000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      4824278000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   298856786250                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  34929182250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     13606935500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  69194190500                       # Time in different power states
+system.physmem_1.actEnergy                  486640980                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  258644430                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1344519120                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                763837380                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           10801683360.000002                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             7884425820                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              575860800                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       29572982250                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       12813870240                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        74790220020                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             139297315230                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              329.820729                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           403542198250                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      850086750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      4586322000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   305319724750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  33369590750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     13363845750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  64852936500                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 422342506500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               124433445                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          87996604                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6213149                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             71713401                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                67452940                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.059221                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15161942                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1121063                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.059045                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15161931                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1121038                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups            7034                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits               4431                       # Number of indirect target hits.
 system.cpu.branchPred.indirectMisses             2603                       # Number of indirect misses.
@@ -298,22 +309,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    149830726                       # DTB read hits
-system.cpu.dtb.read_misses                     559355                       # DTB read misses
+system.cpu.dtb.read_hits                    149830728                       # DTB read hits
+system.cpu.dtb.read_misses                     559329                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                150390081                       # DTB read accesses
-system.cpu.dtb.write_hits                    57603616                       # DTB write hits
-system.cpu.dtb.write_misses                     71398                       # DTB write misses
+system.cpu.dtb.read_accesses                150390057                       # DTB read accesses
+system.cpu.dtb.write_hits                    57603632                       # DTB write hits
+system.cpu.dtb.write_misses                     71396                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                57675014                       # DTB write accesses
-system.cpu.dtb.data_hits                    207434342                       # DTB hits
-system.cpu.dtb.data_misses                     630753                       # DTB misses
+system.cpu.dtb.write_accesses                57675028                       # DTB write accesses
+system.cpu.dtb.data_hits                    207434360                       # DTB hits
+system.cpu.dtb.data_misses                     630725                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                208065095                       # DTB accesses
-system.cpu.itb.fetch_hits                   227957240                       # ITB hits
+system.cpu.dtb.data_accesses                208065085                       # DTB accesses
+system.cpu.itb.fetch_hits                   227956774                       # ITB hits
 system.cpu.itb.fetch_misses                        48                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               227957288                       # ITB accesses
+system.cpu.itb.fetch_accesses               227956822                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -327,16 +338,16 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  485                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    417805983500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        835611967                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    422342506500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        844685013                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   611901617                       # Number of instructions committed
 system.cpu.committedOps                     611901617                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      14840404                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      14840042                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.365599                       # CPI: cycles per instruction
-system.cpu.ipc                               0.732280                       # IPC: instructions per cycle
+system.cpu.cpi                               1.380426                       # CPI: cycles per instruction
+system.cpu.ipc                               0.724414                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass            52179272      8.53%      8.53% # Class of committed instruction
 system.cpu.op_class_0::IntAlu               355264620     58.06%     66.59% # Class of committed instruction
 system.cpu.op_class_0::IntMult                 152833      0.02%     66.61% # Class of committed instruction
@@ -372,107 +383,107 @@ system.cpu.op_class_0::MemWrite              57220983      9.35%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                611901617                       # Class of committed instruction
-system.cpu.tickCycles                       746834854                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        88777113                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 417805983500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           2535509                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.671717                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           203187431                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2539605                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             80.007494                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1657773500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.671717                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997967                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997967                       # Average percentage of cache occupancy
+system.cpu.tickCycles                       746838140                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        97846873                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           2535505                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.585414                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           203187430                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2539601                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             80.007619                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1692948500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.585414                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997946                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997946                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           75                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          828                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3147                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          827                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3149                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         415624617                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        415624617                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 417805983500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    147521260                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       147521260                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     55666171                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       55666171                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     203187431                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        203187431                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    203187431                       # number of overall hits
-system.cpu.dcache.overall_hits::total       203187431                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1811212                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1811212                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1543863                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1543863                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3355075                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3355075                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3355075                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3355075                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  36424837000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  36424837000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  48227162000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  48227162000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  84651999000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  84651999000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  84651999000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  84651999000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    149332472                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    149332472                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         415624517                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        415624517                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 422342506500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    147521210                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       147521210                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     55666220                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       55666220                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     203187430                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        203187430                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    203187430                       # number of overall hits
+system.cpu.dcache.overall_hits::total       203187430                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1811214                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1811214                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1543814                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1543814                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3355028                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3355028                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3355028                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3355028                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  39457833000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  39457833000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  51431912500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  51431912500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  90889745500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  90889745500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  90889745500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  90889745500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    149332424                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    149332424                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     57210034                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     57210034                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    206542506                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    206542506                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    206542506                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    206542506                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    206542458                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    206542458                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    206542458                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    206542458                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012129                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.012129                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026986                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.026986                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026985                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.026985                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.016244                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.016244                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.016244                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.016244                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20110.752910                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 20110.752910                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31237.980313                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31237.980313                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25231.030305                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25231.030305                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25231.030305                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25231.030305                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21785.295940                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21785.295940                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33314.837474                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33314.837474                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 27090.607142                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 27090.607142                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 27090.607142                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 27090.607142                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      2339290                       # number of writebacks
-system.cpu.dcache.writebacks::total           2339290                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        46416                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        46416                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       769054                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       769054                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       815470                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       815470                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       815470                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       815470                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764796                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1764796                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      2339286                       # number of writebacks
+system.cpu.dcache.writebacks::total           2339286                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        46422                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        46422                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       769005                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       769005                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       815427                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       815427                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       815427                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       815427                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764792                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1764792                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       774809                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       774809                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2539605                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2539605                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2539605                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2539605                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33407226500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33407226500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23596131500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  23596131500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  57003358000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  57003358000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  57003358000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  57003358000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      2539601                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2539601                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2539601                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2539601                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  36307875000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  36307875000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  25218661500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  25218661500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61526536500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  61526536500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61526536500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  61526536500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.011818                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011818                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.013543                       # mshr miss rate for WriteReq accesses
@@ -481,70 +492,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012296
 system.cpu.dcache.demand_mshr_miss_rate::total     0.012296                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012296                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.012296                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18929.795002                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18929.795002                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30454.126759                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30454.126759                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22445.757510                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22445.757510                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.757510                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.757510                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 417805983500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20573.458515                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20573.458515                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32548.229951                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32548.229951                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24226.851580                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24226.851580                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24226.851580                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24226.851580                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements              3176                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1116.932847                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           227952235                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1116.241776                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           227951769                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              5005                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          45544.902098                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          45544.808991                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1116.932847                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.545377                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.545377                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1116.241776                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.545040                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.545040                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1829                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           80                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           88                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3           75                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1592                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.893066                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         455919485                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        455919485                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 417805983500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    227952235                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       227952235                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     227952235                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        227952235                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    227952235                       # number of overall hits
-system.cpu.icache.overall_hits::total       227952235                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         455918553                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        455918553                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 422342506500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    227951769                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       227951769                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     227951769                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        227951769                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    227951769                       # number of overall hits
+system.cpu.icache.overall_hits::total       227951769                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         5005                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          5005                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         5005                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total           5005                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         5005                       # number of overall misses
 system.cpu.icache.overall_misses::total          5005                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    240293500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    240293500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    240293500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    240293500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    240293500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    240293500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    227957240                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    227957240                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    227957240                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    227957240                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    227957240                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    227957240                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    293603500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    293603500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    293603500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    293603500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    293603500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    293603500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    227956774                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    227956774                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    227956774                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    227956774                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    227956774                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    227956774                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48010.689311                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 48010.689311                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 48010.689311                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 48010.689311                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 48010.689311                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 48010.689311                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58662.037962                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 58662.037962                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 58662.037962                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 58662.037962                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 58662.037962                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 58662.037962                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -559,104 +570,104 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         5005
 system.cpu.icache.demand_mshr_misses::total         5005                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         5005                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         5005                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    235288500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    235288500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    235288500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    235288500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    235288500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    235288500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    288598500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    288598500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    288598500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    288598500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    288598500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    288598500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47010.689311                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47010.689311                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47010.689311                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 47010.689311                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47010.689311                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 47010.689311                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 417805983500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           348624                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30584.299067                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4701898                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           381392                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.328255                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      70204848000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    42.155334                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.471297                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 30381.672435                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.001286                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004897                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.927175                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.933359                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57662.037962                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57662.037962                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57662.037962                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 57662.037962                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57662.037962                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 57662.037962                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           348623                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30598.806406                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4701891                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           381391                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.328269                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      70474186000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks    42.061592                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   159.646104                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 30397.098711                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.001284                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004872                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.927646                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.933801                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          148                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          114                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          172                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1626                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        30708                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         41047752                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        41047752                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 417805983500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks      2339290                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      2339290                       # number of WritebackDirty hits
+system.cpu.l2cache.tags.tag_accesses         41047687                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        41047687                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 422342506500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2339286                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2339286                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks         3176                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total         3176                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data       571694                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total       571694                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2557                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total         2557                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1589843                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1589843                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1589840                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1589840                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst         2557                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2161537                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2164094                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2161534                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2164091                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst         2557                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2161537                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2164094                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2161534                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2164091                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data       206458                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       206458                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2448                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total         2448                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       171610                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       171610                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       171609                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       171609                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         2448                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       378068                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        380516                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       378067                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        380515                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         2448                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       378068                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       380516                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16474699500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  16474699500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    200914000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    200914000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14008549000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  14008549000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    200914000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  30483248500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  30684162500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    200914000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  30483248500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  30684162500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      2339290                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      2339290                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.data       378067                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       380515                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  18097806000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  18097806000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    254224000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    254224000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  16908659000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  16908659000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    254224000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  35006465000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  35260689000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    254224000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  35006465000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  35260689000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2339286                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2339286                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks         3176                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total         3176                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       778152                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       778152                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5005                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::total         5005                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1761453                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1761453                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1761449                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1761449                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst         5005                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2539605                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2544610                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2539601                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2544606                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst         5005                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2539605                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2544610                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2539601                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2544606                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.265318                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.265318                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.489111                       # miss rate for ReadCleanReq accesses
@@ -669,52 +680,52 @@ system.cpu.l2cache.demand_miss_rate::total     0.149538                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.489111                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.148869                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.149538                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79796.856988                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79796.856988                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82072.712418                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82072.712418                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81630.143931                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81630.143931                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82072.712418                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80629.009861                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80638.297733                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82072.712418                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80629.009861                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80638.297733                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87658.535877                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87658.535877                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103849.673203                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103849.673203                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98530.141193                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98530.141193                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103849.673203                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92593.283730                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 92665.700432                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103849.673203                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92593.283730                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 92665.700432                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks       294363                       # number of writebacks
-system.cpu.l2cache.writebacks::total           294363                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       294362                       # number of writebacks
+system.cpu.l2cache.writebacks::total           294362                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            5                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total            5                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206458                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       206458                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2448                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2448                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       171610                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       171610                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       171609                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       171609                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2448                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       378068                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       380516                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       378067                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       380515                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2448                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       378068                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       380516                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14410119500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14410119500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    176434000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    176434000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12292449000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12292449000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    176434000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26702568500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  26879002500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    176434000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26702568500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  26879002500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data       378067                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       380515                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16033226000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16033226000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    229744000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    229744000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15192569000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15192569000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    229744000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  31225795000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  31455539000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    229744000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  31225795000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  31455539000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.265318                       # mshr miss rate for ReadExReq accesses
@@ -729,90 +740,90 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.149538
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.489111                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.148869                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.149538                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69796.856988                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69796.856988                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72072.712418                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72072.712418                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71630.143931                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71630.143931                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72072.712418                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70629.009861                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70638.297733                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72072.712418                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70629.009861                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70638.297733                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      5083295                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2538685                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77658.535877                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77658.535877                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93849.673203                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93849.673203                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88530.141193                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88530.141193                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93849.673203                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82593.283730                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82665.700432                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93849.673203                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82593.283730                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82665.700432                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      5083287                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2538681                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         2446                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2446                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 417805983500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp       1766458                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      2633653                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 422342506500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp       1766454                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2633648                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean         3176                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict       250480                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       778152                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       778152                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq         5005                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1761453                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1761449                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13186                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7614719                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7627905                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7614707                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7627893                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       523584                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312249280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          312772864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      348624                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              18839232                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      2893234                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312248768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          312772352                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      348623                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic              18839168                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      2893229                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000845                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.029064                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2890788     99.92%     99.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2890783     99.92%     99.92% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1               2446      0.08%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2893234                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4884113500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2893229                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4884105500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       7507500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3809407500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3809401500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests        726699                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       346183                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests        726697                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       346182                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 417805983500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp             174058                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       294363                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 422342506500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp             174057                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       294362                       # Transaction distribution
 system.membus.trans_dist::CleanEvict            51820                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            206458                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           206458                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        174058                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1107215                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1107215                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43192256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43192256                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        174057                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1107212                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1107212                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43192128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43192128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            380516                       # Request fanout histogram
+system.membus.snoop_fanout::samples            380515                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  380516    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  380515    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              380516                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2021728500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              380515                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2021742500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2014027500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2013933750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
index 9fc640f03..2bcdda822 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
@@ -151,7 +151,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -631,7 +631,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -691,7 +691,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -880,6 +880,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -891,7 +892,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -899,29 +900,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -941,6 +949,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -972,9 +981,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout
index 0165cf685..e03b3777c 100755
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:38:21
-gem5 executing on e108600-lin, pid 23072
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:47:38
+gem5 executing on e108600-lin, pid 17428
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -70,4 +70,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 366439129500 because target called exit()
+Exiting @ tick 368600034500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index 3a2939b58..3968e09e7 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.366632                       # Number of seconds simulated
-sim_ticks                                366631719500                       # Number of ticks simulated
-final_tick                               366631719500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.368600                       # Number of seconds simulated
+sim_ticks                                368600034500                       # Number of ticks simulated
+final_tick                               368600034500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 211005                       # Simulator instruction rate (inst/s)
-host_op_rate                                   228546                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              152712719                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277288                       # Number of bytes of host memory used
-host_seconds                                  2400.79                       # Real time elapsed on the host
+host_inst_rate                                 189198                       # Simulator instruction rate (inst/s)
+host_op_rate                                   204927                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              137665575                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 274600                       # Number of bytes of host memory used
+host_seconds                                  2677.50                       # Real time elapsed on the host
 sim_insts                                   506579366                       # Number of instructions simulated
 sim_ops                                     548692589                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            179840                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           9053376                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              9233216                       # Number of bytes read from this memory
@@ -26,54 +26,54 @@ system.physmem.num_reads::cpu.data             141459                       # Nu
 system.physmem.num_reads::total                144269                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           97528                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                97528                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               490519                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             24693379                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                25183898                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          490519                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             490519                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          17024692                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               17024692                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          17024692                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              490519                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            24693379                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42208590                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               487900                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             24561517                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                25049417                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          487900                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             487900                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          16933780                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               16933780                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          16933780                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              487900                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            24561517                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               41983197                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        144269                       # Number of read requests accepted
 system.physmem.writeReqs                        97528                       # Number of write requests accepted
 system.physmem.readBursts                      144269                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      97528                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9226688                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6528                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6240064                       # Total number of bytes written to DRAM
+system.physmem.bytesReadDRAM                  9225856                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6240448                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                   9233216                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                6241792                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      102                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9376                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9372                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                8929                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8964                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8666                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9423                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9371                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8963                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8667                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9424                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9372                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                8974                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8126                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8634                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8127                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8635                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                8697                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8760                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9487                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9347                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9550                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8728                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9135                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6252                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8761                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9485                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9346                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9545                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8729                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9128                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6253                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                6118                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                6042                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                5901                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                6273                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                6263                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6069                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5534                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5815                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5535                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5819                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                5920                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               5985                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6510                       # Per bank write bursts
@@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14               6013                       # Pe
 system.physmem.perBankWrBursts::15               6102                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    366631694000                       # Total gap between requests
+system.physmem.totGap                    368600009000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -98,9 +98,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  97528                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    143840                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       311                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        16                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    143801                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       333                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -145,32 +145,32 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2842                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2979                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5731                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5731                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5736                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5754                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2891                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5701                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5742                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5743                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5744                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5746                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5749                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5745                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5765                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5752                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5747                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
@@ -194,106 +194,116 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        63306                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      244.314283                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     163.017060                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     244.594379                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22538     35.60%     35.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17961     28.37%     63.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7327     11.57%     75.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7996     12.63%     88.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2051      3.24%     91.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1180      1.86%     93.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          835      1.32%     94.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          660      1.04%     95.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         2758      4.36%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          63306                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5727                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.172342                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       18.597400                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      376.088417                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5724     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        63970                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      241.763327                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     162.115864                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     241.210402                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22774     35.60%     35.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18302     28.61%     64.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7461     11.66%     75.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         8049     12.58%     88.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2117      3.31%     91.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1180      1.84%     93.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          776      1.21%     94.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          623      0.97%     95.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         2688      4.20%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          63970                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5740                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.113240                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      375.658190                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5737     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5727                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5727                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.024795                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.995243                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.004050                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2743     47.90%     47.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                142      2.48%     50.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               2814     49.14%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 20      0.35%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  6      0.10%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5727                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1581653750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4284785000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    720835000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10970.98                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5740                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5740                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.987282                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.957535                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.009458                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2852     49.69%     49.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                159      2.77%     52.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               2701     47.06%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 19      0.33%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  6      0.10%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5740                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3577413000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                6280300500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    720770000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       24816.61                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29720.98                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          25.17                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          17.02                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       25.18                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       17.02                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  43566.61                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          25.03                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          16.93                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       25.05                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       16.93                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.20                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     110439                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     67921                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.60                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  69.64                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1516278.92                       # Average gap between requests
-system.physmem.pageHitRate                      73.80                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  239652000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  130762500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 560266200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                313968960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            23946564720                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            47282173740                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           178503263250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             250976651370                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              684.547573                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   296644648000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     12242620000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     57744168750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  238941360                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  130374750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 564213000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                317837520                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            23946564720                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            47121480765                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           178644216000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             250963628115                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              684.512070                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   296880094250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     12242620000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     57508713250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               132103795                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          98193288                       # Number of conditional branches predicted
+system.physmem.avgWrQLen                        20.06                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     110541                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     67141                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.68                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  68.84                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1524419.28                       # Average gap between requests
+system.physmem.pageHitRate                      73.52                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  229615260                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  122028225                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 512851920                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                252929880                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           7711888080.000002                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             3985238790                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              353652480                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       24742370760                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        8329193280                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        68838779610                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             115080424995                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              312.209476                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           358934915250                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      533175250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      3272498000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   282985145000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  21690770000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      5858999750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  54259446500                       # Time in different power states
+system.physmem_1.actEnergy                  227194800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  120737925                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 516407640                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                256056660                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           7588960080.000002                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3990658350                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              342745440                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       24389253480                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        8128930080                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        69135041760                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             114698280525                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              311.172732                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           358951286500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      511434000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      3220288000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   284296674500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  21168817000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      5916972250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  53485848750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               132103819                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          98193306                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           5910048                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             68601542                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                60590460                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups             68601561                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                60590477                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             88.322300                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                10017120                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             88.322301                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                10017121                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect              18743                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         3891574                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            3883027                       # Number of indirect target hits.
+system.cpu.branchPred.indirectLookups         3891575                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            3883028                       # Number of indirect target hits.
 system.cpu.branchPred.indirectMisses             8547                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted        54138                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -323,7 +333,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -353,7 +363,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -383,7 +393,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -414,16 +424,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    366631719500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        733263439                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        737200069                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   506579366                       # Number of instructions committed
 system.cpu.committedOps                     548692589                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      12939754                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      12939783                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.447480                       # CPI: cycles per instruction
-system.cpu.ipc                               0.690856                       # IPC: instructions per cycle
+system.cpu.cpi                               1.455251                       # CPI: cycles per instruction
+system.cpu.ipc                               0.687167                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu               375609862     68.46%     68.46% # Class of committed instruction
 system.cpu.op_class_0::IntMult                 339219      0.06%     68.52% # Class of committed instruction
@@ -459,61 +469,61 @@ system.cpu.op_class_0::MemWrite              56860222     10.36%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                548692589                       # Class of committed instruction
-system.cpu.tickCycles                       694072576                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        39190863                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                       694074439                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        43125630                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements           1141337                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.301946                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           171083822                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4070.214597                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           171083824                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           1145433                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            149.361702                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        5036525500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.301946                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993726                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993726                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            149.361703                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        5072633500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.214597                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993705                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993705                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          549                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3501                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          543                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3507                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         346338109                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        346338109                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    114566017                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114566017                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     53537929                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       53537929                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         346338045                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        346338045                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    114566013                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114566013                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     53537935                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       53537935                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data         2794                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total          2794                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168103946                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168103946                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168106740                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168106740                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       811381                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        811381                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       701120                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       701120                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     168103948                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168103948                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168106742                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168106742                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       811353                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        811353                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       701114                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       701114                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           15                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           15                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1512501                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1512501                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1512516                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1512516                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  13515584500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  13515584500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  22200332500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  22200332500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35715917000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35715917000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35715917000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35715917000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    115377398                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    115377398                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      1512467                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1512467                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1512482                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1512482                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14511838000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14511838000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  24015669000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  24015669000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  38527507000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  38527507000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  38527507000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  38527507000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    115377366                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    115377366                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data         2809                       # number of SoftPFReq accesses(hits+misses)
@@ -522,10 +532,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541
 system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    169616447                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    169616447                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    169619256                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    169619256                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    169616415                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    169616415                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    169619224                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    169619224                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007032                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.007032                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012926                       # miss rate for WriteReq accesses
@@ -536,14 +546,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.008917
 system.cpu.dcache.demand_miss_rate::total     0.008917                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.008917                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.008917                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16657.506769                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16657.506769                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31664.098157                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31664.098157                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23613.813809                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23613.813809                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23613.579625                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23613.579625                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.973183                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.973183                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.586435                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.586435                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.287682                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25473.287682                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.035051                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25473.035051                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -552,14 +562,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.writebacks::writebacks      1068942                       # number of writebacks
 system.cpu.dcache.writebacks::total           1068942                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22348                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        22348                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344732                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       344732                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       367080                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       367080                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       367080                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       367080                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22320                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        22320                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344726                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       344726                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       367046                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       367046                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       367046                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       367046                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       789033                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       789033                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356388                       # number of WriteReq MSHR misses
@@ -570,16 +580,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1145421
 system.cpu.dcache.demand_mshr_misses::total      1145421                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1145433                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1145433                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12423186500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12423186500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11274063500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11274063500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       942500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       942500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23697250000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  23697250000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23698192500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  23698192500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13416891000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  13416891000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12196191000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12196191000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      4297000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      4297000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25613082000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25613082000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  25617379000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  25617379000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006839                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006839                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006571                       # mshr miss rate for WriteReq accesses
@@ -590,26 +600,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006753
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006753                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006753                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006753                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15744.824995                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15744.824995                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31634.239930                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31634.239930                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78541.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78541.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20688.681280                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20688.681280                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20689.287370                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20689.287370                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements             18175                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1187.102530                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           199148962                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             20047                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           9934.102958                       # Average number of references to valid blocks.
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.220356                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.220356                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.665713                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.665713                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.282009                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.282009                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.799163                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.799163                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements             18178                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1186.508914                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           199149017                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             20050                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           9932.619302                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1187.102530                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.579640                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.579640                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1186.508914                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.579350                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.579350                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
@@ -617,180 +627,180 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2           57
 system.cpu.icache.tags.age_task_id_blocks_1024::3          311                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1400                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         398358065                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        398358065                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    199148962                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       199148962                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     199148962                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        199148962                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    199148962                       # number of overall hits
-system.cpu.icache.overall_hits::total       199148962                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        20047                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         20047                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        20047                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          20047                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        20047                       # number of overall misses
-system.cpu.icache.overall_misses::total         20047                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    467837000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    467837000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    467837000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    467837000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    467837000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    467837000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    199169009                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    199169009                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    199169009                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    199169009                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    199169009                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    199169009                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         398358184                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        398358184                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    199149017                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       199149017                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     199149017                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        199149017                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    199149017                       # number of overall hits
+system.cpu.icache.overall_hits::total       199149017                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        20050                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         20050                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        20050                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          20050                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        20050                       # number of overall misses
+system.cpu.icache.overall_misses::total         20050                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    544281000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    544281000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    544281000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    544281000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    544281000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    544281000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    199169067                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    199169067                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    199169067                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    199169067                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    199169067                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    199169067                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000101                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000101                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000101                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000101                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000101                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000101                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23337.008031                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 23337.008031                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 23337.008031                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 23337.008031                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23337.008031                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 23337.008031                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.184539                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 27146.184539                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.184539                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 27146.184539                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.184539                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 27146.184539                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks        18175                       # number of writebacks
-system.cpu.icache.writebacks::total             18175                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        20047                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        20047                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        20047                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        20047                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        20047                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        20047                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    447790000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    447790000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    447790000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    447790000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    447790000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    447790000                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks        18178                       # number of writebacks
+system.cpu.icache.writebacks::total             18178                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        20050                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        20050                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        20050                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        20050                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        20050                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        20050                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    524231000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    524231000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    524231000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    524231000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    524231000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    524231000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000101                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000101                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000101                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22337.008031                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22337.008031                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22337.008031                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22337.008031                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22337.008031                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22337.008031                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.184539                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.184539                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.184539                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.184539                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.184539                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.184539                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements           112761                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29068.883602                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2174452                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        29076.847904                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2174458                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           145529                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            14.941709                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     101788000000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   134.067060                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   307.855024                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 28626.961519                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.004091                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009395                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.873626                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.887112                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.avg_refs            14.941750                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     102118428000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   133.889042                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   307.541070                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417793                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.004086                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009385                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.873884                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.887355                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          111                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          981                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31589                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         18705497                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        18705497                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.tag_accesses         18705537                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18705537                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks      1068942                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total      1068942                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        17938                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        17938                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        17940                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        17940                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data       255660                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total       255660                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        17235                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        17235                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        17239                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        17239                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data       748301                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total       748301                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        17235                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst        17239                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data      1003961                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1021196                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        17235                       # number of overall hits
+system.cpu.l2cache.demand_hits::total         1021200                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        17239                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data      1003961                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1021196                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1021200                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data       100978                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       100978                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2812                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2812                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2811                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2811                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data        40494                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total        40494                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2812                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         2811                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data       141472                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        144284                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2812                       # number of overall misses
+system.cpu.l2cache.demand_misses::total        144283                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2811                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       141472                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       144284                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8057525500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8057525500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    236084500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    236084500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3363607000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   3363607000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    236084500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  11421132500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11657217000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    236084500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  11421132500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11657217000                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total       144283                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8979653000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8979653000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    312477500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    312477500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   4360667500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   4360667500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    312477500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  13340320500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  13652798000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    312477500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  13340320500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  13652798000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks      1068942                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total      1068942                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        17938                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        17938                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        17940                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        17940                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       356638                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       356638                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        20047                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        20047                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        20050                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        20050                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       788795                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total       788795                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        20047                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        20050                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data      1145433                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1165480                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        20047                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1165483                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        20050                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      1145433                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1165480                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1165483                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.283139                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.283139                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.140270                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.140270                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.140200                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.140200                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.051337                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.051337                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.140270                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.140200                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.123510                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.123798                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.140270                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.123797                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.140200                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.123510                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.123798                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79794.861257                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79794.861257                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83956.081081                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83956.081081                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83064.330518                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83064.330518                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83956.081081                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80730.692292                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80793.552993                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83956.081081                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80730.692292                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80793.552993                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.123797                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.825645                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.825645                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111162.397723                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111162.397723                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.756063                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.756063                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111162.397723                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.542779                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 94625.132552                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111162.397723                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.542779                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 94625.132552                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -799,16 +809,16 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.writebacks::writebacks        97528                       # number of writebacks
 system.cpu.l2cache.writebacks::total            97528                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           13                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total           13                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           13                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           15                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           13                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100978                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       100978                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2810                       # number of ReadCleanReq MSHR misses
@@ -821,79 +831,79 @@ system.cpu.l2cache.demand_mshr_misses::total       144269
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2810                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       141459                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       144269                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7047745500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7047745500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    207624000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    207624000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2957433000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2957433000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    207624000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10005178500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10212802500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    207624000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10005178500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10212802500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7969873000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7969873000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    284302500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    284302500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   3953965500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   3953965500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    284302500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11923838500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  12208141000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    284302500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11923838500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  12208141000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283139                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283139                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.140171                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.140171                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.140150                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.140150                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.051320                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.051320                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.140171                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.140150                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.123498                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.123785                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.140171                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.140150                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123498                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.123785                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.861257                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.861257                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73887.544484                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73887.544484                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73057.310837                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73057.310837                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73887.544484                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70728.469026                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70789.999931                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73887.544484                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70728.469026                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70789.999931                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      2324992                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159582                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4996                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.825645                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.825645                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101175.266904                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101175.266904                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.600430                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.600430                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101175.266904                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.833676                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101175.266904                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.833676                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      2324998                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159585                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4997                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         2618                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2615                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp        808842                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp        808845                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty      1166470                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        18175                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        18178                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict        87628                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       356638                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       356638                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        20047                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        20050                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq       788795                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58269                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58278                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3432203                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3490472                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2446208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3490481                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2446592                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141720000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          144166208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          144166592                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                      112761                       # Total snoops (count)
 system.cpu.toL2Bus.snoopTraffic               6241792                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      1278241                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.006014                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.077345                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      1278244                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.006015                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.077350                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1270557     99.40%     99.40% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               7681      0.60%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1270559     99.40%     99.40% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               7682      0.60%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  3      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1278241                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2249613000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1278244                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2249619000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      30094452                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      30098453                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1718157983                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
@@ -903,7 +913,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 366631719500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp              43291                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        97528                       # Transaction distribution
 system.membus.trans_dist::CleanEvict            12615                       # Transaction distribution
@@ -926,9 +936,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total              144269                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           685129000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           685124000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          765930250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          765885250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 74b919a26..4329f3215 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -172,7 +172,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -534,7 +534,7 @@ pipelined=true
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -813,6 +813,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -824,7 +825,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -832,29 +833,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -874,6 +882,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -905,9 +914,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
index 03bbf5323..87601728e 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:27:26
-gem5 executing on e108600-lin, pid 12521
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:43:00
+gem5 executing on e108600-lin, pid 17328
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -70,4 +70,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 232864525000 because target called exit()
+Exiting @ tick 236034256000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index f10b69af3..48fa8fd80 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,121 +1,121 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.233363                       # Number of seconds simulated
-sim_ticks                                233363457000                       # Number of ticks simulated
-final_tick                               233363457000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.236034                       # Number of seconds simulated
+sim_ticks                                236034256000                       # Number of ticks simulated
+final_tick                               236034256000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 153279                       # Simulator instruction rate (inst/s)
-host_op_rate                                   166055                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               70798116                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302508                       # Number of bytes of host memory used
-host_seconds                                  3296.18                       # Real time elapsed on the host
+host_inst_rate                                 147811                       # Simulator instruction rate (inst/s)
+host_op_rate                                   160132                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               69053974                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 301356                       # Number of bytes of host memory used
+host_seconds                                  3418.11                       # Real time elapsed on the host
 sim_insts                                   505234934                       # Number of instructions simulated
 sim_ops                                     547348155                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            641792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10513600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     16409344                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             27564736                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       641792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          641792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18651328                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18651328                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              10028                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             164275                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       256396                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                430699                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          291427                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               291427                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2750182                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             45052469                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     70316682                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               118119333                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2750182                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2750182                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          79923945                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               79923945                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          79923945                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2750182                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            45052469                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     70316682                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              198043278                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        430699                       # Number of read requests accepted
-system.physmem.writeReqs                       291427                       # Number of write requests accepted
-system.physmem.readBursts                      430699                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     291427                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 27407296                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    157440                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18649728                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  27564736                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18651328                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     2460                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       6                       # Number of DRAM write bursts merged with an existing one
+system.physmem.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            637184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10497472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     16389440                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             27524096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       637184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          637184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18641536                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18641536                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               9956                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             164023                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       256085                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                430064                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          291274                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               291274                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2699540                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             44474358                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     69436701                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               116610599                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2699540                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2699540                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          78978095                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               78978095                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          78978095                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2699540                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            44474358                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     69436701                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              195588695                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        430064                       # Number of read requests accepted
+system.physmem.writeReqs                       291274                       # Number of write requests accepted
+system.physmem.readBursts                      430064                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     291274                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 27360896                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    163200                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18638848                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  27524096                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18641536                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     2550                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      11                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               27205                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26463                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25602                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               32969                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               28037                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               29890                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25340                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24398                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25649                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25581                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25884                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              26303                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27555                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              26148                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              24908                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              26307                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18644                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               18139                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               17950                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               17944                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18581                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18235                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               17841                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               17708                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18005                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               17734                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18244                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              18783                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18680                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18156                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              18369                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              18389                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               27217                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26580                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25459                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               32933                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               28005                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               30095                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25324                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24336                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25637                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25661                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25768                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              26242                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              27581                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              26014                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              24864                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25798                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18651                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               18268                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               17926                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               17983                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18558                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18375                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               17786                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               17681                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18027                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               17737                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18114                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18781                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18716                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18163                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              18303                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              18163                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    233363404500                       # Total gap between requests
+system.physmem.totGap                    236034203500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  430699                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  430064                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 291427                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    330391                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     50226                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     12856                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8880                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6027                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5118                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4235                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3274                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        56                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       16                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 291274                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    318869                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     60281                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     13267                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8983                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7229                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6032                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5148                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4295                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3299                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        63                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       23                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -149,41 +149,41 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     7280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    12492                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    15016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    16255                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    16901                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17654                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17875                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    18074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    18193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    18541                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    18646                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    18700                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    18837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17505                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17030                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6756                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7242                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    12113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    14851                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    16256                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    16916                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17615                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17892                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    18128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    18323                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    18440                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    18551                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    18644                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    18821                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    18548                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       50                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
@@ -198,117 +198,124 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       328347                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      140.266048                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      98.833830                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     178.808988                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         208753     63.58%     63.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        80037     24.38%     87.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        14980      4.56%     92.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7256      2.21%     94.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         4857      1.48%     96.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2521      0.77%     96.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1858      0.57%     97.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1524      0.46%     98.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6561      2.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         328347                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         16970                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.230642                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      145.328941                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          16968     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       329061                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      139.787432                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      98.478985                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     178.644390                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         210353     63.93%     63.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        79320     24.10%     88.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        14852      4.51%     92.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7229      2.20%     94.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         4899      1.49%     96.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2483      0.75%     96.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1823      0.55%     97.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1564      0.48%     98.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6538      1.99%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         329061                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17032                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.095820                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      145.258821                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17030     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::18432-19455            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           16970                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         16970                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.171597                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.099419                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.840930                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            9436     55.60%     55.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            6694     39.45%     95.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21             588      3.46%     98.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23             150      0.88%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              55      0.32%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              20      0.12%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29               4      0.02%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31               8      0.05%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33               2      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35               4      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37               1      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43               1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45               1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51               1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62-63               1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-73               1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-77               1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::94-95               1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           16970                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8687632010                       # Total ticks spent queuing
-system.physmem.totMemAccLat               16717113260                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2141195000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20286.88                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           17032                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17032                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.099108                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.028520                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.818567                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17           10039     58.94%     58.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            6203     36.42%     95.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21             545      3.20%     98.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23             139      0.82%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              59      0.35%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              18      0.11%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29               9      0.05%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31               2      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               2      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35               2      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               3      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39               5      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41               2      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61               2      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::70-71               1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-105             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17032                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    14213030846                       # Total ticks spent queuing
+system.physmem.totMemAccLat               22228918346                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2137570000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       33245.77                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39036.88                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         117.44                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          79.92                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      118.12                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       79.92                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  51995.77                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         115.92                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          78.97                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      116.61                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       78.98                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.54                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.92                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           1.52                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.91                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.62                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.12                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.52                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     308039                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     83248                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   71.93                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  28.57                       # Row buffer hit rate for writes
-system.physmem.avgGap                       323161.62                       # Average gap between requests
-system.physmem.pageHitRate                      54.37                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1261242360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  688177875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1715142000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                939872160                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            15242051760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            86511761685                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            64129665000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             170487912840                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              730.572857                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   106127593352                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7792460000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    119441919148                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1221045840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  666245250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1624857000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                948412800                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            15242051760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            81485025165                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            68539083000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             169726720815                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              727.311005                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   113492657633                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7792460000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    112077139867                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               174594135                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         131061438                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           7233022                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             90315091                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                79002409                       # Number of BTB hits
+system.physmem.avgWrQLen                        21.65                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     307655                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     82023                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   71.96                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  28.16                       # Row buffer hit rate for writes
+system.physmem.avgGap                       327217.20                       # Average gap between requests
+system.physmem.pageHitRate                      54.21                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1196014260                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  635677680                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1570435860                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                758090160                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           15730481520.000004                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            13398551100                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              618704160                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       46181225010                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       17503538880                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        15597346500                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             113194744170                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              479.569128                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           205028158054                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      920292705                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      6672444000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    58173065750                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  45581110454                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     23413245991                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 101274097100                       # Time in different power states
+system.physmem_1.actEnergy                 1153531260                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  613108815                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1482014100                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                762140880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           15061753200.000004                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            13366111830                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              607264320                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       42525061470                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       17168834400                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        17794675410                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             110539948695                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              468.321620                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           205130134268                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      923619714                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      6390116000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    67161872750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  44710479181                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     23590386018                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  93257782337                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               174591760                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         131058406                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           7233420                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             90376052                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                79001018                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             87.474206                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                12105110                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             104499                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         4687937                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            4674274                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses            13663                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted        53871                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             87.413664                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                12105632                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104483                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         4688252                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            4674256                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            13996                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        53921                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -338,7 +345,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -368,7 +375,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -398,7 +405,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -429,233 +436,233 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    233363457000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        466726915                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    236034256000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        472068513                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            7649319                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      727510991                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   174594135                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           95781793                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     451018276                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                14520177                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 5415                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           146                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        13360                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 235275678                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 36827                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          465946604                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.690437                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.183518                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles            7651832                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      727514898                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   174591760                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           95780906                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     456008633                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                14520873                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 8018                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            72                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles        15159                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 235276766                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 36821                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          470944150                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.672513                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.189889                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 96241342     20.66%     20.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                132050994     28.34%     49.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 57360477     12.31%     61.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                180293791     38.69%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                101233581     21.50%     21.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                132057346     28.04%     49.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 57356975     12.18%     61.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                180296248     38.28%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            465946604                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.374082                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.558751                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 32536552                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             120918293                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 282902203                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              22817634                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                6771922                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             23855471                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                495849                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              710960604                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              29091371                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                6771922                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 63349282                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                56784032                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       40401553                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 273510163                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              25129652                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              682692967                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              12844145                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               9945202                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2511648                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1805093                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1905777                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           827472920                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3000392013                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        718609980                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups                96                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            470944150                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.369844                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.541121                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32549558                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             125926098                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 282874913                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              22821432                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                6772149                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             23855969                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                495947                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              710956468                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              29088219                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                6772149                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 63367796                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                61282237                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       40473434                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 273481495                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              25567039                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              682687004                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              12847672                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              10037372                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2522908                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1816731                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                2323927                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           827475029                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3000364097                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        718606364                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               112                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             654095674                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                173377246                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1545812                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1536134                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  43839802                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            142358029                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            67522859                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12902461                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11335768                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  664750936                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2979334                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 608926553                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5748894                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       120382115                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    306467952                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1702                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     465946604                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.306859                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.102130                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                173379355                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1545861                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        1536327                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  43857094                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            142358041                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            67520451                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12908238                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11335045                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  664745436                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2979378                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 608905066                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5749480                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       120376659                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    306522000                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1746                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     470944150                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.292945                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.104492                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           149520607     32.09%     32.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           100880237     21.65%     53.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           145552540     31.24%     84.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            63032249     13.53%     98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6960366      1.49%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 605      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           154541552     32.82%     32.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           100868277     21.42%     54.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           145535828     30.90%     85.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            63029448     13.38%     98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6968436      1.48%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 609      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       465946604                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       470944150                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                71896734     53.12%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     30      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     53.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44291867     32.73%     85.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              19147796     14.15%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                71902487     53.13%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     30      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44305814     32.74%     85.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              19132145     14.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             412590919     67.76%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               352109      0.06%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            133574983     21.94%     89.75% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            62408539     10.25%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             412584657     67.76%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               352207      0.06%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            133573210     21.94%     89.75% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            62394989     10.25%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              608926553                       # Type of FU issued
-system.cpu.iq.rate                           1.304674                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   135336427                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.222254                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1824884935                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         788141663                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    594200588                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                  96                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                 76                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              608905066                       # Type of FU issued
+system.cpu.iq.rate                           1.289866                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   135340476                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.222269                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1829844132                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         788130713                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    594185364                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 106                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                 88                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              744262920                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      60                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          7284479                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              744245476                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      66                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          7285563                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     26474746                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        24624                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        29798                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     10662639                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     26474758                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        24641                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        29761                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     10660231                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       225013                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         22508                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       224867                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         23122                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                6771922                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                22843049                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                918168                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           669223084                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                6772149                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                23809987                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                977416                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           669217601                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             142358029                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             67522859                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1490792                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 256633                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                523882                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          29798                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3590923                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3742651                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              7333574                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             598420503                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             129081054                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10506050                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             142358041                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             67520451                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1490836                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 256647                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                583506                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          29761                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3591077                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3742851                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              7333928                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             598406414                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             129080217                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10498652                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       1492814                       # number of nop insts executed
-system.cpu.iew.exec_refs                    190002009                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                131263961                       # Number of branches executed
-system.cpu.iew.exec_stores                   60920955                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.282164                       # Inst execution rate
-system.cpu.iew.wb_sent                      595445456                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     594200604                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 349565575                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 571385188                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.273123                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.611786                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       107116116                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                       1492787                       # number of nop insts executed
+system.cpu.iew.exec_refs                    189993781                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                131261458                       # Number of branches executed
+system.cpu.iew.exec_stores                   60913564                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.267626                       # Inst execution rate
+system.cpu.iew.wb_sent                      595430710                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     594185380                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 349559163                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 571371780                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.258685                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.611789                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       107108792                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           6744856                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    449285999                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.221253                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.890713                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6745133                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    454284606                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.207816                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.884395                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    220514428     49.08%     49.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    116376748     25.90%     74.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     43480691      9.68%     84.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     23177999      5.16%     89.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     11514242      2.56%     92.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7755129      1.73%     94.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8259802      1.84%     95.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4227193      0.94%     96.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     13979767      3.11%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    225505384     49.64%     49.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    116384460     25.62%     75.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     43472433      9.57%     84.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     23172184      5.10%     89.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     11521266      2.54%     92.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7756423      1.71%     94.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8277792      1.82%     95.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4245082      0.93%     96.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     13949582      3.07%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    449285999                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    454284606                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            506578818                       # Number of instructions committed
 system.cpu.commit.committedOps              548692039                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -701,560 +708,559 @@ system.cpu.commit.op_class_0::MemWrite       56860220     10.36%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         548692039                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              13979767                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1091107249                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1328306301                       # The number of ROB writes
-system.cpu.timesIdled                           14326                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          780311                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              13949582                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1096128717                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1328290478                       # The number of ROB writes
+system.cpu.timesIdled                           14613                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1124363                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   505234934                       # Number of Instructions Simulated
 system.cpu.committedOps                     547348155                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.923782                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.923782                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.082507                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.082507                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                610129735                       # number of integer regfile reads
-system.cpu.int_regfile_writes               327331512                       # number of integer regfile writes
+system.cpu.cpi                               0.934354                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.934354                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.070258                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.070258                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                610109745                       # number of integer regfile reads
+system.cpu.int_regfile_writes               327329948                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                2166233884                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                376536291                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               217601523                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                2166188285                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                376531340                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               217592371                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           2817306                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.628303                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168866082                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2817818                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             59.927959                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         501259000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.628303                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           2817297                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.628265                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168862807                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2817809                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             59.926988                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         504720000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.628265                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999274                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999274                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          165                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          280                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          152                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          293                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         355259202                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        355259202                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    114162091                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114162091                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     51724043                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       51724043                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         2789                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          2789                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         355255813                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        355255813                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    114160281                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114160281                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     51722579                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       51722579                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2790                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2790                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488560                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      1488560                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     165886134                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        165886134                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    165888923                       # number of overall hits
-system.cpu.dcache.overall_hits::total       165888923                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      4839586                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       4839586                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2515006                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2515006                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data           10                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total           10                       # number of SoftPFReq misses
+system.cpu.dcache.demand_hits::cpu.data     165882860                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        165882860                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    165885650                       # number of overall hits
+system.cpu.dcache.overall_hits::total       165885650                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      4839703                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       4839703                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2516470                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2516470                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data           12                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total           12                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data           66                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total           66                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      7354592                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        7354592                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      7354602                       # number of overall misses
-system.cpu.dcache.overall_misses::total       7354602                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  58596122500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  58596122500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18922626430                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18922626430                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1155000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      1155000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  77518748930                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  77518748930                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  77518748930                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  77518748930                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    119001677                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    119001677                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      7356173                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        7356173                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      7356185                       # number of overall misses
+system.cpu.dcache.overall_misses::total       7356185                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  63969719500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  63969719500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  19897650428                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  19897650428                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1356500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      1356500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  83867369928                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  83867369928                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  83867369928                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  83867369928                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    118999984                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    118999984                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2799                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2799                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2802                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2802                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488626                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      1488626                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    173240726                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    173240726                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    173243525                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    173243525                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040668                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040668                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046369                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.046369                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.003573                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.003573                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    173239033                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    173239033                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    173241835                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    173241835                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040670                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040670                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046396                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.046396                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004283                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.004283                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000044                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000044                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.042453                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.042453                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.042452                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.042452                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12107.672536                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 12107.672536                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7523.889180                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  7523.889180                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        17500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        17500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 10540.183457                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 10540.183457                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 10540.169125                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 10540.169125                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           21                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       907373                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          221320                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     4.099824                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      2817306                       # number of writebacks
-system.cpu.dcache.writebacks::total           2817306                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2541564                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      2541564                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1995189                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1995189                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_miss_rate::cpu.data     0.042463                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.042463                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.042462                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.042462                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13217.695280                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13217.695280                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7906.969059                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  7906.969059                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20553.030303                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20553.030303                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 11400.951273                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 11400.951273                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 11400.932675                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 11400.932675                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           25                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      1093581                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          221181                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     8.333333                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     4.944281                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks      2817297                       # number of writebacks
+system.cpu.dcache.writebacks::total           2817297                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2541719                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      2541719                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1996628                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1996628                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           66                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total           66                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4536753                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4536753                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4536753                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4536753                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2298022                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      2298022                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519817                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       519817                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            9                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total            9                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2817839                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2817839                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2817848                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2817848                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30115234500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  30115234500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4603448995                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4603448995                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       602500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       602500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  34718683495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  34718683495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  34719285995                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  34719285995                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data      4538347                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4538347                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4538347                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4538347                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2297984                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      2297984                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519842                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       519842                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           10                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total           10                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2817826                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2817826                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2817836                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2817836                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  32775846000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  32775846000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4786094494                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4786094494                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1244000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1244000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  37561940494                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  37561940494                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  37563184494                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  37563184494                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019311                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019311                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009584                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009584                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003215                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003215                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016265                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016265                       # mshr miss rate for demand accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003569                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003569                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016266                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016266                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016265                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.016265                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13104.850389                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13104.850389                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8855.903126                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8855.903126                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66944.444444                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66944.444444                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12321.031647                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12321.031647                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12321.206110                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12321.206110                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements             76636                       # number of replacements
-system.cpu.icache.tags.tagsinuse           466.486924                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           235189788                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             77148                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3048.553274                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      115712400500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   466.486924                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.911107                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.911107                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14262.869541                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14262.869541                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9206.825332                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9206.825332                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data       124400                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total       124400                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13330.113532                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13330.113532                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13330.507700                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13330.507700                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements             76619                       # number of replacements
+system.cpu.icache.tags.tagsinuse           466.071602                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           235190778                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             77131                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3049.238024                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      116612189500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   466.071602                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.910296                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.910296                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          260                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          120                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          261                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          118                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           17                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         470628332                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        470628332                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    235189788                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       235189788                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     235189788                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        235189788                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    235189788                       # number of overall hits
-system.cpu.icache.overall_hits::total       235189788                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        85789                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         85789                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        85789                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          85789                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        85789                       # number of overall misses
-system.cpu.icache.overall_misses::total         85789                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1556704687                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1556704687                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1556704687                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1556704687                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1556704687                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1556704687                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    235275577                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    235275577                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    235275577                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    235275577                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    235275577                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    235275577                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         470630395                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        470630395                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    235190778                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       235190778                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     235190778                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        235190778                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    235190778                       # number of overall hits
+system.cpu.icache.overall_hits::total       235190778                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        85841                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         85841                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        85841                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          85841                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        85841                       # number of overall misses
+system.cpu.icache.overall_misses::total         85841                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1941915678                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1941915678                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1941915678                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1941915678                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1941915678                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1941915678                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    235276619                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    235276619                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    235276619                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    235276619                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    235276619                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    235276619                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000365                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000365                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000365                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000365                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000365                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000365                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18145.737647                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18145.737647                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18145.737647                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18145.737647                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18145.737647                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18145.737647                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       171831                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          200                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              6857                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    25.059210                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets           50                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks        76636                       # number of writebacks
-system.cpu.icache.writebacks::total             76636                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         8610                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         8610                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         8610                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         8610                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         8610                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         8610                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        77179                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        77179                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        77179                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        77179                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        77179                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        77179                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1268632793                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1268632793                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1268632793                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1268632793                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1268632793                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1268632793                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22622.239699                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22622.239699                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22622.239699                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22622.239699                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22622.239699                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22622.239699                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       206659                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets         2170                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              7236                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets              11                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    28.559840                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets   197.272727                       # average number of cycles each access was blocked
+system.cpu.icache.writebacks::writebacks        76619                       # number of writebacks
+system.cpu.icache.writebacks::total             76619                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         8683                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         8683                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         8683                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         8683                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         8683                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         8683                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        77158                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        77158                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        77158                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        77158                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        77158                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        77158                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1536678279                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1536678279                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1536678279                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1536678279                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1536678279                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1536678279                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000328                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000328                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000328                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000328                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000328                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000328                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16437.538618                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16437.538618                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16437.538618                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16437.538618                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16437.538618                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16437.538618                       # average overall mshr miss latency
-system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.prefetcher.num_hwpf_issued      8513734                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      8515093                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit          374                       # number of redundant prefetches already in prefetch queue
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19915.994181                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19915.994181                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19915.994181                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19915.994181                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19915.994181                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19915.994181                       # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.prefetcher.num_hwpf_issued      8510000                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      8511429                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit          428                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage       743899                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           390403                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        15000.108571                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2699085                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           406018                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.647698                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage       743291                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           389594                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        15007.037789                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2698812                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           405195                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             6.660526                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14926.062493                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    74.046079                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.911015                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.004519                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.915534                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          114                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15501                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 14932.547255                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    74.490534                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.911410                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.004547                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.915957                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022           98                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15503                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           17                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3           46                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4           49                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          261                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          655                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5426                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6626                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2533                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.006958                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.946106                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         95370697                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        95370697                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks      2353941                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      2353941                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       516320                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       516320                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       516934                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       516934                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        67108                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        67108                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      2130993                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      2130993                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        67108                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2647927                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2715035                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        67108                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2647927                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2715035                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           30                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           30                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         5078                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         5078                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        10036                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        10036                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       164813                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       164813                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        10036                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       169891                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        179927                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        10036                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       169891                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       179927                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        21000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total        21000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    484083500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    484083500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    750585000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    750585000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  12710440000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  12710440000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    750585000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  13194523500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  13945108500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    750585000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  13194523500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  13945108500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      2353941                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      2353941                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       516320                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       516320                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           30                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           30                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       522012                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       522012                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        77144                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        77144                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2295806                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      2295806                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        77144                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2817818                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2894962                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        77144                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2817818                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2894962                       # number of overall (read+write) accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2            6                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3           41                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4           50                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          246                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          672                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5433                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6587                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2565                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.005981                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.946228                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         95366335                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        95366335                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2351800                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2351800                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       518252                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       518252                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       516857                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       516857                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        67161                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        67161                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      2130903                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      2130903                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        67161                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2647760                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2714921                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        67161                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2647760                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2714921                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           27                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           27                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         5168                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         5168                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9964                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         9964                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       164881                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       164881                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         9964                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       170049                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        180013                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         9964                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       170049                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       180013                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        20500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total        20500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    668599000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    668599000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1018287500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1018287500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  15371092500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  15371092500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1018287500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  16039691500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  17057979000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1018287500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  16039691500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  17057979000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2351800                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2351800                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       518252                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       518252                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           27                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           27                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       522025                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       522025                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        77125                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        77125                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2295784                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      2295784                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        77125                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2817809                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2894934                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        77125                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2817809                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2894934                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009728                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.009728                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.130094                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.130094                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.071789                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.071789                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.130094                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.060292                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.062152                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.130094                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.060292                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.062152                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data          700                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total          700                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95329.558881                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95329.558881                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74789.258669                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74789.258669                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77120.372786                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77120.372786                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74789.258669                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77664.640858                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77504.257282                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74789.258669                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77664.640858                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77504.257282                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009900                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.009900                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.129193                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.129193                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.071819                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.071819                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.129193                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.060348                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.062182                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.129193                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.060348                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.062182                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   759.259259                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   759.259259                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129372.871517                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129372.871517                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102196.657969                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102196.657969                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93225.371632                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93225.371632                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102196.657969                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94323.938982                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 94759.706243                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102196.657969                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94323.938982                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 94759.706243                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.unused_prefetches             2029                       # number of HardPF blocks evicted w/o reference
-system.cpu.l2cache.writebacks::writebacks       291427                       # number of writebacks
-system.cpu.l2cache.writebacks::total           291427                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1416                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         1416                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.unused_prefetches             2063                       # number of HardPF blocks evicted w/o reference
+system.cpu.l2cache.writebacks::writebacks       291274                       # number of writebacks
+system.cpu.l2cache.writebacks::total           291274                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1581                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         1581                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            8                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            8                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4197                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4197                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4441                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4441                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         5613                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         5621                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         6022                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         6030                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         5613                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         5621                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       356222                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       356222                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           30                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           30                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3662                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3662                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10028                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10028                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       160616                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       160616                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        10028                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       164278                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       174306                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        10028                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       164278                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       356222                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       530528                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  18747915458                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18747915458                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       462000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       462000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    336888000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    336888000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    689794500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    689794500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  11439165000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  11439165000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    689794500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11776053000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  12465847500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    689794500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11776053000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  18747915458                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  31213762958                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_hits::cpu.data         6022                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         6030                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       355324                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       355324                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           27                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           27                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3587                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3587                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9956                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9956                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       160440                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       160440                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         9956                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       164027                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       173983                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         9956                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       164027                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       355324                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       529307                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  21295211595                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  21295211595                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       417500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       417500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    461178500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    461178500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    956729500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    956729500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  14002333000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  14002333000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    956729500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  14463511500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  15420241000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    956729500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  14463511500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  21295211595                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  36715452595                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007015                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007015                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.129991                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.129991                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.069961                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.069961                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.129991                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.058300                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060210                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.129991                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.058300                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.006871                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.006871                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.129089                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.129089                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.069885                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.069885                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.129089                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.058211                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060099                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.129089                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.058211                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.183259                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 52629.864124                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        15400                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        15400                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91995.630803                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91995.630803                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68786.846829                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68786.846829                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71220.582009                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71220.582009                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68786.846829                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71683.688625                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71517.030395                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68786.846829                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71683.688625                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58835.279114                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      5788969                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2893984                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23717                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops        99826                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops        99825                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.182839                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59931.813204                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15462.962963                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15462.962963                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128569.417340                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128569.417340                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96095.771394                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96095.771394                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87274.576166                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87274.576166                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96095.771394                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88177.626244                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88630.734037                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96095.771394                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88177.626244                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69365.137047                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      5788910                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2893955                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23897                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops        99240                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops        99239                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp       2372984                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      2645368                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       540001                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        98976                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       397627                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp       2372941                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2643074                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       542116                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        98320                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       402261                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           30                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           30                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       522012                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       522012                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        77179                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      2295806                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       230958                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8453003                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8683961                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9841856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    360648000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          370489856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      788066                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              18653632                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      3683057                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.033555                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.180083                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeReq           27                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           27                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       522025                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       522025                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        77158                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      2295784                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       230901                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8452970                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8683871                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9839552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    360646848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          370486400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      791889                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic              18643712                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      3686849                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.033410                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.179705                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3559472     96.64%     96.64% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             123584      3.36%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3563674     96.66%     96.66% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             123174      3.34%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3683057                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5788426505                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3686849                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5788371005                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy         1506                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     115796940                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     115765939                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4226763956                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    4226743467                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.8                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests        821136                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       414105                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests        819690                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       413483                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 233363457000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp             427040                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       291427                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            98976                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               34                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3658                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3658                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        427041                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1251834                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1251834                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     46216000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                46216000                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED 236034256000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp             426481                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       291274                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            98320                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               32                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              3582                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3582                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        426482                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1249753                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1249753                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     46165568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                46165568                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            430733                       # Request fanout histogram
+system.membus.snoop_fanout::samples            430096                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  430733    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  430096    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              430733                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2217216132                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2280002282                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              430096                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2210866206                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2276438586                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index fb202712b..246d6b579 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -179,7 +179,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -552,7 +552,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -756,6 +756,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -767,7 +768,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -775,29 +776,36 @@ width=16
 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -817,6 +825,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -848,9 +857,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index 72c2f65ba..94b6c45b2 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -3,18 +3,18 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:20
-gem5 executing on e108600-lin, pid 18568
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:09:23
+gem5 executing on e108600-lin, pid 17649
 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
 info: Increasing stack size by one page.
- Reading the dictionary files: **info: Increasing stack size by one page.
 info: Increasing stack size by one page.
-***********************************************
+info: Increasing stack size by one page.
+ Reading the dictionary files: *************************************************
  58924 words stored in 3784810 bytes
 
 
@@ -46,13 +46,6 @@ Echoing of input sentence turned on.
 - he ran home so quickly that his mother could hardly believe he had called from school 
 - so many people attended that they spilled over into several neighboring fields 
 - voting in favor of the bill were 36 Republicans and 4 moderate Democrats 
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
 : Grace may not be possible to fix the problem 
   any program as good as ours should be useful 
   biochemically , I think the experiment has a lot of problems 
@@ -79,4 +72,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 481957625500 because target called exit()
+Exiting @ tick 487015166000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index bc9a5d8a0..97084638c 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.482382                       # Number of seconds simulated
-sim_ticks                                482382057000                       # Number of ticks simulated
-final_tick                               482382057000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.487015                       # Number of seconds simulated
+sim_ticks                                487015166000                       # Number of ticks simulated
+final_tick                               487015166000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  90853                       # Simulator instruction rate (inst/s)
-host_op_rate                                   168124                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               53003549                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 321140                       # Number of bytes of host memory used
-host_seconds                                  9100.94                       # Real time elapsed on the host
+host_inst_rate                                 125191                       # Simulator instruction rate (inst/s)
+host_op_rate                                   231667                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               73737953                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 321616                       # Number of bytes of host memory used
+host_seconds                                  6604.67                       # Real time elapsed on the host
 sim_insts                                   826847303                       # Number of instructions simulated
 sim_ops                                    1530082520                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            155136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24650752                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24805888                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       155136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          155136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18911424                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18911424                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2424                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             385168                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                387592                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          295491                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               295491                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               321604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             51102133                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51423737                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          321604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             321604                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          39204244                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               39204244                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          39204244                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              321604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            51102133                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               90627981                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        387592                       # Number of read requests accepted
-system.physmem.writeReqs                       295491                       # Number of write requests accepted
-system.physmem.readBursts                      387592                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     295491                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24786816                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19072                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18910464                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24805888                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18911424                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      298                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            154176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24645952                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24800128                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       154176                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          154176                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18907840                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18907840                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2409                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             385093                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                387502                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          295435                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               295435                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               316573                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             50606128                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50922702                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          316573                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             316573                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          38823924                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               38823924                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          38823924                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              316573                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            50606128                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               89746626                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        387502                       # Number of read requests accepted
+system.physmem.writeReqs                       295435                       # Number of write requests accepted
+system.physmem.readBursts                      387502                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     295435                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24780416                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19712                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18906304                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24800128                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18907840                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      308                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               24694                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26457                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               24696                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24495                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               23285                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23614                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24693                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24448                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23844                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23582                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24812                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24004                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23312                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              22998                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              24024                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              24336                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               19003                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               19960                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               19024                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18975                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18152                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18441                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               19161                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               19119                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18726                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               17970                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18928                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17785                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              17418                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              16994                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17838                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17982                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               24677                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26454                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               24704                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24551                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               23256                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23627                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24680                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24455                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23806                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23529                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24814                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              23994                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23307                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              23001                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              24016                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              24323                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               19004                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               19961                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               19032                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               19001                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18129                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18443                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               19167                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               19127                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18708                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               17947                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18897                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17782                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              17420                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              16998                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17822                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17973                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    482381969500                       # Total gap between requests
+system.physmem.totGap                    487015078500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  387592                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  387502                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 295491                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    381809                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      5176                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       278                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 295435                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    381038                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      5759                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       352                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        36                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -145,31 +145,31 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6707                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    17432                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17641                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17642                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17643                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17648                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17652                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17701                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17719                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17664                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17636                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    17484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17673                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17689                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17692                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17694                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17700                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17696                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17699                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17704                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17708                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17727                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17805                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17713                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17722                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
@@ -194,246 +194,258 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       146280                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      298.722669                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     176.940489                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.258352                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          52888     36.16%     36.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        40462     27.66%     63.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        14063      9.61%     73.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7664      5.24%     78.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5102      3.49%     82.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3857      2.64%     84.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         2918      1.99%     86.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2773      1.90%     88.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16553     11.32%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         146280                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17634                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.962913                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       18.199318                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      216.461189                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17628     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       146349                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      298.501363                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     176.437841                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     325.145824                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          53058     36.25%     36.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        40951     27.98%     64.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13535      9.25%     73.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7606      5.20%     78.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5054      3.45%     82.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3741      2.56%     84.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2872      1.96%     86.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2862      1.96%     88.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16670     11.39%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         146349                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17683                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.896002                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       18.141977                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      216.215491                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17677     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            2      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17634                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17633                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.755969                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.728033                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.977832                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              10918     61.92%     61.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                278      1.58%     63.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               6268     35.55%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                161      0.91%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  7      0.04%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17633                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4311135000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11572897500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1936470000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11131.43                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           17683                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17683                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.705932                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.678736                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.966667                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              11382     64.37%     64.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                280      1.58%     65.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               5890     33.31%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                116      0.66%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 11      0.06%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  2      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17683                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     9773520500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               17033408000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1935970000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25241.92                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29881.43                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          51.38                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          39.20                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       51.42                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       39.20                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  43991.92                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          50.88                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          38.82                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       50.92                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       38.82                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.71                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.70                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.40                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.31                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.28                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     315765                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    220723                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.53                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.70                       # Row buffer hit rate for writes
-system.physmem.avgGap                       706183.54                       # Average gap between requests
-system.physmem.pageHitRate                      78.57                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  566682480                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  309201750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1531779600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                983877840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            31506817680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            69780771990                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           228217880250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             332897011590                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              690.111043                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   379065618250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     16107780000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     87208649000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  539164080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  294186750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1489098000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                930690000                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            31506817680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            67080778605                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           230586295500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             332427030615                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              689.136751                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   383030551000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     16107780000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     83243489000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               297919436                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         297919436                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          23611614                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            229854393                       # Number of BTB lookups
+system.physmem.busUtilWrite                      0.30                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        20.86                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     316194                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    220049                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.66                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.48                       # Row buffer hit rate for writes
+system.physmem.avgGap                       713118.60                       # Average gap between requests
+system.physmem.pageHitRate                      78.56                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  536506740                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  285137325                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1402324560                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                792730080                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           13527611760.000004                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             8827375680                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              730358400                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       36195677160                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       16995876480                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        84126324885                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             163425034830                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              335.564568                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           465742918500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     1151920500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      5744978000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   342106910750                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  44260034250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     14374729750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  79376592750                       # Time in different power states
+system.physmem_1.actEnergy                  508517940                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  270257130                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1362240600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                749315340                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           13073392800.000004                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             8818641570                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              720149760                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       34369694130                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       16456043520                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        85412982225                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             161745926205                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              332.116816                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           465789870750                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     1150076250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      5552712000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   347563722250                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  42854288750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     14522378750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  75371988000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               298029097                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         298029097                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          23616389                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            229942542                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                40311454                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            4410387                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups       229854393                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits          119921311                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses        109933082                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted     11586406                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.usedRAS                40333391                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            4390674                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups       229942542                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits          119860888                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses        110081654                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted     11613915                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    482382057000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        964764115                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    487015166000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        974030333                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          229640733                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1587519909                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   297919436                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          160232765                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     710474501                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                48125197                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                       1838                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                31961                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        395431                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles         7638                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.icacheStallCycles          229618225                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1587637398                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   298029097                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          160194279                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     719695482                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                48136797                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       1337                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                32063                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        398708                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles         8912                       # Number of stall cycles due to pending quiesce instructions
 system.cpu.fetch.IcacheWaitRetryStallCycles           34                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 216406816                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6303131                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.CacheLines                 216378015                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6307023                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.ItlbSquashes                       6                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          964614734                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.081549                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.494827                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples          973823159                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.052791                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.491297                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                473031835     49.04%     49.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 36413294      3.77%     52.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 36207947      3.75%     56.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 33239258      3.45%     60.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 28476947      2.95%     62.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 30017172      3.11%     66.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 40187194      4.17%     70.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 37484755      3.89%     74.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                249556332     25.87%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                482221410     49.52%     49.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 36458558      3.74%     53.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 36184065      3.72%     56.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 33102262      3.40%     60.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 28599787      2.94%     63.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 29969705      3.08%     66.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 40168402      4.12%     70.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 37465076      3.85%     74.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                249653894     25.64%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            964614734                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.308800                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.645501                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                165560291                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             381637451                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 312327895                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              81026499                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               24062598                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2744008679                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               24062598                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                201558349                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               194036216                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          13250                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 351418098                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             193526223                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2626516746                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                906315                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              120859920                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               22304361                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               41770089                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2707207684                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            6591914084                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       4206827635                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           2574467                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            973823159                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.305975                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.629967                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                165565722                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             390830119                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 312240973                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              81117947                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               24068398                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2744223716                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               24068398                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                201650614                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               200101577                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          12340                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 351328141                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             196662089                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2626762649                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                653926                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              121379246                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               22369281                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               44360312                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2707190257                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            6592545635                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4207329612                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           2546306                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1616961572                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps               1090246112                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1066                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            982                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 368286677                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            608256588                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           244134978                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         253265740                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         76368619                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2419508786                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded              132419                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1999186857                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3656712                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       889558685                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1510180986                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         131867                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     964614734                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.072524                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.106121                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps               1090228685                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1055                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            956                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 369291247                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            608349007                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           244126939                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         253380233                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         76614927                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2419683470                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              114601                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1999301644                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3644555                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       889715551                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1510079207                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         114049                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     973823159                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.053044                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.105688                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           336173556     34.85%     34.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           135262022     14.02%     48.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           129832579     13.46%     62.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           119015920     12.34%     74.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            98090682     10.17%     84.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            67084509      6.95%     91.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            45576707      4.72%     96.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            22663670      2.35%     98.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8            10915089      1.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           345234545     35.45%     35.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           135418864     13.91%     49.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           129821558     13.33%     62.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           119307207     12.25%     74.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            97554322     10.02%     84.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            67238440      6.90%     91.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            45741413      4.70%     96.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            22594403      2.32%     98.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8            10912407      1.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       964614734                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       973823159                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                11249182     43.29%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     43.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               11894821     45.77%     89.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2844033     10.94%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                11212757     43.22%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     43.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11924633     45.96%     89.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2807188     10.82%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2910415      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1333514799     66.70%     66.85% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               358060      0.02%     66.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               4798571      0.24%     67.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2915020      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1333663160     66.71%     66.85% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               357468      0.02%     66.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               4798486      0.24%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     67.11% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.11% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  2      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   2      0.00%     67.11% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.11% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.11% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.11% # Type of FU issued
@@ -455,82 +467,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.11% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.11% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.11% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.11% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            471222917     23.57%     90.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           186382093      9.32%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            471201648     23.57%     90.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           186365855      9.32%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1999186857                       # Type of FU issued
-system.cpu.iq.rate                           2.072203                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    25988036                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012999                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4991322155                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3305635589                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1923777377                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             1311041                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            4133688                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       240317                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2021708405                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  556073                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        179295064                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1999301644                       # Type of FU issued
+system.cpu.iq.rate                           2.052607                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    25944578                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012977                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5000714674                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3305993539                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1923953649                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1300906                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            4091270                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       238195                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2021778795                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  552407                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        179914916                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    224173511                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       339017                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       636964                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     94976783                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    224265796                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       337750                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       639215                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     94968744                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        31958                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           747                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        31938                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           869                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               24062598                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               144797851                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6250562                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2419641205                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           1306710                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             608256824                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            244134978                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              45669                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1454928                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3966770                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         636964                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        8731316                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect     20649413                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             29380729                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1945668790                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             456756594                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          53518067                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               24068398                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               149571445                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               6693651                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2419798071                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1305719                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             608349109                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            244126939                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              39730                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1462244                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               4395107                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         639215                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        8704418                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect     20695714                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             29400132                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1945833568                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             456792637                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          53468076                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    635598570                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                185172751                       # Number of branches executed
-system.cpu.iew.exec_stores                  178841976                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.016730                       # Inst execution rate
-system.cpu.iew.wb_sent                     1934534562                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1924017694                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1456930726                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2203703226                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.994288                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.661128                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       889633438                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                    635592905                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                185215439                       # Number of branches executed
+system.cpu.iew.exec_stores                  178800268                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.997714                       # Inst execution rate
+system.cpu.iew.wb_sent                     1934717341                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1924191844                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1457208218                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2204046368                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.975495                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.661151                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       889791004                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          23642184                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    831915086                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.839229                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.465352                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          23647177                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    841074000                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.819201                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.458814                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    352165945     42.33%     42.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    184695932     22.20%     64.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     57945588      6.97%     71.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     87210863     10.48%     81.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     30437769      3.66%     85.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     26536432      3.19%     88.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     10472867      1.26%     90.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      9005135      1.08%     91.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     73444555      8.83%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    361210845     42.95%     42.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    184795052     21.97%     64.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     57840397      6.88%     71.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     87376864     10.39%     82.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     30415751      3.62%     85.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     26609914      3.16%     88.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10385763      1.23%     90.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      9066382      1.08%     91.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     73373032      8.72%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    831915086                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    841074000                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826847303                       # Number of instructions committed
 system.cpu.commit.committedOps             1530082520                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -576,496 +588,495 @@ system.cpu.commit.op_class_0::MemWrite      149158195      9.75%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1530082520                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              73444555                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3178186489                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4973800859                       # The number of ROB writes
-system.cpu.timesIdled                            2058                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          149381                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              73373032                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3187574492                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4974168269                       # The number of ROB writes
+system.cpu.timesIdled                            2040                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          207174                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826847303                       # Number of Instructions Simulated
 system.cpu.committedOps                    1530082520                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.166798                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.166798                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.857046                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.857046                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2928420991                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1576721018                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    241306                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 617864492                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                419924545                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              1064270268                       # number of misc regfile reads
+system.cpu.cpi                               1.178005                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.178005                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.848893                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.848893                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2928663805                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1576907134                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    239166                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                        5                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 617952960                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                419967877                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              1064297744                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           2546182                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.922606                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           421485651                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2550278                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            165.270473                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1898151500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.922606                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998028                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998028                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           2546002                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.987212                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           420920584                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2550098                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            165.060552                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1890456500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.987212                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998044                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998044                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          599                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3454                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          600                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3453                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         852234240                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        852234240                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    273116230                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       273116230                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148366946                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148366946                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     421483176                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        421483176                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    421483176                       # number of overall hits
-system.cpu.dcache.overall_hits::total       421483176                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2567540                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2567540                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       791265                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       791265                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3358805                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3358805                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3358805                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3358805                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  57574934000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  57574934000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  24743790498                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  24743790498                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  82318724498                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  82318724498                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  82318724498                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  82318724498                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    275683770                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    275683770                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         851091222                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        851091222                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    272551011                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       272551011                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148366737                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148366737                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     420917748                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        420917748                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    420917748                       # number of overall hits
+system.cpu.dcache.overall_hits::total       420917748                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2561340                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2561340                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       791474                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       791474                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3352814                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3352814                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3352814                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3352814                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  63063270500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  63063270500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  26380612500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  26380612500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  89443883000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  89443883000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  89443883000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  89443883000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    275112351                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    275112351                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149158211                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149158211                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    424841981                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    424841981                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    424841981                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    424841981                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009313                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.009313                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005305                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.005305                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.007906                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.007906                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.007906                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.007906                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22424.162428                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 22424.162428                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31271.180323                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31271.180323                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24508.336893                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24508.336893                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24508.336893                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24508.336893                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         8828                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         1268                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               857                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              12                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.301050                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   105.666667                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      2337859                       # number of writebacks
-system.cpu.dcache.writebacks::total           2337859                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       801102                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       801102                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         5848                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         5848                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       806950                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       806950                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       806950                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       806950                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1766438                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1766438                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       785417                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       785417                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2551855                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2551855                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2551855                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2551855                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33894644000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33894644000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23857134999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  23857134999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  57751778999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  57751778999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  57751778999                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  57751778999                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006407                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006407                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005266                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005266                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006007                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006007                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006007                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006007                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19188.131143                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19188.131143                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30375.119203                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30375.119203                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22631.293314                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22631.293314                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22631.293314                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22631.293314                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements              4041                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1081.856161                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           216396902                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              5745                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          37666.997737                       # Average number of references to valid blocks.
+system.cpu.dcache.demand_accesses::cpu.data    424270562                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    424270562                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    424270562                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    424270562                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009310                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.009310                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005306                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.005306                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.007903                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.007903                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.007903                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.007903                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24621.202378                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24621.202378                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33330.990658                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33330.990658                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26677.257671                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26677.257671                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26677.257671                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26677.257671                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        10639                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        11942                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               928                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              13                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.464440                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   918.615385                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks      2338096                       # number of writebacks
+system.cpu.dcache.writebacks::total           2338096                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       794970                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       794970                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         5921                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         5921                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       800891                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       800891                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       800891                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       800891                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1766370                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1766370                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       785553                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       785553                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2551923                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2551923                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2551923                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2551923                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  37596158000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  37596158000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  25486712000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  25486712000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63082870000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  63082870000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63082870000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  63082870000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006421                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006421                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005267                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005267                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006015                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006015                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006015                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006015                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21284.418327                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21284.418327                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32444.293383                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32444.293383                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24719.738801                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24719.738801                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24719.738801                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24719.738801                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements              3937                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1075.833508                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           216367909                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              5646                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          38322.335990                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1081.856161                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.528250                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.528250                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1704                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1075.833508                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.525309                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.525309                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1709                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           27                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3           79                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1543                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.832031                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         432820961                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        432820961                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    216397172                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       216397172                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     216397172                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        216397172                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    216397172                       # number of overall hits
-system.cpu.icache.overall_hits::total       216397172                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         9643                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          9643                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         9643                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           9643                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         9643                       # number of overall misses
-system.cpu.icache.overall_misses::total          9643                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    354601499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    354601499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    354601499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    354601499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    354601499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    354601499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    216406815                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    216406815                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    216406815                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    216406815                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    216406815                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    216406815                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1553                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.834473                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         432763508                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        432763508                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    216368192                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       216368192                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     216368192                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        216368192                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    216368192                       # number of overall hits
+system.cpu.icache.overall_hits::total       216368192                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         9822                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          9822                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         9822                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           9822                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         9822                       # number of overall misses
+system.cpu.icache.overall_misses::total          9822                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    562018500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    562018500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    562018500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    562018500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    562018500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    562018500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    216378014                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    216378014                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    216378014                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    216378014                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    216378014                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    216378014                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000045                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000045                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36772.944001                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 36772.944001                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 36772.944001                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 36772.944001                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 36772.944001                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 36772.944001                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          690                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57220.372633                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 57220.372633                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 57220.372633                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 57220.372633                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 57220.372633                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 57220.372633                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          405                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 9                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    76.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    67.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks         4041                       # number of writebacks
-system.cpu.icache.writebacks::total              4041                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2312                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2312                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2312                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2312                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2312                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2312                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7331                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         7331                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         7331                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         7331                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         7331                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         7331                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    251236999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    251236999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    251236999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    251236999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    251236999                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    251236999                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000034                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000034                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000034                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34270.495021                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34270.495021                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34270.495021                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 34270.495021                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34270.495021                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 34270.495021                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           356021                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30615.396519                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4712767                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           388789                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.121657                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      82695006000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    70.818761                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   195.778038                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 30348.799719                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.002161                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005975                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.926172                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.934308                       # Average percentage of cache occupancy
+system.cpu.icache.writebacks::writebacks         3937                       # number of writebacks
+system.cpu.icache.writebacks::total              3937                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2342                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2342                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2342                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2342                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2342                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2342                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7480                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         7480                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         7480                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         7480                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         7480                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         7480                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    378895000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    378895000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    378895000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    378895000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    378895000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    378895000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000035                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000035                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000035                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000035                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000035                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50654.411765                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50654.411765                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50654.411765                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 50654.411765                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50654.411765                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 50654.411765                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           355911                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30630.560827                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4712762                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           388679                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.125075                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      82947046000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks    71.927824                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   191.909939                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 30366.723064                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.002195                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005857                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.926719                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.934771                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          165                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1386                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31150                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          170                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1402                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31132                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         41201341                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        41201341                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks      2337859                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      2337859                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         3935                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         3935                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1572                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1572                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       577284                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       577284                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3232                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         3232                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1587825                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1587825                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3232                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2165109                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2168341                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3232                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2165109                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2168341                       # number of overall hits
+system.cpu.l2cache.tags.tag_accesses         41200319                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        41200319                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2338096                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2338096                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         3847                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         3847                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         1820                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         1820                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       577163                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       577163                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3171                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         3171                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1587839                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1587839                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3171                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2165002                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2168173                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3171                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2165002                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2168173                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206802                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206802                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2424                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2424                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       178367                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       178367                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2424                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       385169                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        387593                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2424                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       385169                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       387593                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        61000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total        61000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16603167500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  16603167500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    203550000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    203550000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14526809000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  14526809000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    203550000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  31129976500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  31333526500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    203550000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  31129976500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  31333526500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      2337859                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      2337859                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         3935                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         3935                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1577                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1577                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       784086                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       784086                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5656                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         5656                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1766192                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1766192                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         5656                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2550278                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2555934                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         5656                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2550278                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2555934                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.003171                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.003171                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.263749                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.263749                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.428571                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.428571                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.100990                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.100990                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.428571                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.151030                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.151644                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.428571                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.151030                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.151644                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        12200                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        12200                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80285.333314                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80285.333314                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83972.772277                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83972.772277                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81443.366766                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81443.366766                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83972.772277                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80821.604283                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80841.311634                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83972.772277                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80821.604283                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80841.311634                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_misses::cpu.data       206795                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206795                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2409                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2409                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       178301                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       178301                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2409                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       385096                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        387505                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2409                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       385096                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       387505                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        30500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total        30500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  18229359500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  18229359500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    331268000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    331268000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  18228771500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  18228771500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    331268000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  36458131000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  36789399000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    331268000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  36458131000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  36789399000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2338096                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2338096                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         3847                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         3847                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1825                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         1825                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       783958                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       783958                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5580                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         5580                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1766140                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1766140                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         5580                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2550098                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2555678                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         5580                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2550098                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2555678                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.002740                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.002740                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.263783                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.263783                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.431720                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.431720                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.100955                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.100955                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.431720                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.151012                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.151625                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.431720                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.151012                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.151625                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data         6100                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total         6100                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88151.838778                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88151.838778                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 137512.660855                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 137512.660855                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102235.946517                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102235.946517                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 137512.660855                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94672.837422                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 94939.159495                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 137512.660855                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94672.837422                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 94939.159495                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks       295491                       # number of writebacks
-system.cpu.l2cache.writebacks::total           295491                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       295435                       # number of writebacks
+system.cpu.l2cache.writebacks::total           295435                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           10                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total           10                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206802                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206802                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2424                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2424                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       178367                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       178367                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2424                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       385169                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       387593                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2424                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       385169                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       387593                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206795                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206795                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2409                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2409                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       178301                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       178301                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2409                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       385096                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       387505                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2409                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       385096                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       387505                       # number of overall MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       102500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       102500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14535147500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14535147500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    179310000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    179310000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12743139000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12743139000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    179310000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  27278286500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  27457596500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    179310000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  27278286500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  27457596500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16161409500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16161409500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    307178000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    307178000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  16445761500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  16445761500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    307178000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  32607171000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  32914349000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    307178000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  32607171000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  32914349000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.003171                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.003171                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.263749                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.263749                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.428571                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.100990                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.100990                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.428571                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151030                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151644                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.428571                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151030                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151644                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.002740                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.002740                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.263783                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.263783                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.431720                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.431720                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.100955                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.100955                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.431720                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151012                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151625                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.431720                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151012                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151625                       # mshr miss rate for overall accesses
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        20500                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        20500                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70285.333314                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70285.333314                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73972.772277                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73972.772277                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71443.366766                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71443.366766                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73972.772277                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70821.604283                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70841.311634                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73972.772277                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70821.604283                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70841.311634                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      5109409                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2551871                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7932                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2949                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2946                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78151.838778                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78151.838778                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 127512.660855                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 127512.660855                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92235.946517                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92235.946517                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 127512.660855                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84672.837422                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84939.159495                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 127512.660855                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84672.837422                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84939.159495                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      5109342                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2551824                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7983                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2956                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2953                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp       1773523                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      2633350                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         4041                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       268853                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         1577                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         1577                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       784086                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       784086                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         7331                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1766192                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17028                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7649892                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7666920                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       620608                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312840768                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          313461376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      357696                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              19018624                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      2915207                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.004295                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.065414                       # Request fanout histogram
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp       1773620                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2633531                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         3937                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       268382                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         1825                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         1825                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       783958                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       783958                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         7480                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1766140                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        16997                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7649848                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7666845                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       609088                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312844416                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          313453504                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      357811                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic              19029440                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      2915314                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.004397                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.066180                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2902688     99.57%     99.57% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              12516      0.43%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2902498     99.56%     99.56% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              12813      0.44%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  3      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2915207                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4896659390                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2915314                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4896765876                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      10998496                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      11220998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3826206608                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3826059624                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests        740700                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       353605                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests        740486                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       353479                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 482382057000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp             180791                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       295491                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            57611                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206801                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206801                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        180791                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1128292                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1128292                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1128292                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43717312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43717312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43717312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED 487015166000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp             180710                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       295435                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            57541                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq                8                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206792                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206792                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        180710                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1127988                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1127988                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1127988                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43707968                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43707968                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43707968                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            387598                       # Request fanout histogram
+system.membus.snoop_fanout::samples            387510                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  387598    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  387510    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              387598                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          1995849000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              387510                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          1995365000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2051150500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2050434250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
index 00cf13ff8..63271ea71 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
@@ -149,7 +149,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -583,7 +583,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -643,7 +643,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -760,6 +760,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -779,29 +780,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -821,6 +829,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -852,9 +861,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
index 33c16c36c..6a622d0db 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:28
-gem5 executing on e108600-lin, pid 4300
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:45
+gem5 executing on e108600-lin, pid 28070
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -14,4 +14,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.233333
-Exiting @ tick 233525789500 because target called exit()
+Exiting @ tick 233641094500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
index 6b30c3cf1..e0c918d80 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.233534                       # Number of seconds simulated
-sim_ticks                                233533887500                       # Number of ticks simulated
-final_tick                               233533887500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.233641                       # Number of seconds simulated
+sim_ticks                                233641094500                       # Number of ticks simulated
+final_tick                               233641094500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 225573                       # Simulator instruction rate (inst/s)
-host_op_rate                                   225573                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              132138421                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 260868                       # Number of bytes of host memory used
-host_seconds                                  1767.34                       # Real time elapsed on the host
+host_inst_rate                                 295188                       # Simulator instruction rate (inst/s)
+host_op_rate                                   295188                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              172997788                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 258004                       # Number of bytes of host memory used
+host_seconds                                  1350.54                       # Real time elapsed on the host
 sim_insts                                   398664651                       # Number of instructions simulated
 sim_ops                                     398664651                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 233533887500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 233641094500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            249280                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            254592                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               503872                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total          249280                       # Nu
 system.physmem.num_reads::cpu.inst               3895                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               3978                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7873                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1067425                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1090172                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2157597                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1067425                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1067425                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1067425                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1090172                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2157597                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1066936                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1089671                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2156607                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1066936                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1066936                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1066936                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1089671                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2156607                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          7873                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        7873                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    233533785500                       # Total gap between requests
+system.physmem.totGap                    233641000500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6853                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       951                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        69                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6664                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1130                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        79                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1544                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      326.051813                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     195.846863                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.937998                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            532     34.46%     34.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          344     22.28%     56.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          193     12.50%     69.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          103      6.67%     75.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           73      4.73%     80.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           45      2.91%     83.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           32      2.07%     85.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           36      2.33%     87.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          186     12.05%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1544                       # Bytes accessed per row activation
-system.physmem.totQLat                       53440000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 201058750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples         1527                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      328.298625                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     196.524272                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.958390                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            522     34.18%     34.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          350     22.92%     57.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          181     11.85%     68.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          105      6.88%     75.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           64      4.19%     80.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           46      3.01%     83.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           30      1.96%     85.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           42      2.75%     87.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          187     12.25%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1527                       # Bytes accessed per row activation
+system.physmem.totQLat                      179319500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 326938250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     39365000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6787.76                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       22776.51                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25537.76                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  41526.51                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.16                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.16                       # Average system read bandwidth in MiByte/s
@@ -217,53 +217,63 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6327                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6337                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.36                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.49                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     29662617.24                       # Average gap between requests
-system.physmem.pageHitRate                      80.36                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    6758640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3687750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  34296600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     29676235.30                       # Average gap between requests
+system.physmem.pageHitRate                      80.49                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    6326040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3347190                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  31444560                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            15253240080                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             6038642700                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           134822908500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             156159534270                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.682165                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   224288059000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7798180000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1447046250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    4914000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2681250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  27058200                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           242168160.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy              105016230                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy               11391840                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy         673376340                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy         320465280                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        55494876360                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              56888412000                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              243.486327                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           233381065000                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE       19761500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       102860000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   231069881000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN    834517500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       137354250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN   1476720250                       # Time in different power states
+system.physmem_1.actEnergy                    4641000                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2447775                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  24768660                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            15253240080                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5739994620                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           135084870750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             156112758900                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.481917                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   224725904750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7798180000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1009185250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 233533887500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                45912940                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          26702743                       # Number of conditional branches predicted
+system.physmem_1.refreshEnergy           215124000.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               84187860                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               12227040                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy         535263060                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy         280836480                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        55611059460                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              56770555335                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              242.981892                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           233423818750                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE       23567500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF        91510000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   231519465750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN    731339000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       101377500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN   1173834750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 233641094500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                45912950                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          26702746                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            565787                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             25186733                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups             25186743                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                18811780                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             74.689242                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             74.689212                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 8285572                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                323                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         2249880                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectLookups         2249876                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits            2235903                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses            13977                       # Number of indirect misses.
+system.cpu.branchPred.indirectMisses            13973                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted       111495                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
@@ -275,17 +285,17 @@ system.cpu.dtb.read_misses                        116                       # DT
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_accesses                 95338572                       # DTB read accesses
 system.cpu.dtb.write_hits                    73578378                       # DTB write hits
-system.cpu.dtb.write_misses                       849                       # DTB write misses
+system.cpu.dtb.write_misses                       847                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                73579227                       # DTB write accesses
+system.cpu.dtb.write_accesses                73579225                       # DTB write accesses
 system.cpu.dtb.data_hits                    168916834                       # DTB hits
-system.cpu.dtb.data_misses                        965                       # DTB misses
+system.cpu.dtb.data_misses                        963                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                168917799                       # DTB accesses
-system.cpu.itb.fetch_hits                    96959232                       # ITB hits
+system.cpu.dtb.data_accesses                168917797                       # DTB accesses
+system.cpu.itb.fetch_hits                    96959253                       # ITB hits
 system.cpu.itb.fetch_misses                      1239                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                96960471                       # ITB accesses
+system.cpu.itb.fetch_accesses                96960492                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -299,16 +309,16 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    233533887500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        467067775                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    233641094500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        467282189                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   398664651                       # Number of instructions committed
 system.cpu.committedOps                     398664651                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                       2289293                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.171581                       # CPI: cycles per instruction
-system.cpu.ipc                               0.853548                       # IPC: instructions per cycle
+system.cpu.cpi                               1.172118                       # CPI: cycles per instruction
+system.cpu.ipc                               0.853156                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass            23123356      5.80%      5.80% # Class of committed instruction
 system.cpu.op_class_0::IntAlu               141652555     35.53%     41.33% # Class of committed instruction
 system.cpu.op_class_0::IntMult                2124322      0.53%     41.86% # Class of committed instruction
@@ -344,18 +354,18 @@ system.cpu.op_class_0::MemWrite              73520764     18.44%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                398664651                       # Class of committed instruction
-system.cpu.tickCycles                       455740572                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        11327203                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                       455741730                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        11540459                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements               771                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3291.924590                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           167817024                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3291.586193                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           167817015                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4165                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          40292.202641                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          40292.200480                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3291.924590                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.803693                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.803693                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3291.586193                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.803610                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803610                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3394                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
@@ -363,41 +373,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          216
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         3113                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.828613                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         335652191                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        335652191                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233533887500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     94302223                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        94302223                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73514801                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73514801                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     167817024                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        167817024                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    167817024                       # number of overall hits
-system.cpu.dcache.overall_hits::total       167817024                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses         335652183                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        335652183                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233641094500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     94302219                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94302219                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73514796                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73514796                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     167817015                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        167817015                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    167817015                       # number of overall hits
+system.cpu.dcache.overall_hits::total       167817015                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data         1061                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total          1061                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         5928                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5928                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         6989                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           6989                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         6989                       # number of overall misses
-system.cpu.dcache.overall_misses::total          6989                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     80682500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     80682500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    434084500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    434084500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    514767000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    514767000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    514767000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    514767000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     94303284                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     94303284                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data         5933                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5933                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         6994                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           6994                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         6994                       # number of overall misses
+system.cpu.dcache.overall_misses::total          6994                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     94695000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     94695000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    540363000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    540363000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    635058000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    635058000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    635058000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    635058000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     94303280                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     94303280                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    167824013                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    167824013                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    167824013                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    167824013                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    167824009                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    167824009                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    167824009                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    167824009                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000011                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000011                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000081                       # miss rate for WriteReq accesses
@@ -406,14 +416,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000042
 system.cpu.dcache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000042                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76043.826579                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 76043.826579                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73226.130229                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73226.130229                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73653.884676                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73653.884676                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73653.884676                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73653.884676                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89250.706880                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 89250.706880                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 91077.532446                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 91077.532446                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 90800.400343                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 90800.400343                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 90800.400343                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 90800.400343                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -424,12 +434,12 @@ system.cpu.dcache.writebacks::writebacks          654                       # nu
 system.cpu.dcache.writebacks::total               654                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           92                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           92                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2732                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2732                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         2824                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         2824                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         2824                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         2824                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2737                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2737                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         2829                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         2829                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         2829                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         2829                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          969                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          969                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3196                       # number of WriteReq MSHR misses
@@ -438,14 +448,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4165
 system.cpu.dcache.demand_mshr_misses::total         4165                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4165                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4165                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     72936500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     72936500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    242391000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    242391000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    315327500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    315327500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    315327500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    315327500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     86354000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     86354000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    303749000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    303749000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    390103000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    390103000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    390103000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    390103000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
@@ -454,139 +464,139 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75269.865841                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75269.865841                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75841.989987                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75841.989987                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75708.883553                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75708.883553                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75708.883553                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75708.883553                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements              3193                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1919.733373                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            96954061                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              5171                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          18749.576678                       # Average number of references to valid blocks.
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89116.615067                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89116.615067                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95040.362954                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95040.362954                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93662.184874                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 93662.184874                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93662.184874                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 93662.184874                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements              3194                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1919.615846                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            96954081                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              5172                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          18745.955336                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1919.733373                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.937370                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.937370                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1919.615846                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.937312                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.937312                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          396                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1287                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.965820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         193923635                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        193923635                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233533887500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     96954061                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        96954061                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      96954061                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         96954061                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     96954061                       # number of overall hits
-system.cpu.icache.overall_hits::total        96954061                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5171                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5171                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5171                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5171                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5171                       # number of overall misses
-system.cpu.icache.overall_misses::total          5171                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    321948500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    321948500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    321948500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    321948500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    321948500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    321948500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     96959232                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     96959232                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     96959232                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     96959232                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     96959232                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     96959232                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         193923678                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        193923678                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233641094500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     96954081                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        96954081                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      96954081                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         96954081                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     96954081                       # number of overall hits
+system.cpu.icache.overall_hits::total        96954081                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5172                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5172                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5172                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5172                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5172                       # number of overall misses
+system.cpu.icache.overall_misses::total          5172                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    373067500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    373067500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    373067500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    373067500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    373067500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    373067500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     96959253                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     96959253                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     96959253                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     96959253                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     96959253                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     96959253                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000053                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000053                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000053                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000053                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000053                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000053                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62260.394508                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62260.394508                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62260.394508                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62260.394508                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62260.394508                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62260.394508                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72132.153906                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 72132.153906                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 72132.153906                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 72132.153906                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 72132.153906                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 72132.153906                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks         3193                       # number of writebacks
-system.cpu.icache.writebacks::total              3193                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5171                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         5171                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         5171                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         5171                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         5171                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         5171                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    316777500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    316777500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    316777500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    316777500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    316777500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    316777500                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks         3194                       # number of writebacks
+system.cpu.icache.writebacks::total              3194                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5172                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         5172                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         5172                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         5172                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         5172                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         5172                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    367895500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    367895500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    367895500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    367895500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    367895500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    367895500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000053                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000053                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61260.394508                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61260.394508                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61260.394508                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 61260.394508                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61260.394508                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 61260.394508                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71132.153906                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71132.153906                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71132.153906                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71132.153906                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71132.153906                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71132.153906                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         7128.160045                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               5427                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         7128.397001                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               5429                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             7873                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.689318                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.689572                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3411.137560                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3717.022485                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.104100                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.113435                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.217534                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3411.799627                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3716.597374                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.104120                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.113422                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.217541                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         7873                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          503                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          502                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         7185                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         7186                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.240265                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           114273                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          114273                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233533887500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.tag_accesses           114289                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          114289                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233641094500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks          654                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total          654                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         3193                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         3193                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         3194                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         3194                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           61                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           61                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1276                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         1276                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1277                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         1277                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data          126                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total          126                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         1276                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         1277                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data          187                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            1463                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         1276                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            1464                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         1277                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data          187                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           1463                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           1464                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         3137                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         3137                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3895                       # number of ReadCleanReq misses
@@ -599,58 +609,58 @@ system.cpu.l2cache.demand_misses::total          7873                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3895                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         3978                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7873                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    237071000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    237071000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    295621500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    295621500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     70008000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     70008000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    295621500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    307079000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    602700500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    295621500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    307079000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    602700500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    298441000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    298441000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    346727500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    346727500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     83414000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     83414000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    346727500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    381855000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    728582500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    346727500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    381855000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    728582500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks          654                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total          654                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         3193                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         3193                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         3194                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         3194                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         3198                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         3198                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5171                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         5171                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5172                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         5172                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          967                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          967                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         5171                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst         5172                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         4165                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         9336                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         5171                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         9337                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         5172                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         4165                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         9336                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         9337                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.980926                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.980926                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.753239                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.753239                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.753094                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.753094                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.869700                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.869700                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.753239                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.753094                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.955102                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.843295                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.753239                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.843204                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.753094                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.955102                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.843295                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75572.521517                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75572.521517                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75897.689345                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75897.689345                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83243.757432                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83243.757432                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75897.689345                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77194.318753                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76552.838816                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75897.689345                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77194.318753                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76552.838816                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.843204                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95135.798534                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95135.798534                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89018.613607                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89018.613607                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99184.304400                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99184.304400                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89018.613607                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95991.704374                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 92541.915407                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89018.613607                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95991.704374                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 92541.915407                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -669,79 +679,79 @@ system.cpu.l2cache.demand_mshr_misses::total         7873
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3895                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         3978                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7873                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    205701000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    205701000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    256671500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    256671500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     61598000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     61598000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    256671500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    267299000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    523970500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    256671500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    267299000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    523970500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    267071000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    267071000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    307777500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    307777500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     75004000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     75004000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    307777500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    342075000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    649852500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    307777500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    342075000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    649852500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.980926                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.980926                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.753239                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.753239                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.753094                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.753094                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.869700                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.869700                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.753239                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.753094                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.955102                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.843295                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.753239                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.843204                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.753094                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955102                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.843295                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65572.521517                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65572.521517                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65897.689345                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65897.689345                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73243.757432                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73243.757432                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65897.689345                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.318753                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66552.838816                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65897.689345                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.318753                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66552.838816                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests        13300                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         3964                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.843204                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85135.798534                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85135.798534                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79018.613607                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79018.613607                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89184.304400                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89184.304400                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79018.613607                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85991.704374                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82541.915407                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79018.613607                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85991.704374                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82541.915407                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests        13302                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         3965                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233533887500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp          6138                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233641094500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp          6139                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty          654                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         3193                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         3194                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict          117                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         3198                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         3198                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         5171                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         5172                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          967                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13535                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13538                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9101                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             22636                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       535296                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             22639                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       535424                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       308416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             843712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             843840                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
 system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples         9336                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         9337                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               9336    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               9337    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           9336                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       10497000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           9337                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       10499000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7756500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7758000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       6247500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
@@ -751,7 +761,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 233533887500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 233641094500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp               4736                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              3137                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             3137                       # Transaction distribution
@@ -772,9 +782,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7873                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9223000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             9215000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           41799750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           41791500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index e7c466732..c2a5884c8 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -591,7 +591,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -708,6 +708,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -727,29 +728,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -769,6 +777,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -800,9 +809,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index 02658fe82..ee5bfc401 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:28
-gem5 executing on e108600-lin, pid 4299
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:44
+gem5 executing on e108600-lin, pid 28057
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -14,4 +14,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.050000
-Exiting @ tick 64188759000 because target called exit()
+Exiting @ tick 64255452000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 71e9e3432..1a8043b05 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,35 +1,35 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.064159                       # Number of seconds simulated
-sim_ticks                                 64159445000                       # Number of ticks simulated
-final_tick                                64159445000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.064255                       # Number of seconds simulated
+sim_ticks                                 64255452000                       # Number of ticks simulated
+final_tick                                64255452000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 223776                       # Simulator instruction rate (inst/s)
-host_op_rate                                   223776                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               38227708                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 261380                       # Number of bytes of host memory used
-host_seconds                                  1678.35                       # Real time elapsed on the host
+host_inst_rate                                 260947                       # Simulator instruction rate (inst/s)
+host_op_rate                                   260947                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               44644346                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 259540                       # Number of bytes of host memory used
+host_seconds                                  1439.27                       # Real time elapsed on the host
 sim_insts                                   375574794                       # Number of instructions simulated
 sim_ops                                     375574794                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  64159445000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            220736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            255360                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED  64255452000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            220800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            255296                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               476096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       220736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          220736                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3449                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               3990                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst       220800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          220800                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3450                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               3989                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7439                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3440429                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3980084                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 7420513                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3440429                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3440429                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3440429                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3980084                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7420513                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              3436284                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3973141                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 7409426                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3436284                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3436284                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3436284                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3973141                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7409426                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          7439                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        7439                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -43,20 +43,20 @@ system.physmem.servicedByWrQ                        0                       # Nu
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 524                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 652                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 651                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 450                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 600                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 446                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 454                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 513                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 523                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 524                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 438                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 408                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                339                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                305                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                306                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                414                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                540                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                453                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                452                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                380                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     64159334500                       # Total gap between requests
+system.physmem.totGap                     64255349500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,11 +91,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4271                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1861                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       920                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       327                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        58                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3982                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2008                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       898                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       438                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       111                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -188,28 +188,28 @@ system.physmem.wrQLenPdf::61                        0                       # Wh
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples         1349                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      352.640474                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     209.024877                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     349.175025                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            440     32.62%     32.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          302     22.39%     55.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          154     11.42%     66.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           83      6.15%     72.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           53      3.93%     76.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           50      3.71%     80.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           36      2.67%     82.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           35      2.59%     85.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      351.644181                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     209.715239                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     347.080632                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            429     31.80%     31.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          311     23.05%     54.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          151     11.19%     66.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           87      6.45%     72.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           68      5.04%     77.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           39      2.89%     80.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           38      2.82%     83.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           30      2.22%     85.47% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151          196     14.53%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total           1349                       # Bytes accessed per row activation
-system.physmem.totQLat                       63577500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 203058750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                      165053250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 304534500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     37195000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8546.51                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       22187.56                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27296.51                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           7.42                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40937.56                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           7.41                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        7.42                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        7.41                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
@@ -217,75 +217,85 @@ system.physmem.busUtilRead                       0.06                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6088                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6085                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.84                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.80                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8624725.70                       # Average gap between requests
-system.physmem.pageHitRate                      81.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5821200                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3176250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  32416800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      8637632.68                       # Average gap between requests
+system.physmem.pageHitRate                      81.80                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    5454960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2880405                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  29716680                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4190534400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             1995176700                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            36745221000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              42972346350                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.779347                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    61126318750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2142400000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       890255000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    4377240                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2388375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  25560600                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           128459760.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy               63558420                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                5463840                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy         397888500                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy         152192640                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        15095921460                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              15881536665                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              247.162475                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime            64101767750                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE        8572500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF        54520000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    62832935750                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN    396328750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        90536500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN    872558500                       # Time in different power states
+system.physmem_1.actEnergy                    4212600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2239050                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  23397780                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4190534400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             1859740425                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            36864024750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              42946625790                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.378459                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    61324552000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2142400000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       692021750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  64159445000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                47856205                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          27886274                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            572784                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             23348714                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                19574502                       # Number of BTB hits
+system.physmem_1.refreshEnergy           172713840.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               67790100                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               10409760                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy         394655460                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy         234464640                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        15065735460                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              15975618690                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              248.626662                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime            64079571000                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE       20607500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF        73504000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    62603628000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN    610590500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        81643000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN    865479000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED  64255452000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                47858833                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          27887840                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            573531                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             23350857                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                19575248                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.835461                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 8687459                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               1418                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         2338624                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            2308001                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses            30623                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       111239                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             83.830962                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 8687752                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1405                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         2338807                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            2307668                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            31139                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       111329                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     98829712                       # DTB read hits
-system.cpu.dtb.read_misses                      28367                       # DTB read misses
-system.cpu.dtb.read_acv                           845                       # DTB read access violations
-system.cpu.dtb.read_accesses                 98858079                       # DTB read accesses
-system.cpu.dtb.write_hits                    75499203                       # DTB write hits
-system.cpu.dtb.write_misses                      1454                       # DTB write misses
+system.cpu.dtb.read_hits                     98831063                       # DTB read hits
+system.cpu.dtb.read_misses                      28342                       # DTB read misses
+system.cpu.dtb.read_acv                           849                       # DTB read access violations
+system.cpu.dtb.read_accesses                 98859405                       # DTB read accesses
+system.cpu.dtb.write_hits                    75501441                       # DTB write hits
+system.cpu.dtb.write_misses                      1449                       # DTB write misses
 system.cpu.dtb.write_acv                            3                       # DTB write access violations
-system.cpu.dtb.write_accesses                75500657                       # DTB write accesses
-system.cpu.dtb.data_hits                    174328915                       # DTB hits
-system.cpu.dtb.data_misses                      29821                       # DTB misses
-system.cpu.dtb.data_acv                           848                       # DTB access violations
-system.cpu.dtb.data_accesses                174358736                       # DTB accesses
-system.cpu.itb.fetch_hits                    46955913                       # ITB hits
-system.cpu.itb.fetch_misses                       420                       # ITB misses
-system.cpu.itb.fetch_acv                            7                       # ITB acv
-system.cpu.itb.fetch_accesses                46956333                       # ITB accesses
+system.cpu.dtb.write_accesses                75502890                       # DTB write accesses
+system.cpu.dtb.data_hits                    174332504                       # DTB hits
+system.cpu.dtb.data_misses                      29791                       # DTB misses
+system.cpu.dtb.data_acv                           852                       # DTB access violations
+system.cpu.dtb.data_accesses                174362295                       # DTB accesses
+system.cpu.itb.fetch_hits                    46958874                       # ITB hits
+system.cpu.itb.fetch_misses                       432                       # ITB misses
+system.cpu.itb.fetch_acv                            5                       # ITB acv
+system.cpu.itb.fetch_accesses                46959306                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -299,141 +309,141 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     64159445000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        128318893                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     64255452000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        128510907                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           47425719                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      424811206                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    47856205                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           30569962                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      79950349                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1246202                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles           47429437                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      424837073                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    47858833                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           30570668                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      80085665                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1247776                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.TlbCycles                         13                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                  270                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         13187                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           60                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  46955913                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                225768                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          128012699                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.318508                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.349839                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.MiscStallCycles                  297                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         13295                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           79                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  46958874                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                226146                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          128152674                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.315086                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.349633                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 53041219     41.43%     41.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4325218      3.38%     44.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  6711253      5.24%     50.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5104898      3.99%     54.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 10968142      8.57%     62.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  7524114      5.88%     68.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5300788      4.14%     72.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1845614      1.44%     74.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 33191453     25.93%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 53168247     41.49%     41.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4330315      3.38%     44.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6713619      5.24%     50.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5107106      3.99%     54.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 10970093      8.56%     62.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  7524949      5.87%     68.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5303300      4.14%     72.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1847075      1.44%     74.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 33187970     25.90%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            128012699                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.372947                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.310590                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 42125446                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              13481218                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  67948873                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3838220                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 618942                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              8882912                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  4201                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              421902807                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 13825                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 618942                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 43678343                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 3058028                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         517106                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  70134710                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              10005570                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              419884966                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                437260                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2526892                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2765017                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                3520699                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           273968908                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             552151473                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        393698766                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         158452706                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            128152674                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.372411                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.305844                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 42097840                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              13659925                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  67904561                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3870622                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 619726                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              8883416                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  4205                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              421920314                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 13831                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 619726                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 43662514                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 3075430                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         529984                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  70109441                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              10155579                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              419899923                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                443686                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2538434                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2849903                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                3565226                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           273976095                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             552171720                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        393714640                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         158457079                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259532319                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 14436589                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              37562                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                 14443776                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              37564                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts            298                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  15635470                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             99735139                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            76519296                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          11859955                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9294086                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  392181792                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                  15805009                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             99734698                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            76520876                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          11857010                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9264279                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  392184083                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                 290                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 389203558                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            195886                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        16607287                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      7664931                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                 389210637                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            196187                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        16609578                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      7664570                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             75                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     128012699                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         3.040351                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.180919                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     128152674                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         3.037086                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.181467                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            17224377     13.46%     13.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19358192     15.12%     28.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            22001472     17.19%     45.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            17955910     14.03%     59.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            19066405     14.89%     74.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            13282652     10.38%     85.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             8794829      6.87%     91.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             6104058      4.77%     96.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4224804      3.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17313559     13.51%     13.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19411245     15.15%     28.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22012922     17.18%     45.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            17948678     14.01%     59.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            19074074     14.88%     74.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            13271943     10.36%     85.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8797733      6.87%     91.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             6095055      4.76%     96.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             4227465      3.30%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       128012699                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       128152674                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  256922      1.42%      1.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      2      0.00%      1.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                138470      0.76%      2.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                 78848      0.44%      2.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  3339      0.02%      2.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult              3443164     19.01%     21.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1648895      9.10%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8039924     44.38%     75.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4505956     24.87%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  253970      1.40%      1.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      2      0.00%      1.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                138834      0.77%      2.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                 79013      0.44%      2.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  3594      0.02%      2.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              3443745     19.00%     21.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1647907      9.09%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8047413     44.40%     75.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4509145     24.88%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             146986421     37.77%     37.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2128250      0.55%     38.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             146989472     37.77%     37.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2128309      0.55%     38.32% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     38.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            36418938      9.36%     47.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             7355017      1.89%     49.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2800646      0.72%     50.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult           16556809      4.25%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv             1584153      0.41%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            36418443      9.36%     47.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7355119      1.89%     49.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2800065      0.72%     50.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16556449      4.25%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1584163      0.41%     54.95% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.95% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.95% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.95% # Type of FU issued
@@ -455,82 +465,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.95% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.95% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.95% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             99502900     25.57%     80.51% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            75836843     19.49%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             99502948     25.57%     80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            75842088     19.49%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              389203558                       # Type of FU issued
-system.cpu.iq.rate                           3.033096                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    18115520                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.046545                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          592493180                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         242176639                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    227925873                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           332238041                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          166682962                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    158291544                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              234723560                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               172561937                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         19352464                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              389210637                       # Type of FU issued
+system.cpu.iq.rate                           3.028619                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    18123623                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.046565                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          592644502                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         242185048                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    227933309                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           332249256                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          166679024                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    158288157                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              234729597                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               172571082                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         19364531                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4980653                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        92349                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        70589                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2998568                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4980212                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        92962                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        70485                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      3000148                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       383293                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          3853                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       382479                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          3666                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 618942                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1854909                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                149633                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           415904338                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            108226                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              99735139                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             76519296                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                 619726                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1854972                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                162334                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           415907776                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            109026                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              99734698                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             76520876                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                290                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   7462                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                141873                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          70589                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         411438                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       230495                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               641933                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             387616397                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              98858950                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1587161                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                   8920                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                152322                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          70485                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         412161                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       230865                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               643026                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             387624331                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              98860283                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1586306                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      23722256                       # number of nop insts executed
-system.cpu.iew.exec_refs                    174359643                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 45862472                       # Number of branches executed
-system.cpu.iew.exec_stores                   75500693                       # Number of stores executed
-system.cpu.iew.exec_rate                     3.020727                       # Inst execution rate
-system.cpu.iew.wb_sent                      386480663                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     386217417                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 192328787                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 273868663                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       3.009825                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.702266                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        17240745                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                      23723403                       # number of nop insts executed
+system.cpu.iew.exec_refs                    174363211                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 45864022                       # Number of branches executed
+system.cpu.iew.exec_stores                   75502928                       # Number of stores executed
+system.cpu.iew.exec_rate                     3.016276                       # Inst execution rate
+system.cpu.iew.wb_sent                      386484413                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     386221466                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 192314001                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 273852153                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       3.005359                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.702255                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        17244606                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            568625                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    125549188                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     3.175366                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.248155                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            569369                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    125687681                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     3.171867                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.248348                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     42020703     33.47%     33.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     17522364     13.96%     47.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      8729636      6.95%     54.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9062074      7.22%     61.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6240745      4.97%     66.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4112376      3.28%     69.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      4753795      3.79%     73.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2410879      1.92%     75.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     30696616     24.45%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     42136978     33.53%     33.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     17569311     13.98%     47.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      8725420      6.94%     54.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9050963      7.20%     61.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6228783      4.96%     66.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4113989      3.27%     69.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      4743327      3.77%     73.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2404790      1.91%     75.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     30714120     24.44%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    125549188                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    125687681                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            398664569                       # Number of instructions committed
 system.cpu.commit.committedOps              398664569                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -576,33 +586,33 @@ system.cpu.commit.op_class_0::MemWrite       73520728     18.44%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         398664569                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              30696616                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    510754909                       # The number of ROB reads
-system.cpu.rob.rob_writes                   834280363                       # The number of ROB writes
-system.cpu.timesIdled                            3150                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          306194                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              30714120                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    510879759                       # The number of ROB reads
+system.cpu.rob.rob_writes                   834289662                       # The number of ROB writes
+system.cpu.timesIdled                            3136                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          358233                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   375574794                       # Number of Instructions Simulated
 system.cpu.committedOps                     375574794                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.341660                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.341660                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.926886                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.926886                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                385442521                       # number of integer regfile reads
-system.cpu.int_regfile_writes               165246956                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 154535424                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                102076666                       # number of floating regfile writes
+system.cpu.cpi                               0.342171                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.342171                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.922513                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.922513                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                385452576                       # number of integer regfile reads
+system.cpu.int_regfile_writes               165252743                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 154537274                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                102070951                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  64159445000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements               779                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3291.925722                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           152589979                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4179                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          36513.514956                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  64255452000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements               774                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3291.451205                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           152580730                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4174                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          36555.038333                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3291.925722                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.803693                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.803693                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3291.451205                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.803577                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803577                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3400                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
@@ -610,304 +620,304 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          211
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         3116                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.830078                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         305227185                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        305227185                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  64159445000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     79088959                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        79088959                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73501014                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73501014                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         305207642                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        305207642                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  64255452000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     79079190                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        79079190                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73501534                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73501534                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data            6                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total            6                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     152589973                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        152589973                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    152589973                       # number of overall hits
-system.cpu.dcache.overall_hits::total       152589973                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     152580724                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        152580724                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    152580724                       # number of overall hits
+system.cpu.dcache.overall_hits::total       152580724                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data         1810                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total          1810                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19714                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19714                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data        21524                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          21524                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        21524                       # number of overall misses
-system.cpu.dcache.overall_misses::total         21524                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    128203000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    128203000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1194602455                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1194602455                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1322805455                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1322805455                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1322805455                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1322805455                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     79090769                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     79090769                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data        19194                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19194                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        21004                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          21004                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        21004                       # number of overall misses
+system.cpu.dcache.overall_misses::total         21004                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    137671000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    137671000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1331646003                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1331646003                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1469317003                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1469317003                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1469317003                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1469317003                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     79081000                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     79081000                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520728                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520728                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data            6                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total            6                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    152611497                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    152611497                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    152611497                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    152611497                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    152601728                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    152601728                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    152601728                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    152601728                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000023                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000023                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000268                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000268                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000141                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000141                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000141                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000141                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70830.386740                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 70830.386740                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60596.654915                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60596.654915                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61457.231695                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61457.231695                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61457.231695                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61457.231695                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        49869                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           82                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               741                       # number of cycles access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000261                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000261                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000138                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000138                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000138                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000138                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76061.325967                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 76061.325967                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69378.243357                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69378.243357                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 69954.151733                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 69954.151733                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 69954.151733                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 69954.151733                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        57813                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           94                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               689                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    67.299595                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets           82                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks          658                       # number of writebacks
-system.cpu.dcache.writebacks::total               658                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          821                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          821                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16524                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16524                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        17345                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        17345                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        17345                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        17345                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          989                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          989                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3190                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3190                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4179                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4179                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4179                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4179                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     76039500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     76039500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    251163000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    251163000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    327202500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    327202500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    327202500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    327202500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000013                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000013                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    83.908563                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           94                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks          655                       # number of writebacks
+system.cpu.dcache.writebacks::total               655                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          824                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          824                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16006                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16006                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        16830                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        16830                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        16830                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        16830                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          986                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          986                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3188                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3188                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4174                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4174                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4174                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4174                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     83512000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     83512000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    299984000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    299984000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    383496000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    383496000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    383496000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    383496000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000012                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000043                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76885.237614                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76885.237614                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78734.482759                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78734.482759                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78296.841350                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78296.841350                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78296.841350                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78296.841350                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  64159445000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements              2131                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1829.791655                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            46950265                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4058                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          11569.804091                       # Average number of references to valid blocks.
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84697.768763                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84697.768763                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94097.867001                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94097.867001                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 91877.335889                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 91877.335889                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 91877.335889                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 91877.335889                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  64255452000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements              2132                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1829.599220                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            46953196                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4059                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          11567.675782                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1829.791655                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.893453                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.893453                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1829.599220                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.893359                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.893359                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1927                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          179                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          297                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1343                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1342                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.940918                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          93915884                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         93915884                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  64159445000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     46950265                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        46950265                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      46950265                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         46950265                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     46950265                       # number of overall hits
-system.cpu.icache.overall_hits::total        46950265                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5648                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5648                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5648                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5648                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5648                       # number of overall misses
-system.cpu.icache.overall_misses::total          5648                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    373323999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    373323999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    373323999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    373323999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    373323999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    373323999                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     46955913                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     46955913                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     46955913                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     46955913                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     46955913                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     46955913                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000120                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000120                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000120                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000120                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000120                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000120                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66098.441749                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 66098.441749                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 66098.441749                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 66098.441749                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 66098.441749                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 66098.441749                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          575                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          93921805                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         93921805                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  64255452000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     46953196                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        46953196                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      46953196                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         46953196                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     46953196                       # number of overall hits
+system.cpu.icache.overall_hits::total        46953196                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5677                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5677                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5677                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5677                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5677                       # number of overall misses
+system.cpu.icache.overall_misses::total          5677                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    436957499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    436957499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    436957499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    436957499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    436957499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    436957499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     46958873                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     46958873                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     46958873                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     46958873                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     46958873                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     46958873                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000121                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000121                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000121                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000121                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000121                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000121                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76969.790206                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76969.790206                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76969.790206                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76969.790206                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76969.790206                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76969.790206                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          896                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 9                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    63.888889                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    59.733333                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks         2131                       # number of writebacks
-system.cpu.icache.writebacks::total              2131                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1590                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1590                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1590                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1590                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1590                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1590                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4058                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4058                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4058                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4058                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4058                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4058                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    277954000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    277954000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    277954000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    277954000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    277954000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    277954000                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks         2132                       # number of writebacks
+system.cpu.icache.writebacks::total              2132                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1618                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1618                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1618                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1618                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1618                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1618                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4059                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4059                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4059                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4059                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4059                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4059                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    323146500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    323146500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    323146500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    323146500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    323146500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    323146500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000086                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000086                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000086                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68495.317891                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68495.317891                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68495.317891                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 68495.317891                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68495.317891                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 68495.317891                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  64159445000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79612.342942                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79612.342942                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79612.342942                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 79612.342942                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79612.342942                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 79612.342942                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  64255452000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         6688.615033                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               3708                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         6685.408988                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               3700                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             7439                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.498454                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.497379                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2966.248754                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3722.366279                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090523                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.113598                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.204120                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2964.630490                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3720.778498                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090473                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.113549                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.204022                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         7439                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          426                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          147                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          428                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         6758                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         6755                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.227020                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            96615                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           96615                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  64159445000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks          658                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total          658                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         2131                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         2131                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data           62                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           62                       # number of ReadExReq hits
+system.cpu.l2cache.tags.tag_accesses            96551                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           96551                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  64255452000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks          655                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total          655                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         2132                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         2132                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           60                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           60                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          609                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total          609                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data          127                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total          127                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data          125                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total          125                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst          609                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          189                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total             798                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          185                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total             794                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst          609                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          189                       # number of overall hits
-system.cpu.l2cache.overall_hits::total            798                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          185                       # number of overall hits
+system.cpu.l2cache.overall_hits::total            794                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         3128                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         3128                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3449                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3449                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          862                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          862                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3449                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         3990                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3450                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3450                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          861                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          861                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3450                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         3989                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total          7439                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3449                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         3990                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst         3450                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         3989                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7439                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    245628000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    245628000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    265369000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    265369000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     73132500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     73132500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    265369000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    318760500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    584129500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    265369000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    318760500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    584129500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks          658                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total          658                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         2131                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         2131                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         3190                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         3190                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4058                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         4058                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          989                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          989                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4058                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4179                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         8237                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4058                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         4179                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8237                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.980564                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.980564                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.849926                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.849926                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.871587                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.871587                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.849926                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.954774                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.903120                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.849926                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.954774                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.903120                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78525.575448                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78525.575448                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76940.852421                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76940.852421                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84840.487239                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84840.487239                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76940.852421                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79889.849624                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78522.583681                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76940.852421                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79889.849624                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78522.583681                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    294472000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    294472000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    310569500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    310569500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     80627500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     80627500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    310569500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    375099500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    685669000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    310569500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    375099500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    685669000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks          655                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total          655                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         2132                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         2132                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         3188                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3188                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4059                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         4059                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          986                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          986                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4059                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4174                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8233                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4059                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4174                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8233                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981179                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.981179                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.849963                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.849963                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.873225                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.873225                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.849963                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.955678                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.903559                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.849963                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.955678                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.903559                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94140.664962                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94140.664962                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 90020.144928                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 90020.144928                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93644.018583                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93644.018583                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 90020.144928                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94033.467034                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 92172.200565                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 90020.144928                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94033.467034                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 92172.200565                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -916,91 +926,91 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3128                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         3128                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3449                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3449                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          862                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          862                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3449                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         3990                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3450                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3450                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          861                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          861                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3450                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3989                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         7439                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3449                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         3990                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3450                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         3989                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7439                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    214348000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    214348000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    230879000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    230879000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     64512500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     64512500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    230879000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    278860500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    509739500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    230879000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    278860500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    509739500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.980564                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.980564                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.849926                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.849926                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.871587                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.871587                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.849926                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.954774                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.903120                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.849926                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.954774                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.903120                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68525.575448                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68525.575448                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66940.852421                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66940.852421                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74840.487239                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74840.487239                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66940.852421                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69889.849624                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68522.583681                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66940.852421                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69889.849624                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68522.583681                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests        11147                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         2910                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    263192000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    263192000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    276069500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    276069500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     72017500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     72017500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    276069500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    335209500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    611279000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    276069500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    335209500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    611279000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981179                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981179                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.849963                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.849963                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.873225                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.873225                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.849963                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.955678                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.903559                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.849963                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955678                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.903559                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84140.664962                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84140.664962                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80020.144928                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80020.144928                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83644.018583                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83644.018583                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80020.144928                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84033.467034                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82172.200565                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80020.144928                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84033.467034                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82172.200565                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests        11139                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         2906                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  64159445000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp          5047                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty          658                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         2131                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict          121                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         3190                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         3190                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         4058                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          989                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10247                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9137                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             19384                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       396096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       309568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             705664                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  64255452000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp          5045                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty          655                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         2132                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          119                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         3188                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         3188                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4059                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          986                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10250                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9122                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             19372                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       396224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       309056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             705280                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
 system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples         8237                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         8233                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               8237    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               8233    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           8237                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        8362500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           8233                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        8356500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6087499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6088500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6268500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6261000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.membus.snoop_filter.tot_requests          7439                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -1008,7 +1018,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  64159445000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED  64255452000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp               4311                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              3128                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             3128                       # Transaction distribution
@@ -1029,9 +1039,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7439                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9245500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             9229500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           39234750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           39165500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
index 76d7daa42..3e9f2ae1c 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
@@ -151,7 +151,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -631,7 +631,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -691,7 +691,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -880,6 +880,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -891,7 +892,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -899,29 +900,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -941,6 +949,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -972,9 +981,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout
index ab196f487..feeb32deb 100755
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:38:22
-gem5 executing on e108600-lin, pid 23074
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:47:28
+gem5 executing on e108600-lin, pid 17426
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -16,4 +16,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.220000
-Exiting @ tick 225030243000 because target called exit()
+Exiting @ tick 225206521000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
index a1a985a56..c3dd06017 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.225041                       # Number of seconds simulated
-sim_ticks                                225040911000                       # Number of ticks simulated
-final_tick                               225040911000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.225207                       # Number of seconds simulated
+sim_ticks                                225206521000                       # Number of ticks simulated
+final_tick                               225206521000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 161529                       # Simulator instruction rate (inst/s)
-host_op_rate                                   193933                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              133133968                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 280148                       # Number of bytes of host memory used
-host_seconds                                  1690.33                       # Real time elapsed on the host
+host_inst_rate                                 132189                       # Simulator instruction rate (inst/s)
+host_op_rate                                   158707                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              109031633                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 278744                       # Number of bytes of host memory used
+host_seconds                                  2065.52                       # Real time elapsed on the host
 sim_insts                                   273037855                       # Number of instructions simulated
 sim_ops                                     327812212                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            219136                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            266432                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               485568                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total          219136                       # Nu
 system.physmem.num_reads::cpu.inst               3424                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               4163                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7587                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               973761                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1183927                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2157688                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          973761                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             973761                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              973761                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1183927                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2157688                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               973045                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1183056                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2156101                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          973045                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             973045                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              973045                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1183056                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2156101                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          7587                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        7587                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    225040663000                       # Total gap between requests
+system.physmem.totGap                    225206267000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,8 +91,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6713                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       823                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6691                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       845                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        51                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1537                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      314.836695                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     187.294672                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.034747                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            563     36.63%     36.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          357     23.23%     59.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          158     10.28%     70.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           85      5.53%     75.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           84      5.47%     81.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           48      3.12%     84.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           39      2.54%     86.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           28      1.82%     88.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          175     11.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1537                       # Bytes accessed per row activation
-system.physmem.totQLat                       55497500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 197753750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples         1511                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      320.635341                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     191.281375                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     328.659938                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            540     35.74%     35.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          351     23.23%     58.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          165     10.92%     69.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           80      5.29%     75.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           78      5.16%     80.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           55      3.64%     83.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           33      2.18%     86.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           36      2.38%     88.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          173     11.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1511                       # Bytes accessed per row activation
+system.physmem.totQLat                      232482000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 374738250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     37935000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7314.81                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       30642.15                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26064.81                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  49392.15                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.16                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.16                       # Average system read bandwidth in MiByte/s
@@ -217,56 +217,66 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6044                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6073                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.66                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.04                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     29661350.07                       # Average gap between requests
-system.physmem.pageHitRate                      79.66                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5110560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2788500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  29967600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     29683177.41                       # Average gap between requests
+system.physmem.pageHitRate                      80.04                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    4726680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2504700                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  27553260                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            14698401120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5878157490                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           129866796000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             150481221270                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.691134                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   216043617250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7514520000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1481090250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6501600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3547500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  29000400                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           284578320.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy              100450530                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy               15488640                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy         721250640                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy         385416480                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        53424510300                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              54966479550                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              244.071438                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           224945701750                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE       29370000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       121010000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   222360521000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN   1003697750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       110222000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN   1581700250                       # Time in different power states
+system.physmem_1.actEnergy                    6083280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3229545                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  26617920                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            14698401120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             6069721950                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           129698757000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             150505929570                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.800930                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   215760799500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7514520000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1763151750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                32430292                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16924100                       # Number of conditional branches predicted
+system.physmem_1.refreshEnergy           394598880.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy              121239570                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               22348800                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy         914379180                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy         605052000                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        53195794545                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              55289408190                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              245.505361                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           224881567000                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE       42133000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       167838000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   221301429000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN   1575669750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       114195250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN   2005256000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                32430299                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16924101                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            738493                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             17494982                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                12858504                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups             17494977                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                12858505                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             73.498241                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 6523127                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             73.498268                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6523139                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups         2303930                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits            2264813                       # Number of indirect target hits.
 system.cpu.branchPred.indirectMisses            39117                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted       128237                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -296,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -326,7 +336,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -356,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -387,16 +397,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    225040911000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        450081822                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    225206521000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        450413042                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   273037855                       # Number of instructions committed
 system.cpu.committedOps                     327812212                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2063975                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2063976                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.648423                       # CPI: cycles per instruction
-system.cpu.ipc                               0.606640                       # IPC: instructions per cycle
+system.cpu.cpi                               1.649636                       # CPI: cycles per instruction
+system.cpu.ipc                               0.606194                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu               104312542     31.82%     31.82% # Class of committed instruction
 system.cpu.op_class_0::IntMult                2145905      0.65%     32.48% # Class of committed instruction
@@ -432,62 +442,62 @@ system.cpu.op_class_0::MemWrite              82375599     25.13%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                327812212                       # Class of committed instruction
-system.cpu.tickCycles                       434887274                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        15194548                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                       434950533                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        15462509                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements              1355                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3086.207714                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168654219                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3085.768112                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168654205                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4512                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37379.037899                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37379.034796                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3086.207714                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.753469                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.753469                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3085.768112                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.753361                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.753361                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          677                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         2431                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.770752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         337326820                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        337326820                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     86521434                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        86521434                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     82047457                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82047457                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         337326812                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        337326812                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     86521430                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        86521430                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82047447                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82047447                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data        63538                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total         63538                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168568891                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168568891                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168632429                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168632429                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     168568877                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168568877                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168632415                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168632415                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data         1710                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total          1710                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         5220                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5220                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         5230                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5230                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            5                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            5                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         6930                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           6930                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         6935                       # number of overall misses
-system.cpu.dcache.overall_misses::total          6935                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    116252000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    116252000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    401349000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    401349000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    517601000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    517601000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    517601000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    517601000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     86523144                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     86523144                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         6940                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           6940                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         6945                       # number of overall misses
+system.cpu.dcache.overall_misses::total          6945                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    177324000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    177324000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    487891500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    487891500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    665215500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    665215500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    665215500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    665215500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     86523140                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     86523140                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data        63543                       # number of SoftPFReq accesses(hits+misses)
@@ -496,10 +506,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895
 system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    168575821                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168575821                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    168639364                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168639364                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    168575817                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168575817                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168639360                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168639360                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000020                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000020                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000064                       # miss rate for WriteReq accesses
@@ -510,14 +520,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000041
 system.cpu.dcache.demand_miss_rate::total     0.000041                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000041                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000041                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 74689.898990                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 74636.049027                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103698.245614                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 103698.245614                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93287.093690                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 93287.093690                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 95852.377522                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 95852.377522                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 95783.369330                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 95783.369330                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -528,12 +538,12 @@ system.cpu.dcache.writebacks::writebacks         1010                       # nu
 system.cpu.dcache.writebacks::total              1010                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           71                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           71                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2350                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2350                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         2421                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         2421                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         2421                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         2421                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2360                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2360                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         2431                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         2431                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         2431                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         2431                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1639                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total         1639                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2870                       # number of WriteReq MSHR misses
@@ -544,16 +554,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4509
 system.cpu.dcache.demand_mshr_misses::total         4509                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4512                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4512                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    111802000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    111802000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    223602000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    223602000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       241000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       241000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    335404000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    335404000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    335645000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    335645000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    172098000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    172098000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    285707500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    285707500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       259000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       259000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    457805500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    457805500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    458064500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    458064500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -564,72 +574,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105001.830384                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105001.830384                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99549.651568                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99549.651568                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101531.492570                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 101531.492570                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             38188                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1924.983594                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            69819782                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1924.800725                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            69819801                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             40125                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1740.056872                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1740.057346                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1924.983594                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.939933                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.939933                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1924.800725                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.939844                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.939844                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           86                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3          277                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1484                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         139759941                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        139759941                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     69819782                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        69819782                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      69819782                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         69819782                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     69819782                       # number of overall hits
-system.cpu.icache.overall_hits::total        69819782                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         139759979                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        139759979                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     69819801                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        69819801                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      69819801                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         69819801                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     69819801                       # number of overall hits
+system.cpu.icache.overall_hits::total        69819801                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        40126                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         40126                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        40126                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          40126                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        40126                       # number of overall misses
 system.cpu.icache.overall_misses::total         40126                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    763080000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    763080000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    763080000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    763080000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    763080000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    763080000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     69859908                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     69859908                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     69859908                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     69859908                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     69859908                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     69859908                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    817901000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    817901000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    817901000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    817901000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    817901000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    817901000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     69859927                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     69859927                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     69859927                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     69859927                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     69859927                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     69859927                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000574                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000574                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000574                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000574                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000574                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000574                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19017.096147                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19017.096147                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.317550                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20383.317550                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.317550                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20383.317550                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.317550                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20383.317550                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -644,46 +654,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        40126
 system.cpu.icache.demand_mshr_misses::total        40126                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        40126                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        40126                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    722955000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    722955000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    722955000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    722955000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    722955000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    722955000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    777776000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    777776000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    777776000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    777776000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    777776000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    777776000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000574                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000574                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000574                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000574                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000574                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000574                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.342471                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.342471                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.342471                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.342471                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.342471                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.342471                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         6597.313111                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         6596.216026                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              61516                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             7587                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             8.108080                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3168.373403                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3428.939708                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.096691                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.104643                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.201334                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3167.840745                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3428.375281                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.096675                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.104626                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.201301                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         7587                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           46                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          789                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         6671                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.231537                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses           560755                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses          560755                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks         1010                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total         1010                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks        23270                       # number of WritebackClean hits
@@ -712,18 +722,18 @@ system.cpu.l2cache.demand_misses::total          7630                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3426                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         4204                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7630                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    219100000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    219100000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    262492500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    262492500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    106317000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total    106317000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    262492500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    325417000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    587909500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    262492500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    325417000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    587909500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    281205000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    281205000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    317313000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    317313000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    166631000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total    166631000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    317313000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    447836000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    765149000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    317313000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    447836000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    765149000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks         1010                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total         1010                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks        23270                       # number of WritebackClean accesses(hits+misses)
@@ -752,18 +762,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.170931                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.085381                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.931738                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.170931                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92619.089317                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92619.089317                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92619.089317                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 100281.651376                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92619.089317                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 100281.651376                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -792,18 +802,18 @@ system.cpu.l2cache.demand_mshr_misses::total         7587
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3424                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         4163                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7587                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    190560000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    190560000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    228116000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    228116000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     90492000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     90492000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    228116000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    281052000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    509168000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    228116000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    281052000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    509168000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    252665000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    252665000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    282924500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    282924500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    150580000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    150580000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    282924500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    403245000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    686169500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    282924500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    403245000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    686169500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994425                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994425                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.085331                       # mshr miss rate for ReadCleanReq accesses
@@ -816,25 +826,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.169967
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.085331                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922651                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.169967                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82629.818925                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82629.818925                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82629.818925                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90440.160801                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82629.818925                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90440.160801                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests        84181                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests        39645                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        15035                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp         41767                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty         1010                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        38188                       # Transaction distribution
@@ -874,7 +884,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp               4733                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              2854                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             2854                       # Transaction distribution
@@ -895,9 +905,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7587                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9083000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             9082000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           40294250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           40299000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index 7f3ecc8dc..3870e90de 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -172,7 +172,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -534,7 +534,7 @@ pipelined=true
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -813,6 +813,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -824,7 +825,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -832,29 +833,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -874,6 +882,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -905,9 +914,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index c5508bf05..5ac8e5d82 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/sim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:10:34
-gem5 executing on e108600-lin, pid 12223
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:51:10
+gem5 executing on e108600-lin, pid 17461
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -15,5 +15,5 @@ Eon, Version 1.1
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
-OO-style eon Time= 0.110000
-Exiting @ tick 111753553500 because target called exit()
+OO-style eon Time= 0.120000
+Exiting @ tick 122177531500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 3bab29953..9802024db 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,67 +1,67 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.120480                       # Number of seconds simulated
-sim_ticks                                120480458500                       # Number of ticks simulated
-final_tick                               120480458500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.122178                       # Number of seconds simulated
+sim_ticks                                122177531500                       # Number of ticks simulated
+final_tick                               122177531500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 129515                       # Simulator instruction rate (inst/s)
-host_op_rate                                   155497                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               57149813                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293332                       # Number of bytes of host memory used
-host_seconds                                  2108.15                       # Real time elapsed on the host
+host_inst_rate                                 120262                       # Simulator instruction rate (inst/s)
+host_op_rate                                   144388                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               53814187                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292180                       # Number of bytes of host memory used
+host_seconds                                  2270.36                       # Real time elapsed on the host
 sim_insts                                   273037218                       # Number of instructions simulated
 sim_ops                                     327811600                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst           1888064                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          14651392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       167808                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             16707264                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1888064                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1888064                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst              29501                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             228928                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         2622                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                261051                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst             15671122                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            121608037                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher      1392823                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               138671982                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        15671122                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           15671122                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            15671122                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           121608037                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher      1392823                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              138671982                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        261052                       # Number of read requests accepted
+system.physmem.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst           1888192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          14650048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       169280                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             16707520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1888192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1888192                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst              29503                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             228907                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         2645                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                261055                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst             15454495                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            119907874                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher      1385525                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               136747893                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        15454495                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           15454495                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            15454495                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           119907874                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher      1385525                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              136747893                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        261056                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                      261052                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      261056                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 16707328                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                 16707584                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  16707328                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                  16707584                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1258                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1259                       # Per bank write bursts
 system.physmem.perBankRdBursts::1               69992                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                1296                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10757                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10759                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               42908                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              121820                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              121819                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 160                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 266                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 224                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 257                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 228                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 562                       # Per bank write bursts
 system.physmem.perBankRdBursts::10               7776                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                812                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               1213                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                743                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                656                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                609                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                662                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                610                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    120480449000                       # Total gap between requests
+system.physmem.totGap                    122177522000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  261052                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  261056                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -95,20 +95,20 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    204297                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     43283                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     12075                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       298                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       234                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       208                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       182                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       216                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       113                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        58                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       21                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       18                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       18                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    204133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     43349                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     12134                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       301                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       235                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       214                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       176                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       231                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       127                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        64                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       33                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       24                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       19                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       16                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -191,86 +191,96 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        67045                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      249.160415                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     181.717328                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     205.520754                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          18369     27.40%     27.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        21159     31.56%     58.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        11457     17.09%     76.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         6629      9.89%     85.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         4618      6.89%     92.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2220      3.31%     96.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1372      2.05%     98.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          491      0.73%     98.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          730      1.09%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          67045                       # Bytes accessed per row activation
-system.physmem.totQLat                     2500931533                       # Total ticks spent queuing
-system.physmem.totMemAccLat                7395656533                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1305260000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9580.20                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples        67229                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      248.480388                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     181.727737                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     204.056429                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          18253     27.15%     27.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        21438     31.89%     59.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        11486     17.08%     76.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         6691      9.95%     86.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         4636      6.90%     92.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2199      3.27%     96.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1378      2.05%     98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          426      0.63%     98.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          722      1.07%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          67229                       # Bytes accessed per row activation
+system.physmem.totQLat                     4621160381                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9515960381                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1305280000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       17701.80                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28330.20                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         138.67                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  36451.80                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         136.75                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      138.67                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      136.75                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.08                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.08                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           1.07                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.07                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.60                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     193998                       # Number of row buffer hits during reads
+system.physmem.readRowHits                     193817                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.31                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   74.24                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                       461518.97                       # Average gap between requests
-system.physmem.pageHitRate                      74.31                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  469687680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  256278000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1937777400                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                       468012.69                       # Average gap between requests
+system.physmem.pageHitRate                      74.24                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  445443180                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  236747280                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1773933000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             7868948880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            73664414550                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             7668236250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              91865342760                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              762.514125                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    12350213739                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      4022980000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    104104852261                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                   37134720                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   20262000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  98069400                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           9531222480.000002                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             4632019500                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              224464800                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       45099806190                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        3562907040                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy          919525950                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              66426265230                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              543.686420                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           111434381144                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      154081000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      4033332000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF     3253133750                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN   9278182481                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      6555604606                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  98903197663                       # Time in different power states
+system.physmem_1.actEnergy                   34636140                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   18382980                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  89999700                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             7868948880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            16939770435                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            57426696000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              82390881435                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              683.872818                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    95444315624                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      4022980000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     21009739880                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                35971487                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          19266966                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            984300                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             17894295                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13923321                       # Number of BTB hits
+system.physmem_1.refreshEnergy           3038165520.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy              716380560                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              121415040                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       10108537890                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        3723173760                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        21583783695                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              39434924925                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              322.767403                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           120289757500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      194586000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1289158000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    88425719250                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN   9695988513                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       404030000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  22168049737                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                35971486                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          19267078                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            984296                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             17894197                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13923261                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             77.808715                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 6951891                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             77.808806                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6951889                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect               4417                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         2517210                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectLookups         2517219                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits            2473355                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses            43855                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       128902                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.indirectMisses            43864                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       128904                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -300,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -330,7 +340,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -360,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -391,97 +401,97 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    120480458500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        240960918                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    122177531500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        244355064                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           12852393                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      309387545                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    35971487                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           23348567                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     224289895                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1990323                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1871                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles           12854090                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      309386185                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    35971486                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           23348505                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     227028352                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1990311                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 1601                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            93                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles         3026                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  82204082                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 34266                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          238142439                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.562665                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.293284                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         3162                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  82203694                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 34298                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          240882453                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.544883                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.296552                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 77933727     32.73%     32.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 40203358     16.88%     49.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 28082672     11.79%     61.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 91922682     38.60%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 80675861     33.49%     33.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 40201773     16.69%     50.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 28081031     11.66%     61.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 91923788     38.16%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            238142439                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.149283                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.283974                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 26809492                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              87975457                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  98235303                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              24260898                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 861289                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              6686645                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                134215                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              348536073                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3411178                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 861289                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 43087679                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                34729777                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         287359                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 105264108                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              53912227                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              344595535                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               1451317                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               7117459                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  85486                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                7456793                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               27429966                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents          3277218                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           394867605                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2218081796                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        335910446                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         192911530                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            240882453                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.147210                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.266134                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 26812973                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              90710528                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  98252382                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              24245286                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 861284                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              6686689                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                134210                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              348538542                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3411137                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 861284                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 43083632                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                37000044                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         289266                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 105269732                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              54378495                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              344597413                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               1451618                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               7112089                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  85489                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                7460814                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               27903739                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents          3277402                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           394869828                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2218091968                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        335911643                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         192912802                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             372230048                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 22637557                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 22639780                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts              11606                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          11573                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  57394706                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             89984018                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            84392471                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1976841                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1898355                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  343274386                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               22623                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 339465004                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            967637                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        15485409                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     37250778                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            503                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     238142439                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.425470                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.136916                       # Number of insts issued each cycle
+system.cpu.rename.tempSerializingInsts          11574                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  57375410                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             89984183                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            84392474                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1977179                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1898949                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  343275804                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               22622                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 339466020                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            967573                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        15486826                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     37253539                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            502                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     240882453                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.409260                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.140571                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            57979720     24.35%     24.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            76155774     31.98%     56.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            59457503     24.97%     81.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            34550396     14.51%     95.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             9286722      3.90%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5              677796      0.28%     99.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6               34528      0.01%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            60724616     25.21%     25.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            76160793     31.62%     56.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            59430978     24.67%     81.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            34569007     14.35%     95.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             9283720      3.85%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5              678664      0.28%     99.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6               34675      0.01%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       238142439                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       240882453                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9217758      7.75%      7.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   7319      0.01%      7.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9218221      7.75%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   7322      0.01%      7.76% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.76% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.76% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.76% # attempts to use FU when none available
@@ -500,22 +510,22 @@ system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.76% # at
 system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.76% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.76% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd            238781      0.20%      7.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd            238834      0.20%      7.96% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp            138932      0.12%      8.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt             70694      0.06%      8.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv             68373      0.06%      8.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           637081      0.54%      8.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult           296736      0.25%      8.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        541785      0.46%      9.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               51510154     43.32%     52.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              56187310     47.25%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp            138891      0.12%      8.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt             70679      0.06%      8.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv             68365      0.06%      8.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           640804      0.54%      8.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult           296732      0.25%      8.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        541759      0.46%      9.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               51504063     43.31%     52.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              56187426     47.25%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             108183295     31.87%     31.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2148337      0.63%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             108184064     31.87%     31.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2148340      0.63%     32.50% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     32.50% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     32.50% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     32.50% # Type of FU issued
@@ -534,91 +544,91 @@ system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     32.50% # Ty
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     32.50% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     32.50% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     32.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6792696      2.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6792701      2.00%     34.50% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8634939      2.54%     37.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3210556      0.95%     37.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8634973      2.54%     37.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3210554      0.95%     37.99% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv         1592986      0.47%     38.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       20863290      6.15%     44.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult        7179112      2.11%     46.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc      7141893      2.10%     48.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       20863316      6.15%     44.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7179113      2.11%     46.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7141894      2.10%     48.83% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt         175297      0.05%     48.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             90024001     26.52%     75.40% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            83518602     24.60%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             90024187     26.52%     75.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            83518595     24.60%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              339465004                       # Type of FU issued
-system.cpu.iq.rate                           1.408797                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   118914923                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.350301                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          753593457                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         235149136                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    219170609                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           283361550                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          123645361                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    116917491                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              293630516                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               164749411                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          5409371                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              339466020                       # Type of FU issued
+system.cpu.iq.rate                           1.389233                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   118913096                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.350295                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          756328552                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         235151256                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    219171646                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           283366610                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          123646075                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    116917582                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              293624810                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               164754306                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5408815                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4251743                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         7382                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4251908                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7378                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation        12082                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2016854                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores      2016857                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       126951                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        613385                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       126936                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        613330                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 861289                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1346418                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1223561                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           343298428                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 861284                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1350225                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1508994                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           343299844                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              89984018                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             84392471                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              11590                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   7654                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               1216581                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewDispLoadInsts              89984183                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             84392474                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              11589                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   7652                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               1502014                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents          12082                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         438027                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       454511                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               892538                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             337435973                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              89435470                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2029031                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect         438026                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       454508                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               892534                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             337437017                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              89435625                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2029003                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1419                       # number of nop insts executed
-system.cpu.iew.exec_refs                    172563167                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31555788                       # Number of branches executed
-system.cpu.iew.exec_stores                   83127697                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.400376                       # Inst execution rate
-system.cpu.iew.wb_sent                      336234414                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     336088100                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 151781597                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 263546089                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.394783                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.575921                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        14163176                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                          1418                       # number of nop insts executed
+system.cpu.iew.exec_refs                    172563316                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31556143                       # Number of branches executed
+system.cpu.iew.exec_stores                   83127691                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.380929                       # Inst execution rate
+system.cpu.iew.wb_sent                      336235772                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     336089228                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 151786231                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 263562514                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.375413                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.575902                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        14164375                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            850428                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    235953046                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.389311                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.042233                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            850425                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    238692959                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.373364                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.035708                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    104793604     44.41%     44.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     67594704     28.65%     73.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     20883417      8.85%     81.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     13239055      5.61%     87.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8655759      3.67%     91.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4517031      1.91%     93.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      3019754      1.28%     94.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2590982      1.10%     95.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     10658740      4.52%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    107534765     45.05%     45.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     67583251     28.31%     73.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     20880103      8.75%     82.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     13256001      5.55%     87.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8658859      3.63%     91.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4515867      1.89%     93.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3014415      1.26%     94.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2598093      1.09%     95.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     10651605      4.46%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    235953046                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    238692959                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            273037830                       # Number of instructions committed
 system.cpu.commit.committedOps              327812212                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -664,96 +674,96 @@ system.cpu.commit.op_class_0::MemWrite       82375617     25.13%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         327812212                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              10658740                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    567267171                       # The number of ROB reads
-system.cpu.rob.rob_writes                   686142351                       # The number of ROB writes
-system.cpu.timesIdled                           39413                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         2818479                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              10651605                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    570015418                       # The number of ROB reads
+system.cpu.rob.rob_writes                   686144847                       # The number of ROB writes
+system.cpu.timesIdled                           39403                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         3472611                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   273037218                       # Number of Instructions Simulated
 system.cpu.committedOps                     327811600                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.882520                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.882520                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.133118                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.133118                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                325162337                       # number of integer regfile reads
-system.cpu.int_regfile_writes               134093699                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 186638060                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                131662989                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                1279404689                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 80058303                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              1056730531                       # number of misc regfile reads
+system.cpu.cpi                               0.894951                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.894951                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.117379                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.117379                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                325163205                       # number of integer regfile reads
+system.cpu.int_regfile_writes               134094196                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 186638267                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                131663703                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                1279409265                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 80058845                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              1056731782                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           1542807                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.846983                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           162052499                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1543319                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            105.002594                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          87321000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.846983                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999701                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999701                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           1542799                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.841241                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           162053309                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1543311                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            105.003664                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          91635000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.841241                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999690                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999690                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          308                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           91                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         333478959                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        333478959                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     81039652                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        81039652                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     80921351                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       80921351                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        69633                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         69633                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         333480485                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        333480485                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     81040424                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        81040424                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     80921391                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       80921391                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        69631                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         69631                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        10908                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10908                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     161961003                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        161961003                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    162030636                       # number of overall hits
-system.cpu.dcache.overall_hits::total       162030636                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2784011                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2784011                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1131348                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1131348                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     161961815                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        161961815                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    162031446                       # number of overall hits
+system.cpu.dcache.overall_hits::total       162031446                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2784008                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2784008                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1131308                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1131308                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           18                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           18                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      3915359                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3915359                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3915377                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3915377                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  45256653500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  45256653500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9138834402                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9138834402                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       184000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       184000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  54395487902                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  54395487902                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  54395487902                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  54395487902                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     83823663                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     83823663                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      3915316                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3915316                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3915334                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3915334                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  47872980500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  47872980500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9172353414                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9172353414                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       194000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       194000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  57045333914                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  57045333914                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  57045333914                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  57045333914                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     83824432                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     83824432                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052699                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052699                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data        69651                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total        69651                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        69649                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        69649                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10912                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        10912                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    165876362                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    165876362                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    165946013                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    165946013                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033213                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.033213                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    165877131                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    165877131                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    165946780                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    165946780                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033212                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.033212                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013788                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.013788                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000258                       # miss rate for SoftPFReq accesses
@@ -764,54 +774,54 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.023604
 system.cpu.dcache.demand_miss_rate::total     0.023604                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.023594                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.023594                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16255.917631                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16255.917631                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8077.827867                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  8077.827867                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        46000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        46000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13892.848115                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13892.848115                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13892.784246                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13892.784246                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.705077                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.705077                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8107.742024                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  8107.742024                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        48500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        48500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14569.790513                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14569.790513                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14569.723532                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14569.723532                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      1086145                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      1090477                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          136219                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          136210                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     7.973521                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      1542807                       # number of writebacks
-system.cpu.dcache.writebacks::total           1542807                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1461430                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1461430                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       910604                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       910604                       # number of WriteReq MSHR hits
+system.cpu.dcache.avg_blocked_cycles::no_targets     8.005851                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks      1542799                       # number of writebacks
+system.cpu.dcache.writebacks::total           1542799                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1461435                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1461435                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       910564                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       910564                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2372034                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2372034                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2372034                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2372034                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1322581                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1322581                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      2371999                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2371999                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2371999                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2371999                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1322573                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1322573                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       220744                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       220744                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           11                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total           11                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1543325                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1543325                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1543336                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1543336                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  25407816000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  25407816000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1834277181                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1834277181                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       705000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       705000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27242093181                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  27242093181                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27242798181                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  27242798181                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      1543317                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1543317                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1543328                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1543328                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27142024000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  27142024000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1845028694                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1845028694                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1269000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1269000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28987052694                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  28987052694                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28988321694                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28988321694                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015778                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015778                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002690                       # mshr miss rate for WriteReq accesses
@@ -822,26 +832,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.009304
 system.cpu.dcache.demand_mshr_miss_rate::total     0.009304                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.009300                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.009300                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19210.782553                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19210.782553                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8309.522257                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8309.522257                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64090.909091                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64090.909091                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17651.559575                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17651.559575                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17651.890568                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17651.890568                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements            725593                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.815316                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            81471161                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            726105                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            112.203002                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         334835500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.815316                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999639                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999639                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20522.136774                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20522.136774                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8358.228056                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8358.228056                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115363.636364                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115363.636364                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18782.306353                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18782.306353                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18782.994732                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18782.994732                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements            725588                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.809147                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            81470653                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            726100                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            112.203075                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         346654500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.809147                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999627                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999627                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
@@ -849,369 +859,370 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          243
 system.cpu.icache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           70                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         165134244                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        165134244                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     81471161                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        81471161                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      81471161                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         81471161                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     81471161                       # number of overall hits
-system.cpu.icache.overall_hits::total        81471161                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       732901                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        732901                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       732901                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         732901                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       732901                       # number of overall misses
-system.cpu.icache.overall_misses::total        732901                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   8031652441                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   8031652441                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   8031652441                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   8031652441                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   8031652441                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   8031652441                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     82204062                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     82204062                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     82204062                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     82204062                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     82204062                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     82204062                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008916                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.008916                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.008916                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.008916                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.008916                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.008916                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10958.713989                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 10958.713989                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 10958.713989                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 10958.713989                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 10958.713989                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 10958.713989                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       128534                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          100                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              4274                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         165133459                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        165133459                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     81470653                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        81470653                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      81470653                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         81470653                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     81470653                       # number of overall hits
+system.cpu.icache.overall_hits::total        81470653                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       733019                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        733019                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       733019                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         733019                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       733019                       # number of overall misses
+system.cpu.icache.overall_misses::total        733019                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   8417582442                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   8417582442                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   8417582442                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   8417582442                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   8417582442                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   8417582442                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     82203672                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     82203672                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     82203672                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     82203672                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     82203672                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     82203672                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008917                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.008917                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.008917                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.008917                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.008917                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.008917                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11483.443733                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 11483.443733                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.443733                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 11483.443733                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.443733                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 11483.443733                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       142274                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          124                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              4376                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    30.073467                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    33.333333                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks       725593                       # number of writebacks
-system.cpu.icache.writebacks::total            725593                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         6780                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         6780                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         6780                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         6780                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         6780                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         6780                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       726121                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       726121                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       726121                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       726121                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       726121                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       726121                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   7527879949                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   7527879949                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   7527879949                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   7527879949                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   7527879949                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   7527879949                       # number of overall MSHR miss cycles
+system.cpu.icache.avg_blocked_cycles::no_mshrs    32.512340                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    41.333333                       # average number of cycles each access was blocked
+system.cpu.icache.writebacks::writebacks       725588                       # number of writebacks
+system.cpu.icache.writebacks::total            725588                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         6903                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         6903                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         6903                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         6903                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         6903                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         6903                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       726116                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       726116                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       726116                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       726116                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       726116                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       726116                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   7892899950                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   7892899950                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   7892899950                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   7892899950                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   7892899950                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   7892899950                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008833                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.008833                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.008833                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.008833                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.008833                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.008833                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10367.252771                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10367.252771                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10367.252771                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 10367.252771                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10367.252771                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 10367.252771                       # average overall mshr miss latency
-system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.prefetcher.num_hwpf_issued       402848                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       402975                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit          113                       # number of redundant prefetches already in prefetch queue
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10870.026208                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10870.026208                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10870.026208                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 10870.026208                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10870.026208                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 10870.026208                       # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.prefetcher.num_hwpf_issued       404432                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       404544                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit          102                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        27937                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.prefetcher.pfSpanPage        28328                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         5253.562311                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1811987                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             6314                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           286.979252                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         5246.342429                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1813751                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             6313                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           287.304134                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  5154.206528                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    99.355783                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.314588                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006064                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.320652                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  5152.962075                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    93.380354                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.314512                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.005699                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.320211                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1022          192                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         6122                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::0           12                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         6121                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::0           16                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1           22                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::2           48                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          110                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          166                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          555                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1137                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          139                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4125                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3            3                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          103                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          162                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          554                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1140                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          141                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4124                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1022     0.011719                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.373657                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         70548606                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        70548606                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       968253                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       968253                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1045699                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1045699                       # number of WritebackClean hits
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.373596                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         70548166                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        70548166                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks       968244                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       968244                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1045693                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1045693                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       219932                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       219932                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       696525                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       696525                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1094373                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1094373                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       696525                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1314305                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2010830                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       696525                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1314305                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2010830                       # number of overall hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       219960                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       219960                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       696520                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       696520                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1094361                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1094361                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       696520                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1314321                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2010841                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       696520                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1314321                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2010841                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data           16                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total           16                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          807                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          807                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data          779                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          779                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        29515                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total        29515                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       228207                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       228207                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       228211                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       228211                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst        29515                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       229014                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        258529                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       228990                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        258505                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst        29515                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       229014                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       258529                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       228990                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       258505                       # number of overall misses
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        43000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total        43000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     59970500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     59970500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2262045500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   2262045500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  16271473000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  16271473000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   2262045500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  16331443500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  18593489000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   2262045500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  16331443500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  18593489000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       968253                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       968253                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1045699                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1045699                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     70551500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     70551500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2627115000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   2627115000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  18006396500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  18006396500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   2627115000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  18076948000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  20704063000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   2627115000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  18076948000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  20704063000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       968244                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       968244                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1045693                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1045693                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       220739                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       220739                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       726040                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       726040                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1322580                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1322580                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       726040                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1543319                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2269359                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       726040                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1543319                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2269359                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       726035                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       726035                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1322572                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1322572                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       726035                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1543311                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2269346                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       726035                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1543311                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2269346                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.941176                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.941176                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003656                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.003656                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003529                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.003529                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.040652                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.040652                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.172547                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.172547                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.172551                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.172551                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.040652                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.148391                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.113922                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.148376                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.113912                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.040652                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.148391                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.113922                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.148376                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.113912                       # miss rate for overall accesses
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  2687.500000                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  2687.500000                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74312.887237                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74312.887237                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76640.538709                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76640.538709                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 71301.375506                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 71301.375506                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76640.538709                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71311.987477                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71920.322285                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76640.538709                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71311.987477                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71920.322285                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90566.752246                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90566.752246                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89009.486702                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89009.486702                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78902.403916                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78902.403916                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89009.486702                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78942.084807                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80091.537881                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89009.486702                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78942.084807                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80091.537881                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           50                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total           50                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           36                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           36                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           86                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           99                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           86                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           99                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        54157                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total        54157                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           49                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total           49                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           11                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           34                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           34                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           11                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           83                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           94                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           11                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           83                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           94                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        54467                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total        54467                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           16                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total           16                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          757                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          757                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        29502                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        29502                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       228171                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       228171                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        29502                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       228928                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       258430                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        29502                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       228928                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        54157                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       312587                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    187753381                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    187753381                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          730                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          730                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        29504                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        29504                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       228177                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       228177                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        29504                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       228907                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       258411                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        29504                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       228907                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        54467                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       312878                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    206471258                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    206471258                       # number of HardPFReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       251000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       251000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     53315000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     53315000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2084473500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2084473500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  14900259000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  14900259000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2084473500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  14953574000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  17038047500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2084473500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  14953574000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    187753381                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  17225800881                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     64550000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     64550000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2449507500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2449507500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  16634852500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  16634852500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2449507500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16699402500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  19148910000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2449507500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16699402500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    206471258                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  19355381258                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.941176                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.941176                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003429                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003429                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.040634                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040634                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.172520                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.172520                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.040634                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.148335                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.113878                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.040634                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.148335                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003307                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003307                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.040637                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040637                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.172525                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.172525                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.040637                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.148322                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.113870                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.040637                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.148322                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.137742                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3466.834961                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  3466.834961                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.137871                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3790.758771                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  3790.758771                       # average HardPFReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70429.326288                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70429.326288                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70655.328452                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70655.328452                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65303.035881                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65303.035881                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70655.328452                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65319.987070                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65929.062028                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70655.328452                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65319.987070                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3466.834961                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55107.220969                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      4537857                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2268434                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests       254467                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops        51535                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops        51534                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88424.657534                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88424.657534                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83022.895201                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83022.895201                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72903.283416                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72903.283416                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83022.895201                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72952.782134                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74102.534335                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83022.895201                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72952.782134                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3790.758771                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61862.391277                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      4537831                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2268421                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests       254469                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops        51822                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops        51821                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp       2048700                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       968253                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1300147                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq        55525                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp       2048687                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       968244                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1300143                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq        55841                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       220739                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       220739                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       726121                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1322580                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2177753                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4629479                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6807232                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     92904448                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    197512064                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          290416512                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       55606                       # Total snoops (count)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       726116                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1322572                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2177738                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4629455                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6807193                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     92903808                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    197511040                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          290414848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       55922                       # Total snoops (count)
 system.cpu.toL2Bus.snoopTraffic                  5184                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      2324982                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.131629                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.338088                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      2325285                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.131736                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.338205                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2018948     86.84%     86.84% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             306033     13.16%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2018962     86.83%     86.83% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             306322     13.17%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2324982                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4537328500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          3.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1089458442                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2325285                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4537302500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          3.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    1089460423                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2315007958                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2314997455                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.9                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests        261068                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       253748                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests        261072                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       253753                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp             260294                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 122177531500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp             260325                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq               16                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               757                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              757                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        260295                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       522119                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 522119                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16707264                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                16707264                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq               730                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              730                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        260326                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       522127                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 522127                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16707520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                16707520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            261068                       # Request fanout histogram
+system.membus.snoop_fanout::samples            261072                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  261068    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  261072    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              261068                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           329929457                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              261072                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           329884354                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1377865586                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1377672131                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
index ca9122542..1dc6d91c8 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
@@ -149,7 +149,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -583,7 +583,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -643,7 +643,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -760,6 +760,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -779,29 +780,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -821,6 +829,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -852,9 +861,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
index b5d01fab2..c97afb693 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:28
-gem5 executing on e108600-lin, pid 4301
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:44
+gem5 executing on e108600-lin, pid 28059
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -650,4 +650,4 @@ info: Increasing stack size by one page.
 2000: 2845746745
 1000: 2068042552
 0: 290958364
-Exiting @ tick 508215534000 because target called exit()
+Exiting @ tick 521167228000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
index cfec5db38..40d44c1cb 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,80 +1,80 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.508441                       # Number of seconds simulated
-sim_ticks                                508441445000                       # Number of ticks simulated
-final_tick                               508441445000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.521167                       # Number of seconds simulated
+sim_ticks                                521167228000                       # Number of ticks simulated
+final_tick                               521167228000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 272638                       # Simulator instruction rate (inst/s)
-host_op_rate                                   272638                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              149248503                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 263860                       # Number of bytes of host memory used
-host_seconds                                  3406.68                       # Real time elapsed on the host
+host_inst_rate                                 258077                       # Simulator instruction rate (inst/s)
+host_op_rate                                   258077                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              144813393                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260992                       # Number of bytes of host memory used
+host_seconds                                  3598.89                       # Real time elapsed on the host
 sim_insts                                   928789150                       # Number of instructions simulated
 sim_ops                                     928789150                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 508441445000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            185856                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 521167228000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            185984                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          18520896                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18706752                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       185856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          185856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total             18706880                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       185984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          185984                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2904                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2906                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data             289389                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                292293                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                292295                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               365541                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             36426802                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                36792343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          365541                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             365541                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           8393714                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                8393714                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           8393714                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              365541                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            36426802                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               45186057                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        292293                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               356861                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             35537338                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                35894199                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          356861                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             356861                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           8188757                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                8188757                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           8188757                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              356861                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            35537338                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               44082956                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        292295                       # Number of read requests accepted
 system.physmem.writeReqs                        66683                       # Number of write requests accepted
-system.physmem.readBursts                      292293                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      292295                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18685888                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     20864                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4266496                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18706752                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18686976                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19904                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4265856                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18706880                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      326                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      311                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               18028                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18361                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18399                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18347                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18249                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18247                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18319                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               18291                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18230                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18239                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18229                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18377                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18369                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18396                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18341                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18255                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18258                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18325                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18297                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18227                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18235                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18232                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18375                       # Per bank write bursts
 system.physmem.perBankRdBursts::12              18268                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18136                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18134                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              18057                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18190                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18187                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4123                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4160                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4142                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4099                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4221                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4157                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4141                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4097                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4260                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4224                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4188                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4192                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
@@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    508441362500                       # Total gap between requests
+system.physmem.totGap                    521167139500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  292293                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  292295                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -98,9 +98,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    291491                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       464                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    291434                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       537                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      907                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      908                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      896                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4047                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4055                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4055                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4055                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4055                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4055                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4055                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::26                     4055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4059                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4054                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -194,102 +194,111 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       103424                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      221.899134                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     143.895688                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     268.440022                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          37597     36.35%     36.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43798     42.35%     78.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9078      8.78%     87.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          804      0.78%     88.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1585      1.53%     89.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1026      0.99%     90.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          543      0.53%     91.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          660      0.64%     91.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8333      8.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         103424                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4053                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        71.164816                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.696519                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      767.230213                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4045     99.80%     99.80% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        95989                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      239.106731                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     159.105135                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     271.560992                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          28950     30.16%     30.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        41784     43.53%     73.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        11694     12.18%     85.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2599      2.71%     88.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          913      0.95%     89.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          756      0.79%     90.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          331      0.34%     90.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          447      0.47%     91.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8515      8.87%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          95989                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4054                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        68.753823                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.637200                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      730.740597                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4046     99.80%     99.80% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359            4      0.10%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-16383            2      0.05%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::7168-8191            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            5      0.12%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4053                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4053                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.448063                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.427763                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.835172                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3146     77.62%     77.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                906     22.35%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4053                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2452616250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                7926997500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1459835000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8400.32                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4054                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4054                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.441539                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.421503                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.829633                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3159     77.92%     77.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                895     22.08%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4054                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    15194551500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               20669251500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1459920000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       52038.99                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27150.32                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          36.75                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           8.39                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       36.79                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        8.39                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  70788.99                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          35.86                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           8.19                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       35.89                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        8.19                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.35                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.29                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.07                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.34                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.28                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.39                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     203097                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     52099                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.56                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.13                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1416365.89                       # Average gap between requests
-system.physmem.pageHitRate                      71.15                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  390353040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  212990250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1140196200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            33208459440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           103170345705                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           214560479250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             352899262365                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              694.089734                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   356274409500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     16977740000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    135182501000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  391426560                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  213576000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1136460000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                215544240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            33208459440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           103438175310                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           214325517750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             352929159300                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              694.148589                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   355878371250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     16977740000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    135579179250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 508441445000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               123851654                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          79872946                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            686743                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            102066133                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                68190143                       # Number of BTB hits
+system.physmem.avgWrQLen                        24.40                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     210474                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     52167                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   72.08                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.23                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1451808.02                       # Average gap between requests
+system.physmem.pageHitRate                      73.23                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  341770380                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  181632495                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1044360660                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                174280140                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           28691395200.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             8105258640                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             1605839040                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       57337999170                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       51043667520                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        64046185080                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             212592411075                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              407.915916                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           499165974500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     3167480750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     12206580000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   240498579500                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 132926079750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      6626927000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 125741581000                       # Time in different power states
+system.physmem_1.actEnergy                  343648200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  182645760                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1040405100                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                173653740                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           28803874320.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             8196268830                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             1616284320                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       57528037740                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       51141308640                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        63870409695                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             212914803135                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              408.534516                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           498942805750                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     3183963500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     12254448000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   239604631750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 133180372750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      6785962500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 126157849500                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 521167228000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               123851675                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          79872959                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            686742                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            102066154                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                68190152                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             66.809764                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18697398                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              11224                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups        14052177                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits           14048616                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses             3561                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted        11655                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             66.809759                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18697401                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              11223                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        14052181                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           14048615                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             3566                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        11656                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -299,18 +308,18 @@ system.cpu.dtb.read_hits                    237539296                       # DT
 system.cpu.dtb.read_misses                     195211                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_accesses                237734507                       # DTB read accesses
-system.cpu.dtb.write_hits                    98305021                       # DTB write hits
+system.cpu.dtb.write_hits                    98305023                       # DTB write hits
 system.cpu.dtb.write_misses                      7170                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                98312191                       # DTB write accesses
-system.cpu.dtb.data_hits                    335844317                       # DTB hits
+system.cpu.dtb.write_accesses                98312193                       # DTB write accesses
+system.cpu.dtb.data_hits                    335844319                       # DTB hits
 system.cpu.dtb.data_misses                     202381                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                336046698                       # DTB accesses
-system.cpu.itb.fetch_hits                   286584411                       # ITB hits
+system.cpu.dtb.data_accesses                336046700                       # DTB accesses
+system.cpu.itb.fetch_hits                   286584578                       # ITB hits
 system.cpu.itb.fetch_misses                       119                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               286584530                       # ITB accesses
+system.cpu.itb.fetch_accesses               286584697                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -324,16 +333,16 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    508441445000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       1016882890                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    521167228000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       1042334456                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   928789150                       # Number of instructions committed
 system.cpu.committedOps                     928789150                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                        319599                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                        319598                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.094848                       # CPI: cycles per instruction
-system.cpu.ipc                               0.913369                       # IPC: instructions per cycle
+system.cpu.cpi                               1.122251                       # CPI: cycles per instruction
+system.cpu.ipc                               0.891066                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass            86206875      9.28%      9.28% # Class of committed instruction
 system.cpu.op_class_0::IntAlu               486529511     52.38%     61.66% # Class of committed instruction
 system.cpu.op_class_0::IntMult                   7040      0.00%     61.67% # Class of committed instruction
@@ -369,60 +378,60 @@ system.cpu.op_class_0::MemWrite              98308071     10.58%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                928789150                       # Class of committed instruction
-system.cpu.tickCycles                       962815783                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        54067107                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                       962817000                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        79517456                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            776559                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.323693                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           320318732                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4092.209717                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           320318705                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            780655                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            410.320477                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         911974500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.323693                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999102                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999102                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            410.320442                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         968708500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.209717                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999075                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999075                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          212                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          956                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1381                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1491                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          957                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1349                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1527                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         643115727                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        643115727                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508441445000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    222154683                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       222154683                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     98164049                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       98164049                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     320318732                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        320318732                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    320318732                       # number of overall hits
-system.cpu.dcache.overall_hits::total       320318732                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses         643115675                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        643115675                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 521167228000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    222154657                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       222154657                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     98164048                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       98164048                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     320318705                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        320318705                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    320318705                       # number of overall hits
+system.cpu.dcache.overall_hits::total       320318705                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       711653                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        711653                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       137151                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       137151                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       848804                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         848804                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       848804                       # number of overall misses
-system.cpu.dcache.overall_misses::total        848804                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24607511500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24607511500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10163393500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10163393500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34770905000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34770905000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34770905000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34770905000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    222866336                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    222866336                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data       137152                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       137152                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       848805                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         848805                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       848805                       # number of overall misses
+system.cpu.dcache.overall_misses::total        848805                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  36922839000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  36922839000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10957317000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10957317000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  47880156000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  47880156000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  47880156000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  47880156000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    222866310                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    222866310                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    321167536                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    321167536                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    321167536                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    321167536                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    321167510                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    321167510                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    321167510                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    321167510                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003193                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.003193                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001395                       # miss rate for WriteReq accesses
@@ -431,14 +440,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002643
 system.cpu.dcache.demand_miss_rate::total     0.002643                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002643                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002643                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34577.963558                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34577.963558                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74103.677698                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74103.677698                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40964.586642                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40964.586642                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40964.586642                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40964.586642                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51883.205720                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 51883.205720                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79891.777007                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 79891.777007                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56408.899571                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56408.899571                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 56408.899571                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 56408.899571                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -449,12 +458,12 @@ system.cpu.dcache.writebacks::writebacks        88440                       # nu
 system.cpu.dcache.writebacks::total             88440                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            9                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total            9                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68140                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        68140                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        68149                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        68149                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        68149                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        68149                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68141                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68141                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        68150                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        68150                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        68150                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        68150                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       711644                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       711644                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69011                       # number of WriteReq MSHR misses
@@ -463,14 +472,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       780655
 system.cpu.dcache.demand_mshr_misses::total       780655                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       780655                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       780655                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23895183000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23895183000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5097981500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5097981500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28993164500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  28993164500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28993164500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28993164500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  36210490500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  36210490500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5501688000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5501688000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  41712178500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  41712178500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  41712178500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  41712178500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003193                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003193                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000702                       # mshr miss rate for WriteReq accesses
@@ -479,24 +488,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002431
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002431                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002431                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002431                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33577.439000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33577.439000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73872.013157                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73872.013157                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37139.536031                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 37139.536031                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37139.536031                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 37139.536031                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements             10578                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1690.178313                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           286572086                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             12324                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          23253.171535                       # Average number of references to valid blocks.
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50882.871913                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50882.871913                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79721.899407                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79721.899407                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53432.282506                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53432.282506                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53432.282506                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53432.282506                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements             10581                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1690.101724                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           286572250                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             12327                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          23247.525756                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1690.178313                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.825282                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.825282                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1690.101724                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.825245                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.825245                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1746                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
@@ -504,181 +513,181 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2            2
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1576                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.852539                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         573181146                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        573181146                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 508441445000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    286572086                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       286572086                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     286572086                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        286572086                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    286572086                       # number of overall hits
-system.cpu.icache.overall_hits::total       286572086                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        12325                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         12325                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        12325                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          12325                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        12325                       # number of overall misses
-system.cpu.icache.overall_misses::total         12325                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    354631500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    354631500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    354631500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    354631500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    354631500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    354631500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    286584411                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    286584411                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    286584411                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    286584411                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    286584411                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    286584411                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         573181483                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        573181483                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 521167228000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    286572250                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       286572250                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     286572250                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        286572250                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    286572250                       # number of overall hits
+system.cpu.icache.overall_hits::total       286572250                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        12328                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         12328                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        12328                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          12328                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        12328                       # number of overall misses
+system.cpu.icache.overall_misses::total         12328                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    376885500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    376885500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    376885500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    376885500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    376885500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    376885500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    286584578                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    286584578                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    286584578                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    286584578                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    286584578                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    286584578                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000043                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000043                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000043                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000043                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28773.346856                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28773.346856                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28773.346856                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28773.346856                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28773.346856                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28773.346856                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30571.503894                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 30571.503894                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 30571.503894                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 30571.503894                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 30571.503894                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 30571.503894                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks        10578                       # number of writebacks
-system.cpu.icache.writebacks::total             10578                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12325                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        12325                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        12325                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        12325                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        12325                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        12325                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    342307500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    342307500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    342307500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    342307500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    342307500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    342307500                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks        10581                       # number of writebacks
+system.cpu.icache.writebacks::total             10581                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12328                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        12328                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        12328                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        12328                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        12328                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        12328                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    364558500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    364558500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    364558500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    364558500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    364558500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    364558500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000043                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000043                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000043                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27773.427992                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27773.427992                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27773.427992                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 27773.427992                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27773.427992                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 27773.427992                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           259981                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32663.117880                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1287366                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           292749                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.397508                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       3599699000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    51.758593                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    79.280290                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 32532.078996                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.001580                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002419                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.992800                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996799                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29571.585010                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29571.585010                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29571.585010                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 29571.585010                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29571.585010                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 29571.585010                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           259984                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32658.667775                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1287369                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           292752                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.397473                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       3857784000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks    51.730334                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    79.865838                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 32527.071603                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.001579                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002437                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.992647                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996663                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          153                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          302                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2944                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29072                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          151                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          294                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2875                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29149                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         12933685                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        12933685                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 508441445000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.tag_accesses         12933736                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        12933736                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 521167228000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks        88440                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total        88440                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        10578                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        10578                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        10581                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        10581                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         2366                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         2366                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         9420                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         9420                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         9421                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         9421                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data       488900                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total       488900                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         9420                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         9421                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data       491266                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          500686                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         9420                       # number of overall hits
+system.cpu.l2cache.demand_hits::total          500687                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         9421                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data       491266                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         500686                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         500687                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data        66645                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66645                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2905                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2905                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2907                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2907                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222744                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total       222744                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2905                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         2907                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data       289389                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        292294                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2905                       # number of overall misses
+system.cpu.l2cache.demand_misses::total        292296                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2907                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       289389                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       292294                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4969595000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4969595000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    224911500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    224911500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17694256000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  17694256000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    224911500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  22663851000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  22888762500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    224911500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  22663851000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  22888762500                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total       292296                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5373301500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5373301500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    247147500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    247147500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  30009565500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  30009565500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    247147500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  35382867000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  35630014500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    247147500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  35382867000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  35630014500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks        88440                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total        88440                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        10578                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        10578                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        10581                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        10581                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        69011                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        69011                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        12325                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        12325                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        12328                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        12328                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       711644                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total       711644                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        12325                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        12328                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       780655                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       792980                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        12325                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       792983                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        12328                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       780655                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       792980                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       792983                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.965716                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.965716                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.235700                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.235700                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.235805                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.235805                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312999                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312999                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.235700                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.235805                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.370700                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.368602                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.235700                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.368603                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.235805                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.370700                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.368602                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74568.159652                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74568.159652                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77422.203098                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77422.203098                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79437.632439                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79437.632439                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77422.203098                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78316.214507                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78307.329264                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77422.203098                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78316.214507                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78307.329264                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.368603                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80625.725861                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80625.725861                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85018.059856                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85018.059856                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134726.706443                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134726.706443                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85018.059856                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 122267.491162                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 121897.030750                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85018.059856                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 122267.491162                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 121897.030750                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -691,126 +700,126 @@ system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1
 system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66645                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66645                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2905                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2905                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2907                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2907                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222744                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222744                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2905                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2907                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data       289389                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       292294                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2905                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       292296                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2907                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       289389                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       292294                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4303145000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4303145000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    195871500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    195871500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15466816000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15466816000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    195871500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19769961000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  19965832500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    195871500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19769961000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  19965832500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total       292296                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4706851500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4706851500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    218087500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    218087500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  27782125500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  27782125500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    218087500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  32488977000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  32707064500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    218087500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  32488977000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  32707064500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.965716                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965716                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.235700                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.235700                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.235805                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.235805                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312999                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312999                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.235700                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.235805                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370700                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.368602                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.235700                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.368603                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.235805                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370700                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.368602                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64568.159652                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64568.159652                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67425.645439                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67425.645439                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69437.632439                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69437.632439                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67425.645439                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68316.214507                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68307.363476                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67425.645439                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68316.214507                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68307.363476                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      1580117                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       787137                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.368603                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70625.725861                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70625.725861                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75021.499828                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75021.499828                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124726.706443                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124726.706443                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75021.499828                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 112267.491162                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 111897.064962                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75021.499828                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 112267.491162                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 111897.064962                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      1580123                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       787140                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2095                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2095                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2096                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2096                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508441445000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp        723968                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 521167228000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp        723971                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       155123                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        10578                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       881417                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        10581                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       881420                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69011                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69011                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        12325                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        12328                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq       711644                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        35227                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        35236                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2337869                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2373096                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1465728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2373105                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1466112                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55622080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           57087808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      259981                       # Total snoops (count)
+system.cpu.toL2Bus.pkt_size::total           57088192                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      259984                       # Total snoops (count)
 system.cpu.toL2Bus.snoopTraffic               4267712                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      1052961                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001990                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.044561                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      1052967                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001991                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.044571                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1050866     99.80%     99.80% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2095      0.20%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1050871     99.80%     99.80% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2096      0.20%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1052961                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      889076500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1052967                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      889082500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      18486000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      18490500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1170982999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1170982500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests        550179                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       257886                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests        550183                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       257888                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 508441445000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp             225648                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 521167228000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp             225650                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        66683                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191203                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           191205                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66645                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66645                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225648                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842472                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 842472                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22974464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22974464                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        225650                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842478                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 842478                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22974592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22974592                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            292293                       # Request fanout histogram
+system.membus.snoop_fanout::samples            292295                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  292293    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  292295    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              292293                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           925378500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              292295                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           925387500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1556878500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1555624500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 0e87d435d..49d14f26b 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -591,7 +591,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -708,6 +708,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -727,29 +728,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -769,6 +777,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -800,9 +809,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index 8e7b7a0be..2bef733aa 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-ti
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:28
-gem5 executing on e108600-lin, pid 4303
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:46
+gem5 executing on e108600-lin, pid 28086
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -650,4 +650,4 @@ info: Increasing stack size by one page.
 2000: 2845746745
 1000: 2068042552
 0: 290958364
-Exiting @ tick 174766258500 because target called exit()
+Exiting @ tick 180964610500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index c74410070..d1e4abf0c 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,70 +1,70 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.175004                       # Number of seconds simulated
-sim_ticks                                175004412500                       # Number of ticks simulated
-final_tick                               175004412500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.180965                       # Number of seconds simulated
+sim_ticks                                180964610500                       # Number of ticks simulated
+final_tick                               180964610500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 244500                       # Simulator instruction rate (inst/s)
-host_op_rate                                   244500                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               50794673                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265392                       # Number of bytes of host memory used
-host_seconds                                  3445.33                       # Real time elapsed on the host
+host_inst_rate                                 216717                       # Simulator instruction rate (inst/s)
+host_op_rate                                   216717                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               46556270                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262532                       # Number of bytes of host memory used
+host_seconds                                  3887.01                       # Real time elapsed on the host
 sim_insts                                   842382029                       # Number of instructions simulated
 sim_ops                                     842382029                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 175004412500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 180964610500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            173952                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18525120                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18699072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18525056                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18699008                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       173952                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          173952                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267648                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267648                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst               2718                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             289455                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                292173                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                292172                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66682                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66682                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               993986                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            105855160                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               106849146                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          993986                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             993986                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          24385945                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               24385945                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          24385945                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              993986                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           105855160                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              131235091                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        292173                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               961249                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            102368391                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               103329640                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          961249                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             961249                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          23582777                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               23582777                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          23582777                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              961249                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           102368391                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              126912416                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        292172                       # Number of read requests accepted
 system.physmem.writeReqs                        66682                       # Number of write requests accepted
-system.physmem.readBursts                      292173                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      292172                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66682                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18679488                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19584                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4266624                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18699072                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18678912                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20096                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4266048                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18699008                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4267648                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      306                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      314                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18012                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18010                       # Per bank write bursts
 system.physmem.perBankRdBursts::1               18337                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18383                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18348                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18239                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18237                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18320                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               18308                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18229                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18225                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18220                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18382                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18388                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18350                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18232                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18236                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18319                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18311                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18232                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18232                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18215                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18381                       # Per bank write bursts
 system.physmem.perBankRdBursts::12              18250                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18123                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18058                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18196                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18122                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18054                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18189                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::5                4099                       # Pe
 system.physmem.perBankWrBursts::6                4261                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4191                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4182                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
@@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    175004322000                       # Total gap between requests
+system.physmem.totGap                    180964514000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  292173                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  292172                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -98,12 +98,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66682                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    215232                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     46701                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     29729                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       174                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    214643                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     47013                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     29962                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       202                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -145,25 +145,25 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4080                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4069                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4076                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4079                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4098                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4097                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4508                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      884                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      892                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2498                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4242                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4605                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
@@ -194,126 +194,136 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        96708                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      237.268147                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     153.455294                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     282.430006                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          31632     32.71%     32.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        41779     43.20%     75.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        11320     11.71%     87.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          443      0.46%     88.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          357      0.37%     88.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          304      0.31%     88.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          669      0.69%     89.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1569      1.62%     91.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8635      8.93%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          96708                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4054                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        71.658609                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.711074                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      765.890247                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4045     99.78%     99.78% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359            3      0.07%     99.93% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        95105                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      241.251837                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     155.294089                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     287.548448                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          30650     32.23%     32.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        40922     43.03%     75.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        11798     12.41%     87.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          210      0.22%     87.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          215      0.23%     88.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          192      0.20%     88.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          361      0.38%     88.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1740      1.83%     90.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9017      9.48%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          95105                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4055                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        69.502343                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.667312                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      739.938886                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4047     99.80%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-11263            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13312-14335            2      0.05%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            1      0.02%     99.93% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::15360-16383            2      0.05%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4054                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4054                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.444499                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.424176                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.836057                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3157     77.87%     77.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                892     22.00%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  2      0.05%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  3      0.07%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4054                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3688779750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9161286000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1459335000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12638.56                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4055                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4055                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.438224                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.418308                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.827243                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3164     78.03%     78.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  7      0.17%     78.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                882     21.75%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  2      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4055                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    10146386000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               15618723500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1459290000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       34764.80                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31388.56                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         106.74                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          24.38                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      106.85                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       24.39                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  53514.80                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         103.22                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          23.57                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      103.33                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       23.58                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.83                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.19                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.99                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.81                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.18                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.52                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     209722                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     52099                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   71.86                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.13                       # Row buffer hit rate for writes
-system.physmem.avgGap                       487674.19                       # Average gap between requests
-system.physmem.pageHitRate                      73.02                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  365095080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  199208625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1140180600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                216432000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            11430394560                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            63710720865                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            49115814750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             126177846480                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              720.999703                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    81290875500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      5843760000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     87869398250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  366002280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  199703625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1136311800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                215563680                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            11430394560                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            64026816075                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            48838535250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             126213327270                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              721.202467                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    80826473000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      5843760000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     88334018000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 175004412500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               129267773                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          83048997                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            145228                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             93512308                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                70602709                       # Number of BTB hits
+system.physmem.avgWrQLen                        24.36                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     211326                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     52079                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   72.41                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.10                       # Row buffer hit rate for writes
+system.physmem.avgGap                       504284.51                       # Average gap between requests
+system.physmem.pageHitRate                      73.47                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  339192840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  180273885                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1043746620                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                174348000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           16047635760.000004                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5505974850                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              757646880                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       38977794150                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       26263488480                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy         5833398105                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              95148801450                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              525.786736                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           166860797500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     1403220500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      6819966000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    12988477500                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  68394436250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      5880505500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  85478004750                       # Time in different power states
+system.physmem_1.actEnergy                  339892560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  180649590                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1040119500                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                173601540                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           16056240720.000004                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5469389970                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              750054720                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       39161701800                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       26293456800                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy         5720767110                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              95209751490                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              526.123579                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           166963691000                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     1377166250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      6823618000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    12610325250                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  68472559500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      5800086000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  85880855500                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 180964610500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               129261099                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          83045520                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            145257                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             93509067                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                70599314                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             75.500980                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                19428222                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               1139                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups        14846516                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits           14819690                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses            26826                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted         4927                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             75.499966                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                19428116                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1153                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        14846448                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           14825593                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            20855                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted         4929                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    243602594                       # DTB read hits
-system.cpu.dtb.read_misses                     267810                       # DTB read misses
+system.cpu.dtb.read_hits                    243608266                       # DTB read hits
+system.cpu.dtb.read_misses                     267709                       # DTB read misses
 system.cpu.dtb.read_acv                             2                       # DTB read access violations
-system.cpu.dtb.read_accesses                243870404                       # DTB read accesses
-system.cpu.dtb.write_hits                   101634629                       # DTB write hits
-system.cpu.dtb.write_misses                     39603                       # DTB write misses
+system.cpu.dtb.read_accesses                243875975                       # DTB read accesses
+system.cpu.dtb.write_hits                   101634051                       # DTB write hits
+system.cpu.dtb.write_misses                     39619                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               101674232                       # DTB write accesses
-system.cpu.dtb.data_hits                    345237223                       # DTB hits
-system.cpu.dtb.data_misses                     307413                       # DTB misses
+system.cpu.dtb.write_accesses               101673670                       # DTB write accesses
+system.cpu.dtb.data_hits                    345242317                       # DTB hits
+system.cpu.dtb.data_misses                     307328                       # DTB misses
 system.cpu.dtb.data_acv                             2                       # DTB access violations
-system.cpu.dtb.data_accesses                345544636                       # DTB accesses
-system.cpu.itb.fetch_hits                   116218491                       # ITB hits
-system.cpu.itb.fetch_misses                      1583                       # ITB misses
+system.cpu.dtb.data_accesses                345549645                       # DTB accesses
+system.cpu.itb.fetch_hits                   116218000                       # ITB hits
+system.cpu.itb.fetch_misses                      1612                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               116220074                       # ITB accesses
+system.cpu.itb.fetch_accesses               116219612                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -327,99 +337,99 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    175004412500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        350008826                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    180964610500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        361929222                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          116537595                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      973721565                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   129267773                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          104850621                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     232833162                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                  756818                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  821                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         12983                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles          116540326                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      973682349                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   129261099                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          104853023                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     244730119                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                  756754                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  840                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         15490                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           28                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 116218491                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                171000                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          349762998                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.783947                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.089679                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                 116218000                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                168019                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          361665180                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.692220                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.078693                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                153044218     43.76%     43.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 21853200      6.25%     50.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 15619262      4.47%     54.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 24569789      7.02%     61.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 38589030     11.03%     72.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 15690779      4.49%     77.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 12536762      3.58%     80.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3989777      1.14%     81.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 63870181     18.26%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                164951201     45.61%     45.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 21852654      6.04%     51.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 15621060      4.32%     55.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 24569981      6.79%     62.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 38586382     10.67%     73.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 15690881      4.34%     77.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 12539815      3.47%     81.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3986839      1.10%     82.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 63866367     17.66%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            349762998                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.369327                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.781991                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 85730052                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              86245168                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 158924333                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              18491829                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 371616                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             11931982                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  7013                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              968682189                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 25467                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 371616                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 93247100                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                12146615                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          14284                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 169253997                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              74729386                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              966801753                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1559                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               25162616                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               40511587                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                7290496                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           666571567                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1151541399                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1114502328                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          37039070                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            361665180                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.357145                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.690256                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 85732697                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              98146269                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 158921683                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              18492948                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 371583                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             11928940                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  7011                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              968666226                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 25451                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 371583                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 93249960                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                12380390                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          15406                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 169252258                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              86395583                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              966785843                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1367                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               25166874                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               51736906                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                7729074                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           666569704                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1151545318                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1114509565                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          37035752                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             638967158                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27604409                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1367                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                 27602546                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1366                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             87                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  87953522                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            245057905                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           102624371                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          35358842                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          4732178                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  877945283                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  77                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 871653931                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             10631                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        35563330                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     10945081                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             40                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     349762998                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.492127                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.135671                       # Number of insts issued each cycle
+system.cpu.rename.skidInsts                  87961020                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            245059340                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           102632582                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          35344831                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          4698812                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  877945756                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  74                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 871651299                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             10628                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        35563800                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     10965429                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             37                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     361665180                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.410106                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.146787                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            75990310     21.73%     21.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            61353138     17.54%     39.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            57501132     16.44%     55.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            51071612     14.60%     70.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            45054201     12.88%     83.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            20633149      5.90%     89.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            18143842      5.19%     94.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            10286820      2.94%     97.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             9728794      2.78%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            87893149     24.30%     24.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            61352794     16.96%     41.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            57499290     15.90%     57.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            51081168     14.12%     71.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            45042350     12.45%     83.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            20636672      5.71%     89.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            18146014      5.02%     94.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            10282367      2.84%     97.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             9731376      2.69%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       349762998                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       361665180                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 3589530     19.39%     19.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 3586644     19.39%     19.39% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     19.39% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.39% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.39% # attempts to use FU when none available
@@ -448,16 +458,16 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.39% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.39% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.39% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               11797020     63.73%     83.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3124042     16.88%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11792491     63.74%     83.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3122167     16.88%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              1276      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             505112247     57.95%     57.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                 7850      0.00%     57.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             505104722     57.95%     57.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 7855      0.00%     57.95% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            13300875      1.53%     59.48% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             3826555      0.44%     59.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            13297886      1.53%     59.47% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             3826557      0.44%     59.91% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt             3339806      0.38%     60.30% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     60.30% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.30% # Type of FU issued
@@ -482,82 +492,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     60.30% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.30% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.30% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.30% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            244260355     28.02%     88.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           101804963     11.68%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            244265808     28.02%     88.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           101807385     11.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              871653931                       # Type of FU issued
-system.cpu.iq.rate                           2.490377                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    18510592                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.021236                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2042303381                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         876767032                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    835994185                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            69288702                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           36778589                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     34169846                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              855062076                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                35101171                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         65597395                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              871651299                       # Type of FU issued
+system.cpu.iq.rate                           2.408347                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    18501302                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.021226                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2054197029                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         876768256                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    835988686                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            69282679                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           36778231                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     34166819                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              855053167                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                35098158                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         65597237                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      7547308                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         5161                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        37165                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      4323171                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      7548743                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         5138                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        37089                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      4331382                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2714                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          4324                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2716                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          4307                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 371616                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 4020858                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                620837                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           966016228                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             16689                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             245057905                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            102624371                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 77                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 538553                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 95932                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          37165                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         128220                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect        15953                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               144173                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             871032011                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             243870521                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            621920                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 371583                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 4257057                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                608088                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           966007295                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             16673                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             245059340                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            102632582                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 74                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 538259                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 83477                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          37089                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         128251                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect        15992                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               144243                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             871026557                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             243876094                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            624742                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      88070868                       # number of nop insts executed
-system.cpu.iew.exec_refs                    345545074                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                127159833                       # Number of branches executed
-system.cpu.iew.exec_stores                  101674553                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.488600                       # Inst execution rate
-system.cpu.iew.wb_sent                      870625746                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     870164031                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 525002727                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 821961915                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       2.486120                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.638719                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        31814193                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                      88061465                       # number of nop insts executed
+system.cpu.iew.exec_refs                    345550079                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                127153600                       # Number of branches executed
+system.cpu.iew.exec_stores                  101673985                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.406621                       # Inst execution rate
+system.cpu.iew.wb_sent                      870617196                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     870155505                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 525001925                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 821956019                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       2.404215                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.638723                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        31805123                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            138436                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    345634386                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.686618                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.059575                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            138464                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    357537289                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.597177                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.046569                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    109896722     31.80%     31.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     81929003     23.70%     55.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     29947850      8.66%     64.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     19779542      5.72%     69.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     17820096      5.16%     75.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7961930      2.30%     77.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      3040428      0.88%     78.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3978823      1.15%     79.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     71279992     20.62%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    121797842     34.07%     34.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     81929888     22.92%     56.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     29949089      8.38%     65.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     19779772      5.53%     70.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     17819434      4.98%     75.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7962754      2.23%     78.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3039675      0.85%     78.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3979990      1.11%     80.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     71278845     19.94%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    345634386                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    357537289                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            928587628                       # Number of instructions committed
 system.cpu.commit.committedOps              928587628                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -603,127 +613,127 @@ system.cpu.commit.op_class_0::MemWrite       98301200     10.59%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         928587628                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              71279992                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1232135077                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1924934508                       # The number of ROB writes
-system.cpu.timesIdled                            3150                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          245828                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              71278845                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1244030057                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1924915650                       # The number of ROB writes
+system.cpu.timesIdled                            3145                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          264042                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   842382029                       # Number of Instructions Simulated
 system.cpu.committedOps                     842382029                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.415499                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.415499                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.406745                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.406745                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1104178752                       # number of integer regfile reads
-system.cpu.int_regfile_writes               635595888                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  36406844                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 24680552                       # number of floating regfile writes
+system.cpu.cpi                               0.429650                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.429650                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.327477                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.327477                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1104175341                       # number of integer regfile reads
+system.cpu.int_regfile_writes               635597274                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  36400867                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 24677538                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements            776667                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4091.035125                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           273851714                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            780763                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            350.748837                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         374790500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4091.035125                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998788                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998788                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements            776666                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4090.964650                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           273860034                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            780762                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            350.759942                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         396630500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4090.964650                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998771                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998771                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          421                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1013                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         2512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          412                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1011                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2527                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           62                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         553380005                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        553380005                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 175004412500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    176443372                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       176443372                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     97408329                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       97408329                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         553391630                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        553391630                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 180964610500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    176451824                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       176451824                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     97408197                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       97408197                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           13                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           13                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     273851701                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        273851701                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    273851701                       # number of overall hits
-system.cpu.dcache.overall_hits::total       273851701                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1555036                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1555036                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       892871                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       892871                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2447907                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2447907                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2447907                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2447907                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  84877374000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  84877374000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  62367572330                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  62367572330                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 147244946330                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 147244946330                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 147244946330                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 147244946330                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    177998408                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    177998408                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     273860021                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        273860021                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    273860021                       # number of overall hits
+system.cpu.dcache.overall_hits::total       273860021                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1552397                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1552397                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       893003                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       893003                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2445400                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2445400                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2445400                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2445400                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  96567477000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  96567477000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  65926918364                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  65926918364                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 162494395364                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 162494395364                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 162494395364                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 162494395364                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    178004221                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    178004221                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    276299608                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    276299608                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    276299608                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    276299608                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008736                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.008736                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009083                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.009083                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.008860                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.008860                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.008860                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.008860                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54582.256617                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54582.256617                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69850.596928                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69850.596928                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 60151.364545                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 60151.364545                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60151.364545                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60151.364545                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        24555                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        63758                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               349                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             520                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    70.358166                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   122.611538                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks        88567                       # number of writebacks
-system.cpu.dcache.writebacks::total             88567                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       842892                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       842892                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       824252                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       824252                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1667144                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1667144                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1667144                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1667144                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712144                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712144                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_accesses::cpu.data    276305421                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    276305421                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    276305421                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    276305421                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008721                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.008721                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009084                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.009084                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008850                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.008850                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008850                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.008850                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62205.400423                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 62205.400423                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73826.088338                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73826.088338                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 66449.004402                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66449.004402                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 66449.004402                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66449.004402                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        25561                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       192860                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               308                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             519                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    82.990260                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   371.599229                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks        88570                       # number of writebacks
+system.cpu.dcache.writebacks::total             88570                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       840254                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       840254                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       824384                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       824384                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1664638                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1664638                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1664638                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1664638                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712143                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712143                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68619                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total        68619                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       780763                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       780763                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       780763                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       780763                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24487996000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24487996000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5721430497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5721430497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  30209426497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  30209426497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  30209426497                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  30209426497                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       780762                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       780762                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       780762                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       780762                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30603980500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30603980500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   6049145998                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   6049145998                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36653126498                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  36653126498                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36653126498                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  36653126498                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.004001                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.004001                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000698                       # mshr miss rate for WriteReq accesses
@@ -732,212 +742,212 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002826
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002826                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002826                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002826                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34386.298277                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34386.298277                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83379.683426                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83379.683426                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38692.185077                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 38692.185077                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38692.185077                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 38692.185077                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements              4616                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1647.876124                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           116210243                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6321                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          18384.787692                       # Average number of references to valid blocks.
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42974.487568                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42974.487568                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88155.554555                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88155.554555                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46945.325846                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 46945.325846                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46945.325846                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 46945.325846                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements              4618                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1647.809929                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           116209747                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6323                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          18378.894038                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1647.876124                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.804627                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.804627                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1647.809929                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.804595                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.804595                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1705                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1541                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1545                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.832520                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         232443303                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        232443303                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 175004412500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    116210243                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       116210243                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     116210243                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        116210243                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    116210243                       # number of overall hits
-system.cpu.icache.overall_hits::total       116210243                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         8248                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          8248                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         8248                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           8248                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         8248                       # number of overall misses
-system.cpu.icache.overall_misses::total          8248                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    355215499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    355215499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    355215499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    355215499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    355215499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    355215499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    116218491                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    116218491                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    116218491                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    116218491                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    116218491                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    116218491                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         232442323                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        232442323                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 180964610500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    116209747                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       116209747                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     116209747                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        116209747                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    116209747                       # number of overall hits
+system.cpu.icache.overall_hits::total       116209747                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         8253                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          8253                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         8253                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           8253                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         8253                       # number of overall misses
+system.cpu.icache.overall_misses::total          8253                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    382535999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    382535999                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    382535999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    382535999                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    382535999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    382535999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    116218000                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    116218000                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    116218000                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    116218000                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    116218000                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    116218000                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000071                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000071                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000071                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000071                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000071                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000071                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43066.864573                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 43066.864573                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 43066.864573                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 43066.864573                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 43066.864573                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 43066.864573                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          726                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46351.144917                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 46351.144917                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 46351.144917                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 46351.144917                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 46351.144917                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 46351.144917                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          811                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                13                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    60.500000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    62.384615                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks         4616                       # number of writebacks
-system.cpu.icache.writebacks::total              4616                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1926                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1926                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1926                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1926                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1926                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1926                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6322                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         6322                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         6322                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         6322                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         6322                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         6322                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    265463000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    265463000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    265463000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    265463000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    265463000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    265463000                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks         4618                       # number of writebacks
+system.cpu.icache.writebacks::total              4618                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1929                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1929                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1929                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1929                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1929                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1929                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6324                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         6324                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         6324                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         6324                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         6324                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         6324                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    282422000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    282422000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    282422000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    282422000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    282422000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    282422000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000054                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000054                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000054                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000054                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000054                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000054                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41990.351155                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41990.351155                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41990.351155                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 41990.351155                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41990.351155                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 41990.351155                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           259809                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32656.861347                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1275789                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           292577                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.360524                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       1215633000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    43.546736                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    68.196705                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 32545.117905                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.001329                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002081                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.993198                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996608                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44658.760278                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44658.760278                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44658.760278                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 44658.760278                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44658.760278                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 44658.760278                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           259808                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32653.135367                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1275792                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           292576                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.360549                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       1306360000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks    44.057169                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    68.938267                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 32540.139931                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.001345                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002104                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.993046                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996495                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          214                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          858                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8605                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        22785                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          207                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          834                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8358                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        23070                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         12839521                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        12839521                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 175004412500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks        88567                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total        88567                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         4616                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         4616                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         1994                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         1994                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3603                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         3603                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       489314                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       489314                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3603                       # number of demand (read+write) hits
+system.cpu.l2cache.tags.tag_accesses         12839536                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        12839536                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 180964610500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks        88570                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total        88570                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         4618                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         4618                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         1993                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         1993                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3605                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         3605                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       489315                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       489315                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3605                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data       491308                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          494911                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3603                       # number of overall hits
+system.cpu.l2cache.demand_hits::total          494913                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3605                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data       491308                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         494911                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data        66625                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66625                       # number of ReadExReq misses
+system.cpu.l2cache.overall_hits::total         494913                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data        66626                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66626                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2719                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total         2719                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222830                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       222830                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222828                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       222828                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         2719                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       289455                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        292174                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       289454                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        292173                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         2719                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       289455                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       292174                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5597249000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5597249000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    218052500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    218052500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  18275822500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  18275822500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    218052500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  23873071500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  24091124000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    218052500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  23873071500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  24091124000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks        88567                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total        88567                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         4616                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         4616                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.data       289454                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       292173                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5925054000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5925054000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    234987000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    234987000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  24391913000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  24391913000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    234987000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  30316967000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  30551954000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    234987000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  30316967000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  30551954000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks        88570                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total        88570                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         4618                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         4618                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        68619                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        68619                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         6322                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         6322                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       712144                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       712144                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         6322                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       780763                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       787085                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         6322                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       780763                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       787085                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.970941                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.970941                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.430085                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.430085                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312900                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312900                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.430085                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.370734                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.371210                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.430085                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.370734                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.371210                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84011.242026                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84011.242026                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80195.844060                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80195.844060                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82016.885069                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82016.885069                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80195.844060                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82475.934083                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 82454.715341                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80195.844060                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82475.934083                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 82454.715341                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         6324                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         6324                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       712143                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       712143                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         6324                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       780762                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       787086                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         6324                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       780762                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       787086                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.970956                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.970956                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.429949                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.429949                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312898                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312898                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.429949                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.370733                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.371208                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.429949                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.370733                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.371208                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88930.057335                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88930.057335                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86424.052961                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86424.052961                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109465.206347                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109465.206347                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86424.052961                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104738.462761                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 104568.026477                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86424.052961                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104738.462761                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 104568.026477                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -948,128 +958,128 @@ system.cpu.l2cache.writebacks::writebacks        66682                       # n
 system.cpu.l2cache.writebacks::total            66682                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66625                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66625                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66626                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66626                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2719                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2719                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222830                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222830                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222828                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222828                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2719                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       289455                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       292174                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       289454                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       292173                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2719                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       289455                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       292174                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4930999000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4930999000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    190872500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    190872500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  16047522500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  16047522500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    190872500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20978521500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  21169394000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    190872500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20978521500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  21169394000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data       289454                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       292173                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5258794000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5258794000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    207807000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    207807000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  22163633000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  22163633000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    207807000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  27422427000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  27630234000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    207807000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  27422427000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  27630234000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.970941                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.970941                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.430085                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.430085                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312900                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312900                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.430085                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370734                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.371210                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.430085                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370734                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.371210                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74011.242026                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74011.242026                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70199.521883                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70199.521883                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72016.885069                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72016.885069                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70199.521883                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72475.934083                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72454.749567                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70199.521883                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72475.934083                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72454.749567                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      1568368                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       781283                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.970956                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.970956                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.429949                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.429949                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312898                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312898                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.429949                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370733                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.371208                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.429949                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370733                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.371208                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78930.057335                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78930.057335                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76427.730783                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76427.730783                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99465.206347                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99465.206347                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76427.730783                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94738.462761                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94568.060704                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76427.730783                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94738.462761                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94568.060704                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      1568370                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       781284                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2008                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2008                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2012                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2012                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 175004412500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp        718465                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       155249                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         4616                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       881227                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 180964610500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp        718466                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       155252                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         4618                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       881222                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        68619                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        68619                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         6322                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       712144                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17259                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2338193                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2355452                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       699968                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55637120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56337088                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      259809                       # Total snoops (count)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         6324                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       712143                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17265                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2338190                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2355455                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       700224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55637248                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56337472                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      259808                       # Total snoops (count)
 system.cpu.toL2Bus.snoopTraffic               4267648                       # Total snoop traffic (bytes)
 system.cpu.toL2Bus.snoop_fanout::samples      1046894                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001918                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.043754                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001922                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.043797                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1044886     99.81%     99.81% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2008      0.19%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1044882     99.81%     99.81% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2012      0.19%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::total        1046894                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      877367000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy      877373000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       9481500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       9484500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1171144500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests        549975                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       257802                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.respLayer1.occupancy    1171143000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
+system.membus.snoop_filter.tot_requests        549969                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       257797                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 175004412500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp             225548                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 180964610500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp             225546                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        66682                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191120                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66625                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66625                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225548                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842148                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 842148                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22966720                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22966720                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::CleanEvict           191115                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66626                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66626                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        225546                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842141                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 842141                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22966656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22966656                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            292173                       # Request fanout histogram
+system.membus.snoop_fanout::samples            292172                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  292173    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  292172    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              292173                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           877549500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              292172                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           877590500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1551106000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1551176250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
index 4149684ba..bcc7e805c 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
@@ -151,7 +151,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -631,7 +631,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -691,7 +691,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -880,6 +880,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -891,7 +892,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -899,29 +900,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -941,6 +949,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -972,9 +981,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout
index 99e686564..2e501adb4 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:40:10
-gem5 executing on e108600-lin, pid 23109
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:05:24
+gem5 executing on e108600-lin, pid 17596
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -650,4 +650,4 @@ info: Increasing stack size by one page.
 2000: 2845746745
 1000: 2068042552
 0: 290958364
-Exiting @ tick 512588680500 because target called exit()
+Exiting @ tick 525654485500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index 228ad0113..d38edd9f8 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.512877                       # Number of seconds simulated
-sim_ticks                                512876814500                       # Number of ticks simulated
-final_tick                               512876814500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.525654                       # Number of seconds simulated
+sim_ticks                                525654485500                       # Number of ticks simulated
+final_tick                               525654485500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 169706                       # Simulator instruction rate (inst/s)
-host_op_rate                                   208931                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              135858559                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 281524                       # Number of bytes of host memory used
-host_seconds                                  3775.08                       # Real time elapsed on the host
+host_inst_rate                                 213828                       # Simulator instruction rate (inst/s)
+host_op_rate                                   263250                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              175444467                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 278324                       # Number of bytes of host memory used
+host_seconds                                  2996.13                       # Real time elapsed on the host
 sim_insts                                   640655085                       # Number of instructions simulated
 sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            164160                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          18474496                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             18638656                       # Number of bytes read from this memory
@@ -26,64 +26,64 @@ system.physmem.num_reads::cpu.data             288664                       # Nu
 system.physmem.num_reads::total                291229                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               320077                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             36021312                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                36341389                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          320077                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             320077                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           8248125                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                8248125                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           8248125                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              320077                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            36021312                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               44589514                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               312296                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             35145702                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                35457999                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          312296                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             312296                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           8047628                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                8047628                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           8047628                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              312296                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            35145702                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               43505627                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        291229                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
 system.physmem.readBursts                      291229                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18616640                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     22016                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4228352                       # Total number of bytes written to DRAM
+system.physmem.bytesReadDRAM                 18617024                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21632                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4229248                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                  18638656                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      344                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      338                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18285                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18130                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18219                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18177                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18281                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18133                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18221                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18176                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               18285                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18413                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18173                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               17985                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18026                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18055                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18102                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18206                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18220                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18274                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18073                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18262                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18412                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18178                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               17990                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18034                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18056                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18101                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18200                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18218                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18271                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18077                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18258                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4171                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4098                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4134                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4099                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4135                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4223                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4224                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4092                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4093                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4140                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    512876719500                       # Total gap between requests
+system.physmem.totGap                    525654384500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -98,9 +98,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    290520                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       355                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    290516                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       364                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        11                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      915                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      890                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      889                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::17                     4011                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4017                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4017                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4015                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4022                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4021                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4019                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -194,91 +194,101 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       110420                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      206.874986                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     134.678155                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     257.334201                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          45202     40.94%     40.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43704     39.58%     80.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9014      8.16%     88.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2046      1.85%     90.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          604      0.55%     91.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          569      0.52%     91.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          621      0.56%     92.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          527      0.48%     92.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8133      7.37%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         110420                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4015                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.540971                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.171361                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      506.693530                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4013     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       102767                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      222.307005                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     147.372317                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     261.848294                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          36138     35.16%     35.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        41898     40.77%     75.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13163     12.81%     88.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1012      0.98%     89.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          489      0.48%     90.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1030      1.00%     91.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          399      0.39%     91.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          484      0.47%     92.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8154      7.93%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         102767                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4019                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.497387                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.151985                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      506.429034                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4017     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4015                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4015                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.455293                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.434809                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.838731                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3101     77.24%     77.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                914     22.76%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4015                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2756382250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8210476000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1454425000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9475.85                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4019                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4019                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.442399                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.422334                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.830212                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3130     77.88%     77.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                889     22.12%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4019                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    15538679500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               20992885750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1454455000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       53417.53                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28225.85                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          36.30                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           8.24                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       36.34                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        8.25                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  72167.53                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          35.42                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           8.05                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       35.46                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        8.05                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.35                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.34                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.28                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.56                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     194946                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     51576                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   67.02                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.03                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1435314.77                       # Average gap between requests
-system.physmem.pageHitRate                      69.06                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  418362840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  228273375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1136124600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                215531280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            33498338640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           103989168945                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           216505087500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             355990887180                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              694.111511                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   359471319000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     17125940000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    136275516000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  416336760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  227167875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1132396200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212589360                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            33498338640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           103752790515                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           216712437000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             355952056350                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              694.035798                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   359820444250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     17125940000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    135926935750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               147261658                       # Number of BP lookups
+system.physmem.avgWrQLen                        19.65                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     202495                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     51707                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.61                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.23                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1471073.79                       # Average gap between requests
+system.physmem.pageHitRate                      71.21                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  367124520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  195116130                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1040126640                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                173653740                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           28870255440.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             8266537290                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             1634065440                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       57360982710                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       51276223200                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        64953258915                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             214157919585                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              407.411950                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           503225172750                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     3206676000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     12282762000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   243901523000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 133531907000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      6939814000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 125791803500                       # Time in different power states
+system.physmem_1.actEnergy                  366660420                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  194884635                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1036835100                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                171294300                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           28737493200.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             8178131430                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             1630074720                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       56926536120                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       51134645280                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        65306601210                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             213703234155                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              406.546781                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           503430400500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     3200172000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     12226116000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   245428473250                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 133163073250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      6797797000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 124838854000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               147261657                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          98231058                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           1384734                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             89949366                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                63294628                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups             89949365                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                63294627                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct             70.366953                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                19276105                       # Number of times the RAS was used to get a target.
@@ -288,7 +298,7 @@ system.cpu.branchPred.indirectHits           15988941                       # Nu
 system.cpu.branchPred.indirectMisses             6214                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted      1280093                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -318,7 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -348,7 +358,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -378,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -409,16 +419,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    512876814500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       1025753629                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    525654485500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       1051308971                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   640655085                       # Number of instructions committed
 system.cpu.committedOps                     788730744                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       8621768                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       8621767                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.601101                       # CPI: cycles per instruction
-system.cpu.ipc                               0.624570                       # IPC: instructions per cycle
+system.cpu.cpi                               1.640991                       # CPI: cycles per instruction
+system.cpu.ipc                               0.609388                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu               385757467     48.91%     48.91% # Class of committed instruction
 system.cpu.op_class_0::IntMult                5173441      0.66%     49.56% # Class of committed instruction
@@ -454,28 +464,28 @@ system.cpu.op_class_0::MemWrite             128980497     16.35%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                788730744                       # Class of committed instruction
-system.cpu.tickCycles                       955906199                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        69847430                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                       955911046                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        95397925                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            778100                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.223033                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4092.108689                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           378449407                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            782196                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            483.829382                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         804340500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.223033                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999078                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999078                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle         850386500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.108689                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999050                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999050                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          968                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1421                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1501                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          970                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1388                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1537                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         759383100                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses        759383100                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data    249620680                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       249620680                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    128813765                       # number of WriteReq hits
@@ -500,14 +510,14 @@ system.cpu.dcache.demand_misses::cpu.data       850904                       # n
 system.cpu.dcache.demand_misses::total         850904                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       851045                       # number of overall misses
 system.cpu.dcache.overall_misses::total        851045                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24857030500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24857030500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10252359000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10252359000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35109389500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35109389500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35109389500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35109389500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  37269485500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  37269485500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10946218000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10946218000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  48215703500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  48215703500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  48215703500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  48215703500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    250333872                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    250333872                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
@@ -532,14 +542,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002243
 system.cpu.dcache.demand_miss_rate::total     0.002243                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002244                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002244                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41261.281531                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41254.445417                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52257.296072                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 52257.296072                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79486.304752                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.304752                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56664.093129                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56664.093129                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 56654.705098                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 56654.705098                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -566,16 +576,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       782057
 system.cpu.dcache.demand_mshr_misses::total       782057                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       782196                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       782196                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24135855500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24135855500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5141186000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5141186000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1790000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1790000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29277041500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29277041500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29278831500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29278831500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  36547770500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  36547770500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5489520000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5489520000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1802000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1802000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  42037290500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  42037290500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  42039092500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  42039092500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002847                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002847                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
@@ -586,70 +596,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002062                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51278.203680                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51278.203680                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79188.713540                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79188.713540                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53752.207959                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53752.207959                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53744.959703                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53744.959703                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             24885                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1711.965016                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           257789646                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1711.889727                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           257789639                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             26636                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           9678.241703                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs           9678.241440                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1711.965016                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.835920                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.835920                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1711.889727                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.835884                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.835884                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1751                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1596                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.854980                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         515659202                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        515659202                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    257789646                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       257789646                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     257789646                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        257789646                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    257789646                       # number of overall hits
-system.cpu.icache.overall_hits::total       257789646                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         515659188                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        515659188                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    257789639                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       257789639                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     257789639                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        257789639                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    257789639                       # number of overall hits
+system.cpu.icache.overall_hits::total       257789639                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        26637                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         26637                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        26637                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          26637                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        26637                       # number of overall misses
 system.cpu.icache.overall_misses::total         26637                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    518689000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    518689000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    518689000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    518689000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    518689000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    518689000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    257816283                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    257816283                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    257816283                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    257816283                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    257816283                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    257816283                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    539890500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    539890500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    539890500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    539890500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    539890500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    539890500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    257816276                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    257816276                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    257816276                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    257816276                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    257816276                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    257816276                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000103                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000103                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000103                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000103                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000103                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000103                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19472.500657                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19472.500657                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20268.442392                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20268.442392                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20268.442392                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20268.442392                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20268.442392                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20268.442392                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -664,48 +674,48 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        26637
 system.cpu.icache.demand_mshr_misses::total        26637                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        26637                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        26637                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    492053000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    492053000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    492053000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    492053000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    492053000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    492053000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    513254500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    513254500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    513254500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    513254500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    513254500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    513254500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000103                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000103                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000103                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000103                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000103                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000103                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19268.479934                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19268.479934                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19268.479934                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19268.479934                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19268.479934                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19268.479934                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements           258837                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32655.350813                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        32651.524409                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1316948                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           291605                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             4.516205                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       3732066000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    41.642986                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    88.982590                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.001271                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002716                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.992576                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996562                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.warmup_cycle       3958369000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks    41.514151                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    89.268254                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.742004                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.001267                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002724                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.992454                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996445                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          308                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2976                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29149                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          300                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2912                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29221                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         13160277                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        13160277                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks        88688                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total        88688                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks        23552                       # number of WritebackClean hits
@@ -734,18 +744,18 @@ system.cpu.l2cache.demand_misses::total        291260                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2570                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       288690                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       291260                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5003275000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5003275000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    198116500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    198116500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17918475000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  17918475000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    198116500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  22921750000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  23119866500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    198116500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  22921750000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  23119866500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5351609000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5351609000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    219318000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    219318000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  30330402000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  30330402000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    219318000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  35682011000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  35901329000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    219318000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  35682011000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  35901329000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks        88688                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total        88688                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks        23552                       # number of WritebackClean accesses(hits+misses)
@@ -774,18 +784,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.360099                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.096482                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.369076                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.360099                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80973.339789                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80973.339789                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85337.743191                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85337.743191                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136255.787313                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136255.787313                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85337.743191                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123599.747134                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 123262.133489                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85337.743191                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123599.747134                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 123262.133489                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -816,18 +826,18 @@ system.cpu.l2cache.demand_mshr_misses::total       291230
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2566                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       288664                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       291230                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4342365000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4342365000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    172194500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    172194500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15690918500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15690918500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    172194500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20033283500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20205478000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    172194500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20033283500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20205478000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4690699000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4690699000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    193386000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    193386000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  28102659500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  28102659500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    193386000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  32793358500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  32986744500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    193386000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  32793358500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  32986744500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953391                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953391                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.096332                       # mshr miss rate for ReadCleanReq accesses
@@ -840,25 +850,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.360062
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.096332                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.369043                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.360062                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70973.339789                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70973.339789                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75364.770070                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75364.770070                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126262.662138                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126262.662138                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75364.770070                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113603.908004                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113266.986574                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75364.770070                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113603.908004                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113266.986574                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      1611818                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       803044                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3234                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         2036                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2021                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           15                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp        739510                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       154786                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        24885                       # Transaction distribution
@@ -898,7 +908,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp             225138                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        66098                       # Transaction distribution
 system.membus.trans_dist::CleanEvict           190702                       # Transaction distribution
@@ -921,9 +931,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total              291229                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           917201000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           917205000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1554703000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1553500250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 2ff40d14a..155d03811 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -172,7 +172,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -534,7 +534,7 @@ pipelined=true
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -813,6 +813,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -824,7 +825,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -832,29 +833,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -874,6 +882,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -905,9 +914,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
index 0920df90d..4ad08cdbb 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:20:09
-gem5 executing on e108600-lin, pid 12407
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:55:26
+gem5 executing on e108600-lin, pid 17505
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -650,4 +650,4 @@ info: Increasing stack size by one page.
 2000: 2845746745
 1000: 2068042552
 0: 290958364
-Exiting @ tick 326731324000 because target called exit()
+Exiting @ tick 339012932000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 2975218ad..0a89473ad 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,121 +1,121 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.327896                       # Number of seconds simulated
-sim_ticks                                327895638000                       # Number of ticks simulated
-final_tick                               327895638000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.339013                       # Number of seconds simulated
+sim_ticks                                339012932000                       # Number of ticks simulated
+final_tick                               339012932000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 125299                       # Simulator instruction rate (inst/s)
-host_op_rate                                   154259                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               64130088                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277300                       # Number of bytes of host memory used
-host_seconds                                  5112.98                       # Real time elapsed on the host
+host_inst_rate                                 140345                       # Simulator instruction rate (inst/s)
+host_op_rate                                   172783                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               74266222                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 275384                       # Number of bytes of host memory used
+host_seconds                                  4564.83                       # Real time elapsed on the host
 sim_insts                                   640649299                       # Number of instructions simulated
 sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            266368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          48003200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     12980224                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             61249792                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       266368                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          266368                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4244096                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4244096                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               4162                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             750050                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       202816                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                957028                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66314                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66314                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               812356                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            146397800                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     39586449                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               186796605                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          812356                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             812356                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          12943435                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               12943435                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          12943435                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              812356                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           146397800                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     39586449                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              199740040                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        957029                       # Number of read requests accepted
-system.physmem.writeReqs                        66314                       # Number of write requests accepted
-system.physmem.readBursts                      957029                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      66314                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 61231232                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     18624                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4237440                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  61249856                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4244096                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      291                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      72                       # Number of DRAM write bursts merged with an existing one
+system.physmem.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            269632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          48043328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     12965504                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             61278464                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       269632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          269632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4245696                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4245696                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               4213                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             750677                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       202586                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                957476                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66339                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66339                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               795344                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            141715325                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     38244866                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               180755535                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          795344                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             795344                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          12523699                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               12523699                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          12523699                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              795344                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           141715325                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     38244866                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              193279235                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        957477                       # Number of read requests accepted
+system.physmem.writeReqs                        66339                       # Number of write requests accepted
+system.physmem.readBursts                      957477                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66339                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 61258752                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19776                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4240576                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  61278528                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4245696                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      309                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      54                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               19913                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               19609                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              657177                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               20974                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               19738                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               20841                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               19544                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               20056                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               19527                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               20071                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              19467                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              19786                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              19618                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              21115                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              19501                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              19801                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4241                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4104                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4141                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4151                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4245                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               19910                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               19533                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              657271                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               20982                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               19710                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               21143                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               19634                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               20055                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               19495                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               20079                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              19428                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              19728                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              19649                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              21208                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              19490                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              19853                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4286                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4105                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4145                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4153                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4249                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4230                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4095                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4094                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4151                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4149                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    327895627500                       # Total gap between requests
+system.physmem.totGap                    339012921500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  957029                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  957477                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66314                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    765529                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    120932                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     14410                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      6616                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6427                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7705                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      8957                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      9890                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      6812                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      3724                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2470                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1588                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1057                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      621                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66339                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    764538                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    120546                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     15621                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      6697                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6433                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7720                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      9109                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     10145                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      6841                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      3643                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2525                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1571                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1107                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      672                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -149,175 +149,187 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                      852                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2097                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     2585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3077                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     3558                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4078                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4529                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5085                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5966                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6331                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5957                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4447                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      537                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      585                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                      883                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     1456                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2089                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     2622                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3068                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     3545                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4483                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4939                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5348                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4797                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       194181                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      337.148207                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     191.280987                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     364.158297                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          64676     33.31%     33.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        60636     31.23%     64.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        15729      8.10%     72.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3217      1.66%     74.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3574      1.84%     76.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2317      1.19%     77.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         2364      1.22%     78.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        21831     11.24%     89.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19837     10.22%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         194181                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3990                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       177.226065                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.842577                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     1813.556545                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095           3969     99.47%     99.47% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-8191            9      0.23%     99.70% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-12287            4      0.10%     99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-16383            2      0.05%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16384-20479            1      0.03%     99.87% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::24576-28671            1      0.03%     99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::28672-32767            2      0.05%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::36864-40959            1      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::86016-90111            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3990                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3990                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.593985                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.513577                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.886226                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3332     83.51%     83.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  5      0.13%     83.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                452     11.33%     94.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 50      1.25%     96.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 19      0.48%     96.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 17      0.43%     97.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 10      0.25%     97.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 19      0.48%     97.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 12      0.30%     98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 15      0.38%     98.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 16      0.40%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 15      0.38%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  9      0.23%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  5      0.13%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  4      0.10%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  3      0.08%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  1      0.03%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  1      0.03%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  3      0.08%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  1      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  1      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3990                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    12587538724                       # Total ticks spent queuing
-system.physmem.totMemAccLat               30526376224                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4783690000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13156.72                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples       195212                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      335.517735                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     192.597798                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     355.506182                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          64341     32.96%     32.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        60661     31.07%     64.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        15753      8.07%     72.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3211      1.64%     73.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3578      1.83%     75.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2458      1.26%     76.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2478      1.27%     78.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        34211     17.53%     95.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8521      4.36%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         195212                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          3994                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean       204.692539                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       35.349556                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2360.542955                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095           3971     99.42%     99.42% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-8191           10      0.25%     99.67% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-12287            5      0.13%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-16383            1      0.03%     99.82% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16384-20479            1      0.03%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24576-28671            1      0.03%     99.87% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::28672-32767            1      0.03%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::36864-40959            1      0.03%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-49151            1      0.03%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::69632-73727            1      0.03%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::98304-102399            1      0.03%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            3994                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          3994                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.589634                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.506417                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.926291                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3368     84.33%     84.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 17      0.43%     84.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                396      9.91%     94.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 46      1.15%     95.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 24      0.60%     96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 17      0.43%     96.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 21      0.53%     97.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 18      0.45%     97.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 15      0.38%     98.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 17      0.43%     98.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 13      0.33%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 10      0.25%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  7      0.18%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  8      0.20%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  8      0.20%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  4      0.10%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  1      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.03%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  1      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  1      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  1      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            3994                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    27473404757                       # Total ticks spent queuing
+system.physmem.totMemAccLat               45420304757                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4785840000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       28702.80                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31906.72                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         186.74                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          12.92                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      186.80                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       12.94                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47452.80                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         180.70                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          12.51                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      180.76                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       12.52                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.56                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.46                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           1.51                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.41                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.10                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.87                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     805843                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     22921                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.23                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  34.60                       # Row buffer hit rate for writes
-system.physmem.avgGap                       320416.15                       # Average gap between requests
-system.physmem.pageHitRate                      81.01                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  934317720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  509796375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6223237800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                216334800                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            21416478720                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           220944760020                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             2925699000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             253170624435                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              772.109253                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE     3595093339                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     10949120000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    313351421161                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  533690640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  291200250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1239209400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212706000                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            21416478720                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            88116969465                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           119441319000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             231251573475                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              705.261391                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   198129163855                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     10949120000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    118816573145                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               174659739                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         119113225                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           4015668                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             96720974                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                67755362                       # Number of BTB hits
+system.physmem.avgWrQLen                        24.53                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     805066                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     23137                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   84.11                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  34.91                       # Row buffer hit rate for writes
+system.physmem.avgGap                       331126.81                       # Average gap between requests
+system.physmem.pageHitRate                      80.92                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  894020820                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  475164360                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5699412180                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                174541140                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           27331811520.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            14462317590                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              674820000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy      138340924320                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy         704060640                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       673701120.000000                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             189477322380                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              558.908824                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           305437641889                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      528629764                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     11569144000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF      223118500                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN   1833570381                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     21477516347                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 303380953008                       # Time in different power states
+system.physmem_1.actEnergy                  499878540                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  265665180                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1134760200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                171330840                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           25420895760.000004                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             7011060990                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             1362065280                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       70491607590                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       31027049280                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        25487678070                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             162872491950                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              480.431501                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           320089357075                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     2604072271                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     10809446000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    84703185250                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  80799625521                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      5510033904                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 154586569054                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               174656775                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         119110803                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           4015685                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             96721345                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                67754534                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.052398                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18785155                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1299597                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups        16716286                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits           16701799                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses            14487                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted      1279501                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             70.051274                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18785121                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1299599                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        16716580                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           16702336                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            14244                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted      1279516                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -347,7 +359,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -377,7 +389,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -407,7 +419,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -438,85 +450,85 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    327895638000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        655791277                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    339012932000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        678025865                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           34353189                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      824276690                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   174659739                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          103242316                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     616975428                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 8068049                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 2182                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles           34354212                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      824273790                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   174656775                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          103241991                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     639159762                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 8068079                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 2457                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            17                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles         3170                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 247740649                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 12515                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          655368010                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.551156                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.253828                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         3206                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 247740942                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 12520                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          677553693                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.500365                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.263651                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                193301276     29.50%     29.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                148337850     22.63%     52.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72946568     11.13%     63.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                240782316     36.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                215486043     31.80%     31.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                148340760     21.89%     53.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72943473     10.77%     64.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                240783417     35.54%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            655368010                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.266334                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.256919                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 75112130                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             236493276                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 277761287                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              61980307                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4021010                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             20809608                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 13112                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              924575224                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              11804312                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4021010                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                118055519                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               135785787                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         212608                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 294557237                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             102735849                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              906541412                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6891100                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              27959034                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2218150                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               49337765                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 468731                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           980926815                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            4318009248                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1001835221                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          34457086                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            677553693                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.257596                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.215697                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 75112537                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             258679606                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 277758053                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              61982472                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4021025                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             20810112                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 13117                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              924576668                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              11804380                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4021025                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                118056358                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               157938220                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         213059                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 294555904                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             102769127                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              906541450                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6890856                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              27990855                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2220094                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               49338949                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 500517                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           980921468                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4318014727                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1001837715                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          34457090                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                106148585                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               6844                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           6835                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 138814111                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            271882035                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           160585921                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           6159068                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         12159693                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  899827224                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               12580                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 860029296                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           9216848                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       111114846                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    244387313                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            426                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     655368010                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.312285                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.094624                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                106143238                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               6855                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           6838                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 138815476                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            271882151                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           160587217                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           6164479                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         12153288                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  899827421                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               12582                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 860030622                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           9216880                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       111115045                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    244388609                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            428                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     677553693                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.269317                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.101593                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           192710599     29.40%     29.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           182406257     27.83%     57.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           175554116     26.79%     84.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            92275656     14.08%     98.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12419071      1.89%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           214894884     31.72%     31.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           182407403     26.92%     58.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           175555467     25.91%     84.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            92273782     13.62%     98.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12419846      1.83%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                2311      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -524,9 +536,9 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       655368010                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       677553693                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                66605310     24.62%     24.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                66603323     24.62%     24.62% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                  18142      0.01%     24.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     24.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     24.63% # attempts to use FU when none available
@@ -555,13 +567,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     24.87% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     24.87% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     24.87% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     24.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              134121363     49.58%     74.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              69112589     25.55%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              134116736     49.58%     74.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              69116750     25.55%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             413090005     48.03%     48.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              5187656      0.60%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             413090046     48.03%     48.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              5187659      0.60%     48.64% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     48.64% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     48.64% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     48.64% # Type of FU issued
@@ -583,88 +595,88 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     48.64% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd          637528      0.07%     48.71% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     48.71% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp         3187674      0.37%     49.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         2550150      0.30%     49.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         2550149      0.30%     49.38% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     49.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       11478194      1.33%     50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       11478193      1.33%     50.71% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     50.71% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.71% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     50.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            266665504     31.01%     81.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           157232585     18.28%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            266665907     31.01%     81.72% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           157233466     18.28%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              860029296                       # Type of FU issued
-system.cpu.iq.rate                           1.311438                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   270494293                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.314518                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2597595667                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         980331886                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    820082893                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            57542076                       # Number of floating instruction queue reads
+system.cpu.iq.FU_type_0::total              860030622                       # Type of FU issued
+system.cpu.iq.rate                           1.268433                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   270491840                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.314514                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2619781164                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         980332291                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    820083655                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            57542493                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes           30641581                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     24878673                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1098503163                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                32020426                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         13986768                       # Number of loads that had data forwarded from stores
+system.cpu.iq.fp_inst_queue_wakeup_accesses     24878671                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1098501615                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                32020847                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         13986301                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     19641097                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses          121                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18820                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     31605425                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     19641213                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          120                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18827                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     31606721                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      1918936                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         17201                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      1918912                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         17820                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4021010                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                10590461                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                  6281                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           899849934                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                4021025                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                10591534                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                  6199                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           899849877                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             271882035                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            160585921                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               6840                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    959                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  3423                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18820                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3295129                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3290187                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              6585316                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             850173752                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             263373804                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           9855544                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             271882151                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            160587217                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               6842                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    967                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  3331                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18827                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3295145                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3289956                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              6585101                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             850175089                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             263374398                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           9855533                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         10130                       # number of nop insts executed
-system.cpu.iew.exec_refs                    416063188                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                143381327                       # Number of branches executed
-system.cpu.iew.exec_stores                  152689384                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.296409                       # Inst execution rate
-system.cpu.iew.wb_sent                      846297655                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     844961566                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 487343298                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 808106626                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.288461                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.603068                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       103169122                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                          9874                       # number of nop insts executed
+system.cpu.iew.exec_refs                    416064413                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                143381564                       # Number of branches executed
+system.cpu.iew.exec_stores                  152690015                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.253898                       # Inst execution rate
+system.cpu.iew.wb_sent                      846298256                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     844962326                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 487342605                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 808106527                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.246210                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.603067                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       103169288                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           4002654                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    640787345                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.230876                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.070419                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           4002671                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    662973012                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.189687                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.047483                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    350447626     54.69%     54.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    137241088     21.42%     76.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     51341072      8.01%     84.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     28220230      4.40%     88.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     14380949      2.24%     90.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14774505      2.31%     93.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      7871971      1.23%     94.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      6561231      1.02%     95.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     29948673      4.67%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    372633677     56.21%     56.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    137240232     20.70%     76.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     51341106      7.74%     84.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     28220443      4.26%     88.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     14381462      2.17%     91.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14774618      2.23%     93.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7871678      1.19%     94.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      6561077      0.99%     95.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     29948719      4.52%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    640787345                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    662973012                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            640654411                       # Number of instructions committed
 system.cpu.commit.committedOps              788730070                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -710,82 +722,82 @@ system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         788730070                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              29948673                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1502729113                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1798382436                       # The number of ROB writes
-system.cpu.timesIdled                           10485                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          423267                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              29948719                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1524914900                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1798382781                       # The number of ROB writes
+system.cpu.timesIdled                           10519                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          472172                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   640649299                       # Number of Instructions Simulated
 system.cpu.committedOps                     788724958                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.023635                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.023635                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.976910                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.976910                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                868461212                       # number of integer regfile reads
-system.cpu.int_regfile_writes               500699124                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  30616064                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 22959493                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                3322386264                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                369207629                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               606832888                       # number of misc regfile reads
+system.cpu.cpi                               1.058342                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.058342                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.944874                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.944874                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                868463326                       # number of integer regfile reads
+system.cpu.int_regfile_writes               500698648                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  30616063                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 22959490                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                3322389826                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                369207773                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               606833337                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           2756458                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.912011                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           371050492                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2756970                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            134.586336                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         274880000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.912011                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999828                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999828                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           2756453                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.911144                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           371050846                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2756965                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            134.586709                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         285699000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.911144                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999826                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999826                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          249                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          167                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          173                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         751746846                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        751746846                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    243126867                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       243126867                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    127907624                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      127907624                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         751747893                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        751747893                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    243127355                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       243127355                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    127907428                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      127907428                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data         3157                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total          3157                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         5738                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         5738                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     371034491                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        371034491                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    371037648                       # number of overall hits
-system.cpu.dcache.overall_hits::total       371037648                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2401310                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2401310                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1043853                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1043853                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     371034783                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        371034783                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    371037940                       # number of overall hits
+system.cpu.dcache.overall_hits::total       371037940                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2401348                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2401348                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1044049                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1044049                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data          647                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total          647                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      3445163                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3445163                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3445810                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3445810                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  69278020000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  69278020000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9882341350                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9882341350                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       168500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       168500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  79160361350                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  79160361350                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  79160361350                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  79160361350                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    245528177                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    245528177                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      3445397                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3445397                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3446044                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3446044                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  80462385500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  80462385500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10017236850                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10017236850                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       140000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       140000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  90479622350                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  90479622350                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  90479622350                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  90479622350                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    245528703                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    245528703                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data         3804                       # number of SoftPFReq accesses(hits+misses)
@@ -794,469 +806,470 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5741
 system.cpu.dcache.LoadLockedReq_accesses::total         5741                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    374479654                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    374479654                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    374483458                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    374483458                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    374480180                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    374480180                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    374483984                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    374483984                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009780                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.009780                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008095                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.008095                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008096                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.008096                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.170084                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.170084                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000523                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000523                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000348                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000348                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.009200                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.009200                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.009202                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.009202                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28850.094324                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28850.094324                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9467.177227                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  9467.177227                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56166.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56166.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22977.247042                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22977.247042                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22972.932736                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22972.932736                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       322646                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets            4628                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    69.716076                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      2756458                       # number of writebacks
-system.cpu.dcache.writebacks::total           2756458                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       365828                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       365828                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       322833                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       322833                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       688661                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       688661                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       688661                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       688661                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035482                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      2035482                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       721020                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       721020                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33507.174096                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 33507.174096                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9594.604133                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  9594.604133                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        70000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        70000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26261.015015                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26261.015015                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26256.084470                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26256.084470                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           71                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       355259                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets            4691                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs           71                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    75.732040                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks      2756453                       # number of writebacks
+system.cpu.dcache.writebacks::total           2756453                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       365871                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       365871                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       323013                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       323013                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       688884                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       688884                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       688884                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       688884                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035477                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      2035477                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       721036                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       721036                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          642                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total          642                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2756502                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2756502                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2757144                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2757144                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  64102936000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  64102936000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5940509850                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5940509850                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5561000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5561000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  70043445850                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  70043445850                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  70049006850                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  70049006850                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      2756513                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2756513                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2757155                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2757155                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75218139500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  75218139500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5959023850                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5959023850                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5957500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5957500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  81177163350                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  81177163350                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  81183120850                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  81183120850                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.008290                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.008290                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005591                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005591                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005592                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005592                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.168770                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.168770                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.007361                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.007361                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.007363                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.007363                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31492.755033                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31492.755033                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8239.036157                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8239.036157                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8661.993769                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8661.993769                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25410.264839                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25410.264839                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25406.365010                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25406.365010                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36953.568869                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36953.568869                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8264.530273                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8264.530273                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  9279.595016                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  9279.595016                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29449.222024                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29449.222024                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29444.525553                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29444.525553                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements           1979522                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.874726                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           245757404                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           510.550232                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           245757624                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs           1980032                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            124.117895                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         264413500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.874726                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997802                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997802                       # Average percentage of cache occupancy
+system.cpu.icache.tags.avg_refs            124.118006                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         275112500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.550232                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997168                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997168                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          111                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          113                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          335                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          332                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         497461440                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        497461440                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    245757408                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       245757408                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     245757408                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        245757408                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    245757408                       # number of overall hits
-system.cpu.icache.overall_hits::total       245757408                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1983209                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1983209                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1983209                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1983209                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1983209                       # number of overall misses
-system.cpu.icache.overall_misses::total       1983209                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  16177953926                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  16177953926                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  16177953926                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  16177953926                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  16177953926                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  16177953926                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    247740617                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    247740617                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    247740617                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    247740617                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    247740617                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    247740617                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         497462038                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        497462038                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    245757684                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       245757684                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     245757684                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        245757684                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    245757684                       # number of overall hits
+system.cpu.icache.overall_hits::total       245757684                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1983224                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1983224                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1983224                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1983224                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1983224                       # number of overall misses
+system.cpu.icache.overall_misses::total       1983224                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16215368926                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16215368926                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16215368926                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16215368926                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16215368926                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16215368926                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    247740908                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    247740908                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    247740908                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    247740908                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    247740908                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    247740908                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008005                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.008005                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.008005                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.008005                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.008005                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.008005                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8157.462943                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8157.462943                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8157.462943                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8157.462943                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8157.462943                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8157.462943                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        75964                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          122                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              2856                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    26.598039                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    24.400000                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8176.266991                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  8176.266991                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8176.266991                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  8176.266991                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8176.266991                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8176.266991                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        83168                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          761                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              2904                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               7                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    28.639118                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets   108.714286                       # average number of cycles each access was blocked
 system.cpu.icache.writebacks::writebacks      1979522                       # number of writebacks
 system.cpu.icache.writebacks::total           1979522                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3001                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3001                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3001                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3001                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3001                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3001                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1980208                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1980208                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1980208                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1980208                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1980208                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1980208                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  15149087440                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  15149087440                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  15149087440                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  15149087440                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  15149087440                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  15149087440                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3000                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3000                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3000                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3000                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3000                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3000                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1980224                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1980224                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1980224                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1980224                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1980224                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1980224                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  15180539440                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  15180539440                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  15180539440                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  15180539440                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  15180539440                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  15180539440                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.007993                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.007993                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.007993                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.007993                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.007993                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.007993                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7650.250600                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7650.250600                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7650.250600                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  7650.250600                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7650.250600                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  7650.250600                       # average overall mshr miss latency
-system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.prefetcher.num_hwpf_issued      1350340                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      1355050                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         4121                       # number of redundant prefetches already in prefetch queue
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7666.071838                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7666.071838                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7666.071838                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  7666.071838                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7666.071838                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  7666.071838                       # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.prefetcher.num_hwpf_issued      1350153                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      1355017                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         4256                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4790102                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           297234                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16098.063865                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3815891                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           313429                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.174658                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage      4789879                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           297323                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        16097.800949                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3937547                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           313525                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.558957                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15670.505298                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   427.558566                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.956452                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.026096                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.982548                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          418                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15777                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 15677.943381                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   419.857568                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.956906                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.025626                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.982532                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          424                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15778                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1            6                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           61                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3          259                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4           92                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          412                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1577                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3842                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         9849                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.025513                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962952                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        145585225                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       145585225                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       735545                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       735545                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      3357840                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      3357840                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       718742                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       718742                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1975871                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1975871                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1286733                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1286733                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1975871                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2005475                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         3981346                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1975871                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2005475                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        3981346                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          174                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          174                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         2104                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         2104                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         4164                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         4164                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       749391                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       749391                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         4164                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       751495                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        755659                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         4164                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       751495                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       755659                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    179065000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    179065000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    319741500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    319741500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  52681851500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  52681851500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    319741500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  52860916500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  53180658000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    319741500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  52860916500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  53180658000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       735545                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       735545                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      3357840                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      3357840                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          174                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          174                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           63                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3          273                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4           82                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          408                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1549                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3670                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10056                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.025879                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.963013                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        145579085                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       145579085                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks       735952                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       735952                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      3357075                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      3357075                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       718660                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       718660                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1975820                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1975820                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1285803                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1285803                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      1975820                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2004463                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         3980283                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      1975820                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2004463                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        3980283                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          190                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          190                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         2186                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         2186                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         4215                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         4215                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       750316                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       750316                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         4215                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       752502                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        756717                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         4215                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       752502                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       756717                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    197785000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    197785000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    351484000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    351484000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  63803558500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  63803558500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    351484000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  64001343500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  64352827500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    351484000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  64001343500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  64352827500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       735952                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       735952                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      3357075                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      3357075                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          190                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          190                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       720846                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       720846                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1980035                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::total      1980035                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2036124                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      2036124                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2036119                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      2036119                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst      1980035                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2756970                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      4737005                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2756965                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      4737000                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst      1980035                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2756970                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      4737005                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2756965                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      4737000                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002919                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.002919                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.002103                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.002103                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.368048                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.368048                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.002103                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.272580                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.159523                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.002103                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.272580                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.159523                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85106.939163                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85106.939163                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76787.103746                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76787.103746                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70299.551903                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70299.551903                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76787.103746                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70341.008922                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70376.529625                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76787.103746                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70341.008922                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70376.529625                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003033                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.003033                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.002129                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.002129                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.368503                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.368503                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.002129                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.272946                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.159746                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.002129                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.272946                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.159746                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90478.042086                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90478.042086                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83388.849348                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83388.849348                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85035.583008                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85035.583008                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83388.849348                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85051.393219                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 85042.132660                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83388.849348                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85051.393219                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 85042.132660                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.unused_prefetches             3678                       # number of HardPF blocks evicted w/o reference
-system.cpu.l2cache.writebacks::writebacks        66314                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66314                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          742                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total          742                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.unused_prefetches             3567                       # number of HardPF blocks evicted w/o reference
+system.cpu.l2cache.writebacks::writebacks        66339                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66339                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          799                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total          799                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          703                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          703                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         1026                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total         1026                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         1445                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         1446                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         1825                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         1826                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         1445                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         1446                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       202914                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       202914                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          174                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          174                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1362                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1362                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         4163                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         4163                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       748688                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       748688                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         4163                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       750050                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       754213                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         4163                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       750050                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       202914                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       957127                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  16536801285                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  16536801285                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      2630000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      2630000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    133214500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    133214500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    294714000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    294714000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  48154340500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  48154340500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    294714000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  48287555000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  48582269000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    294714000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  48287555000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  16536801285                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  65119070285                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_hits::cpu.data         1825                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         1826                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       202675                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       202675                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          190                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          190                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1387                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1387                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         4214                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         4214                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       749290                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       749290                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         4214                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       750677                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       754891                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         4214                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       750677                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       202675                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       957566                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  20310287954                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  20310287954                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      2871000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      2871000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    146425000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    146425000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    326144500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    326144500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  59240775500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  59240775500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    326144500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  59387200500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  59713345000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    326144500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  59387200500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  20310287954                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  80023632954                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001889                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001889                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.002102                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.002102                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.367703                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.367703                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.002102                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.272056                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.159217                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.002102                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.272056                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001924                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001924                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.002128                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.002128                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.367999                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.367999                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.002128                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.272284                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.159361                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.002128                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.272284                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.202053                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 81496.600949                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15114.942529                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15114.942529                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97808.002937                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97808.002937                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70793.658419                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70793.658419                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64318.301482                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64318.301482                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70793.658419                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64379.114726                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64414.520832                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70793.658419                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64379.114726                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68035.976715                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      9473332                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      4736180                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests       642769                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops           98                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops           97                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.202146                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100211.116092                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15110.526316                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15110.526316                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 105569.574621                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 105569.574621                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77395.467489                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77395.467489                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79062.546544                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79062.546544                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.467489                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79111.522666                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79101.943194                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.467489                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79111.522666                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83569.835347                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      9473354                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      4736191                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests       643138                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops           89                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops           88                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp       4016330                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       801859                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      4000435                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       230920                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       258553                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          174                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          174                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp       4016341                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       802291                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      4000023                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       230984                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       255300                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          190                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          190                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       720846                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       720846                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1980208                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      2036124                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5939763                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8270746                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          14210509                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1980224                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      2036119                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5939779                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8270763                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          14210542                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    253411520                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    352859392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          606270912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      555960                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               4255168                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      5293139                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.121491                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.326697                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    352858752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          606270272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      552812                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               4257792                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      5290002                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.121634                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.326863                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            4650072     87.85%     87.85% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             643066     12.15%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            4646559     87.84%     87.84% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             643442     12.16%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5293139                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     9472646000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2970310996                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5290002                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     9472652000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    2970335495                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4135552978                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests       1254437                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       940010                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.respLayer1.occupancy    4135554975                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
+system.membus.snoop_filter.tot_requests       1254990                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       940467                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp             955666                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        66314                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           230920                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              174                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1362                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1362                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        955667                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2211465                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                2211465                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     65493888                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                65493888                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED 339012932000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp             956088                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        66339                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           230984                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              190                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1387                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1387                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        956090                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2212465                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                2212465                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     65524096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                65524096                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            957203                       # Request fanout histogram
+system.membus.snoop_fanout::samples            957667                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  957203    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  957667    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              957203                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          1755655982                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              957667                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          1758860478                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         5035261795                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         5031633569                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
index 4117f093b..46094eb94 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
@@ -149,7 +149,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -583,7 +583,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -643,7 +643,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -760,6 +760,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -779,29 +780,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -821,6 +829,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -852,9 +861,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout
index dcc24233a..a86af0918 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:29
-gem5 executing on e108600-lin, pid 4306
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:45
+gem5 executing on e108600-lin, pid 28063
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 60000593000 because target called exit()
+Exiting @ tick 61709224000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index 58628a22b..4a990b700 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,106 +1,106 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.060094                       # Number of seconds simulated
-sim_ticks                                 60093931000                       # Number of ticks simulated
-final_tick                                60093931000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.061709                       # Number of seconds simulated
+sim_ticks                                 61709224000                       # Number of ticks simulated
+final_tick                                61709224000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 276952                       # Simulator instruction rate (inst/s)
-host_op_rate                                   276952                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              188189933                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 264524                       # Number of bytes of host memory used
-host_seconds                                   319.33                       # Real time elapsed on the host
+host_inst_rate                                 242211                       # Simulator instruction rate (inst/s)
+host_op_rate                                   242211                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              169006859                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262168                       # Number of bytes of host memory used
+host_seconds                                   365.13                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  60093931000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            438272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10168832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10607104                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       438272                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          438272                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7376000                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7376000                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6848                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158888                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                165736                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115250                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115250                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              7293116                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            169215623                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               176508739                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         7293116                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            7293116                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         122741180                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              122741180                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         122741180                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             7293116                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           169215623                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              299249919                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        165736                       # Number of read requests accepted
-system.physmem.writeReqs                       115250                       # Number of write requests accepted
-system.physmem.readBursts                      165736                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     115250                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10606464                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       640                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7374720                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10607104                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7376000                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       10                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.pwrStateResidencyTicks::UNDEFINED  61709224000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            438336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10169024                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10607360                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       438336                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          438336                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7376064                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7376064                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6849                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158891                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                165740                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115251                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115251                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              7103249                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            164789368                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               171892617                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         7103249                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            7103249                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         119529359                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              119529359                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         119529359                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             7103249                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           164789368                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              291421976                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        165740                       # Number of read requests accepted
+system.physmem.writeReqs                       115251                       # Number of write requests accepted
+system.physmem.readBursts                      165740                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     115251                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10606656                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       704                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7374400                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10607360                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7376064                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       11                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               10345                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10388                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10387                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               10224                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10067                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10068                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               10353                       # Per bank write bursts
 system.physmem.perBankRdBursts::5               10360                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                9794                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10229                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10230                       # Per bank write bursts
 system.physmem.perBankRdBursts::8               10568                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               10626                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10567                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10568                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              10241                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10307                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10590                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10306                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10592                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              10494                       # Per bank write bursts
 system.physmem.perBankRdBursts::15              10573                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7166                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7280                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7281                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7303                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7011                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7144                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7304                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7012                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7145                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7305                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6890                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7170                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7244                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7072                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7215                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7164                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7246                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7071                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7213                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               7126                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               7072                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7397                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7353                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7351                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7483                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     60093907500                       # Total gap between requests
+system.physmem.totGap                     61709200500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  165736                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  165740                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 115250                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    164444                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1265                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 115251                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    163346                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2365                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      503                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6946                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      469                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6962                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                     7138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7141                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
@@ -194,124 +194,134 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        47112                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      381.637629                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     228.425229                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     356.616158                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14360     30.48%     30.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9586     20.35%     50.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5012     10.64%     61.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3327      7.06%     68.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2470      5.24%     73.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1960      4.16%     77.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1618      3.43%     81.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1472      3.12%     84.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7307     15.51%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          47112                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7135                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.226489                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       17.911576                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      310.890099                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           7133     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        47213                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      380.822570                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     228.196479                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     355.752308                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14428     30.56%     30.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         9567     20.26%     50.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5069     10.74%     61.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3353      7.10%     68.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2454      5.20%     73.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2040      4.32%     78.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1589      3.37%     81.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1422      3.01%     84.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7291     15.44%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          47213                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7138                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.216307                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       17.901212                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      310.822959                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           7136     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::25600-26623            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7135                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7135                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.149965                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.141117                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.557028                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6628     92.89%     92.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 11      0.15%     93.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                441      6.18%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 47      0.66%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  7      0.10%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7135                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1892978500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5000341000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    828630000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11422.34                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7138                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7138                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.142477                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.134126                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.540383                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6653     93.21%     93.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 14      0.20%     93.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                420      5.88%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 44      0.62%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  4      0.06%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  3      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7138                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3617300750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                6724719500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    828645000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       21826.60                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30172.34                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         176.50                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         122.72                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      176.51                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      122.74                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40576.60                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         171.88                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         119.50                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      171.89                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      119.53                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.34                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.38                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.96                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.81                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     144145                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     89685                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   86.98                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.82                       # Row buffer hit rate for writes
-system.physmem.avgGap                       213867.98                       # Average gap between requests
-system.physmem.pageHitRate                      83.22                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  171128160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   93373500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 637486200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                370921680                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3924557520                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            12045269070                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            25486025250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              42728761380                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              711.117850                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    42256937250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2006420000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     15823407750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  184781520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  100823250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 654677400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                375431760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3924557520                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            12738285900                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            24878115750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              42856673100                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              713.246634                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    41240527500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2006420000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     16840206000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  60093931000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                14696108                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9501028                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            386035                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             10214286                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6368013                       # Number of BTB hits
+system.physmem.busUtil                           2.28                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.34                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.93                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.15                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144262                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     89468                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.05                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  77.63                       # Row buffer hit rate for writes
+system.physmem.avgGap                       219612.73                       # Average gap between requests
+system.physmem.pageHitRate                      83.18                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  162377880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   86290710                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 583773540                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                298928520                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           2622054240.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2778043200                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              161720640                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy        5591253690                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        3285210240                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy         8699758440                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              24270201780                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              393.299410                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime            55193955500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      247892750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1114164000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    34377330500                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN   8555206500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      5153163500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  12261466750                       # Time in different power states
+system.physmem_1.actEnergy                  174801480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   92882625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 599531520                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                302545980                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           2751743280.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2889138480                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              174840000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy        5978432460                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        3387317760                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy         8384762130                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              24736693185                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              400.858918                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime            54916270500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      273467750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1169204000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    32984792500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN   8821175750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      5350059500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  13110524500                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED  61709224000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                14696527                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9501310                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            386077                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             10213333                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6368117                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             62.344181                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1712199                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              84611                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups           37560                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits              31792                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses             5768                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted         7597                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             62.351017                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1712242                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              84707                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           37535                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              31848                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             5687                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted         7575                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20579333                       # DTB read hits
-system.cpu.dtb.read_misses                      95423                       # DTB read misses
+system.cpu.dtb.read_hits                     20579387                       # DTB read hits
+system.cpu.dtb.read_misses                      95377                       # DTB read misses
 system.cpu.dtb.read_acv                            10                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20674756                       # DTB read accesses
-system.cpu.dtb.write_hits                    14666035                       # DTB write hits
+system.cpu.dtb.read_accesses                 20674764                       # DTB read accesses
+system.cpu.dtb.write_hits                    14666029                       # DTB write hits
 system.cpu.dtb.write_misses                      8840                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14674875                       # DTB write accesses
-system.cpu.dtb.data_hits                     35245368                       # DTB hits
-system.cpu.dtb.data_misses                     104263                       # DTB misses
+system.cpu.dtb.write_accesses                14674869                       # DTB write accesses
+system.cpu.dtb.data_hits                     35245416                       # DTB hits
+system.cpu.dtb.data_misses                     104217                       # DTB misses
 system.cpu.dtb.data_acv                            10                       # DTB access violations
-system.cpu.dtb.data_accesses                 35349631                       # DTB accesses
-system.cpu.itb.fetch_hits                    25649355                       # ITB hits
-system.cpu.itb.fetch_misses                      5175                       # ITB misses
+system.cpu.dtb.data_accesses                 35349633                       # DTB accesses
+system.cpu.itb.fetch_hits                    25650137                       # ITB hits
+system.cpu.itb.fetch_misses                      5179                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                25654530                       # ITB accesses
+system.cpu.itb.fetch_accesses                25655316                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -325,16 +335,16 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     60093931000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        120187862                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     61709224000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        123418448                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    88438073                       # Number of instructions committed
 system.cpu.committedOps                      88438073                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1085816                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1086074                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.359006                       # CPI: cycles per instruction
-system.cpu.ipc                               0.735832                       # IPC: instructions per cycle
+system.cpu.cpi                               1.395535                       # CPI: cycles per instruction
+system.cpu.ipc                               0.716571                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass             8748916      9.89%      9.89% # Class of committed instruction
 system.cpu.op_class_0::IntAlu                44394799     50.20%     60.09% # Class of committed instruction
 system.cpu.op_class_0::IntMult                  41101      0.05%     60.14% # Class of committed instruction
@@ -370,106 +380,106 @@ system.cpu.op_class_0::MemWrite              14620629     16.53%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                 88438073                       # Class of committed instruction
-system.cpu.tickCycles                        91997493                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        28190369                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  60093931000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements            200806                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.595144                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34648172                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            204902                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            169.096309                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         696470500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.595144                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993798                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993798                       # Average percentage of cache occupancy
+system.cpu.tickCycles                        92007988                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        31410460                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  61709224000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements            200809                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4069.967962                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34647996                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            204905                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            169.092975                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         742257500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4069.967962                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993645                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993645                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          646                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3399                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          592                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3460                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          70184522                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         70184522                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  60093931000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     20314904                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20314904                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     14333268                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       14333268                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      34648172                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34648172                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34648172                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34648172                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        61529                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         61529                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       280109                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       280109                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       341638                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         341638                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       341638                       # number of overall misses
-system.cpu.dcache.overall_misses::total        341638                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   2787384000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   2787384000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21745232000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21745232000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  24532616000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  24532616000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  24532616000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  24532616000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20376433                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20376433                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          70184119                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70184119                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  61709224000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     20314695                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20314695                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     14333301                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       14333301                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      34647996                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34647996                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34647996                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34647996                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        61535                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         61535                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       280076                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       280076                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       341611                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         341611                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       341611                       # number of overall misses
+system.cpu.dcache.overall_misses::total        341611                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   3155082500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   3155082500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  23960624000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  23960624000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  27115706500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  27115706500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  27115706500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  27115706500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20376230                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20376230                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     34989810                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     34989810                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     34989810                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     34989810                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     34989607                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     34989607                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     34989607                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     34989607                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003020                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.003020                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.019168                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.019168                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009764                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009764                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009764                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009764                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45301.955176                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 45301.955176                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77631.322092                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 77631.322092                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 71808.803470                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 71808.803470                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 71808.803470                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 71808.803470                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.019166                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.019166                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009763                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009763                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009763                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009763                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51272.974730                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 51272.974730                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85550.436310                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 85550.436310                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 79375.975891                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 79375.975891                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 79375.975891                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 79375.975891                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       168116                       # number of writebacks
-system.cpu.dcache.writebacks::total            168116                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          194                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          194                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136542                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       136542                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       136736                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       136736                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       136736                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       136736                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61335                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        61335                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       168117                       # number of writebacks
+system.cpu.dcache.writebacks::total            168117                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          197                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          197                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136509                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       136509                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       136706                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       136706                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       136706                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       136706                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61338                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        61338                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143567                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       143567                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       204902                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       204902                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       204902                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       204902                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2722762000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2722762000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10994246500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10994246500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13717008500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  13717008500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13717008500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  13717008500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       204905                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       204905                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       204905                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       204905                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3088657500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3088657500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12182218500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12182218500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15270876000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15270876000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15270876000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15270876000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009824                       # mshr miss rate for WriteReq accesses
@@ -478,338 +488,338 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005856
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005856                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005856                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005856                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44391.652401                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44391.652401                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76579.203438                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76579.203438                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66944.239197                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66944.239197                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66944.239197                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66944.239197                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  60093931000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements            153916                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1931.382130                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25493390                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            155964                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            163.456887                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       42683279500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1931.382130                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.943058                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.943058                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50354.714859                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50354.714859                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84853.890518                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84853.890518                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74526.614773                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74526.614773                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74526.614773                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74526.614773                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  61709224000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements            153962                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1929.475732                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25494126                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            156010                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            163.413409                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       43906590500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1929.475732                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.942127                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.942127                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          163                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          172                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1033                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          801                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1010                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          824                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          51454674                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         51454674                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  60093931000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     25493390                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25493390                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25493390                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25493390                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25493390                       # number of overall hits
-system.cpu.icache.overall_hits::total        25493390                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       155965                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        155965                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       155965                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         155965                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       155965                       # number of overall misses
-system.cpu.icache.overall_misses::total        155965                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2518921000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2518921000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2518921000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2518921000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2518921000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2518921000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25649355                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25649355                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25649355                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25649355                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25649355                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25649355                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006081                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.006081                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.006081                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.006081                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.006081                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.006081                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16150.553009                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16150.553009                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16150.553009                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16150.553009                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16150.553009                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16150.553009                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          51456284                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         51456284                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  61709224000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     25494126                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25494126                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25494126                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25494126                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25494126                       # number of overall hits
+system.cpu.icache.overall_hits::total        25494126                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       156011                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        156011                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       156011                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         156011                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       156011                       # number of overall misses
+system.cpu.icache.overall_misses::total        156011                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2690499000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2690499000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2690499000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2690499000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2690499000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2690499000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25650137                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25650137                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25650137                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25650137                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25650137                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25650137                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006082                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.006082                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.006082                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.006082                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.006082                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.006082                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17245.572428                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 17245.572428                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 17245.572428                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 17245.572428                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 17245.572428                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 17245.572428                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks       153916                       # number of writebacks
-system.cpu.icache.writebacks::total            153916                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       155965                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       155965                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       155965                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       155965                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       155965                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       155965                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2362957000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2362957000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2362957000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2362957000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2362957000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2362957000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006081                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006081                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006081                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006081                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006081                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006081                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15150.559420                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15150.559420                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15150.559420                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15150.559420                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15150.559420                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15150.559420                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  60093931000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           135276                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31728.322423                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             547427                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           168044                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             3.257641                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      13928082000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   716.089195                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1994.899360                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29017.333867                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.021853                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.060879                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.885539                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.968272                       # Average percentage of cache occupancy
+system.cpu.icache.writebacks::writebacks       153962                       # number of writebacks
+system.cpu.icache.writebacks::total            153962                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       156011                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       156011                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       156011                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       156011                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       156011                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       156011                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2534489000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2534489000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2534489000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2534489000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2534489000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2534489000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006082                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006082                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006082                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006082                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006082                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006082                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16245.578837                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16245.578837                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16245.578837                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16245.578837                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16245.578837                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16245.578837                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  61709224000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           135280                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31691.220276                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             547521                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           168048                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             3.258123                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      14447297000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   710.430921                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1986.776331                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 28994.013023                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.021681                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.060632                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.884827                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.967139                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          147                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          968                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9499                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        22051                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          928                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         8856                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        22759                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4          103                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          5892756                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         5892756                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  60093931000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       168116                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       168116                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       153916                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       153916                       # number of WritebackClean hits
+system.cpu.l2cache.tags.tag_accesses          5893544                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         5893544                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  61709224000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks       168117                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       168117                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       153962                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       153962                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data        12659                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total        12659                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       149116                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       149116                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       149161                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       149161                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data        33355                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total        33355                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       149116                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       149161                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data        46014                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          195130                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       149116                       # number of overall hits
+system.cpu.l2cache.demand_hits::total          195175                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       149161                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data        46014                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         195130                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         195175                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data       130908                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       130908                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         6849                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         6849                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27980                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        27980                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         6849                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       158888                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        165737                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         6849                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       158888                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       165737                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10645913500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10645913500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    563137000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    563137000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2280269500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   2280269500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    563137000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  12926183000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  13489320000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    563137000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  12926183000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  13489320000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       168116                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       168116                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       153916                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       153916                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         6850                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         6850                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27983                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        27983                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         6850                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       158891                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        165741                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         6850                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       158891                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       165741                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  11833894500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  11833894500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    734127500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    734127500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2646160500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   2646160500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    734127500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  14480055000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  15214182500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    734127500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  14480055000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  15214182500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       168117                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       168117                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       153962                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       153962                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       143567                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       143567                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       155965                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       155965                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        61335                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        61335                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       155965                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       204902                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       360867                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       155965                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       204902                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       360867                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       156011                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       156011                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        61338                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        61338                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       156011                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       204905                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       360916                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       156011                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       204905                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       360916                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911825                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.911825                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.043914                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.043914                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.456183                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.456183                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.043914                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.775434                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.459274                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.043914                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.775434                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.459274                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81323.628044                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81323.628044                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82221.784202                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82221.784202                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81496.408149                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81496.408149                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82221.784202                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81354.054428                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81389.912934                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82221.784202                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81354.054428                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81389.912934                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.043907                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.043907                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.456210                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.456210                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.043907                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.775437                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.459223                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.043907                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.775437                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.459223                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90398.558530                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90398.558530                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107171.897810                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107171.897810                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94563.145481                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94563.145481                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107171.897810                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91132.002442                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 91794.924008                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107171.897810                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91132.002442                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 91794.924008                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks       115251                       # number of writebacks
-system.cpu.l2cache.writebacks::total           115251                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       115252                       # number of writebacks
+system.cpu.l2cache.writebacks::total           115252                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          117                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          117                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130908                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       130908                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         6849                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         6849                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27980                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27980                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         6849                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158888                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       165737                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         6849                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158888                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       165737                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9336833500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9336833500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    494657000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    494657000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2000469500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2000469500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    494657000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11337303000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11831960000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    494657000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11337303000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  11831960000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         6850                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         6850                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27983                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27983                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         6850                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158891                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       165741                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         6850                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158891                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       165741                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  10524814500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  10524814500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    665637500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    665637500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2366330500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2366330500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    665637500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12891145000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  13556782500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    665637500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12891145000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  13556782500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911825                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911825                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.043914                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.043914                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.456183                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.456183                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.043914                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.775434                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.459274                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.043914                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.775434                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.459274                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71323.628044                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71323.628044                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72223.244269                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72223.244269                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71496.408149                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71496.408149                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72223.244269                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71354.054428                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71389.973271                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72223.244269                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71354.054428                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71389.973271                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests       715589                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       354722                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.043907                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.043907                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.456210                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.456210                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.043907                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.775437                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.459223                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.043907                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.775437                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.459223                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80398.558530                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80398.558530                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97173.357664                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97173.357664                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84563.145481                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84563.145481                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97173.357664                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81132.002442                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81794.984343                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97173.357664                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81132.002442                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81794.984343                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests       715687                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       354771                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         4259                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4259                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  60093931000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp        217299                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       283367                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       153916                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        52715                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  61709224000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp        217348                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       283369                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       153962                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        52720                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       143567                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       143567                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       155965                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        61335                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       465845                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       610610                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1076455                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     19832320                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23873152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           43705472                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      135276                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               7376064                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples       496143                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.008584                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.092253                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       156011                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        61338                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       465983                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       610619                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1076602                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     19838208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23873408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           43711616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      135280                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               7376128                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples       496196                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.008583                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.092248                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             491884     99.14%     99.14% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             491937     99.14%     99.14% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1               4259      0.86%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         496143                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      679826500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         496196                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      679922500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     233946499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     234015499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     307357491                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     307361991                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests        296869                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       131133                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests        296877                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       131137                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  60093931000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp              34828                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       115250                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            15883                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED  61709224000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp              34832                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       115251                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            15886                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            130908                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           130908                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         34828                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       462605                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 462605                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17983104                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17983104                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq         34832                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       462617                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 462617                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17983424                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17983424                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            165736                       # Request fanout histogram
+system.membus.snoop_fanout::samples            165740                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  165736    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  165740    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              165736                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           829286500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          875094750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.5                       # Layer utilization (%)
+system.membus.snoop_fanout::total              165740                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           829256000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          875104000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index d19d770e5..42d282c4a 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -591,7 +591,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -708,6 +708,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -727,29 +728,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -769,6 +777,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -800,9 +809,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
index e4880ad37..03964c60a 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:29
-gem5 executing on e108600-lin, pid 4308
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:44
+gem5 executing on e108600-lin, pid 28054
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 22275010500 because target called exit()
+Exiting @ tick 22819771500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 4f7e5b26f..6ed69f426 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,109 +1,109 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.022294                       # Number of seconds simulated
-sim_ticks                                 22293541500                       # Number of ticks simulated
-final_tick                                22293541500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.022820                       # Number of seconds simulated
+sim_ticks                                 22819771500                       # Number of ticks simulated
+final_tick                                22819771500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 223643                       # Simulator instruction rate (inst/s)
-host_op_rate                                   223643                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               62642230                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265292                       # Number of bytes of host memory used
-host_seconds                                   355.89                       # Real time elapsed on the host
+host_inst_rate                                 186519                       # Simulator instruction rate (inst/s)
+host_op_rate                                   186519                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               53476835                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263708                       # Number of bytes of host memory used
+host_seconds                                   426.72                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            413888                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10171008                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10584896                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       413888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          413888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7372800                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7372800                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6467                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158922                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                165389                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115200                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115200                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             18565377                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            456231147                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               474796523                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        18565377                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           18565377                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         330714615                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              330714615                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         330714615                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            18565377                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           456231147                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              805511139                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        165389                       # Number of read requests accepted
-system.physmem.writeReqs                       115200                       # Number of write requests accepted
-system.physmem.readBursts                      165389                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     115200                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10584320                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       576                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7371392                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10584896                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7372800                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        9                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.pwrStateResidencyTicks::UNDEFINED  22819771500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            414016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10170944                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10584960                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       414016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          414016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7372608                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7372608                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6469                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158921                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                165390                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115197                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115197                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             18142864                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            445707530                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               463850394                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        18142864                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           18142864                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         323079835                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              323079835                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         323079835                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            18142864                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           445707530                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              786930228                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        165390                       # Number of read requests accepted
+system.physmem.writeReqs                       115197                       # Number of write requests accepted
+system.physmem.readBursts                      165390                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     115197                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10584512                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7370752                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10584960                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7372608                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               10310                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10350                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10353                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               10221                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10037                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10036                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               10349                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10325                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10326                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                9802                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10210                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10556                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10619                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10209                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10557                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10617                       # Per bank write bursts
 system.physmem.perBankRdBursts::10              10516                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10224                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10277                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10556                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10223                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10279                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10557                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              10475                       # Per bank write bursts
 system.physmem.perBankRdBursts::15              10553                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7167                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7278                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7277                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7300                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                7008                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7143                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7301                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7142                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7300                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6892                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7161                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7241                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7068                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7158                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7240                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7069                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               7202                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7125                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7121                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               7069                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7390                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               7350                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7483                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     22293510500                       # Total gap between requests
+system.physmem.totGap                     22819740500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  165389                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  165390                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 115200                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     51841                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     42842                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     37971                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     32721                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 115197                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     51469                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     42313                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     37455                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     34126                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        18                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -145,34 +145,34 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      573                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      592                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5795                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7342                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7855                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7431                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7928                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    11020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7854                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7759                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      585                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      604                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4086                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5723                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7623                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7552                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9529                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     9432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7837                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8541                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      945                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
@@ -194,125 +194,136 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        44806                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      400.727760                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     239.628821                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     367.162466                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13215     29.49%     29.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8315     18.56%     48.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5340     11.92%     59.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2750      6.14%     66.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2605      5.81%     71.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1593      3.56%     75.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1654      3.69%     79.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1106      2.47%     81.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8228     18.36%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          44806                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7098                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.298957                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       17.933264                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      317.077516                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           7097     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        44648                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      402.130084                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     240.586732                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     367.720381                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13091     29.32%     29.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8315     18.62%     47.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5360     12.01%     59.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2692      6.03%     65.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2549      5.71%     71.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1575      3.53%     75.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1705      3.82%     79.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1125      2.52%     81.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8236     18.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          44648                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7096                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.304961                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       17.955367                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      317.126574                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           7095     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7098                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7098                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.226824                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.209944                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.780993                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6477     91.25%     91.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 22      0.31%     91.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                336      4.73%     96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                168      2.37%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 66      0.93%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 27      0.38%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7098                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5599085250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8699960250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    826900000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       33855.88                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7096                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7096                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.229989                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.211978                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.816035                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6480     91.32%     91.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 18      0.25%     91.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                334      4.71%     96.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                161      2.27%     98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 74      1.04%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 24      0.34%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7096                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     7131716500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10232647750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    826915000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       43122.43                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  52605.88                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         474.77                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         330.65                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      474.80                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      330.71                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  61872.43                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         463.83                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         323.00                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      463.85                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      323.08                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           6.29                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       3.71                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      2.58                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.93                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.72                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     145830                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     89913                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   88.18                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.05                       # Row buffer hit rate for writes
-system.physmem.avgGap                        79452.55                       # Average gap between requests
-system.physmem.pageHitRate                      84.02                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  163424520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   89170125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 636441000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                370882800                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             1456007280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             6110627715                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             8015176500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              16841729940                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              755.495604                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    13256940500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF       744380000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      8290987000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  175218120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   95605125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 653343600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                375366960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             1456007280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             6480752940                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             7690505250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              16926799275                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              759.311692                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    12714890500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF       744380000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      8833037000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                16464676                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          10658312                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            322373                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8884191                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7232535                       # Number of BTB hits
+system.physmem.busUtil                           6.15                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.62                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      2.52                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.98                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.48                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     145971                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     89923                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   88.26                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.06                       # Row buffer hit rate for writes
+system.physmem.avgGap                        81328.57                       # Average gap between requests
+system.physmem.pageHitRate                      84.07                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  153103020                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   81361005                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 582666840                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                298813680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           1398920640.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             1820142240                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy               87895200                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy        2523555300                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        1884269760                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy         2191410645                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              11023267740                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              483.057740                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime            18596850000                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      135529000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       594334000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF     8155766000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN   4906976500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      3493009750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN   5534156250                       # Time in different power states
+system.physmem_1.actEnergy                  165747960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   88078155                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 598167780                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                302363280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           1429652640.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             1911531480                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               82258560                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy        2724848520                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        1880202720                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy         2026371015                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              11210189940                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              491.248979                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime            18411251500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      119903000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       607208000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF     7539541250                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN   4896374750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      3681289750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN   5975454750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED  22819771500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                16458678                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          10655092                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            320474                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8794743                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7227596                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             81.409044                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1975403                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3321                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups           39323                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits              31540                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses             7783                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted         2655                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             82.180866                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1974394                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               3324                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           39317                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              31522                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             7795                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted         2656                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     22505585                       # DTB read hits
-system.cpu.dtb.read_misses                     226699                       # DTB read misses
+system.cpu.dtb.read_hits                     22495361                       # DTB read hits
+system.cpu.dtb.read_misses                     227004                       # DTB read misses
 system.cpu.dtb.read_acv                            16                       # DTB read access violations
-system.cpu.dtb.read_accesses                 22732284                       # DTB read accesses
-system.cpu.dtb.write_hits                    15808846                       # DTB write hits
-system.cpu.dtb.write_misses                     44546                       # DTB write misses
+system.cpu.dtb.read_accesses                 22722365                       # DTB read accesses
+system.cpu.dtb.write_hits                    15803250                       # DTB write hits
+system.cpu.dtb.write_misses                     44602                       # DTB write misses
 system.cpu.dtb.write_acv                            6                       # DTB write access violations
-system.cpu.dtb.write_accesses                15853392                       # DTB write accesses
-system.cpu.dtb.data_hits                     38314431                       # DTB hits
-system.cpu.dtb.data_misses                     271245                       # DTB misses
+system.cpu.dtb.write_accesses                15847852                       # DTB write accesses
+system.cpu.dtb.data_hits                     38298611                       # DTB hits
+system.cpu.dtb.data_misses                     271606                       # DTB misses
 system.cpu.dtb.data_acv                            22                       # DTB access violations
-system.cpu.dtb.data_accesses                 38585676                       # DTB accesses
-system.cpu.itb.fetch_hits                    13724143                       # ITB hits
-system.cpu.itb.fetch_misses                     29345                       # ITB misses
+system.cpu.dtb.data_accesses                 38570217                       # DTB accesses
+system.cpu.itb.fetch_hits                    13713928                       # ITB hits
+system.cpu.itb.fetch_misses                     29641                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                13753488                       # ITB accesses
+system.cpu.itb.fetch_accesses                13743569                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -326,101 +337,101 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     22293541500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                         44587088                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     22819771500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                         45639548                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           15537600                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      105003279                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16464676                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9239478                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      27573681                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                  883330                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        247                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 4700                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        330450                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           85                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13724143                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                187041                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.icacheStallCycles           15527632                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      104958165                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16458678                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9233512                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      28526394                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                  879432                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       1335                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 4713                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        342280                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           91                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13713928                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                186437                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples           43888428                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.392505                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.127693                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples           44842161                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.340613                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.113400                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 24387762     55.57%     55.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1515251      3.45%     59.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1377134      3.14%     62.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1500310      3.42%     65.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4190997      9.55%     75.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1825571      4.16%     79.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   669926      1.53%     80.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1050385      2.39%     83.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  7371092     16.80%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 25352844     56.54%     56.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1513864      3.38%     59.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1375551      3.07%     62.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1499198      3.34%     66.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4186922      9.34%     75.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1824752      4.07%     79.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   669001      1.49%     81.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1050081      2.34%     83.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  7369948     16.44%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             43888428                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.369270                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.355015                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 14897050                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               9776190                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18280655                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                589828                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 344705                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3701787                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 98635                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              103032848                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                312916                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 344705                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15240775                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4552016                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          97125                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18511621                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5142186                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              102032260                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  5895                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  92509                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 354670                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4626637                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            61342957                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             123044735                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        122725402                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            319332                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             44842161                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.360623                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.299720                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 14899514                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              10738608                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18272960                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                588305                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 342774                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3699945                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 98528                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              102994976                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                312859                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 342774                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15240271                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5029380                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          97820                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18506228                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5625688                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102003977                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  6871                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  88609                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 422499                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                5043111                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            61324692                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             123005722                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        122686459                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            319262                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8796076                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               5684                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           5736                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   2358572                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             23134576                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16358313                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1246652                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           504576                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   90719727                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5556                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  88603709                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             68043                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        11133526                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      4439018                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            973                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      43888428                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.018840                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.245634                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  8777811                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5683                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5735                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   2339310                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             23131891                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16353716                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1249387                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           502474                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   90699211                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5558                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  88573949                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             67838                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        11113012                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4439512                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            975                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      44842161                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.975238                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.240795                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            17434377     39.72%     39.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             5720394     13.03%     52.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5103914     11.63%     64.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             4383916      9.99%     74.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4317842      9.84%     84.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2637316      6.01%     90.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1940633      4.42%     94.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1378295      3.14%     97.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              971741      2.21%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            18402096     41.04%     41.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             5711089     12.74%     53.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5105714     11.39%     65.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4382501      9.77%     74.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4313150      9.62%     84.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2637224      5.88%     90.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1940283      4.33%     94.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1377321      3.07%     97.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              972783      2.17%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        43888428                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        44842161                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  241284      9.57%      9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  241463      9.57%      9.57% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      9.57% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.57% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.57% # attempts to use FU when none available
@@ -449,19 +460,19 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.57% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.57% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.57% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1166228     46.24%     55.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               1114848     44.20%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1168337     46.29%     55.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1114013     44.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49379489     55.73%     55.73% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                44005      0.05%     55.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49366935     55.74%     55.74% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                43991      0.05%     55.78% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              121171      0.14%     55.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  92      0.00%     55.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt              120707      0.14%     56.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 62      0.00%     56.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv               39092      0.04%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              121159      0.14%     55.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  93      0.00%     55.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt              120693      0.14%     56.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 63      0.00%     56.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               39087      0.04%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.10% # Type of FU issued
@@ -483,82 +494,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.10% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             22899221     25.84%     81.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            15999870     18.06%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             22887844     25.84%     81.94% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            15994084     18.06%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               88603709                       # Type of FU issued
-system.cpu.iq.rate                           1.987206                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2522360                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.028468                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          223074890                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         101458980                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     86835527                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              611359                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             420488                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       299878                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               90820238                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  305831                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1672227                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               88573949                       # Type of FU issued
+system.cpu.iq.rate                           1.940728                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2523813                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.028494                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          223970382                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         101417859                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     86818116                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              611328                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             420538                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       299902                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               90791946                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  305816                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1674439                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2857938                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         5878                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        20874                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1744936                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2855253                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         5856                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        20836                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1740339                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3021                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        200758                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3017                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        190756                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 344705                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1315985                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               2729229                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           100214269                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            118431                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              23134576                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16358313                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5556                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3898                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               2727794                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          20874                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         113179                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       152389                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               265568                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              87909421                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              22732927                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            694288                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 342774                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1435868                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3107979                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           100192818                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            116708                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              23131891                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16353716                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5558                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3773                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3106841                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          20836                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         111267                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       152585                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               263852                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              87883972                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              22722991                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            689977                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       9488986                       # number of nop insts executed
-system.cpu.iew.exec_refs                     38586655                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15119960                       # Number of branches executed
-system.cpu.iew.exec_stores                   15853728                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.971634                       # Inst execution rate
-system.cpu.iew.wb_sent                       87537444                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      87135405                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  33842966                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  44247648                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.954274                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.764853                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         8653815                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                       9488049                       # number of nop insts executed
+system.cpu.iew.exec_refs                     38571182                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15118040                       # Number of branches executed
+system.cpu.iew.exec_stores                   15848191                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.925610                       # Inst execution rate
+system.cpu.iew.wb_sent                       87519959                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87118018                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  33843453                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  44250497                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.908827                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.764815                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         8632074                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            225413                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     42617548                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.072871                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.885939                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            223532                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     43575084                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.027321                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.870724                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     21149374     49.63%     49.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      6281932     14.74%     64.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      2908445      6.82%     71.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1738602      4.08%     75.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1681485      3.95%     79.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1121192      2.63%     81.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1200701      2.82%     84.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       796598      1.87%     86.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5739219     13.47%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     22117259     50.76%     50.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      6277727     14.41%     65.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      2900957      6.66%     71.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1737731      3.99%     75.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1677521      3.85%     79.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1124025      2.58%     82.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1202727      2.76%     85.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       795829      1.83%     86.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5741308     13.18%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     42617548                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     43575084                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
 system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -604,471 +615,471 @@ system.cpu.commit.op_class_0::MemWrite       14613377     16.54%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5739219                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    132555474                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195263120                       # The number of ROB writes
-system.cpu.timesIdled                           45271                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          698660                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               5741308                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    133489180                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195215826                       # The number of ROB writes
+system.cpu.timesIdled                           45373                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          797387                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.560197                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.560197                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.785085                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.785085                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                116363135                       # number of integer regfile reads
-system.cpu.int_regfile_writes                57669565                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    255561                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   240404                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                   38263                       # number of misc regfile reads
+system.cpu.cpi                               0.573421                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.573421                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.743921                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.743921                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                116327818                       # number of integer regfile reads
+system.cpu.int_regfile_writes                57658172                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    255578                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   240399                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                   38260                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements            201400                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.443451                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            33984025                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            205496                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            165.375603                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         232048500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.443451                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993761                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993761                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  22819771500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements            201413                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4069.948439                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            33978122                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            205509                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            165.336418                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         244590500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4069.948439                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993640                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993640                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2679                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1341                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2488                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1533                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          70817108                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         70817108                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     20422994                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20422994                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13560978                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       13560978                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           53                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           53                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      33983972                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         33983972                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     33983972                       # number of overall hits
-system.cpu.dcache.overall_hits::total        33983972                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       269382                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        269382                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1052399                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1052399                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1321781                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1321781                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1321781                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1321781                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  18043068500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  18043068500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  88421559159                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  88421559159                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 106464627659                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 106464627659                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 106464627659                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 106464627659                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20692376                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20692376                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          70808789                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70808789                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  22819771500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     20418812                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20418812                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13559258                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13559258                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           52                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           52                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      33978070                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         33978070                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     33978070                       # number of overall hits
+system.cpu.dcache.overall_hits::total        33978070                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       269399                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        269399                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1054119                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1054119                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1323518                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1323518                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1323518                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1323518                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  19371317500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  19371317500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  94432641988                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  94432641988                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 113803959488                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 113803959488                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 113803959488                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 113803959488                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20688211                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20688211                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           53                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           53                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     35305753                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     35305753                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     35305753                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     35305753                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.013018                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.013018                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.072016                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.072016                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037438                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037438                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037438                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037438                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66979.488236                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66979.488236                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84019.045209                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 84019.045209                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 80546.344409                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 80546.344409                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 80546.344409                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 80546.344409                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      6874865                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          279                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             86609                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           52                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           52                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     35301588                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     35301588                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     35301588                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     35301588                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.013022                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.013022                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.072134                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.072134                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037492                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037492                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037492                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037492                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71905.677081                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71905.677081                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89584.422620                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 89584.422620                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 85985.955225                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 85985.955225                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 85985.955225                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 85985.955225                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      7415690                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          299                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             82797                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    79.378182                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   139.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       168502                       # number of writebacks
-system.cpu.dcache.writebacks::total            168502                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207279                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       207279                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       909006                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       909006                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1116285                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1116285                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1116285                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1116285                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62103                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        62103                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143393                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143393                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       205496                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       205496                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       205496                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       205496                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3336459000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3336459000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14128429272                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  14128429272                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17464888272                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17464888272                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17464888272                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  17464888272                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003001                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003001                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009812                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009812                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005820                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.005820                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005820                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.005820                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53724.602676                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53724.602676                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98529.421046                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98529.421046                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84988.945147                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 84988.945147                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84988.945147                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 84988.945147                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements             90436                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1916.490065                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            13619166                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             92484                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            147.259699                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       18779712500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1916.490065                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.935786                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.935786                       # Average percentage of cache occupancy
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    89.564719                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   149.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks       168510                       # number of writebacks
+system.cpu.dcache.writebacks::total            168510                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207284                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       207284                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       910725                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       910725                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1118009                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1118009                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1118009                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1118009                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62115                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        62115                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143394                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143394                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       205509                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       205509                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       205509                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       205509                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3617431500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3617431500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  15283982713                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  15283982713                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18901414213                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  18901414213                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18901414213                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  18901414213                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003002                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003002                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009813                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009813                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005822                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.005822                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005822                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.005822                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58237.647911                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58237.647911                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106587.323828                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106587.323828                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 91973.656691                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 91973.656691                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 91973.656691                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 91973.656691                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  22819771500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements             90457                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1914.919853                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            13608920                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             92505                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            147.115507                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       19216549500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1914.919853                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.935019                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.935019                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          106                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1460                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          389                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1462                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          388                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          27540768                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         27540768                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     13619166                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        13619166                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      13619166                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         13619166                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     13619166                       # number of overall hits
-system.cpu.icache.overall_hits::total        13619166                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       104976                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        104976                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       104976                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         104976                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       104976                       # number of overall misses
-system.cpu.icache.overall_misses::total        104976                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1956506499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1956506499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1956506499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1956506499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1956506499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1956506499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13724142                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13724142                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13724142                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13724142                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13724142                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13724142                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007649                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.007649                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.007649                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.007649                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.007649                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.007649                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18637.655264                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18637.655264                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18637.655264                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18637.655264                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18637.655264                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18637.655264                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1136                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          27520357                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27520357                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  22819771500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     13608920                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        13608920                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      13608920                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         13608920                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     13608920                       # number of overall hits
+system.cpu.icache.overall_hits::total        13608920                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       105006                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        105006                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       105006                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         105006                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       105006                       # number of overall misses
+system.cpu.icache.overall_misses::total        105006                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2088801499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2088801499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2088801499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2088801499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2088801499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2088801499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13713926                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13713926                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13713926                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13713926                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13713926                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13713926                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007657                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.007657                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.007657                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.007657                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.007657                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.007657                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19892.210912                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19892.210912                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19892.210912                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19892.210912                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19892.210912                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19892.210912                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          683                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                16                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    75.733333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    42.687500                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks        90436                       # number of writebacks
-system.cpu.icache.writebacks::total             90436                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12491                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        12491                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        12491                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        12491                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        12491                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        12491                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        92485                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        92485                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        92485                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        92485                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        92485                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        92485                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1595124000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1595124000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1595124000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1595124000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1595124000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1595124000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006739                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006739                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006739                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006739                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006739                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006739                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17247.380656                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17247.380656                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17247.380656                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17247.380656                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17247.380656                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17247.380656                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           134874                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31863.975507                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             422062                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           167642                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.517639                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       4859656000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   722.364840                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1777.470792                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29364.139876                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.022045                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.054244                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.896122                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.972411                       # Average percentage of cache occupancy
+system.cpu.icache.writebacks::writebacks        90457                       # number of writebacks
+system.cpu.icache.writebacks::total             90457                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12500                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        12500                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        12500                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        12500                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        12500                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        12500                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        92506                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        92506                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        92506                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        92506                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        92506                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        92506                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1693618500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1693618500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1693618500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1693618500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1693618500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1693618500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006745                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006745                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006745                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006745                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006745                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006745                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18308.201630                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18308.201630                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18308.201630                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18308.201630                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18308.201630                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18308.201630                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  22819771500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           134872                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31840.102351                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             422133                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           167640                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.518092                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       5003072000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   716.868966                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1773.767441                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 29349.465945                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.021877                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.054131                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.895675                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.971683                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          208                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2938                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        29364                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          202                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          200                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2733                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28770                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1005                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4           60                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          4886178                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         4886178                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       168502                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       168502                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        90436                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        90436                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12584                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12584                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        86017                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        86017                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        33990                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        33990                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        86017                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        46574                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          132591                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        86017                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        46574                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         132591                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       130811                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130811                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         6468                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         6468                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        28111                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        28111                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         6468                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       158922                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        165390                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         6468                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       158922                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       165390                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13777150000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  13777150000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    548837500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    548837500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2881866500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   2881866500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    548837500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  16659016500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  17207854000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    548837500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  16659016500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  17207854000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       168502                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       168502                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        90436                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        90436                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       143395                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143395                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        92485                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        92485                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        62101                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        62101                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        92485                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       205496                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       297981                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        92485                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       205496                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       297981                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912242                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.912242                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.069936                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.069936                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.452666                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.452666                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.069936                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.773358                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.555035                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.069936                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.773358                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.555035                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105321.035693                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105321.035693                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84854.282622                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84854.282622                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102517.395326                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102517.395326                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84854.282622                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104825.112319                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 104044.101820                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84854.282622                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104825.112319                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 104044.101820                       # average overall miss latency
+system.cpu.l2cache.tags.tag_accesses          4886720                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         4886720                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  22819771500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks       168510                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       168510                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        90457                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        90457                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12581                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12581                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        86036                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        86036                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        34007                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        34007                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        86036                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        46588                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          132624                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        86036                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        46588                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         132624                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       130815                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       130815                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         6470                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         6470                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        28106                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        28106                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         6470                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       158921                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        165391                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         6470                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       158921                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       165391                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14933033000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  14933033000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    647096000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    647096000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3162742000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   3162742000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    647096000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  18095775000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  18742871000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    647096000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  18095775000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  18742871000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       168510                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       168510                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        90457                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        90457                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143396                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143396                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        92506                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        92506                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        62113                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        62113                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        92506                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       205509                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       298015                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        92506                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       205509                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       298015                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912264                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.912264                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.069941                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.069941                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.452498                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.452498                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.069941                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.773304                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.554975                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.069941                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.773304                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.554975                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 114153.827925                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 114153.827925                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 100014.837713                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 100014.837713                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 112529.068526                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 112529.068526                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 100014.837713                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 113866.480830                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 113324.612585                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 100014.837713                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 113866.480830                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 113324.612585                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks       115201                       # number of writebacks
-system.cpu.l2cache.writebacks::total           115201                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          112                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          112                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130811                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130811                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         6468                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         6468                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        28111                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        28111                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         6468                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158922                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       165390                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         6468                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158922                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       165390                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12469040000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12469040000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    484167500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    484167500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2600756500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2600756500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    484167500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15069796500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  15553964000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    484167500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15069796500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  15553964000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks       115198                       # number of writebacks
+system.cpu.l2cache.writebacks::total           115198                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          111                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          111                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130815                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       130815                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         6470                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         6470                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        28106                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        28106                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         6470                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158921                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       165391                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         6470                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158921                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       165391                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13624883000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13624883000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    582406000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    582406000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2881682000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2881682000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    582406000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16506565000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  17088971000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    582406000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16506565000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  17088971000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912242                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912242                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.069936                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.069936                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.452666                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.452666                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.069936                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.773358                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.555035                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.069936                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.773358                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.555035                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95321.035693                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95321.035693                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74855.828695                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74855.828695                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92517.395326                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92517.395326                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74855.828695                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94825.112319                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94044.162283                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74855.828695                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94825.112319                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94044.162283                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests       589817                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       291836                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912264                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912264                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.069941                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.069941                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.452498                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.452498                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.069941                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.773304                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.554975                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.069941                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.773304                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.554975                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 104153.827925                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 104153.827925                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90016.383308                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90016.383308                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102529.068526                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102529.068526                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90016.383308                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 103866.480830                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 103324.673048                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90016.383308                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 103866.480830                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 103324.673048                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests       589885                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       291870                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         4239                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4239                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         4237                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4237                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp        154585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       283703                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        90436                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        52571                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143395                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143395                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        92485                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        62101                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       275405                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612392                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            887797                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     11706880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23935872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           35642752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      134874                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               7372864                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples       432855                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.009793                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.098475                       # Request fanout histogram
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  22819771500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp        154618                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       283708                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        90457                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        52577                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143396                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143396                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        92506                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        62113                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       275468                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612431                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            887899                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     11709568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23937216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           35646784                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      134872                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               7372672                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples       432887                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.009788                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.098448                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             428616     99.02%     99.02% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               4239      0.98%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             428650     99.02%     99.02% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               4237      0.98%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         432855                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      553846500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     138734483                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         432887                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      553909500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.4                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     138764985                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     308248491                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     308272981                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
 system.membus.snoop_filter.tot_requests        296135                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       130746                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_single_requests       130745                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp              34578                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       115200                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            15546                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130811                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130811                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         34578                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       461524                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 461524                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17957696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17957696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED  22819771500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp              34575                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       115197                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            15548                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130815                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130815                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34575                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       461525                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 461525                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17957568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17957568                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            165389                       # Request fanout histogram
+system.membus.snoop_fanout::samples            165390                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  165389    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  165390    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              165389                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           780841500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          854544750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              3.8                       # Layer utilization (%)
+system.membus.snoop_fanout::total              165390                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           779827500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               3.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          851966000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              3.7                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
index 7debe9727..3119a9994 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
@@ -151,7 +151,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -631,7 +631,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -691,7 +691,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -880,6 +880,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -891,7 +892,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -899,29 +900,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -941,6 +949,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -972,9 +981,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout
index 9e5ee29fe..9fd7ec0be 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 15:05:27
-gem5 executing on e108600-lin, pid 24209
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:42:59
+gem5 executing on e108600-lin, pid 17323
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/arm/linux/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 58768125500 because target called exit()
+Exiting @ tick 60130734500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index 7abf225fd..feef465f0 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.058750                       # Number of seconds simulated
-sim_ticks                                 58750410500                       # Number of ticks simulated
-final_tick                                58750410500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.060131                       # Number of seconds simulated
+sim_ticks                                 60130734500                       # Number of ticks simulated
+final_tick                                60130734500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 179920                       # Simulator instruction rate (inst/s)
-host_op_rate                                   230092                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              149057017                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 281832                       # Number of bytes of host memory used
-host_seconds                                   394.15                       # Real time elapsed on the host
+host_inst_rate                                 142105                       # Simulator instruction rate (inst/s)
+host_op_rate                                   181732                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              120494644                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 279144                       # Number of bytes of host memory used
+host_seconds                                   499.03                       # Real time elapsed on the host
 sim_insts                                    70915150                       # Number of instructions simulated
 sim_ops                                      90690106                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            286336                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7938624                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8224960                       # Number of bytes read from this memory
@@ -26,27 +26,27 @@ system.physmem.num_reads::cpu.data             124041                       # Nu
 system.physmem.num_reads::total                128515                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           86552                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                86552                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              4873770                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            135124571                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               139998341                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         4873770                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            4873770                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          94285775                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               94285775                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          94285775                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             4873770                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           135124571                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              234284116                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              4761891                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            132022735                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               136784626                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         4761891                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            4761891                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          92121409                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               92121409                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          92121409                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             4761891                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           132022735                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              228906035                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        128515                       # Number of read requests accepted
 system.physmem.writeReqs                        86552                       # Number of write requests accepted
 system.physmem.readBursts                      128515                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      86552                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  8224512                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5537600                       # Total number of bytes written to DRAM
+system.physmem.bytesReadDRAM                  8224640                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5537472                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                   8224960                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                5539328                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                8086                       # Per bank write bursts
@@ -57,24 +57,24 @@ system.physmem.perBankRdBursts::4                8301                       # Pe
 system.physmem.perBankRdBursts::5                8413                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                8070                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                7917                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8053                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7612                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8054                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7613                       # Per bank write bursts
 system.physmem.perBankRdBursts::10               7771                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               7825                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               7888                       # Per bank write bursts
 system.physmem.perBankRdBursts::13               7870                       # Per bank write bursts
 system.physmem.perBankRdBursts::14               7981                       # Per bank write bursts
 system.physmem.perBankRdBursts::15               7974                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5399                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5400                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                5549                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5476                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5348                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                5475                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5349                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                5387                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5588                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5586                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                5325                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                5260                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                5187                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5136                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5135                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               5306                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               5279                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               5541                       # Per bank write bursts
@@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14               5706                       # Pe
 system.physmem.perBankWrBursts::15               5441                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     58750379000                       # Total gap between requests
+system.physmem.totGap                     60130703000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -98,11 +98,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  86552                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    116239                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     12249                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    116093                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     12374                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        41                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      470                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      477                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4747                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5340                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5346                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5349                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5355                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5356                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5371                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5382                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5490                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5469                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5417                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5499                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      442                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4746                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5341                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5356                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5356                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5373                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5413                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5459                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5434                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5406                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5596                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
@@ -194,104 +194,115 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        32968                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      417.384130                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     256.722785                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     362.908382                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           8749     26.54%     26.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         6430     19.50%     46.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3309     10.04%     56.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2430      7.37%     63.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2267      6.88%     70.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1599      4.85%     75.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1281      3.89%     79.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1267      3.84%     82.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         5636     17.10%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          32968                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5346                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.036289                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       17.665302                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      347.416280                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5344     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        32872                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      418.606960                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     258.790126                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     361.910519                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           8567     26.06%     26.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         6423     19.54%     45.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3392     10.32%     55.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2472      7.52%     63.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2230      6.78%     70.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1616      4.92%     75.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1339      4.07%     79.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1211      3.68%     82.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         5622     17.10%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          32872                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5350                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.018131                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       17.666671                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      347.276238                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5348     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5346                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5346                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.184998                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.174634                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.600598                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4870     91.10%     91.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  4      0.07%     91.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                438      8.19%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 27      0.51%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  7      0.13%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5346                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1552277750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                3961802750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    642540000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12079.23                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5350                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5350                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.172523                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.162775                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.583592                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4904     91.66%     91.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  3      0.06%     91.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                417      7.79%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 22      0.41%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  3      0.06%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5350                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3048956750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5458519250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    642550000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       23725.44                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30829.23                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         139.99                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          94.26                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      140.00                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       94.29                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  42475.44                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         136.78                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          92.09                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      136.78                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       92.12                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.83                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.09                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.74                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           1.79                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.07                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.72                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.56                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     112029                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     70027                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.18                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.91                       # Row buffer hit rate for writes
-system.physmem.avgGap                       273172.45                       # Average gap between requests
-system.physmem.pageHitRate                      84.65                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  130599000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   71259375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 511009200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                280655280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3837085200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            11237331690                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            25391203500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41459143245                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              705.717335                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    42124223000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1961700000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     14661610750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  118555920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   64688250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 491072400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                279819360                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3837085200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            10919729115                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            25669800000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41380750245                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              704.382975                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    42589738750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1961700000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     14196261750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                14827613                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9922572                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            342024                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9662819                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6571830                       # Number of BTB hits
+system.physmem.avgWrQLen                        23.60                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     112228                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     69923                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.33                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.79                       # Row buffer hit rate for writes
+system.physmem.avgGap                       279590.56                       # Average gap between requests
+system.physmem.pageHitRate                      84.70                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  123522000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   65634525                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 467912760                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                226187820                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           2501584800.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2202428130                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              166870080                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy        5871636120                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        2984284320                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy         8652824730                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              23263603845                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              386.883743                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime            54864406750                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      285894000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1063168000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    34216733000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN   7771569500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      3916970000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  12876400000                       # Time in different power states
+system.physmem_1.actEnergy                  111255480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   59114715                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 449648640                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                225462240                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           2476999200.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2186718930                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              154089120                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy        5325084780                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        3204564480                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy         8848391460                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              23042110905                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              383.200220                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime            54932244750                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      256290500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1053008000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    34909248000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN   8345212750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      3889130500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  11677844750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                14827796                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9922694                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            342031                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9662876                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6571901                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             68.011519                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1720035                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             68.011853                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1720083                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups          175655                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits             158613                       # Number of indirect target hits.
+system.cpu.branchPred.indirectLookups          175657                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             158615                       # Number of indirect target hits.
 system.cpu.branchPred.indirectMisses            17042                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted        24764                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -321,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -351,7 +362,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -381,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -412,16 +423,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     58750410500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        117500821                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        120261469                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70915150                       # Number of instructions committed
 system.cpu.committedOps                      90690106                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1179078                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1179235                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.656921                       # CPI: cycles per instruction
-system.cpu.ipc                               0.603529                       # IPC: instructions per cycle
+system.cpu.cpi                               1.695850                       # CPI: cycles per instruction
+system.cpu.ipc                               0.589675                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu                47187979     52.03%     52.03% # Class of committed instruction
 system.cpu.op_class_0::IntMult                  80119      0.09%     52.12% # Class of committed instruction
@@ -457,106 +468,106 @@ system.cpu.op_class_0::MemWrite              20555739     22.67%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                 90690106                       # Class of committed instruction
-system.cpu.tickCycles                        97998947                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        19501874                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                        98354903                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        21906566                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            156451                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4067.791520                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42637484                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4067.127252                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42637295                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            160547                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            265.576336                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         830343500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4067.791520                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993113                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993113                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            265.575159                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         880684500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4067.127252                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.992951                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.992951                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1054                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2998                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1009                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3044                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          86035297                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         86035297                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     22880319                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22880319                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     19642152                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       19642152                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        83175                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         83175                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses          86034713                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         86034713                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     22880152                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22880152                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     19642142                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       19642142                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        83163                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         83163                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      42522471                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         42522471                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42605646                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42605646                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        47369                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         47369                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       207749                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       207749                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        44773                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        44773                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       255118                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         255118                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       299891                       # number of overall misses
-system.cpu.dcache.overall_misses::total        299891                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1548941500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1548941500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  16628210000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  16628210000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  18177151500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  18177151500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  18177151500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  18177151500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22927688                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22927688                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      42522294                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         42522294                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42605457                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42605457                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        47246                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         47246                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       207759                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       207759                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        44783                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        44783                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       255005                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         255005                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       299788                       # number of overall misses
+system.cpu.dcache.overall_misses::total        299788                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1839858000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1839858000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18545282000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18545282000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  20385140000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  20385140000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  20385140000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  20385140000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22927398                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22927398                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       127948                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       127948                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       127946                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       127946                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42777589                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42777589                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42905537                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42905537                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002066                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002066                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010466                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.010466                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.349931                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.349931                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.005964                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.005964                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.006990                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.006990                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32699.476451                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32699.476451                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80039.903923                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 80039.903923                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 71249.976481                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 71249.976481                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60612.527552                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60612.527552                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     42777299                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42777299                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42905245                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42905245                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002061                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002061                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010467                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.010467                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.350015                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.350015                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.005961                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.005961                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.006987                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.006987                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 79940.158036                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 67998.518953                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          185                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          185                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.writebacks::writebacks       128145                       # number of writebacks
 system.cpu.dcache.writebacks::total            128145                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        17840                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        17840                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100712                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       100712                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       118552                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       118552                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       118552                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       118552                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        17717                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        17717                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100722                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       100722                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       118439                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       118439                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       118439                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       118439                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29529                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total        29529                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107037                       # number of WriteReq MSHR misses
@@ -567,92 +578,92 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       136566
 system.cpu.dcache.demand_mshr_misses::total       136566                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       160547                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       160547                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    586674000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    586674000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8401236500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8401236500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1788829000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1788829000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8987910500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   8987910500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10776739500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10776739500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    773644500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    773644500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9479497500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9479497500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1896776500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1896776500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10253142000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  10253142000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12149918500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12149918500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001288                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001288                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187428                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187428                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187431                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187431                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003192                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.003192                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19867.723255                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19867.723255                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78489.087885                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78489.087885                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74593.594929                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74593.594929                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65813.676171                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65813.676171                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67125.137810                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67125.137810                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             43545                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1854.190293                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25047618                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1852.001681                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25048343                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             45587                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            549.446509                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs            549.462413                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1854.190293                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.905366                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.905366                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1852.001681                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.904298                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.904298                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           50                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           54                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          913                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1006                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          898                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1021                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          50231999                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         50231999                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     25047618                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25047618                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25047618                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25047618                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25047618                       # number of overall hits
-system.cpu.icache.overall_hits::total        25047618                       # number of overall hits
+system.cpu.icache.tags.tag_accesses          50233449                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         50233449                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     25048343                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25048343                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25048343                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25048343                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25048343                       # number of overall hits
+system.cpu.icache.overall_hits::total        25048343                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        45588                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         45588                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        45588                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          45588                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        45588                       # number of overall misses
 system.cpu.icache.overall_misses::total         45588                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    918433000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    918433000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    918433000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    918433000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    918433000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    918433000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25093206                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25093206                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25093206                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25093206                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25093206                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25093206                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1042270000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1042270000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1042270000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1042270000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1042270000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1042270000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25093931                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25093931                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25093931                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25093931                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25093931                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25093931                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001817                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.001817                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.001817                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.001817                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.001817                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.001817                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20146.376239                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20146.376239                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20146.376239                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20146.376239                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20146.376239                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20146.376239                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22862.814776                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22862.814776                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -667,88 +678,88 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        45588
 system.cpu.icache.demand_mshr_misses::total        45588                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        45588                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        45588                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    872846000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    872846000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    872846000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    872846000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    872846000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    872846000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    996683000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    996683000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    996683000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    996683000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    996683000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    996683000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001817                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001817                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001817                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.001817                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001817                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.001817                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19146.398175                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19146.398175                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19146.398175                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19146.398175                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19146.398175                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19146.398175                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.836711                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.836711                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.836711                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.836711                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements            97176                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31328.460689                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             268173                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        31292.334990                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             268174                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           129944                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.063758                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      10596662000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   480.299456                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1381.968758                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29466.192474                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.014658                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.042174                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.899237                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.956069                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.avg_refs             2.063766                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      10980034000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   476.637646                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1378.081673                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.014546                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.042056                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.898365                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.954966                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          179                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1189                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        13615                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17003                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          171                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1141                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12834                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17840                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4          782                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses          3316240                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses         3316240                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks       128145                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       128145                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks        39944                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total        39944                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         4720                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         4720                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        41100                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        41100                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        41101                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        41101                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data        31726                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total        31726                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        41100                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst        41101                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data        36446                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           77546                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        41100                       # number of overall hits
+system.cpu.l2cache.demand_hits::total           77547                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        41101                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data        36446                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          77546                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          77547                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data       102317                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       102317                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         4488                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         4488                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         4487                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         4487                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data        21784                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total        21784                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         4488                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         4487                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data       124101                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        128589                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         4488                       # number of overall misses
+system.cpu.l2cache.demand_misses::total        128588                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         4487                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       124101                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       128589                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8191072500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8191072500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    369038000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    369038000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1957896000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1957896000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    369038000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10148968500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10518006500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    369038000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10148968500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10518006500                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total       128588                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9269336000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9269336000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    492869500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    492869500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2252818000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   2252818000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    492869500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  11522154000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  12015023500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    492869500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  11522154000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  12015023500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks       128145                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total       128145                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks        39944                       # number of WritebackClean accesses(hits+misses)
@@ -767,28 +778,28 @@ system.cpu.l2cache.overall_accesses::cpu.data       160547
 system.cpu.l2cache.overall_accesses::total       206135                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955903                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.955903                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.098447                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.098447                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.098425                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.098425                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.407101                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.407101                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.098447                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.098425                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.772989                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.623810                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.098447                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.623805                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.098425                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.772989                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.623810                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80055.831387                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80055.831387                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82227.718360                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82227.718360                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89877.708410                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89877.708410                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82227.718360                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81779.909106                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81795.538499                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82227.718360                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81779.909106                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81795.538499                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.623805                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103416.177011                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109843.882327                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92844.973046                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 93438.139640                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109843.882327                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92844.973046                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 93438.139640                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -797,16 +808,16 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.writebacks::writebacks        86552                       # number of writebacks
 system.cpu.l2cache.writebacks::total            86552                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           12                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           60                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total           60                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           12                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           60                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           73                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           72                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           12                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           60                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           73                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           72                       # number of overall MSHR hits
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           96                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total           96                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102317                       # number of ReadExReq MSHR misses
@@ -821,18 +832,18 @@ system.cpu.l2cache.demand_mshr_misses::total       128516
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         4475                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       124041                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       128516                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7167902500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7167902500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    323146000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    323146000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1736095500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1736095500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    323146000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8903998000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9227144000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    323146000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8903998000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9227144000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8246166000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8246166000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    446702000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    446702000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2029430500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2029430500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    446702000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10275596500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10722298500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    446702000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10275596500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10722298500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955903                       # mshr miss rate for ReadExReq accesses
@@ -847,25 +858,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.623456
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.098162                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.772615                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.623456                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70055.831387                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70055.831387                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72211.396648                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72211.396648                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79916.014546                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79916.014546                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72211.396648                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71782.700881                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71797.628311                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72211.396648                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71782.700881                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71797.628311                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests       406131                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       200034                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7844                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         3482                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3452                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           30                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp         99097                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       214697                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        43545                       # Transaction distribution
@@ -895,7 +906,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value            2                       #
 system.cpu.toL2Bus.snoop_fanout::total         303311                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy      374755500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      68396468                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      68395969                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy     240852935                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
@@ -905,7 +916,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  58750410500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp              26198                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        86552                       # Transaction distribution
 system.membus.trans_dist::CleanEvict             7237                       # Transaction distribution
@@ -928,9 +939,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total              128515                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           587526000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           588253000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          677474000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          677385750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 8b084cbe5..e2ac8f237 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -172,7 +172,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -534,7 +534,7 @@ pipelined=true
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -813,6 +813,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -824,7 +825,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -832,29 +833,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -874,6 +882,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -905,9 +914,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
index 1832c357f..77b319c20 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:10:34
-gem5 executing on e108600-lin, pid 12236
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:59:48
+gem5 executing on e108600-lin, pid 17544
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/arm/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 33524756000 because target called exit()
+Exiting @ tick 37982056000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 7d5e42cd5..6270a4a24 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.037283                       # Number of seconds simulated
-sim_ticks                                 37283333000                       # Number of ticks simulated
-final_tick                                37283333000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.037982                       # Number of seconds simulated
+sim_ticks                                 37982056000                       # Number of ticks simulated
+final_tick                                37982056000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 125888                       # Simulator instruction rate (inst/s)
-host_op_rate                                   160996                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               66191855                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 284264                       # Number of bytes of host memory used
-host_seconds                                   563.26                       # Real time elapsed on the host
+host_inst_rate                                 105525                       # Simulator instruction rate (inst/s)
+host_op_rate                                   134954                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               56525025                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 282344                       # Number of bytes of host memory used
+host_seconds                                   671.95                       # Real time elapsed on the host
 sim_insts                                    70907652                       # Number of instructions simulated
 sim_ops                                      90682607                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst           2379328                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           5690752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher      6174592                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             14244672                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      2379328                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         2379328                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6224768                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6224768                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              37177                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              88918                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        96478                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                222573                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           97262                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                97262                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             63817470                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            152635281                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher    165612661                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               382065412                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        63817470                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           63817470                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         166958464                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              166958464                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         166958464                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            63817470                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           152635281                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher    165612661                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              549023876                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        222574                       # Number of read requests accepted
-system.physmem.writeReqs                        97262                       # Number of write requests accepted
-system.physmem.readBursts                      222574                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      97262                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 14235136                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9600                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6223360                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  14244736                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6224768                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      150                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst           2372544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           5696640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher      6178368                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             14247552                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      2372544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         2372544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6227072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6227072                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              37071                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              89010                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        96537                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                222618                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97298                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97298                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             62464865                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            149982402                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher    162665444                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               375112711                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        62464865                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           62464865                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         163947734                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              163947734                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         163947734                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            62464865                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           149982402                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher    162665444                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              539060445                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        222619                       # Number of read requests accepted
+system.physmem.writeReqs                        97298                       # Number of write requests accepted
+system.physmem.readBursts                      222619                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97298                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 14237568                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10048                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6225984                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  14247616                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6227072                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      157                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9684                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9951                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12571                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25345                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               17391                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               22070                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11722                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               14054                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11726                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               15447                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11755                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11322                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9441                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9563                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9879                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              20503                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5981                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6205                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6090                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6159                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6110                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6252                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5998                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5984                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5961                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6093                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6222                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5895                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6037                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6052                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6175                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6026                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9655                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9974                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12579                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25363                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               17343                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               22132                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11760                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               14137                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11660                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               15453                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11698                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11338                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9437                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9564                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9858                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              20511                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5992                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6239                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6121                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6129                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6098                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6229                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6018                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5980                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5938                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6095                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6202                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5916                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6046                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6090                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6173                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6015                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     37283321500                       # Total gap between requests
+system.physmem.totGap                     37982044500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  222574                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  222619                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  97262                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    113358                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     61350                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     14014                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     10209                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      5990                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      5097                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4548                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4202                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3541                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        77                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97298                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    111989                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     59707                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     15764                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     10925                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6262                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      5252                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4622                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4266                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3549                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        76                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
@@ -149,34 +149,34 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4946                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5524                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6446                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6870                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7426                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7971                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8650                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7379                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6528                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1089                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2518                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4935                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5530                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6796                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7367                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7813                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8377                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7998                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6745                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      207                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       12                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
@@ -198,109 +198,120 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       132565                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      154.319345                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     102.621145                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     210.186270                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          82651     62.35%     62.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        32256     24.33%     86.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6354      4.79%     91.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2721      2.05%     93.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1163      0.88%     94.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1002      0.76%     95.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          846      0.64%     95.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          812      0.61%     96.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4760      3.59%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         132565                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5874                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        37.864488                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      211.288279                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            5866     99.86%     99.86% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            7      0.12%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       132891                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      153.980270                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     102.520664                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     209.589027                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          82855     62.35%     62.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        32511     24.46%     86.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6209      4.67%     91.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2728      2.05%     93.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1195      0.90%     94.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          994      0.75%     95.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          885      0.67%     95.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          776      0.58%     96.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4738      3.57%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         132891                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5883                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        37.813870                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      211.295819                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            5876     99.88%     99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            6      0.10%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::15360-15871            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5874                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5874                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.554307                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.512747                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.243213                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4672     79.54%     79.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 38      0.65%     80.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                729     12.41%     92.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                209      3.56%     96.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                107      1.82%     97.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 58      0.99%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 31      0.53%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 16      0.27%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 11      0.19%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5874                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7261518854                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11431968854                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1112120000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       32647.19                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5883                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5883                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.535951                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.496117                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.216118                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4707     80.01%     80.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 47      0.80%     80.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                703     11.95%     92.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                205      3.48%     96.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                109      1.85%     98.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 61      1.04%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 33      0.56%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 11      0.19%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  4      0.07%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5883                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8417974819                       # Total ticks spent queuing
+system.physmem.totMemAccLat               12589137319                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1112310000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       37840.06                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  51397.19                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         381.81                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         166.92                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      382.07                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      166.96                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  56590.06                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         374.85                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         163.92                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      375.11                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      163.95                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           4.29                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.30                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.36                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.45                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     157163                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     29925                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   70.66                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  30.77                       # Row buffer hit rate for writes
-system.physmem.avgGap                       116570.12                       # Average gap between requests
-system.physmem.pageHitRate                      58.52                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  537077520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  293048250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 957496800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                315958320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             2434985280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            23206024395                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             2012333250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              29756923815                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              798.183082                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE     3201879547                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1244880000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32834079203                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  464871960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  253650375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 777051600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                313949520                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             2434985280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            21592790730                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             3427453500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              29264752965                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              784.981262                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE     5568954615                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1244880000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30467009135                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                17068882                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11456187                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            597693                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9279962                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7373647                       # Number of BTB hits
+system.physmem.busUtil                           4.21                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.93                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      1.28                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.38                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.49                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     157076                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     29766                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   70.61                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  30.59                       # Row buffer hit rate for writes
+system.physmem.avgGap                       118724.68                       # Average gap between requests
+system.physmem.pageHitRate                      58.43                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  508332300                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  270162255                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 877813020                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                254767320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3007433520.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2937544590                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy               74566560                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       13007568150                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        1007588640                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy           71626485                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              22017862440                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              579.691165                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime            31344656336                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE       41004063                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1272480000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF      195565250                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN   2624595348                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      5323818601                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  28524592738                       # Time in different power states
+system.physmem_1.actEnergy                  440580840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  234159090                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 710558520                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                253039500                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           2889422640.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2771748120                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               73304160                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       11932439280                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        1384694400                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy          508589940                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              21198847170                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              558.127949                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime            31712588164                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE       50452548                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1222746000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF     1938473750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN   3605935527                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      4996269288                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  26168178887                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                17071043                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11458506                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            598065                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9277652                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7374059                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             79.457728                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1854916                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             101589                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups          233217                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits             195584                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses            37633                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted        22185                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             79.481953                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1854771                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             101571                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups          233347                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             194967                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            38380                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        22266                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -330,7 +341,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -360,7 +371,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -390,7 +401,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -421,96 +432,96 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     37283333000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                         74566667                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     37982056000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                         75964113                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            5541341                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       87099155                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17068882                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9424147                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      65038748                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1222021                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                11659                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            48                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        30739                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  22432357                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 69340                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           71233545                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.545306                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.327706                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles            5537723                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       87105546                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17071043                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9423797                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      66074321                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1222765                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                12043                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            60                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles        33616                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  22433583                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 69302                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           72269145                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.523281                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.330897                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 26059108     36.58%     36.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  8166381     11.46%     48.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9112889     12.79%     60.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 27895167     39.16%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 27092588     37.49%     37.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  8164913     11.30%     48.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9113637     12.61%     61.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 27898007     38.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             71233545                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.228908                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.168071                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8928507                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              25221623                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  30949867                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               5689167                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 444381                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3134053                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                168503                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              100299686                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               2798262                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 444381                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 13572247                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                10675080                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         842433                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  31772787                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              13926617                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               98328841                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                859440                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               4124148                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  69439                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                4596367                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                5265270                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           103255092                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             453545884                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        114277398                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               716                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             72269145                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.224725                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.146667                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8914938                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              26268747                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  30971085                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               5669704                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 444671                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3134143                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                168562                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              100303161                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               2799230                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 444671                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13550474                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11467047                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         876029                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  31784130                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14146794                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               98330583                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                860090                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               4210253                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  70388                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                4670257                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                5435231                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           103259286                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             453553071                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        114279094                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               706                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              93629369                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  9625723                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              18974                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          19002                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12839389                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             24155878                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21759886                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1433320                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2321800                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   97398916                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               34841                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  94478155                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            593843                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         6751150                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     17960313                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1055                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      71233545                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.326316                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.168839                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  9629917                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              18998                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          19022                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12803731                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             24155645                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21760500                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1435489                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2293932                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   97400499                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               34856                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  94484787                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            595355                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         6752748                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     17957034                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1070                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      72269145                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.307401                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.171287                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            23112455     32.45%     32.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17441476     24.48%     56.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            17040128     23.92%     80.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            11602976     16.29%     97.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2035055      2.86%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                1455      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            24146655     33.41%     33.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17449315     24.14%     57.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            17027031     23.56%     81.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            11604628     16.06%     97.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2040054      2.82%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                1462      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        71233545                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        72269145                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 6731709     22.63%     22.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     38      0.00%     22.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 6736684     22.63%     22.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     37      0.00%     22.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.63% # attempts to use FU when none available
@@ -538,13 +549,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.63% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               11081856     37.26%     59.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              11930481     40.11%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11088474     37.25%     59.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              11940322     40.11%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49303920     52.19%     52.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                86563      0.09%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49305598     52.18%     52.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                86530      0.09%     52.28% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.28% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                  32      0.00%     52.28% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.28% # Type of FU issued
@@ -565,89 +576,89 @@ system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.28% # Ty
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.28% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.28% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp              12      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp              11      0.00%     52.28% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.28% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc             19      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc             18      0.00%     52.28% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.28% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.28% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             23954982     25.36%     77.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21132627     22.37%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             23958877     25.36%     77.63% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21133721     22.37%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               94478155                       # Type of FU issued
-system.cpu.iq.rate                           1.267029                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    29744084                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.314825                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          290527434                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         104196109                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     93201296                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 348                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                616                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           96                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              124222040                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     199                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1368179                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               94484787                       # Type of FU issued
+system.cpu.iq.rate                           1.243808                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    29765517                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.315030                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          291599265                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         104199326                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     93203450                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 326                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                598                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           92                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              124250121                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     183                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1368397                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1289616                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         2048                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1289383                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2091                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation        11973                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1204148                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores      1204762                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       144864                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        185613                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       147075                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        188044                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 444381                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  624509                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1115710                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            97447803                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 444671                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  622988                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1195662                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            97449431                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              24155878                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21759886                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              18921                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   1617                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               1111435                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewDispLoadInsts              24155645                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21760500                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              18936                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   1589                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               1191442                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents          11973                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         249911                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       221890                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               471801                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              93685311                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23691817                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            792844                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect         249986                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       222081                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               472067                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              93691189                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23695668                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            793598                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         14046                       # number of nop insts executed
-system.cpu.iew.exec_refs                     44616394                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14207133                       # Number of branches executed
-system.cpu.iew.exec_stores                   20924577                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.256397                       # Inst execution rate
-system.cpu.iew.wb_sent                       93308677                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      93201392                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  44951021                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  76633881                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.249907                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.586569                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         5894305                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                         14076                       # number of nop insts executed
+system.cpu.iew.exec_refs                     44621004                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14207535                       # Number of branches executed
+system.cpu.iew.exec_stores                   20925336                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.233361                       # Inst execution rate
+system.cpu.iew.wb_sent                       93310594                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      93203542                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  44951761                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  76639550                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.226942                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.586535                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         5895620                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            431064                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     70277782                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.290424                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.118209                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            431354                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     71312758                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.271696                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.107515                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     36842990     52.42%     52.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     16674938     23.73%     76.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4291723      6.11%     82.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4149088      5.90%     88.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1947878      2.77%     90.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1240751      1.77%     92.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       737656      1.05%     93.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       580756      0.83%     94.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3812002      5.42%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     37859507     53.09%     53.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     16683603     23.39%     76.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4297164      6.03%     82.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4156384      5.83%     88.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1956005      2.74%     91.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1240140      1.74%     92.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       732437      1.03%     93.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       578410      0.81%     94.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3809108      5.34%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     70277782                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     71312758                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             70913204                       # Number of instructions committed
 system.cpu.commit.committedOps               90688159                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -693,552 +704,552 @@ system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          90688159                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3812002                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    163022945                       # The number of ROB reads
-system.cpu.rob.rob_writes                   194122181                       # The number of ROB writes
-system.cpu.timesIdled                           54257                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         3333122                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               3809108                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    164062130                       # The number of ROB reads
+system.cpu.rob.rob_writes                   194125448                       # The number of ROB writes
+system.cpu.timesIdled                           54252                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         3694968                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    70907652                       # Number of Instructions Simulated
 system.cpu.committedOps                      90682607                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.051603                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.051603                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.950930                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.950930                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                101976703                       # number of integer regfile reads
-system.cpu.int_regfile_writes                56611271                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        60                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       48                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 345090037                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 38758670                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                44101489                       # number of misc regfile reads
+system.cpu.cpi                               1.071311                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.071311                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.933436                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.933436                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                101982930                       # number of integer regfile reads
+system.cpu.int_regfile_writes                56612163                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       45                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 345107562                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 38759661                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                44102170                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements            484862                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           510.874566                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40338135                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            485374                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             83.107325                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         151605500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   510.874566                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997802                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997802                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements            484814                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           510.868965                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40339815                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            485326                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             83.119007                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         154595500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   510.868965                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997791                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997791                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          456                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          84467396                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         84467396                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     21414103                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21414103                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18832546                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18832546                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        60212                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         60212                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        15310                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        15310                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          84466838                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         84466838                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     21417711                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21417711                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18830642                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18830642                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        60188                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         60188                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15309                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15309                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40246649                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40246649                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40306861                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40306861                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       566310                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        566310                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1017355                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1017355                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        68643                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        68643                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data          613                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total          613                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1583665                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1583665                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1652308                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1652308                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  13581553500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  13581553500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  13903205430                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  13903205430                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5738500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      5738500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  27484758930                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  27484758930                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  27484758930                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  27484758930                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     21980413                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     21980413                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      40248353                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40248353                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40308541                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40308541                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       562442                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        562442                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1019259                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1019259                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        68672                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        68672                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data          614                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total          614                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1581701                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1581701                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1650373                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1650373                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14412910000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14412910000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  14258561428                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  14258561428                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5705500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      5705500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  28671471428                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  28671471428                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  28671471428                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  28671471428                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     21980153                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     21980153                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       128855                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       128855                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       128860                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       128860                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15923                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15923                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41830314                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41830314                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     41959169                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     41959169                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025764                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.025764                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051252                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.051252                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532715                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.532715                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.038498                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.038498                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037859                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037859                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.039379                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.039379                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23982.542247                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 23982.542247                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13666.031454                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 13666.031454                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9361.337684                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9361.337684                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 17355.159664                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 17355.159664                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16634.161990                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16634.161990                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           36                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      2820837                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          130956                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     7.200000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    21.540342                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       484862                       # number of writebacks
-system.cpu.dcache.writebacks::total            484862                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       267183                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       267183                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       868792                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       868792                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          613                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total          613                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1135975                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1135975                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1135975                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1135975                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299127                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       299127                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148563                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       148563                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37696                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        37696                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       447690                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       447690                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       485386                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       485386                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6671017500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6671017500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2276896471                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2276896471                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1910092000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1910092000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8947913971                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   8947913971                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10858005971                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10858005971                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013609                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013609                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     41830054                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41830054                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     41958914                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     41958914                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025589                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.025589                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051348                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.051348                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532919                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.532919                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.038561                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.038561                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037813                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037813                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.039333                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.039333                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.593395                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.593395                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13989.144494                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 13989.144494                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9292.345277                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9292.345277                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18126.985712                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18126.985712                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17372.722062                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17372.722062                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          115                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      2956958                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                15                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          131265                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     7.666667                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    22.526629                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks       484814                       # number of writebacks
+system.cpu.dcache.writebacks::total            484814                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       263368                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       263368                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870698                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       870698                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          614                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total          614                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1134066                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1134066                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1134066                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1134066                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299074                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       299074                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148561                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       148561                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37704                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        37704                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       447635                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       447635                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       485339                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       485339                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   7124794500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   7124794500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2343478471                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2343478471                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1981400500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1981400500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9468272971                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9468272971                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11449673471                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11449673471                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013607                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013607                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007484                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007484                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.292546                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.292546                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010703                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.010703                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011568                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.011568                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22301.622722                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22301.622722                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15326.134172                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15326.134172                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50670.946520                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50670.946520                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19986.852445                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19986.852445                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22369.837554                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22369.837554                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements            325915                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.404253                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22094458                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            326427                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             67.685755                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        1157973500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.404253                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996883                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996883                       # Average percentage of cache occupancy
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.292597                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.292597                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010701                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.010701                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011567                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.011567                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23822.848191                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23822.848191                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15774.520036                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15774.520036                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52551.466688                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52551.466688                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21151.770909                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 21151.770909                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23591.084728                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23591.084728                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements            325639                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.373274                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22095836                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            326151                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             67.747258                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        1176670500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.373274                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996823                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996823                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           27                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          329                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4            8                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           67                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          328                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          45190725                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         45190725                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     22094458                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22094458                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      22094458                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22094458                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     22094458                       # number of overall hits
-system.cpu.icache.overall_hits::total        22094458                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       337685                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        337685                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       337685                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         337685                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       337685                       # number of overall misses
-system.cpu.icache.overall_misses::total        337685                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   5566889382                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   5566889382                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   5566889382                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   5566889382                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   5566889382                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   5566889382                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22432143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22432143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22432143                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22432143                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22432143                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22432143                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015054                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.015054                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.015054                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.015054                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.015054                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.015054                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16485.450589                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16485.450589                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16485.450589                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16485.450589                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16485.450589                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16485.450589                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       546680                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           53                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs             25668                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          45192862                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45192862                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     22095836                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22095836                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22095836                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22095836                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22095836                       # number of overall hits
+system.cpu.icache.overall_hits::total        22095836                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       337513                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        337513                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       337513                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         337513                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       337513                       # number of overall misses
+system.cpu.icache.overall_misses::total        337513                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   5817859355                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   5817859355                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   5817859355                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   5817859355                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   5817859355                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   5817859355                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22433349                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22433349                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22433349                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22433349                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22433349                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22433349                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015045                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.015045                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.015045                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.015045                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.015045                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.015045                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17237.437832                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 17237.437832                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 17237.437832                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 17237.437832                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 17237.437832                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 17237.437832                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       562602                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           94                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs             26054                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    21.298114                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    26.500000                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks       325915                       # number of writebacks
-system.cpu.icache.writebacks::total            325915                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        11245                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        11245                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        11245                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        11245                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        11245                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        11245                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       326440                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       326440                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       326440                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       326440                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       326440                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       326440                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   5156036946                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   5156036946                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   5156036946                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   5156036946                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   5156036946                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   5156036946                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014552                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014552                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014552                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.014552                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014552                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.014552                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15794.746189                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15794.746189                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15794.746189                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15794.746189                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15794.746189                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15794.746189                       # average overall mshr miss latency
-system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.prefetcher.num_hwpf_issued       822007                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       825699                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         3235                       # number of redundant prefetches already in prefetch queue
+system.cpu.icache.avg_blocked_cycles::no_mshrs    21.593690                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           47                       # average number of cycles each access was blocked
+system.cpu.icache.writebacks::writebacks       325639                       # number of writebacks
+system.cpu.icache.writebacks::total            325639                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        11348                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        11348                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        11348                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        11348                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        11348                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        11348                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       326165                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       326165                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       326165                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       326165                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       326165                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       326165                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   5383419413                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   5383419413                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   5383419413                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   5383419413                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   5383419413                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   5383419413                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014539                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014539                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014539                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.014539                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014539                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.014539                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16505.202621                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16505.202621                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16505.202621                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16505.202621                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16505.202621                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16505.202621                       # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.prefetcher.num_hwpf_issued       823055                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       826389                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         2921                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        78661                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           125486                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        15697.579441                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             682126                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           141813                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.810039                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage        78691                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           125520                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        15698.936659                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             681800                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           141835                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.806994                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15632.148504                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    65.430937                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.954111                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.003994                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.958104                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022           23                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        16304                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 15629.036475                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    69.900184                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.953921                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.004266                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.958187                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022           27                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        16288                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3           12                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2745                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12082                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          548                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          792                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.001404                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995117                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         25510486                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        25510486                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       254711                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       254711                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       476176                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       476176                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       137223                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       137223                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       289219                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       289219                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       256138                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       256138                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       289219                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       393361                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          682580                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       289219                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       393361                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         682580                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           12                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           12                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        11378                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        11378                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        37206                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        37206                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        80635                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        80635                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        37206                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        92013                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        129219                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        37206                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        92013                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       129219                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1158421000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1158421000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2926655500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   2926655500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   6384062000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   6384062000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   2926655500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   7542483000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10469138500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   2926655500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   7542483000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10469138500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       254711                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       254711                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       476176                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       476176                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           12                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           12                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       148601                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       148601                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       326425                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       326425                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       336773                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       336773                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       326425                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       485374                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       811799                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       326425                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       485374                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       811799                       # number of overall (read+write) accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3           14                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4            4                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2543                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12218                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          510                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          881                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.001648                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         25499859                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        25499859                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks       257633                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       257633                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       472926                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       472926                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       137172                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       137172                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       289056                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       289056                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       255940                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       255940                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       289056                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       393112                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          682168                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       289056                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       393112                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         682168                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        11425                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        11425                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        37095                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        37095                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        80789                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        80789                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        37095                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        92214                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        129309                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        37095                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        92214                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       129309                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1226064500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1226064500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   3155473000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   3155473000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   6910815500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   6910815500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   3155473000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   8136880000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  11292353000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   3155473000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   8136880000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  11292353000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       257633                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       257633                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       472926                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       472926                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           13                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           13                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       148597                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       148597                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       326151                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       326151                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       336729                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       336729                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       326151                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       485326                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       811477                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       326151                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       485326                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       811477                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.076567                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.076567                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.113980                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.113980                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.239434                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.239434                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.113980                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.189571                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.159176                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.113980                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.189571                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.159176                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101812.357181                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101812.357181                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78660.847713                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78660.847713                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79172.344515                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79172.344515                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78660.847713                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81971.927880                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81018.569251                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78660.847713                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81971.927880                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81018.569251                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.076886                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.076886                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.113736                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.113736                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.239923                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.239923                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.113736                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.190004                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.159350                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.113736                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.190004                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.159350                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107314.179431                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107314.179431                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85064.644831                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85064.644831                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85541.540309                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85541.540309                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85064.644831                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88239.096016                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 87328.438082                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85064.644831                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88239.096016                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 87328.438082                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.unused_prefetches              412                       # number of HardPF blocks evicted w/o reference
-system.cpu.l2cache.writebacks::writebacks        97262                       # number of writebacks
-system.cpu.l2cache.writebacks::total            97262                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         2980                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         2980                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           28                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           28                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          115                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          115                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           28                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         3095                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         3123                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           28                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         3095                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         3123                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       115252                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       115252                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           12                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           12                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8398                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         8398                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        37178                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        37178                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        80520                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        80520                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        37178                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        88918                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       126096                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        37178                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        88918                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       115252                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       241348                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher   9954483724                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total   9954483724                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       185500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       185500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    680267500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    680267500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2701591500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2701591500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   5893524000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   5893524000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2701591500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6573791500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9275383000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2701591500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6573791500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher   9954483724                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  19229866724                       # number of overall MSHR miss cycles
+system.cpu.l2cache.unused_prefetches              452                       # number of HardPF blocks evicted w/o reference
+system.cpu.l2cache.writebacks::writebacks        97298                       # number of writebacks
+system.cpu.l2cache.writebacks::total            97298                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3085                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         3085                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           23                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           23                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          119                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          119                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           23                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         3204                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         3227                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           23                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         3204                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         3227                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       115310                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       115310                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8340                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         8340                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        37072                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        37072                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        80670                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        80670                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        37072                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        89010                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       126082                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        37072                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        89010                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       115310                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       241392                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10321796922                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10321796922                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       201500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       201500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    722790000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    722790000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2931479000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2931479000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   6418843000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   6418843000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2931479000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7141633000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10073112000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2931479000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7141633000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10321796922                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20394908922                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.056514                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.056514                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.113894                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.113894                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.239093                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.239093                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.113894                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.183195                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.155329                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.113894                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.183195                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.056125                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.056125                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.113665                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.113665                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.239570                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.239570                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.113665                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.183402                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.155373                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.113665                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.183402                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.297300                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 86371.461875                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15458.333333                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15458.333333                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81003.512741                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81003.512741                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72666.402173                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72666.402173                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73193.293592                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73193.293592                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72666.402173                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73930.941991                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73558.106522                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72666.402173                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73930.941991                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79676.925949                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      1622603                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       810817                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        79904                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops        18775                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops        18774                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.297472                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89513.458694                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        15500                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        15500                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86665.467626                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86665.467626                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79075.285930                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79075.285930                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79569.145903                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79569.145903                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79075.285930                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80234.052354                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79893.339255                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79075.285930                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80234.052354                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84488.752411                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      1621957                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       810494                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        79908                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops        18773                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops        18772                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp        663212                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       351973                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       556066                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        28224                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       144126                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           12                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           12                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       148601                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       148601                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       326440                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       336773                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       978779                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1455634                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2434413                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41749696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     62095104                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          103844800                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      269627                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               6225728                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      1081438                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.091286                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.288019                       # Request fanout histogram
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp        662893                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       354931                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       552820                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        28222                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       146565                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           13                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           13                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       148597                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       148597                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       326165                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       336729                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       977954                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1455492                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2433446                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41714496                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     62088960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          103803456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      272099                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               6227968                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      1083589                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.091107                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.287765                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             982719     90.87%     90.87% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              98718      9.13%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             984867     90.89%     90.89% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              98721      9.11%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1081438                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1622078500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          4.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     489794228                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1083589                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1621431500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          4.3                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     489373744                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     728148836                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          2.0                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests        348072                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       205263                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.respLayer1.occupancy     728066857                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.9                       # Layer utilization (%)
+system.membus.snoop_filter.tot_requests        348152                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       205320                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  37283333000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp             214175                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        97262                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            28224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               12                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              8398                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             8398                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        214176                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       570645                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 570645                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     20469440                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20469440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp             214278                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        97298                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            28222                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               13                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              8340                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             8340                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        214279                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       570770                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 570770                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     20474624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20474624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            222586                       # Request fanout histogram
+system.membus.snoop_fanout::samples            222632                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  222586    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  222632    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              222586                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           837454269                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              222632                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           835899979                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1175863136                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              3.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1175524166                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              3.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
index 10131fd38..0a31f5d4d 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
@@ -149,7 +149,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -583,7 +583,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -643,7 +643,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -760,6 +760,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -779,29 +780,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -821,6 +829,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -852,9 +861,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout
index cd35cd53a..871055fe1 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:29
-gem5 executing on e108600-lin, pid 4307
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:45
+gem5 executing on e108600-lin, pid 28067
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -26,4 +26,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 1219570622500 because target called exit()
+Exiting @ tick 1241902335500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
index d8a41d287..5d202194f 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.222275                       # Number of seconds simulated
-sim_ticks                                1222274983500                       # Number of ticks simulated
-final_tick                               1222274983500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.241902                       # Number of seconds simulated
+sim_ticks                                1241902335500                       # Number of ticks simulated
+final_tick                               1241902335500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 407632                       # Simulator instruction rate (inst/s)
-host_op_rate                                   407632                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              272801132                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 256700                       # Number of bytes of host memory used
-host_seconds                                  4480.46                       # Real time elapsed on the host
+host_inst_rate                                 311711                       # Simulator instruction rate (inst/s)
+host_op_rate                                   311711                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              211957790                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254092                       # Number of bytes of host memory used
+host_seconds                                  5859.20                       # Real time elapsed on the host
 sim_insts                                  1826378509                       # Number of instructions simulated
 sim_ops                                    1826378509                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1222274983500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst             61440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         126177664                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            126239104                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        61440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           61440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     66092544                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          66092544                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                960                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1971526                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1972486                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1032696                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1032696                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                50267                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            103231814                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               103282081                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           50267                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              50267                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          54073384                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               54073384                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          54073384                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               50267                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           103231814                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              157355465                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1972486                       # Number of read requests accepted
-system.physmem.writeReqs                      1032696                       # Number of write requests accepted
-system.physmem.readBursts                     1972486                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1032696                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                126156992                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     82112                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  66090816                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 126239104                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               66092544                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1283                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1241902335500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst             61632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         126178240                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            126239872                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        61632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           61632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     66092288                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          66092288                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                963                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1971535                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1972498                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1032692                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1032692                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                49627                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            101600775                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               101650402                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           49627                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              49627                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          53218587                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               53218587                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          53218587                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               49627                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           101600775                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              154868990                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1972498                       # Number of read requests accepted
+system.physmem.writeReqs                      1032692                       # Number of write requests accepted
+system.physmem.readBursts                     1972498                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1032692                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                126161536                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     78336                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  66090880                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 126239872                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               66092288                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1224                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              119355                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              114736                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116711                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              118315                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              118360                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              118227                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              120694                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              125539                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              127875                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130856                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             129453                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             131175                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126741                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125953                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             123325                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123888                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              119357                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              114729                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116715                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              118322                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              118352                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              118237                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              120696                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              125562                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              127868                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130858                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             129451                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             131187                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             126743                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125956                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             123338                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123903                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               62004                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               62322                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               61319                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               62011                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               62436                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63988                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               65064                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               66489                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               66234                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               66705                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              66339                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              66709                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              65174                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              65212                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              65629                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              65034                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               62324                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               61320                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               62012                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               62437                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63989                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               65066                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               66492                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               66230                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66701                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              66337                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              66707                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              65162                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              65226                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              65630                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              65033                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1222274866500                       # Total gap between requests
+system.physmem.totGap                    1241902212500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1972486                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1972498                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1032696                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1847755                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    123438                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1032692                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1834002                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    137262                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    30048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    31196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    55895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    61015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    61109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    61152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61085                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61071                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    61067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    61245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    61296                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    60829                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    60715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    60557                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    28680                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    29758                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    55879                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    61072                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    61319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    61406                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61215                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    61200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    61213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    61359                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    61719                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61033                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    60943                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
@@ -194,137 +194,147 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1846311                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      104.123632                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.172382                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     131.523418                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1463397     79.26%     79.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       266113     14.41%     93.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        48771      2.64%     96.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20101      1.09%     97.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        12770      0.69%     98.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7489      0.41%     98.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5280      0.29%     98.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4734      0.26%     99.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        17656      0.96%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1846311                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         60557                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.510131                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       23.099317                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      136.122575                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           60389     99.72%     99.72% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023          130      0.21%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            8      0.01%     99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1848577                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.999494                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.158472                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     130.975371                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1464855     79.24%     79.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       267102     14.45%     93.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        48426      2.62%     96.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20608      1.11%     97.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12613      0.68%     98.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7404      0.40%     98.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5582      0.30%     98.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         4649      0.25%     99.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        17338      0.94%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1848577                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         60747                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.448697                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       23.033030                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      139.766082                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           60580     99.73%     99.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023          126      0.21%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535           11      0.02%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1536-2047            5      0.01%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-2559            4      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2560-3071            4      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-3583            1      0.00%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-4095            4      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4608-5119            4      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583            2      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095            3      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-4607            3      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4608-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::9216-9727            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-12799            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::12800-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60557                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         60557                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.052843                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.021089                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.041900                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              29161     48.15%     48.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1164      1.92%     50.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              28160     46.50%     96.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               2021      3.34%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 45      0.07%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  6      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60557                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    36942736250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               73902792500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9856015000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18741.21                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           60747                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         60747                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.999523                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.968024                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.037878                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              30790     50.69%     50.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1097      1.81%     52.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              26995     44.44%     96.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1834      3.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 26      0.04%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  5      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           60747                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    58523135000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               95484522500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9856370000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       29687.98                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37491.21                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         103.21                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          54.07                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      103.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       54.07                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  48437.98                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         101.59                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          53.22                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      101.65                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       53.22                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.23                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.81                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           1.21                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.79                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.42                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.40                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     727606                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    429946                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   36.91                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  41.63                       # Row buffer hit rate for writes
-system.physmem.avgGap                       406722.41                       # Average gap between requests
-system.physmem.pageHitRate                      38.53                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6766986240                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3692304000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7425061800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3276501840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            79832731680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           416045775330                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           368409693000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             885449053890                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              724.429872                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   610096075500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     40814280000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    571360638500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7191102240                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3923716500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7949838000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3415193280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            79832731680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           427319070030                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           358520838000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             888152489730                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              726.641687                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   593574305750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     40814280000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    587881640500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1222274983500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               246953326                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186908369                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15587365                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            168276583                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               165592346                       # Number of BTB hits
+system.physmem.avgWrQLen                        25.33                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     727297                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    428065                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   36.89                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.45                       # Row buffer hit rate for writes
+system.physmem.avgGap                       413252.48                       # Average gap between requests
+system.physmem.pageHitRate                      38.46                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 6395269440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3399162525                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6797065800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               2639461680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           75004519200.000015                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            46893448560                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             2685169920                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy      246120093660                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       85384513440                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        94763106600                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             570117979365                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              459.068285                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           1131989083250                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     3611832250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     31797904000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   369900280750                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 222356311250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     74502708250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 539733299000                       # Time in different power states
+system.physmem_1.actEnergy                 6803606040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3616187190                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7277830560                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               2751075720                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           76383156720.000015                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            47598512910                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             2658705600                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy      254833635780                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       85755552000                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        89279622225                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             576994094775                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              464.605041                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           1130512338500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     3468880500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     32377406000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   348347909000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 223320346000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     75543655250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 558844138750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1241902335500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               246965199                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186917374                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15586746                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            168139701                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               165606683                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.404866                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18556185                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             105918                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups             315                       # Number of indirect predictor lookups.
+system.cpu.branchPred.BTBHitPct             98.493504                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18556232                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             106082                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups             314                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits                 63                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses              252                       # Number of indirect misses.
+system.cpu.branchPred.indirectMisses              251                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted          101                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    453405484                       # DTB read hits
-system.cpu.dtb.read_misses                    5001335                       # DTB read misses
+system.cpu.dtb.read_hits                    453404968                       # DTB read hits
+system.cpu.dtb.read_misses                    5001226                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                458406819                       # DTB read accesses
-system.cpu.dtb.write_hits                   161377349                       # DTB write hits
-system.cpu.dtb.write_misses                   1709149                       # DTB write misses
+system.cpu.dtb.read_accesses                458406194                       # DTB read accesses
+system.cpu.dtb.write_hits                   161377184                       # DTB write hits
+system.cpu.dtb.write_misses                   1709229                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               163086498                       # DTB write accesses
-system.cpu.dtb.data_hits                    614782833                       # DTB hits
-system.cpu.dtb.data_misses                    6710484                       # DTB misses
+system.cpu.dtb.write_accesses               163086413                       # DTB write accesses
+system.cpu.dtb.data_hits                    614782152                       # DTB hits
+system.cpu.dtb.data_misses                    6710455                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                621493317                       # DTB accesses
-system.cpu.itb.fetch_hits                   600105517                       # ITB hits
+system.cpu.dtb.data_accesses                621492607                       # DTB accesses
+system.cpu.itb.fetch_hits                   600133421                       # ITB hits
 system.cpu.itb.fetch_misses                        19                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               600105536                       # ITB accesses
+system.cpu.itb.fetch_accesses               600133440                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -338,16 +348,16 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    1222274983500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       2444549967                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    1241902335500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       2483804671                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1826378509                       # Number of instructions committed
 system.cpu.committedOps                    1826378509                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      55126564                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      55133015                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.338468                       # CPI: cycles per instruction
-system.cpu.ipc                               0.747123                       # IPC: instructions per cycle
+system.cpu.cpi                               1.359962                       # CPI: cycles per instruction
+system.cpu.ipc                               0.735315                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass            83736345      4.58%      4.58% # Class of committed instruction
 system.cpu.op_class_0::IntAlu              1129914150     61.87%     66.45% # Class of committed instruction
 system.cpu.op_class_0::IntMult                     75      0.00%     66.45% # Class of committed instruction
@@ -383,107 +393,107 @@ system.cpu.op_class_0::MemWrite             162429806      8.89%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total               1826378509                       # Class of committed instruction
-system.cpu.tickCycles                      2082292947                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       362257020                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           9121995                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4080.838657                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           602779955                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9126091                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             66.050180                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       16887433500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4080.838657                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.996299                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.996299                       # Average percentage of cache occupancy
+system.cpu.tickCycles                      2082494897                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       401309774                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           9121955                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4080.932596                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           602775567                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9126051                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             66.049989                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       17009517500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4080.932596                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.996321                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.996321                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1547                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2420                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           71                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1466                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2515                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           72                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1233656307                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1233656307                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1222274983500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    444297476                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       444297476                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    158482479                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      158482479                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     602779955                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        602779955                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    602779955                       # number of overall hits
-system.cpu.dcache.overall_hits::total       602779955                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7239130                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7239130                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2246023                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2246023                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      9485153                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9485153                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9485153                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9485153                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 185791393500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 185791393500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 110650401500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 110650401500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 296441795000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 296441795000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 296441795000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 296441795000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    451536606                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    451536606                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses        1233653477                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1233653477                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1241902335500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    444296125                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       444296125                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    158479442                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      158479442                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     602775567                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        602775567                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    602775567                       # number of overall hits
+system.cpu.dcache.overall_hits::total       602775567                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7239086                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7239086                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2249060                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2249060                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      9488146                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9488146                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9488146                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9488146                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 201399177000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 201399177000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 119572112000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 119572112000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 320971289000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 320971289000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 320971289000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 320971289000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    451535211                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    451535211                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    612265108                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    612265108                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    612265108                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    612265108                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    612263713                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    612263713                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    612263713                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    612263713                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016032                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.016032                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013974                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013974                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.015492                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.015492                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.015492                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.015492                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25664.878722                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25664.878722                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49265.034908                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 49265.034908                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31253.243358                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31253.243358                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31253.243358                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31253.243358                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013993                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013993                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.015497                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.015497                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.015497                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.015497                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27821.078103                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 27821.078103                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53165.372200                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53165.372200                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33828.662523                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33828.662523                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 33828.662523                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 33828.662523                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      3671998                       # number of writebacks
-system.cpu.dcache.writebacks::total           3671998                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          362                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          362                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       358700                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       358700                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       359062                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       359062                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       359062                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       359062                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238768                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7238768                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887323                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1887323                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9126091                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9126091                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9126091                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9126091                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 178546113500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 178546113500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  85195528000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  85195528000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263741641500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 263741641500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263741641500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 263741641500                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      3671979                       # number of writebacks
+system.cpu.dcache.writebacks::total           3671979                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          365                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          365                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       361730                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       361730                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       362095                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       362095                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       362095                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       362095                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238721                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7238721                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887330                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1887330                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9126051                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9126051                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9126051                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9126051                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194152625000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 194152625000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  91149337000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  91149337000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 285301962000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 285301962000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 285301962000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 285301962000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016031                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016031                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011742                       # mshr miss rate for WriteReq accesses
@@ -492,67 +502,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014905
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014905                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014905                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014905                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24665.262583                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24665.262583                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45140.936660                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45140.936660                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28899.738289                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28899.738289                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28899.738289                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28899.738289                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26821.399112                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26821.399112                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48295.389254                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48295.389254                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31262.367699                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 31262.367699                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31262.367699                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 31262.367699                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           752.723923                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           600104557                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               960                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          625108.913542                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           754.212981                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           600132458                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               963                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          623190.506750                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   752.723923                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.367541                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.367541                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          957                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   754.212981                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.368268                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.368268                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          960                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          876                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.467285                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1200211994                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1200211994                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1222274983500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    600104557                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       600104557                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     600104557                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        600104557                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    600104557                       # number of overall hits
-system.cpu.icache.overall_hits::total       600104557                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          960                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           960                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          960                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            960                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          960                       # number of overall misses
-system.cpu.icache.overall_misses::total           960                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     77923500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     77923500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     77923500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     77923500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     77923500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     77923500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    600105517                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    600105517                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    600105517                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    600105517                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    600105517                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    600105517                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4          879                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.468750                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        1200267805                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1200267805                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1241902335500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    600132458                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       600132458                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     600132458                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        600132458                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    600132458                       # number of overall hits
+system.cpu.icache.overall_hits::total       600132458                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          963                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           963                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          963                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            963                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          963                       # number of overall misses
+system.cpu.icache.overall_misses::total           963                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     93461000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     93461000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     93461000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     93461000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     93461000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     93461000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    600133421                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    600133421                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    600133421                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    600133421                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    600133421                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    600133421                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81170.312500                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 81170.312500                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 81170.312500                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 81170.312500                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 81170.312500                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 81170.312500                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 97051.921080                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 97051.921080                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 97051.921080                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 97051.921080                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 97051.921080                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 97051.921080                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -561,262 +571,262 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.writebacks::writebacks            3                       # number of writebacks
 system.cpu.icache.writebacks::total                 3                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          960                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          960                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          960                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          960                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          960                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          960                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     76963500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     76963500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     76963500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     76963500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     76963500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     76963500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          963                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          963                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          963                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          963                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          963                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          963                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     92498000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     92498000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     92498000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     92498000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     92498000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     92498000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80170.312500                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80170.312500                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80170.312500                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 80170.312500                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80170.312500                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 80170.312500                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements          1940039                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31449.191087                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           16276000                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1972807                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             8.250173                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      89114668000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     7.970416                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    42.267708                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31398.952962                       # Average occupied blocks per requestor
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 96051.921080                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 96051.921080                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 96051.921080                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 96051.921080                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 96051.921080                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 96051.921080                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements          1940051                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31462.306469                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           16275911                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1972819                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             8.250078                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      89697966000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks     7.975185                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    42.025867                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31412.305417                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000243                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001290                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.958220                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.959753                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001283                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.958627                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.960153                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1022                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2732                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7097                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21795                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          928                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2816                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7096                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21807                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        147965199                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       147965199                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1222274983500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks      3671998                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      3671998                       # number of WritebackDirty hits
+system.cpu.l2cache.tags.tag_accesses        147964595                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       147964595                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1241902335500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3671979                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3671979                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks            3                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total            3                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1095273                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1095273                       # number of ReadExReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6059292                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6059292                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7154565                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7154565                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7154565                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7154565                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       792050                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       792050                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          960                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          960                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1095271                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1095271                       # number of ReadExReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6059245                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6059245                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7154516                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7154516                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      7154516                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7154516                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       792059                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       792059                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          963                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          963                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1179476                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total      1179476                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          960                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1971526                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1972486                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          960                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1971526                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1972486                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  70794470500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  70794470500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     75521000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     75521000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104049458500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 104049458500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     75521000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 174843929000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 174919450000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     75521000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 174843929000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 174919450000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      3671998                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      3671998                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.demand_misses::cpu.inst          963                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1971535                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1972498                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          963                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1971535                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1972498                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  76750433500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  76750433500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     91051000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     91051000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 119656496500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 119656496500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     91051000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 196406930000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 196497981000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     91051000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 196406930000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 196497981000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      3671979                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      3671979                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks            3                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total            3                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1887323                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1887323                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          960                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          960                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7238768                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7238768                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          960                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9126091                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9127051                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          960                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9126091                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9127051                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.419668                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.419668                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1887330                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1887330                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          963                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          963                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7238721                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7238721                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          963                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9126051                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9127014                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          963                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9126051                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9127014                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.419672                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.419672                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162939                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162939                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162940                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162940                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.216032                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.216114                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.216034                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.216116                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.216032                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.216114                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89381.314942                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89381.314942                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78667.708333                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78667.708333                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88216.681391                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88216.681391                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78667.708333                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88684.566676                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 88679.691516                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78667.708333                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88684.566676                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 88679.691516                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.216034                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.216116                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96899.894452                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96899.894452                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 94549.325026                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 94549.325026                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101448.860765                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 101448.860765                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 94549.325026                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99621.325515                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 99618.849297                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 94549.325026                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99621.325515                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 99618.849297                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks      1032696                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1032696                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1032692                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1032692                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          242                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          242                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       792050                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       792050                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          960                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          960                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       792059                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       792059                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          963                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          963                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1179476                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1179476                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          960                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1971526                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1972486                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          960                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1971526                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1972486                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  62873970500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  62873970500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     65921000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     65921000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  92254698500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  92254698500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     65921000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 155128669000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 155194590000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     65921000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 155128669000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 155194590000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          963                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1971535                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1972498                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          963                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1971535                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1972498                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  68829843500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  68829843500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     81421000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     81421000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 107861736500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 107861736500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     81421000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 176691580000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 176773001000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     81421000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 176691580000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 176773001000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.419668                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.419668                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.419672                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.419672                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162939                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162939                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162940                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162940                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216032                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.216114                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216034                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.216116                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216032                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.216114                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79381.314942                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79381.314942                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68667.708333                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68667.708333                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78216.681391                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78216.681391                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68667.708333                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78684.566676                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78679.691516                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68667.708333                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78684.566676                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78679.691516                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     18249049                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      9121998                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216034                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.216116                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86899.894452                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86899.894452                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 84549.325026                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 84549.325026                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 91448.860765                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 91448.860765                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84549.325026                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89621.325515                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89618.849297                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84549.325026                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89621.325515                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89618.849297                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests     18248972                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      9121958                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1439                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1439                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1442                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1442                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1222274983500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp       7239728                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      4704694                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1241902335500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp       7239684                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4704671                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6357340                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1887323                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1887323                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          960                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7238768                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1923                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27374177                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27376100                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    819077696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          819139328                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1940039                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              66092544                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     11067090                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::CleanEvict      6357335                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1887330                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1887330                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          963                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7238721                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1929                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27374057                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27375986                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61824                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    819073920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          819135744                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1940051                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic              66092288                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     11067065                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000130                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.011402                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.011414                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           11065651     99.99%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               1439      0.01%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11065623     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1442      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       11067090                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12796525500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11067065                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12796468000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1440000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1444500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13689136500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13689076500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests       3911328                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1938842                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests       3911349                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      1938851                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1222274983500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp            1180436                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1032696                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           906146                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            792050                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           792050                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1180436                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5883814                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5883814                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    192331648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               192331648                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED 1241902335500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp            1180439                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1032692                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           906159                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            792059                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           792059                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1180439                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5883847                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5883847                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    192332160                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               192332160                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           1972486                       # Request fanout histogram
+system.membus.snoop_fanout::samples           1972498                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 1972486    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 1972498    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             1972486                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8508050000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             1972498                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8507556000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        10787775250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        10783034500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index b191243cb..1d1d7a36d 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -591,7 +591,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -708,6 +708,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -727,29 +728,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -769,6 +777,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -800,9 +809,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
index e33a21652..03b7f79ab 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:29
-gem5 executing on e108600-lin, pid 4309
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:44
+gem5 executing on e108600-lin, pid 28058
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -26,4 +26,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 669587683000 because target called exit()
+Exiting @ tick 684199968000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 7435ab9ce..d6615dc1b 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.629948                       # Number of seconds simulated
-sim_ticks                                629947889500                       # Number of ticks simulated
-final_tick                               629947889500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.684200                       # Number of seconds simulated
+sim_ticks                                684199968000                       # Number of ticks simulated
+final_tick                               684199968000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 297749                       # Simulator instruction rate (inst/s)
-host_op_rate                                   297749                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              111692471                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 257464                       # Number of bytes of host memory used
-host_seconds                                  5640.02                       # Real time elapsed on the host
-sim_insts                                  1679312925                       # Number of instructions simulated
-sim_ops                                    1679312925                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 209715                       # Simulator instruction rate (inst/s)
+host_op_rate                                   209715                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               82651888                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254604                       # Number of bytes of host memory used
+host_seconds                                  8278.09                       # Real time elapsed on the host
+sim_insts                                  1736043781                       # Number of instructions simulated
+sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 629947889500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst             56512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         116052224                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            116108736                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        56512                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           56512                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65771840                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65771840                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                883                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1813316                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1814199                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1027685                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1027685                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                89709                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            184225118                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               184314827                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           89709                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              89709                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         104408382                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              104408382                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         104408382                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               89709                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           184225118                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              288723209                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1814199                       # Number of read requests accepted
-system.physmem.writeReqs                      1027685                       # Number of write requests accepted
-system.physmem.readBursts                     1814199                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1027685                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                116025984                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     82752                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65770240                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 116108736                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65771840                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1293                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.pwrStateResidencyTicks::UNDEFINED 684199968000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst             60736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         126674880                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            126735616                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        60736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           60736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     66206592                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          66206592                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                949                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1979295                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1980244                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1034478                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1034478                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                88769                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            185143066                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               185231836                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           88769                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              88769                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          96764974                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               96764974                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          96764974                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               88769                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           185143066                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              281996809                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1980244                       # Number of read requests accepted
+system.physmem.writeReqs                      1034478                       # Number of write requests accepted
+system.physmem.readBursts                     1980244                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1034478                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                126652288                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     83328                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  66205120                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 126735616                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               66206592                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1302                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              109825                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              106113                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              107421                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              108541                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              108748                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              108721                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              111475                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              116266                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              117532                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              120021                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             119000                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             120366                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             116224                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             115367                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             113352                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             113934                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61679                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               62003                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               61008                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61698                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               62148                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63666                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64723                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               66137                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65915                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               66335                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              66021                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              66389                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64907                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64927                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              65328                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64776                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              119682                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              115093                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              117079                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              118658                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              118799                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              118596                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              121104                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              126057                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              128556                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              131368                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             130043                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             131744                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             127398                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             126519                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             123764                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             124482                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               62070                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               62408                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               61409                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               62103                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               62566                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               64096                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               65160                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               66609                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               66404                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66820                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              66475                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              66816                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              65322                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              65320                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              65711                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              65166                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    629947397500                       # Total gap between requests
+system.physmem.totGap                    684199865500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1814199                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1980244                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1027685                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1469096                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    241446                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     70874                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     31473                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1034478                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1615224                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    253124                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     75634                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     34936                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        22                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -145,34 +145,34 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    25872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    27378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    51064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    57932                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    60149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    61085                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61761                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    63157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    65572                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61767                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    60670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    24649                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    26003                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    51175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    58148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    60543                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    61668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61807                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61824                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61855                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61800                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61827                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61964                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    62700                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    64398                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    66372                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    62691                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    62546                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
@@ -194,139 +194,149 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1631200                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      111.449220                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      84.546651                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     143.577205                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1240852     76.07%     76.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       269138     16.50%     92.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        51923      3.18%     95.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20333      1.25%     97.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        12353      0.76%     97.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         6354      0.39%     98.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4947      0.30%     98.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         3735      0.23%     98.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        21565      1.32%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1631200                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         60546                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.938741                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       22.568202                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      131.498063                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           60449     99.84%     99.84% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023           61      0.10%     99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1786108                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      107.975625                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      82.936522                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     138.228671                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1386417     77.62%     77.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       276583     15.49%     93.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52891      2.96%     96.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20920      1.17%     97.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12358      0.69%     97.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         6524      0.37%     98.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5164      0.29%     98.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3751      0.21%     98.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        21500      1.20%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1786108                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61165                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.352277                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       22.914892                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      140.448273                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           60991     99.72%     99.72% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023          137      0.22%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-1535            7      0.01%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047            6      0.01%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559            2      0.00%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            4      0.01%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            5      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2560-3071            4      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-3583            3      0.00%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-4095            2      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583            2      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095            3      0.00%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4608-5119            4      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::9216-9727            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-12799            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::12800-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60546                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         60546                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.973210                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.937472                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.113084                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              32669     53.96%     53.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1474      2.43%     56.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              22634     37.38%     93.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3027      5.00%     98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                624      1.03%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                106      0.18%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  9      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60546                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    37088946500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               71080934000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9064530000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20458.28                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::15360-15871            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           61165                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61165                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.912532                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.877578                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.101156                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              34708     56.74%     56.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1369      2.24%     58.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              21665     35.42%     94.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               2721      4.45%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                576      0.94%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                109      0.18%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 15      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           61165                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    56581400750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               93686563250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9894710000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       28591.74                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39208.28                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         184.18                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         104.41                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      184.31                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      104.41                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47341.74                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         185.11                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          96.76                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      185.23                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       96.76                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.25                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.44                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.82                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.10                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.61                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     781743                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    427619                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   43.12                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  41.61                       # Row buffer hit rate for writes
-system.physmem.avgGap                       221665.42                       # Average gap between requests
-system.physmem.pageHitRate                      42.57                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 5990438160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3268592250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6841434600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3259841760                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            41145046800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           279886127580                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           132453942750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             472845423900                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              750.611658                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   218497726500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     21035300000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    390413882500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 6341433840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3460107750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7299201000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3399395040                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            41145046800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           287961158835                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           125370582000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             474976925265                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              753.995279                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   206677750500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     21035300000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    402234088500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 629947889500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               393343738                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         308206683                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15638618                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            270406177                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               266678706                       # Number of BTB hits
+system.physmem.busUtil                           2.20                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.45                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.76                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.11                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.71                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     796002                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    431282                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   40.22                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.69                       # Row buffer hit rate for writes
+system.physmem.avgGap                       226952.89                       # Average gap between requests
+system.physmem.pageHitRate                      40.73                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 6177735060                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3283540260                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6819185520                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               2643517620                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           44816475600.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            37044798750                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             1443275040                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy      170396037690                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       31359460320                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        36616359660                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             340610162070                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              497.822532                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           599184631500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     1534958250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     18981984000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   143840379000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  81664935250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     64497738500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 373679973000                       # Time in different power states
+system.physmem_1.actEnergy                 6575111760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3494739600                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7310460360                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               2756337480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           45376412640.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            37526229300                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             1410684000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy      175219175340                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       30265452000                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        34407180735                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             344356241235                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              503.297652                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           598199672750                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     1433387500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     19217296000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   135130926250                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  78815070250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     65349556500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 384253731500                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 684199968000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               409436754                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         318234486                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15963820                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            282367334                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               278623697                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.621529                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                24232356                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 43                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups           11458                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits                743                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses            10715                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted           54                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             98.674196                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                26172484                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 47                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           12628                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits               1002                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            11626                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted           76                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    615604408                       # DTB read hits
-system.cpu.dtb.read_misses                   10829988                       # DTB read misses
+system.cpu.dtb.read_hits                    645003218                       # DTB read hits
+system.cpu.dtb.read_misses                   12159343                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                626434396                       # DTB read accesses
-system.cpu.dtb.write_hits                   204678819                       # DTB write hits
-system.cpu.dtb.write_misses                   7425838                       # DTB write misses
+system.cpu.dtb.read_accesses                657162561                       # DTB read accesses
+system.cpu.dtb.write_hits                   218108239                       # DTB write hits
+system.cpu.dtb.write_misses                   7507876                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               212104657                       # DTB write accesses
-system.cpu.dtb.data_hits                    820283227                       # DTB hits
-system.cpu.dtb.data_misses                   18255826                       # DTB misses
+system.cpu.dtb.write_accesses               225616115                       # DTB write accesses
+system.cpu.dtb.data_hits                    863111457                       # DTB hits
+system.cpu.dtb.data_misses                   19667219                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                838539053                       # DTB accesses
-system.cpu.itb.fetch_hits                   399075166                       # ITB hits
+system.cpu.dtb.data_accesses                882778676                       # DTB accesses
+system.cpu.itb.fetch_hits                   420694791                       # ITB hits
 system.cpu.itb.fetch_misses                        37                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               399075203                       # ITB accesses
+system.cpu.itb.fetch_accesses               420694828                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -339,751 +349,759 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                   23                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    629947889500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       1259895780                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                   29                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    684199968000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       1368399937                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          409587649                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3241372877                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   393343738                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          290911805                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     828631431                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                43212526                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles          431834940                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3410573803                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   409436754                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          304797183                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     913784247                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                45380414                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1670                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          106                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 399075166                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               7874466                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1259827144                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.572871                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.161590                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles          1708                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           42                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 420694791                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               8284167                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1368311169                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.492543                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.138689                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                668246093     53.04%     53.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 43806893      3.48%     56.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 23751936      1.89%     58.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 40823777      3.24%     61.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                134784051     10.70%     72.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 61318653      4.87%     77.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 43063501      3.42%     80.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 28777614      2.28%     82.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                215254626     17.09%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                743223403     54.32%     54.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 47685517      3.48%     57.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 24183643      1.77%     59.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 45097399      3.30%     62.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                142825430     10.44%     73.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 65953370      4.82%     78.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 43585313      3.19%     81.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 29408397      2.15%     83.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                226348697     16.54%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1259827144                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.312203                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.572731                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                336809889                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             370413676                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 497881112                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              33116842                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               21605625                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             58265374                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   679                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3099960384                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  1859                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               21605625                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                354079753                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               199727925                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           5296                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 510193154                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             174215391                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3021993285                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents               1813082                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               19910474                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents              129183664                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30561708                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2254247429                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3918399799                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3918272154                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            127644                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1331032194                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                923215197                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                126                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            124                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  94488821                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            681241316                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           255797496                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          84438658                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         55736283                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2741763403                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 107                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2499259906                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1517170                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined      1062450541                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    465504121                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             84                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1259827144                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.983812                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.153359                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1368311169                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.299208                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.492381                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                353769261                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             432754726                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 524267891                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              34829792                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               22689499                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             62032551                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   750                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3256358950                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2045                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               22689499                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                372017301                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               224454621                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           9976                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 537214927                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             211924845                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3173979679                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents               1947204                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               21862090                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents              161736150                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               34961727                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2371970000                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4117940809                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4117804241                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            136567                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                995767037                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                144                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            143                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  99713027                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            717292360                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           272467386                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          90468830                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         58360421                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2884387847                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 125                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2620166340                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1550282                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined      1148344190                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    502911540                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             96                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1368311169                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.914891                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.143845                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           494791866     39.27%     39.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           161324184     12.81%     52.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           149742004     11.89%     63.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           141543893     11.24%     75.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           119990032      9.52%     84.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            80369213      6.38%     91.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            66025796      5.24%     96.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            32462182      2.58%     98.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8            13577974      1.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           564702258     41.27%     41.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           169734991     12.40%     53.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           158008570     11.55%     65.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           149164272     10.90%     76.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           126054849      9.21%     85.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            84104604      6.15%     91.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            68048276      4.97%     96.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            34057471      2.49%     98.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8            14435878      1.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1259827144                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1368311169                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                12419183     35.12%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               18417667     52.09%     87.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4521757     12.79%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                13157745     35.86%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               18955564     51.66%     87.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4577828     12.48%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1641003125     65.66%     65.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                   98      0.00%     65.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              896111      0.04%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  23      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                 164      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 32      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                  26      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.70% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            640377775     25.62%     91.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           216982552      8.68%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1716973131     65.53%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                  113      0.00%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              895059      0.03%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  21      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                 165      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 32      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                  25      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            671607156     25.63%     91.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           230690638      8.80%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2499259906                       # Type of FU issued
-system.cpu.iq.rate                           1.983704                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    35358607                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014148                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6293293204                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3803117225                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2401572542                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             1929523                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            1233317                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       883284                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2533656719                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  961794                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         60564498                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2620166340                       # Type of FU issued
+system.cpu.iq.rate                           1.914766                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    36691137                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014003                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6644947058                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        4031627633                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2518705843                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1938210                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            1246935                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       885827                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2655891113                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  966364                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         69399237                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    251534222                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       355806                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       138747                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    101659209                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    272696697                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       372755                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       144718                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    111738884                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          256                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       6319064                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads          276                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       6347426                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               21605625                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               137066476                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              20199207                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2888644044                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           6351774                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             681241316                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            255797496                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                107                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 653480                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents              19719948                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         138747                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10434747                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8530204                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             18964951                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2455710851                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             626434405                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          43549049                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               22689499                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               153700665                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              24607409                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3035418130                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           6594075                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             717292360                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            272467386                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                125                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 793020                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              24069505                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         144718                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10634250                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8701065                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             19335315                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2575033857                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             657162570                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          45132483                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     146880534                       # number of nop insts executed
-system.cpu.iew.exec_refs                    838539129                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                303173790                       # Number of branches executed
-system.cpu.iew.exec_stores                  212104724                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.949138                       # Inst execution rate
-system.cpu.iew.wb_sent                     2430569294                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2402455826                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1423499549                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1834375042                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.906869                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.776013                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       934600585                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls              23                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15637980                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1130658933                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.557680                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.564025                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                     151030158                       # number of nop insts executed
+system.cpu.iew.exec_refs                    882778753                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                315511040                       # Number of branches executed
+system.cpu.iew.exec_stores                  225616183                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.881785                       # Inst execution rate
+system.cpu.iew.wb_sent                     2549403036                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2519591670                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1487461563                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1918503373                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.841268                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.775324                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       998993468                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          15963112                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1230277663                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.479162                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.528603                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    654603026     57.90%     57.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    156815138     13.87%     71.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     77634971      6.87%     78.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     50637990      4.48%     83.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28095009      2.48%     85.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     18859448      1.67%     87.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     19659708      1.74%     89.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     22259274      1.97%     90.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    102094369      9.03%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    741569515     60.28%     60.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    159647987     12.98%     73.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     79500884      6.46%     79.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     52016561      4.23%     83.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28471103      2.31%     86.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     19445294      1.58%     87.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     19999560      1.63%     89.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     23041626      1.87%     91.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    106585133      8.66%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1130658933                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts           1761204444                       # Number of instructions committed
-system.cpu.commit.committedOps             1761204444                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1230277663                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
+system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      583845365                       # Number of memory references committed
-system.cpu.commit.loads                     429707085                       # Number of loads committed
+system.cpu.commit.refs                      605324165                       # Number of memory references committed
+system.cpu.commit.loads                     444595663                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                  208988363                       # Number of branches committed
-system.cpu.commit.fp_insts                     805327                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1662744776                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             16089601                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass     81891519      4.65%      4.65% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu       1094662288     62.15%     66.80% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult              66      0.00%     66.80% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.80% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd         805058      0.05%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp             13      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt            100      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult            11      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv             24      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.85% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       429707085     24.40%     91.25% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      154138280      8.75%    100.00% # Class of committed instruction
+system.cpu.commit.branches                  214632552                       # Number of branches committed
+system.cpu.commit.fp_insts                     805525                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1718967519                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             16767440                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass     83736345      4.60%      4.60% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu       1129914149     62.09%     66.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult              75      0.00%     66.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.69% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd         805244      0.04%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp             13      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt            100      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult            11      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv             24      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       444595663     24.43%     91.17% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      160728502      8.83%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1761204444                       # Class of committed instruction
-system.cpu.commit.bw_lim_events             102094369                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3648383709                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5520911290                       # The number of ROB writes
-system.cpu.timesIdled                             650                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           68636                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1679312925                       # Number of Instructions Simulated
-system.cpu.committedOps                    1679312925                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.750245                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.750245                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.332898                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.332898                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3307128958                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1925697564                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                     36300                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      615                       # number of floating regfile writes
+system.cpu.commit.op_class_0::total        1819780126                       # Class of committed instruction
+system.cpu.commit.bw_lim_events             106585133                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3856686924                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5775715040                       # The number of ROB writes
+system.cpu.timesIdled                             709                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           88768                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
+system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.788229                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.788229                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.268667                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.268667                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3463738117                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2019389646                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                     39803                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      598                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 629947889500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           8606834                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4086.896222                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           685926884                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           8610930                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             79.657701                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        5135502500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4086.896222                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997777                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997777                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           9207265                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.531672                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           712311191                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9211361                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             77.329636                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        5174346500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.531672                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997933                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997933                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          950                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2966                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           55                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4           11                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          666                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2980                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          446                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1415363302                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1415363302                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 629947889500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    536911304                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       536911304                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    149015576                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      149015576                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1470218079                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1470218079                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 684199968000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    556814159                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       556814159                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    155497028                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      155497028                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data            4                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total            4                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     685926880                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        685926880                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    685926880                       # number of overall hits
-system.cpu.dcache.overall_hits::total       685926880                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     12326597                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      12326597                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      5122704                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      5122704                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     712311187                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        712311187                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    712311187                       # number of overall hits
+system.cpu.dcache.overall_hits::total       712311187                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     12960693                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      12960693                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5231474                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5231474                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     17449301                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       17449301                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     17449301                       # number of overall misses
-system.cpu.dcache.overall_misses::total      17449301                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 397459380500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 397459380500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 314315569058                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 314315569058                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        73500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        73500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 711774949558                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 711774949558                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 711774949558                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 711774949558                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    549237901                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    549237901                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    154138280                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    154138280                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     18192167                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       18192167                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     18192167                       # number of overall misses
+system.cpu.dcache.overall_misses::total      18192167                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 452018170000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 452018170000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 345871511780                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 345871511780                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        79500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        79500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 797889681780                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 797889681780                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 797889681780                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 797889681780                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    569774852                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    569774852                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data            5                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total            5                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    703376181                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    703376181                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    703376181                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    703376181                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022443                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.022443                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.033234                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.033234                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    730503354                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    730503354                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    730503354                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    730503354                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022747                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.022747                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032549                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032549                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.200000                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.200000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024808                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024808                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.024808                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.024808                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32244.047607                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32244.047607                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61357.355228                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61357.355228                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        73500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        73500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40791.029369                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40791.029369                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40791.029369                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40791.029369                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     16026921                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      9753373                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1104089                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           68174                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.515968                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   143.065876                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      3596228                       # number of writebacks
-system.cpu.dcache.writebacks::total           3596228                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5571741                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      5571741                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3266630                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3266630                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      8838371                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      8838371                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      8838371                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      8838371                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      6754856                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      6754856                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1856074                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1856074                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024904                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024904                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.024904                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.024904                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34876.080315                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34876.080315                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66113.587066                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 66113.587066                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        79500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        79500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 43858.968631                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 43858.968631                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 43858.968631                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 43858.968631                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     16718017                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets     10716708                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1109373                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           69036                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.069789                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   155.233617                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks      3713171                       # number of writebacks
+system.cpu.dcache.writebacks::total           3713171                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5628505                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      5628505                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3352302                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3352302                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      8980807                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      8980807                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      8980807                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      8980807                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7332188                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7332188                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879172                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1879172                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      8610930                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      8610930                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8610930                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8610930                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 164940989000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 164940989000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84797281851                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  84797281851                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        72500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        72500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 249738270851                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 249738270851                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 249738270851                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 249738270851                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.012299                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.012299                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.012042                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.012042                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9211360                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9211360                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9211360                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9211360                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194855974500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 194855974500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  91510360097                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  91510360097                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        78500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        78500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286366334597                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 286366334597                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286366334597                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 286366334597                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.012869                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.012869                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011692                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011692                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.200000                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.200000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012242                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.012242                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012242                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.012242                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24418.135487                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24418.135487                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45686.369105                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45686.369105                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        72500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        72500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29002.473699                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29002.473699                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29002.473699                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29002.473699                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 629947889500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           744.964371                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           399073789                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               883                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          451952.195923                       # Average number of references to valid blocks.
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012610                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.012610                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012610                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.012610                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26575.419847                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26575.419847                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48697.170933                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48697.170933                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        78500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        78500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31088.388099                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 31088.388099                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31088.388099                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 31088.388099                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements                 1                       # number of replacements
+system.cpu.icache.tags.tagsinuse           753.632230                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           420693280                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               949                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          443301.664910                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   744.964371                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.363752                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.363752                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          883                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          883                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.431152                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         798151215                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        798151215                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 629947889500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    399073789                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       399073789                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     399073789                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        399073789                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    399073789                       # number of overall hits
-system.cpu.icache.overall_hits::total       399073789                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1377                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1377                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1377                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1377                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1377                       # number of overall misses
-system.cpu.icache.overall_misses::total          1377                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    106712499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    106712499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    106712499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    106712499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    106712499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    106712499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    399075166                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    399075166                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    399075166                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    399075166                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    399075166                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    399075166                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000003                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000003                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000003                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000003                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000003                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000003                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77496.368192                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 77496.368192                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 77496.368192                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 77496.368192                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 77496.368192                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 77496.368192                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          390                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   753.632230                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.367984                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.367984                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          948                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          882                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.462891                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         841390531                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        841390531                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 684199968000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    420693280                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       420693280                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     420693280                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        420693280                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    420693280                       # number of overall hits
+system.cpu.icache.overall_hits::total       420693280                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1511                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1511                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1511                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1511                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1511                       # number of overall misses
+system.cpu.icache.overall_misses::total          1511                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    138965499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    138965499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    138965499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    138965499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    138965499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    138965499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    420694791                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    420694791                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    420694791                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    420694791                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    420694791                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    420694791                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91969.225017                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 91969.225017                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 91969.225017                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 91969.225017                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 91969.225017                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 91969.225017                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          347                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          130                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs   115.666667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          494                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          494                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          494                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          494                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          494                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          494                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          883                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          883                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          883                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          883                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          883                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          883                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75063499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     75063499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75063499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     75063499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75063499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     75063499                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
+system.cpu.icache.writebacks::total                 1                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          562                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          562                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          562                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          562                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          562                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          562                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          949                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          949                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          949                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          949                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          949                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          949                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     93919999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     93919999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     93919999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     93919999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     93919999                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     93919999                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85009.625142                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85009.625142                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85009.625142                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 85009.625142                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85009.625142                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 85009.625142                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 629947889500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements          1781749                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31982.912242                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           15403967                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1814517                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             8.489293                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      27850464000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     9.216492                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.928604                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31946.767147                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000281                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000822                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.974938                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.976041                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98967.332982                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98967.332982                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98967.332982                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 98967.332982                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98967.332982                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 98967.332982                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements          1947802                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32040.149631                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           16438766                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1980570                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             8.300018                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      28106474000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks     8.660797                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.112733                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 32006.376101                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000264                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000766                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.976757                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.977788                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          476                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4200                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        22514                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         5526                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3407                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          643                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13986                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        14548                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        139563701                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       139563701                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 629947889500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks      3596228                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      3596228                       # number of WritebackDirty hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1089344                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1089344                       # number of ReadExReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5708271                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      5708271                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.data      6797615                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         6797615                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      6797615                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        6797615                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       766745                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       766745                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          883                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          883                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1046571                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      1046571                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          883                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1813316                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1814199                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          883                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1813316                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1814199                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  70017625000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  70017625000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     73732000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     73732000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  93950720500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  93950720500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     73732000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 163968345500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 164042077500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     73732000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 163968345500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 164042077500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      3596228                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      3596228                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1856089                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1856089                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          883                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          883                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6754842                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      6754842                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          883                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      8610931                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      8611814                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          883                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      8610931                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      8611814                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413097                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.413097                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.tags.tag_accesses        149337178                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       149337178                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 684199968000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3713171                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3713171                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks            1                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total            1                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1095576                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1095576                       # number of ReadExReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6136490                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6136490                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7232066                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7232066                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      7232066                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7232066                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       783612                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       783612                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          949                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          949                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1195683                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      1195683                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          949                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1979295                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1980244                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          949                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1979295                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1980244                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  76631269000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  76631269000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     92491000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     92491000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 118466842500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 118466842500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     92491000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 195098111500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 195190602500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     92491000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 195098111500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 195190602500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      3713171                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      3713171                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks            1                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total            1                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1879188                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1879188                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          949                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          949                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7332173                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7332173                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          949                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9211361                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9212310                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          949                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9211361                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9212310                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.416995                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.416995                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.154936                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.154936                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.163073                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.163073                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.210583                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.210664                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.214875                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.214956                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.210583                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.210664                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91318.006638                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91318.006638                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83501.698754                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83501.698754                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89770.039969                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89770.039969                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83501.698754                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90424.584297                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 90421.214817                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83501.698754                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90424.584297                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 90421.214817                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.214875                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.214956                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97792.362802                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97792.362802                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 97461.538462                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 97461.538462                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99078.804750                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99078.804750                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 97461.538462                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98569.496462                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 98568.965491                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 97461.538462                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98569.496462                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 98568.965491                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks      1027685                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1027685                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          164                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          164                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       766745                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       766745                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          883                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          883                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1046571                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1046571                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          883                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1813316                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1814199                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          883                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1813316                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1814199                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  62350175000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  62350175000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     64902000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     64902000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  83485010500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  83485010500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     64902000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145835185500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 145900087500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64902000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145835185500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 145900087500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks      1034478                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1034478                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          240                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          240                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       783612                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       783612                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          949                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          949                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1195683                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1195683                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          949                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1979295                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1980244                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          949                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1979295                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1980244                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  68795149000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  68795149000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     83001000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     83001000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 106510012500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 106510012500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     83001000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 175305161500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 175388162500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     83001000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 175305161500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 175388162500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413097                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413097                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.416995                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.416995                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.154936                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.154936                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.163073                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.163073                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.210583                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.210664                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214875                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.214956                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.210583                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.210664                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81318.006638                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81318.006638                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73501.698754                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73501.698754                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79770.039969                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79770.039969                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73501.698754                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80424.584297                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80421.214817                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73501.698754                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80424.584297                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80421.214817                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     17218648                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      8606834                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214875                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.214956                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87792.362802                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87792.362802                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 87461.538462                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 87461.538462                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89078.804750                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89078.804750                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 87461.538462                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88569.496462                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88568.965491                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 87461.538462                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88569.496462                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88568.965491                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests     18419576                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      9207266                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1383                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1383                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1448                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1448                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 629947889500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp       6755724                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      4623913                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      5764670                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1856089                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1856089                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          883                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6754842                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1766                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     25828695                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          25830461                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56512                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    781258112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          781314624                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1781749                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              65771840                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     10393563                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000133                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.011535                       # Request fanout histogram
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 684199968000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp       7333122                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4747649                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6407418                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1879188                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1879188                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          949                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7332173                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1899                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27629987                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27631886                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        60800                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    827170048                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          827230848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1947802                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic              66206592                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     11160112                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000130                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.011390                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           10392180     99.99%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               1383      0.01%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11158664     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1448      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       10393563                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12205552000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11160112                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12922960000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1324500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1423500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   12916395000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests       3594729                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1780530                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.respLayer1.occupancy   13817041500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          2.0                       # Layer utilization (%)
+system.membus.snoop_filter.tot_requests       3926838                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      1946594                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 629947889500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp            1047454                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1027685                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           752845                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            766745                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           766745                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1047454                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5408928                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5408928                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    181880576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               181880576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED 684199968000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp            1196632                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1034478                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           912116                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            783612                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           783612                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1196632                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5907082                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5907082                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    192942208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               192942208                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           1814199                       # Request fanout histogram
+system.membus.snoop_fanout::samples           1980244                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 1814199    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 1980244    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             1814199                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8122837000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         9853981000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             1980244                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8533086500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        10770167500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
index 9ef5c346e..7df53f247 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
@@ -151,7 +151,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -631,7 +631,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -691,7 +691,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -880,6 +880,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -891,7 +892,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -899,29 +900,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -941,6 +949,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -972,9 +981,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout
index b6bf1e68a..b95f9cdb7 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timin
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:58:37
-gem5 executing on e108600-lin, pid 24092
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:43:01
+gem5 executing on e108600-lin, pid 17341
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -27,4 +27,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 1128033563500 because target called exit()
+Exiting @ tick 1150225722500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
index ddbab1eb8..16fb45e1d 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.130744                       # Number of seconds simulated
-sim_ticks                                1130744162500                       # Number of ticks simulated
-final_tick                               1130744162500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.150226                       # Number of seconds simulated
+sim_ticks                                1150225722500                       # Number of ticks simulated
+final_tick                               1150225722500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 210155                       # Simulator instruction rate (inst/s)
-host_op_rate                                   226410                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              153850224                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 274312                       # Number of bytes of host memory used
-host_seconds                                  7349.64                       # Real time elapsed on the host
+host_inst_rate                                 267770                       # Simulator instruction rate (inst/s)
+host_op_rate                                   288482                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              199406485                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271372                       # Number of bytes of host memory used
+host_seconds                                  5768.25                       # Real time elapsed on the host
 sim_insts                                  1544563088                       # Number of instructions simulated
 sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             50240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         132094976                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            132145216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         132094848                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            132145088                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        50240                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           50240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     67850112                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          67850112                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks     67849984                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          67849984                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                785                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2063984                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2064769                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1060158                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1060158                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                44431                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            116821276                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               116865707                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           44431                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              44431                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          60004831                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               60004831                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          60004831                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               44431                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           116821276                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              176870538                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2064769                       # Number of read requests accepted
-system.physmem.writeReqs                      1060158                       # Number of write requests accepted
-system.physmem.readBursts                     2064769                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1060158                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                132060352                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     84864                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  67848640                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 132145216                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               67850112                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1326                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::cpu.data            2063982                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2064767                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1060156                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1060156                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                43678                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            114842544                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               114886222                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           43678                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              43678                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          58988408                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               58988408                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          58988408                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               43678                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           114842544                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              173874630                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2064767                       # Number of read requests accepted
+system.physmem.writeReqs                      1060156                       # Number of write requests accepted
+system.physmem.readBursts                     2064767                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1060156                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                132061888                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     83200                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  67848256                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 132145088                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               67849984                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1300                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              128520                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              125806                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              122672                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              124571                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              128524                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              125801                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              122666                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              124575                       # Per bank write bursts
 system.physmem.perBankRdBursts::4              123572                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              123679                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              124365                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124958                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              132489                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              134780                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             133233                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             134506                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             134518                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             134594                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             130540                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             130640                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              123680                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              124357                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124965                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              132488                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              134781                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             133246                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             134508                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             134524                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             134597                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             130537                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             130646                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               66781                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               64941                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               64940                       # Per bank write bursts
 system.physmem.perBankWrBursts::2               63173                       # Per bank write bursts
 system.physmem.perBankWrBursts::3               63584                       # Per bank write bursts
 system.physmem.perBankWrBursts::4               63558                       # Per bank write bursts
 system.physmem.perBankWrBursts::5               63644                       # Per bank write bursts
 system.physmem.perBankWrBursts::6               65047                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               66055                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67972                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               68438                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              68161                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              68586                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              68040                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              68530                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               66059                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               67975                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               68435                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              68155                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              68585                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              68036                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              68532                       # Per bank write bursts
 system.physmem.perBankWrBursts::14              67159                       # Per bank write bursts
 system.physmem.perBankWrBursts::15              66466                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1130744067500                       # Total gap between requests
+system.physmem.totGap                    1150225621500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2064769                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2064767                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1060158                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1931837                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    131592                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1060156                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1919491                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    143962                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    32506                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    33515                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    57459                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    62386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    62542                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    62618                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    62533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    62474                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    62468                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    62484                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    62514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    62444                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62521                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    62600                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    62677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62255                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    62124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    61991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    31061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    32150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    57332                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    62506                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    62721                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    62815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    62684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    62639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    62591                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    62502                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    62571                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    62618                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62657                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    62645                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    62805                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    63052                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    62414                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    62339                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
@@ -194,103 +194,114 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1925169                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.839212                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.850367                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     126.421931                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1496084     77.71%     77.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       309482     16.08%     93.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        52255      2.71%     96.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20716      1.08%     97.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        12793      0.66%     98.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7748      0.40%     98.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5753      0.30%     98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5054      0.26%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        15284      0.79%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1925169                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         61990                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.244314                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       23.928422                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      148.698604                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          61952     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           16      0.03%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1927680                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.704050                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.827428                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     125.877785                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1497957     77.71%     77.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       310202     16.09%     93.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52219      2.71%     96.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20801      1.08%     97.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13076      0.68%     98.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7806      0.40%     98.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5210      0.27%     98.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5119      0.27%     99.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        15290      0.79%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1927680                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         62182                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.137773                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       23.854622                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      150.738788                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          62143     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           18      0.03%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            7      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            5      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119            5      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9216-10239            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            5      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-5119            4      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-11263            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14336-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::15360-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::17408-18431            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           61990                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         61990                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.101710                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.070337                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.034747                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              28322     45.69%     45.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1015      1.64%     47.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              30732     49.58%     96.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1873      3.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 43      0.07%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  5      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           61990                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    38536102500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               77225658750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  10317215000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18675.63                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::18432-19455            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           62182                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         62182                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.048808                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.017651                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.031288                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              29885     48.06%     48.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1078      1.73%     49.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              29552     47.53%     97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1636      2.63%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 28      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           62182                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    59945214750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               98635221000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  10317335000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       29050.73                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37425.63                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         116.79                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          60.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      116.87                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       60.00                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47800.73                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         114.81                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          58.99                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      114.89                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       58.99                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.38                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.91                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.47                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           1.36                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.90                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.46                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.42                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     775929                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    422476                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   37.60                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  39.85                       # Row buffer hit rate for writes
-system.physmem.avgGap                       361846.55                       # Average gap between requests
-system.physmem.pageHitRate                      38.37                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 7091695800                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3869476875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7785421800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3348753840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            73854608880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           423921506085                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           306584736000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             826456199280                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              730.896688                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   507283799000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     37757980000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    585701078500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7462581840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 4071845250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                8309316600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3520920960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            73854608880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           432965070225                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           298651785000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             828836128755                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              733.001436                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   494051909000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     37757980000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    598934101500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               240019432                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186610009                       # Number of conditional branches predicted
+system.physmem.avgWrQLen                        24.88                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     775403                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    420503                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   37.58                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  39.66                       # Row buffer hit rate for writes
+system.physmem.avgGap                       368081.27                       # Average gap between requests
+system.physmem.pageHitRate                      38.29                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 6704024460                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3563246940                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7126719600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               2697622920                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           71584047600.000015                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            47598370410                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             2598119520                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy      242886973860                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       71929585440                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        82360762695                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             539073775965                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              468.667814                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           1039023905500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     3501879500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     30346756000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   319059811750                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 187317352250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     77352878250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 532647044750                       # Time in different power states
+system.physmem_1.actEnergy                 7059682140                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3752298660                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7606434780                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               2836250460                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           71064062160.000015                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            47576528010                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             2430223200                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy      248601681570                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       68458810560                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        80907988260                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             540316908180                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              469.748583                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           1039511813000                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     3059644000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     30118792000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   316054273750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 178278810500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     77535412750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 545178789500                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               240019882                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186610383                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          14528957                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            131647101                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               122324380                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups            131646647                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               122324605                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.918400                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             92.918891                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                15657431                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups             535                       # Number of indirect predictor lookups.
@@ -298,7 +309,7 @@ system.cpu.branchPred.indirectHits                232                       # Nu
 system.cpu.branchPred.indirectMisses              303                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted          162                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -328,7 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -358,7 +369,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -388,7 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -419,16 +430,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    1130744162500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       2261488325                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       2300451445                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1544563088                       # Number of instructions committed
 system.cpu.committedOps                    1664032481                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      41363718                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      41363683                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.464161                       # CPI: cycles per instruction
-system.cpu.ipc                               0.682985                       # IPC: instructions per cycle
+system.cpu.cpi                               1.489387                       # CPI: cycles per instruction
+system.cpu.ipc                               0.671417                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu              1030178776     61.91%     61.91% # Class of committed instruction
 system.cpu.op_class_0::IntMult                 700322      0.04%     61.95% # Class of committed instruction
@@ -464,61 +475,61 @@ system.cpu.op_class_0::MemWrite             174847046     10.51%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total               1664032481                       # Class of committed instruction
-system.cpu.tickCycles                      1844743027                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       416745298                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           9220102                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4085.712457                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           624495296                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9224198                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             67.701853                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        9823555500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4085.712457                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997488                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997488                       # Average percentage of cache occupancy
+system.cpu.tickCycles                      1845014986                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       455436459                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           9220107                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4085.805290                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           624493165                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9224203                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             67.701585                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        9872962500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4085.805290                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997511                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997511                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          239                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1231                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2563                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          201                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1190                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2640                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           65                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1277391740                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1277391740                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    454164183                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       454164183                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    170330990                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      170330990                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1277391151                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1277391151                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    454163885                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       454163885                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    170329157                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      170329157                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data            1                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total             1                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     624495173                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        624495173                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    624495174                       # number of overall hits
-system.cpu.dcache.overall_hits::total       624495174                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7333416                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7333416                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2255057                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2255057                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     624493042                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        624493042                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    624493043                       # number of overall hits
+system.cpu.dcache.overall_hits::total       624493043                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7333417                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7333417                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2256890                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2256890                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      9588473                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9588473                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9588475                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9588475                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 192638967000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 192638967000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 111261397000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 111261397000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 303900364000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 303900364000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 303900364000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 303900364000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    461497599                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    461497599                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9590307                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9590307                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9590309                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9590309                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 208195707500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 208195707500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 119902321500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 119902321500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 328098029000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 328098029000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 328098029000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 328098029000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    461497302                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    461497302                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            3                       # number of SoftPFReq accesses(hits+misses)
@@ -527,64 +538,64 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    634083646                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    634083646                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    634083649                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    634083649                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    634083349                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    634083349                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    634083352                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    634083352                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015890                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.015890                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013066                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013066                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013077                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013077                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.666667                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.666667                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.015122                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.015122                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.015122                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.015122                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26268.653926                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26268.653926                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49338.618492                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 49338.618492                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31694.344240                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31694.344240                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31694.337629                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31694.337629                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.015125                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.015125                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.015125                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.015125                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28389.999846                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28389.999846                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.233272                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.233272                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.420865                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 34211.420865                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.413730                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34211.413730                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      3670051                       # number of writebacks
-system.cpu.dcache.writebacks::total           3670051                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      3670055                       # number of writebacks
+system.cpu.dcache.writebacks::total           3670055                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           49                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           49                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       364227                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       364227                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       364276                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       364276                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       364276                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       364276                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7333367                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7333367                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890830                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1890830                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       366056                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       366056                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       366105                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       366105                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       366105                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       366105                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7333368                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7333368                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890834                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1890834                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9224197                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9224197                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9224198                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9224198                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 185303496000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 185303496000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  86626211500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  86626211500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        75000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        75000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 271929707500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 271929707500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 271929782500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 271929782500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      9224202                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9224202                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9224203                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9224203                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200857919000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 200857919000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  92466638500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  92466638500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        81000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        81000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293324557500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 293324557500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293324638500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 293324638500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015890                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015890                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010956                       # mshr miss rate for WriteReq accesses
@@ -595,70 +606,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014547
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014547                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014547                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014547                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25268.542540                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25268.542540                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45813.855027                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45813.855027                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        75000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        75000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29480.041189                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29480.041189                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29480.046124                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29480.046124                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.586749                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.586749                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.568126                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.568126                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        81000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        81000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.450782                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.450782                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.456116                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.456116                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                33                       # number of replacements
-system.cpu.icache.tags.tagsinuse           660.343836                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           466264831                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           660.478132                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           466274661                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               822                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          567232.154501                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          567244.113139                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   660.343836                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.322434                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.322434                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   660.478132                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.322499                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.322499                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          789                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          751                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.385254                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         932532128                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        932532128                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    466264831                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       466264831                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     466264831                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        466264831                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    466264831                       # number of overall hits
-system.cpu.icache.overall_hits::total       466264831                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         932551788                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        932551788                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    466274661                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       466274661                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     466274661                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        466274661                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    466274661                       # number of overall hits
+system.cpu.icache.overall_hits::total       466274661                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          822                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           822                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          822                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            822                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          822                       # number of overall misses
 system.cpu.icache.overall_misses::total           822                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     62977000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     62977000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     62977000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     62977000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     62977000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     62977000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    466265653                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    466265653                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    466265653                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    466265653                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    466265653                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    466265653                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     74803000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     74803000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     74803000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     74803000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     74803000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     74803000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    466275483                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    466275483                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    466275483                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    466275483                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    466275483                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    466275483                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76614.355231                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 76614.355231                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 76614.355231                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 76614.355231                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76614.355231                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 76614.355231                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91001.216545                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 91001.216545                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 91001.216545                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 91001.216545                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 91001.216545                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 91001.216545                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -673,106 +684,106 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          822
 system.cpu.icache.demand_mshr_misses::total          822                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          822                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          822                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     62155000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     62155000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     62155000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     62155000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     62155000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     62155000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     73981000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     73981000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     73981000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     73981000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     73981000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     73981000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75614.355231                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75614.355231                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75614.355231                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75614.355231                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75614.355231                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75614.355231                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements          2032337                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31884.361365                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           16378235                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          2065105                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.930945                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      54418076000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    10.408988                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.813492                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31848.138885                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000318                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000788                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.971928                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.973033                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90001.216545                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90001.216545                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90001.216545                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 90001.216545                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90001.216545                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 90001.216545                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements          2032334                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31895.835750                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           16378248                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          2065102                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.930963                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      54709395000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks    10.372188                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.535695                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.927867                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000317                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000779                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.972288                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.973384                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          912                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2876                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7195                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21737                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          831                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2946                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7191                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21752                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        149613593                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       149613593                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks      3670051                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      3670051                       # number of WritebackDirty hits
+system.cpu.l2cache.tags.tag_accesses        149613670                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       149613670                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3670055                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3670055                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks           33                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total           33                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1078506                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1078506                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1078511                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1078511                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           37                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total           37                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6081702                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6081702                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6081704                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6081704                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           37                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7160208                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7160245                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      7160215                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7160252                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst           37                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7160208                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7160245                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       812324                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       812324                       # number of ReadExReq misses
+system.cpu.l2cache.overall_hits::cpu.data      7160215                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7160252                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       812323                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       812323                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          785                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total          785                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1251666                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      1251666                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1251665                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      1251665                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          785                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      2063990                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2064775                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2063988                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2064773                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          785                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      2063990                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2064775                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  72440693500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  72440693500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     60501000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     60501000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 110442540000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 110442540000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     60501000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 182883233500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 182943734500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     60501000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 182883233500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 182943734500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      3670051                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      3670051                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.data      2063988                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2064773                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  78282559500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  78282559500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     72328000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     72328000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125996723500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 125996723500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     72328000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 204279283000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 204351611000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     72328000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 204279283000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 204351611000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      3670055                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      3670055                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks           33                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total           33                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1890830                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1890830                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1890834                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1890834                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          822                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::total          822                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7333368                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7333368                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7333369                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7333369                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          822                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9224198                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9225020                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9224203                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9225025                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          822                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9224198                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9225020                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.429612                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.429612                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9224203                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9225025                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.429611                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.429611                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.954988                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.954988                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.170681                       # miss rate for ReadSharedReq accesses
@@ -783,26 +794,26 @@ system.cpu.l2cache.demand_miss_rate::total     0.223823                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.954988                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.223758                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.223823                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89177.093746                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89177.093746                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77071.337580                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77071.337580                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88236.430485                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88236.430485                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77071.337580                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88606.647077                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 88602.261505                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77071.337580                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88606.647077                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 88602.261505                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96368.759102                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96368.759102                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92137.579618                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92137.579618                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.295291                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.295291                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92137.579618                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.096258                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 98970.497483                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92137.579618                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.096258                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 98970.497483                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks      1060158                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1060158                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1060156                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1060156                       # number of writebacks
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            6                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data            6                       # number of demand (read+write) MSHR hits
@@ -811,128 +822,128 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data            6
 system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          215                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          215                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       812324                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       812324                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       812323                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       812323                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          785                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total          785                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1251660                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1251660                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1251659                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1251659                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          785                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      2063984                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2064769                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2063982                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2064767                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          785                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      2063984                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2064769                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  64317453500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  64317453500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     52651000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     52651000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  97925523500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  97925523500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     52651000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162242977000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 162295628000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     52651000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162242977000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 162295628000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2063982                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2064767                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  70159329500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  70159329500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     64478000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     64478000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113479586000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113479586000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     64478000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183638915500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 183703393500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64478000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183638915500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 183703393500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.429612                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.429612                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.429611                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.429611                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.954988                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.954988                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.170680                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.170680                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.954988                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223758                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.223823                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223757                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.223822                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.954988                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223758                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.223823                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79177.093746                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79177.093746                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67071.337580                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67071.337580                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78236.520701                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78236.520701                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67071.337580                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78606.702862                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78602.317257                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67071.337580                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78606.702862                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78602.317257                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     18445155                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      9220147                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223757                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.223822                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86368.759102                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86368.759102                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.340415                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.340415                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.118709                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.519918                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.118709                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.519918                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests     18445165                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      9220152                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1594                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1445                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1439                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1444                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1438                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp       7334190                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      4730209                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp       7334191                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4730211                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean           33                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict      6522230                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1890830                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1890830                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1890834                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1890834                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          822                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7333368                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7333369                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1677                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27668498                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27670175                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27668513                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27670190                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54720                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    825231936                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          825286656                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2032337                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              67850112                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     11257357                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000272                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.016509                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    825232512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          825287232                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2032334                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic              67849984                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     11257359                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000271                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.016506                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           11254306     99.97%     99.97% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3045      0.03%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11254309     99.97%     99.97% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               3044      0.03%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  6      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       11257357                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12892661500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11257359                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12892670500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1233000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13836299994                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13836307494                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests       4095876                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      2031264                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests       4095872                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      2031262                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp            1252445                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1060158                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp            1252444                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1060156                       # Transaction distribution
 system.membus.trans_dist::CleanEvict           970949                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            812324                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           812324                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1252445                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6160645                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6160645                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    199995328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               199995328                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq            812323                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           812323                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1252444                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6160639                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6160639                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    199995072                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               199995072                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2064769                       # Request fanout histogram
+system.membus.snoop_fanout::samples           2064767                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2064769    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2064767    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             2064769                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8803577000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2064767                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8804910500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        11289358000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        11285155750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 8b8fd1b4f..5a7d7b1a5 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -172,7 +172,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -534,7 +534,7 @@ pipelined=true
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -813,6 +813,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -824,7 +825,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -832,29 +833,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -874,6 +882,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -905,9 +914,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index 00cbc440d..fbc8b4e01 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/s
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:10:34
-gem5 executing on e108600-lin, pid 12200
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:48:52
+gem5 executing on e108600-lin, pid 17438
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -27,4 +27,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 767803843500 because target called exit()
+Exiting @ tick 787742202500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 4f03996ba..ea5c16164 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,123 +1,123 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.770752                       # Number of seconds simulated
-sim_ticks                                770752376500                       # Number of ticks simulated
-final_tick                               770752376500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.787742                       # Number of seconds simulated
+sim_ticks                                787742202500                       # Number of ticks simulated
+final_tick                               787742202500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 147248                       # Simulator instruction rate (inst/s)
-host_op_rate                                   158637                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               73478006                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 329736                       # Number of bytes of host memory used
-host_seconds                                 10489.57                       # Real time elapsed on the host
+host_inst_rate                                 201500                       # Simulator instruction rate (inst/s)
+host_op_rate                                   217086                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              102767126                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 327820                       # Number of bytes of host memory used
+host_seconds                                  7665.31                       # Real time elapsed on the host
 sim_insts                                  1544563024                       # Number of instructions simulated
 sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             65664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         236002624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     63781504                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            299849792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         236035776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     63780672                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            299882112                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        65664                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           65664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    104607936                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         104607936                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks    104579136                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         104579136                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst               1026                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            3687541                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       996586                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               4685153                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1634499                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1634499                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                85195                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            306197725                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     82752264                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               389035183                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           85195                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              85195                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         135721847                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              135721847                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         135721847                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               85195                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           306197725                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     82752264                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              524757030                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       4685154                       # Number of read requests accepted
-system.physmem.writeReqs                      1634499                       # Number of write requests accepted
-system.physmem.readBursts                     4685154                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1634499                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                299347712                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    502144                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 104604544                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 299849856                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              104607936                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     7846                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      26                       # Number of DRAM write bursts merged with an existing one
+system.physmem.num_reads::cpu.data            3688059                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       996573                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               4685658                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1634049                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1634049                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                83357                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            299635814                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     80966428                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               380685599                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           83357                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              83357                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         132758072                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              132758072                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         132758072                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               83357                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           299635814                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     80966428                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              513443671                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       4685658                       # Number of read requests accepted
+system.physmem.writeReqs                      1634049                       # Number of write requests accepted
+system.physmem.readBursts                     4685658                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1634049                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                299378880                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    503232                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 104576512                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 299882112                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              104579136                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     7863                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      17                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              301314                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              301808                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              285079                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              287721                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              288732                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              286480                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              281880                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              278193                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              293719                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              299847                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             291529                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             297903                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             299405                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             299387                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             294305                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             290006                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              103629                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              101748                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               99222                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               99944                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               98990                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               98822                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              102440                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              104048                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              105134                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              103994                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             101818                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             102570                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             102850                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             102376                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             104237                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             102624                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              301431                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              301123                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              285299                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              287676                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              288751                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              286469                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              281133                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              278330                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              294107                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              299584                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             292343                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             297976                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             299704                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             299189                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             294388                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             290292                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              103694                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              101682                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               99052                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               99844                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               99095                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               98699                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              102473                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              104090                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              105068                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              104102                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             101990                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             102510                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             102612                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             102296                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             104281                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             102520                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    770752366000                       # Total gap between requests
+system.physmem.totGap                    787742161500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 4685154                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 4685658                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1634499                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   2776424                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1031022                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    327510                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    229431                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    146630                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     80164                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     37430                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     23802                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     17710                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1619                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      771                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      426                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      239                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1634049                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   2727854                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                   1051064                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    327817                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    232993                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    158136                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     89940                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     39970                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     24320                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     17966                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      4404                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1761                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      825                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      484                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      248                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                       11                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
@@ -149,40 +149,40 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    25690                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    28168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    56471                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    73716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    85142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    93999                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   100116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   103738                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   105456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   106103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   107040                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   108147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   109209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   110723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   110766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   103820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   100949                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   100270                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      505                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    24393                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    26784                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    55742                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    73104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    84746                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    93459                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    99625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   103284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   105129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   105804                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   106233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   107403                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   108454                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   109545                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   110077                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   108778                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   102213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   101052                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     4490                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1853                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      898                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      461                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
@@ -198,130 +198,133 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      4255173                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean       94.931559                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      78.862227                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     102.833954                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        3394354     79.77%     79.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       663703     15.60%     95.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        94226      2.21%     97.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        35436      0.83%     98.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        22765      0.53%     98.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12171      0.29%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7342      0.17%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5345      0.13%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19831      0.47%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        4255173                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         97794                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        47.827914                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       99.473591                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-127           93707     95.82%     95.82% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::128-255          1671      1.71%     97.53% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-383           768      0.79%     98.31% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::384-511           406      0.42%     98.73% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-639           365      0.37%     99.10% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::640-767           337      0.34%     99.45% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-895           234      0.24%     99.69% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::896-1023          165      0.17%     99.86% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1151           89      0.09%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1152-1279           24      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1280-1407           12      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1408-1535            4      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1664-1791            3      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2175            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2176-2303            2      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2304-2431            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2688-2815            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2944-3071            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3456-3583            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-3711            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3968-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           97794                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         97794                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.713152                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.671812                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.223073                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              68724     70.27%     70.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1896      1.94%     72.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              18671     19.09%     91.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               5634      5.76%     97.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20               1729      1.77%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                613      0.63%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                266      0.27%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                147      0.15%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 67      0.07%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 30      0.03%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  9      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  6      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           97794                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   128325813562                       # Total ticks spent queuing
-system.physmem.totMemAccLat              216025338562                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  23386540000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27435.83                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples      4258602                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean       94.856263                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      78.818587                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     102.740363                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        3399214     79.82%     79.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       662534     15.56%     95.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        94110      2.21%     97.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        35203      0.83%     98.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        22640      0.53%     98.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        12473      0.29%     99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7407      0.17%     99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5223      0.12%     99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        19798      0.46%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        4258602                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         97968                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        47.747867                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       99.462080                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-255           95523     97.50%     97.50% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-511          1197      1.22%     98.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-767           705      0.72%     99.45% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::768-1023          407      0.42%     99.86% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1279          106      0.11%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1280-1535           17      0.02%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-1791            4      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1792-2047            4      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2303            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2304-2559            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-3839            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4352-4607            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4608-4863            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           97968                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         97968                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.678997                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.638691                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.208217                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              70313     71.77%     71.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1920      1.96%     73.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              17565     17.93%     91.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               5314      5.42%     97.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20               1711      1.75%     98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                637      0.65%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                262      0.27%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                130      0.13%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 63      0.06%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 33      0.03%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 13      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           97968                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   162666982970                       # Total ticks spent queuing
+system.physmem.totMemAccLat              250375639220                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  23388975000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       34774.29                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46185.83                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         388.38                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         135.72                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      389.04                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      135.72                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  53524.29                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         380.05                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         132.75                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      380.69                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      132.76                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           4.09                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       3.03                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.06                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.42                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.86                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1715091                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    341475                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   36.67                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  20.89                       # Row buffer hit rate for writes
-system.physmem.avgGap                       121961.18                       # Average gap between requests
-system.physmem.pageHitRate                      32.58                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                15989112720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 8724218250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy               18025846800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5241069360                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            50341337280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           417928675995                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            95843265750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             612093526155                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              794.157652                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   156909498029                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     25736880000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    588099785971                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                16179556680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 8828131125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy               18455494200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5349602880                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            50341337280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           412908393870                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           100247038500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             612309554535                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              794.437909                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   164276600328                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     25736880000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    580733308672                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               286275195                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         223398341                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14628424                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            157667483                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               150349199                       # Number of BTB hits
+system.physmem.busUtil                           4.01                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      1.04                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.44                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.91                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1712898                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    340301                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   36.62                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  20.83                       # Row buffer hit rate for writes
+system.physmem.avgGap                       124648.53                       # Average gap between requests
+system.physmem.pageHitRate                      32.53                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                15106540680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 8029309200                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy               16494913680                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4221043380                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           59407414560.000015                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            64582002630                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             1606944480                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy      223006056720                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       35875852320                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        16122239730                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             444464207160                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              564.225454                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           641904162368                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     1401750889                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     25151370000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    59428702250                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  93425472309                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    119284909993                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 489049997059                       # Time in different power states
+system.physmem_1.actEnergy                15299891880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 8132085390                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy               16904542620                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4308478380                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           58934141760.000015                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            64765265610                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             1612336320                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy      219700492200                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       35552759520                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        18091245240                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             443312102310                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              562.762917                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           641480248383                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     1450220904                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     24952394000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    67105561000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  92583809905                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    119858377963                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 481791838728                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               286283098                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         223408244                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14630421                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            158004936                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               150354998                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.358406                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                16643020                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 63                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups            3069                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits               1906                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses             1163                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted          137                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             95.158418                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                16643073                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 65                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups            3065                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits               1898                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             1167                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          134                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -351,7 +354,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -381,7 +384,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -411,7 +414,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -442,129 +445,129 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    770752376500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       1541504754                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    787742202500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       1575484406                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           13925502                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2067484101                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   286275195                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          166994125                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                    1512857238                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                29281631                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  279                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles         1018                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 656940019                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   946                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1541424852                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.436951                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.229037                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           13928690                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2067537239                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   286283098                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          166999969                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                    1546809233                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                29285745                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  303                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          986                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 656964714                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   942                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1575382084                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.406011                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.233492                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                459011037     29.78%     29.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                465435057     30.20%     59.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                101419068      6.58%     66.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                515559690     33.45%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                492942163     31.29%     31.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                465443083     29.54%     60.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                101428647      6.44%     67.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                515568191     32.73%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1541424852                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.185712                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.341212                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 74709451                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             544021839                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 849845592                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              58207832                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               14640138                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             42201657                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   726                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             2037180089                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              52484609                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               14640138                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                139806563                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               462600801                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          15884                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 837785307                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              86576159                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1976384850                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              26739549                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              45323653                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 126929                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1602638                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               25499860                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1985860548                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            9128169124                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2432875929                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               133                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1575382084                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.181711                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.312318                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 74686824                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             577980395                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 849907031                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              58165638                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               14642196                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             42200734                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   724                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2037196735                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              52499519                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               14642196                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                139768268                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               492678513                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          15538                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 837819054                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              90458515                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1976393108                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              26740093                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              45400307                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 126273                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1723349                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               29315109                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1985867653                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            9128208959                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2432891999                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               131                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                310961603                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                175                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            175                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 111534180                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            542566077                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           199303375                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          26892889                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         29237160                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1947969517                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 231                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1857492369                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          13496690                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       283937332                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    647289356                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             61                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1541424852                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.205049                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.150817                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                310968708                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                177                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            176                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 111448171                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            542564068                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           199306440                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          26831952                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         28868587                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1947979256                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 230                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1857513748                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          13517148                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       283947070                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    647252748                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             60                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1575382084                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.179088                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.151868                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           588435916     38.17%     38.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           326131475     21.16%     59.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           378210554     24.54%     83.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           219654013     14.25%     98.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            28986723      1.88%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                6171      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           622503864     39.51%     39.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           326012726     20.69%     60.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           378121823     24.00%     84.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           219723484     13.95%     98.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            29014011      1.84%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                6176      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1541424852                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1575382084                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu               166021321     40.99%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   1993      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              191489776     47.28%     88.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              47539480     11.74%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu               166098751     40.96%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   2024      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     40.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              191460462     47.22%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              47920671     11.82%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1138243662     61.28%     61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               800931      0.04%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1138250302     61.28%     61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               801028      0.04%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
@@ -592,82 +595,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc             22      0.00%     61.32% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            532135699     28.65%     89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           186312026     10.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            532139540     28.65%     89.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           186322827     10.03%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1857492369                       # Type of FU issued
-system.cpu.iq.rate                           1.204986                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   405052570                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.218064                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5674958613                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2231919871                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1805704142                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total             1857513748                       # Type of FU issued
+system.cpu.iq.rate                           1.179011                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   405481908                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.218293                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5709408399                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2231939413                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1805717250                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 237                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                230                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           70                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2262544806                       # Number of integer alu accesses
+system.cpu.iq.fp_inst_queue_writes                228                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           69                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2262995523                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     133                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         17811536                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads         17822173                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     84259743                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        66618                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        13244                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     24456330                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     84257734                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        66715                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        13309                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     24459395                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      4512030                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       4891489                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      4550351                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       4849996                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               14640138                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                25364964                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1346928                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1947969899                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               14642196                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                25436916                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1454941                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1947979633                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             542566077                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            199303375                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                169                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 159350                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               1186169                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          13244                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        7699482                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8703162                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             16402644                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1827831567                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             516957415                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          29660802                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             542564068                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            199306440                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                168                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 159182                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               1294449                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          13309                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        7700831                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8703764                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             16404595                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1827842620                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             516961097                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          29671128                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                           151                       # number of nop insts executed
-system.cpu.iew.exec_refs                    698708795                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                229542425                       # Number of branches executed
-system.cpu.iew.exec_stores                  181751380                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.185745                       # Inst execution rate
-system.cpu.iew.wb_sent                     1808736265                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1805704212                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1169174812                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1689572222                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.171391                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.691995                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       258041892                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                           147                       # number of nop insts executed
+system.cpu.iew.exec_refs                    698716504                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                229543654                       # Number of branches executed
+system.cpu.iew.exec_stores                  181755407                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.160178                       # Inst execution rate
+system.cpu.iew.wb_sent                     1808745333                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1805717319                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1169202335                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1689603795                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.146135                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.691998                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       258049766                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          14627747                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1501940299                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.107922                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.025263                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          14629745                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1535892995                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.083430                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.009496                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    921653315     61.36%     61.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    250636600     16.69%     78.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    110060462      7.33%     85.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     55269176      3.68%     89.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     29319156      1.95%     91.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     34080655      2.27%     93.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     24723288      1.65%     94.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     18133421      1.21%     96.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     58064226      3.87%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    955612705     62.22%     62.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    250634240     16.32%     78.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    110090472      7.17%     85.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     55300497      3.60%     89.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     29246766      1.90%     91.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     34056030      2.22%     93.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     24731317      1.61%     95.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     18107101      1.18%     96.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     58113867      3.78%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1501940299                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1535892995                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1544563042                       # Number of instructions committed
 system.cpu.commit.committedOps             1664032434                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -713,78 +716,78 @@ system.cpu.commit.op_class_0::MemWrite      174847045     10.51%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1664032434                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              58064226                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3365949800                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3883638365                       # The number of ROB writes
-system.cpu.timesIdled                             837                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           79902                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              58113867                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3399860729                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3883658641                       # The number of ROB writes
+system.cpu.timesIdled                             841                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          102322                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1544563024                       # Number of Instructions Simulated
 system.cpu.committedOps                    1664032416                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.998020                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.998020                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.001984                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.001984                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2175818987                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1261576435                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        42                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       52                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                6965775009                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                551856674                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               675846934                       # number of misc regfile reads
+system.cpu.cpi                               1.020020                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.020020                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.980373                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.980373                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2175838440                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1261579513                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        40                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       51                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                6965813253                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                551861987                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               675852638                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements          17003150                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.964340                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           638065664                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          17003662                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.525191                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          79206500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.964340                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999930                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999930                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements          17003360                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.963277                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           638058665                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          17003872                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             37.524316                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          83293500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.963277                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999928                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999928                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          406                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          106                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          382                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1335709608                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1335709608                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    469347574                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       469347574                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    168717937                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      168717937                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1335696042                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1335696042                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    469342719                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       469342719                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    168715791                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      168715791                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           57                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     638065511                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        638065511                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    638065511                       # number of overall hits
-system.cpu.dcache.overall_hits::total       638065511                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     17419228                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      17419228                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3868110                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3868110                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     638058510                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        638058510                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    638058510                       # number of overall hits
+system.cpu.dcache.overall_hits::total       638058510                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     17417195                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      17417195                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3870256                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3870256                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     21287338                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       21287338                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21287340                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21287340                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 416423435500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 416423435500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 150253086257                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 150253086257                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       199500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       199500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 566676521757                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 566676521757                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 566676521757                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 566676521757                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    486766802                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    486766802                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     21287451                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       21287451                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     21287453                       # number of overall misses
+system.cpu.dcache.overall_misses::total      21287453                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 440618340000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 440618340000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 157333375444                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 157333375444                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       245500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       245500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 597951715444                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 597951715444                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 597951715444                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 597951715444                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    486759914                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    486759914                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            2                       # number of SoftPFReq accesses(hits+misses)
@@ -793,470 +796,475 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    659352849                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    659352849                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    659352851                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    659352851                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035786                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.035786                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022413                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.022413                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    659345961                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    659345961                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    659345963                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    659345963                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035782                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.035782                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022425                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.022425                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.065574                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.065574                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032285                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032285                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.032285                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.032285                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23905.963887                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 23905.963887                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38844.057242                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38844.057242                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        49875                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        49875                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26620.356277                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26620.356277                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26620.353776                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26620.353776                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     20685246                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3452781                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            946049                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           67233                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.864878                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    51.355450                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks     17003150                       # number of writebacks
-system.cpu.dcache.writebacks::total          17003150                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3153076                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      3153076                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1130592                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1130592                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_miss_rate::cpu.data     0.032286                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.032286                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.032286                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.032286                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25297.893260                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25297.893260                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40651.929858                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 40651.929858                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        61375                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        61375                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 28089.399499                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 28089.399499                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28089.396859                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28089.396859                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     21254267                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3791320                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            940376                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           67438                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    22.601882                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    56.219342                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks     17003360                       # number of writebacks
+system.cpu.dcache.writebacks::total          17003360                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3150878                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      3150878                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1132695                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1132695                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4283668                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4283668                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4283668                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4283668                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14266152                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total     14266152                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737518                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2737518                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4283573                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4283573                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4283573                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4283573                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14266317                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total     14266317                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737561                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2737561                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data     17003670                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total     17003670                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     17003671                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     17003671                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335207977500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 335207977500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116679674033                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 116679674033                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        69000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        69000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451887651533                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 451887651533                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451887720533                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 451887720533                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029308                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029308                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data     17003878                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total     17003878                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     17003879                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     17003879                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354302060000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 354302060000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121168074300                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 121168074300                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        75000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        75000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475470134300                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 475470134300                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475470209300                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 475470209300                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029309                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029309                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015862                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015862                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025788                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025788                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025788                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025788                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23496.733913                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23496.733913                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42622.431718                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42622.431718                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        69000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        69000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26575.889295                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26575.889295                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26575.891790                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26575.891790                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements               588                       # number of replacements
-system.cpu.icache.tags.tagsinuse           444.874436                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           656938405                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1074                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          611674.492551                       # Average number of references to valid blocks.
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025789                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025789                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025789                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025789                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24834.865228                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24834.865228                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44261.323967                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44261.323967                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        75000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        75000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27962.452700                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 27962.452700                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27962.455467                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 27962.455467                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements               589                       # number of replacements
+system.cpu.icache.tags.tagsinuse           445.623702                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           656963104                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1076                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          610560.505576                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   444.874436                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.868895                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.868895                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          486                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   445.623702                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.870359                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.870359                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          487                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          443                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.949219                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1313881106                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1313881106                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    656938405                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       656938405                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     656938405                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        656938405                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    656938405                       # number of overall hits
-system.cpu.icache.overall_hits::total       656938405                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1611                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1611                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1611                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1611                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1611                       # number of overall misses
-system.cpu.icache.overall_misses::total          1611                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    103785485                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    103785485                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    103785485                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    103785485                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    103785485                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    103785485                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    656940016                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    656940016                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    656940016                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    656940016                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    656940016                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    656940016                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          442                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.951172                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        1313930500                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1313930500                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    656963104                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       656963104                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     656963104                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        656963104                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    656963104                       # number of overall hits
+system.cpu.icache.overall_hits::total       656963104                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1608                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1608                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1608                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1608                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1608                       # number of overall misses
+system.cpu.icache.overall_misses::total          1608                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    127367486                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    127367486                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    127367486                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    127367486                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    127367486                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    127367486                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    656964712                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    656964712                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    656964712                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    656964712                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    656964712                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    656964712                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64423.019863                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 64423.019863                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 64423.019863                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 64423.019863                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 64423.019863                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 64423.019863                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        16825                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          586                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               185                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets              10                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    90.945946                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    58.600000                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks          588                       # number of writebacks
-system.cpu.icache.writebacks::total               588                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          535                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          535                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          535                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          535                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          535                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          535                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1076                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1076                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1076                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1076                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1076                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1076                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75943989                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     75943989                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75943989                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     75943989                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75943989                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     75943989                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79208.635572                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 79208.635572                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 79208.635572                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 79208.635572                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 79208.635572                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 79208.635572                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        21110                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          318                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               193                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               9                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs   109.378238                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    35.333333                       # average number of cycles each access was blocked
+system.cpu.icache.writebacks::writebacks          589                       # number of writebacks
+system.cpu.icache.writebacks::total               589                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          531                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          531                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          531                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          531                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          531                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          531                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1077                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1077                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1077                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1077                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1077                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1077                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     92273990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     92273990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     92273990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     92273990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     92273990                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     92273990                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70579.915428                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70579.915428                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70579.915428                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 70579.915428                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70579.915428                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 70579.915428                       # average overall mshr miss latency
-system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.prefetcher.num_hwpf_issued     11612917                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified     11641367                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit        19112                       # number of redundant prefetches already in prefetch queue
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85676.870938                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85676.870938                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85676.870938                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 85676.870938                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85676.870938                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 85676.870938                       # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.prefetcher.num_hwpf_issued     11610963                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified     11639700                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit        19388                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4655505                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements          4647068                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        15866.736257                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           13267029                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          4662976                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.845185                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage      4657940                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements          4647528                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        15870.760193                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           13267468                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          4663442                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.844995                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15646.626307                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   220.109950                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.954994                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.013434                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.968429                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          143                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15765                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::0            5                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1          115                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3           23                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          463                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         4068                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         7095                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2886                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1253                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.008728                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962219                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        561777243                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       561777243                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks      4835234                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      4835234                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     12147319                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     12147319                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1756866                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1756866                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           49                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           49                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11510992                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total     11510992                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           49                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data     13267858                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        13267907                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           49                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data     13267858                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       13267907                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            9                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            9                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       980689                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       980689                       # number of ReadExReq misses
+system.cpu.l2cache.tags.occ_blocks::writebacks 15649.753914                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   221.006278                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.955185                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.013489                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.968674                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          144                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15770                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1          116                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3           27                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          430                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         4072                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         7121                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2569                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1578                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.008789                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962524                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        561783529                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       561783529                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks      4825740                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      4825740                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     12156985                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     12156985                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1756408                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1756408                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           50                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           50                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11511753                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total     11511753                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           50                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data     13268161                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        13268211                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           50                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data     13268161                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       13268211                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            7                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            7                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       981196                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       981196                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1027                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total         1027                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      2755115                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      2755115                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      2754515                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      2754515                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         1027                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      3735804                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       3736831                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      3735711                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       3736738                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         1027                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      3735804                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      3736831                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       191500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       191500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100034737999                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 100034737999                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     74500500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     74500500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 237611587999                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 237611587999                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     74500500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 337646325998                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 337720826498                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     74500500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 337646325998                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 337720826498                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      4835234                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      4835234                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks     12147319                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total     12147319                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            9                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            9                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737555                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      2737555                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1076                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         1076                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data     14266107                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total     14266107                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1076                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data     17003662                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     17004738                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1076                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data     17003662                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     17004738                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_misses::cpu.data      3735711                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      3736738                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       148500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       148500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104535366500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 104535366500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     90830000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     90830000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256701151000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 256701151000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     90830000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 361236517500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 361327347500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     90830000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 361236517500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 361327347500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      4825740                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      4825740                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     12156985                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     12156985                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            7                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            7                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737604                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      2737604                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1077                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         1077                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data     14266268                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total     14266268                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1077                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data     17003872                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     17004949                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1077                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data     17003872                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     17004949                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.358235                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.358235                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.954461                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.954461                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.193123                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.193123                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.954461                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.219706                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.219752                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.954461                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.219706                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.219752                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21277.777778                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21277.777778                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102004.547822                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102004.547822                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72541.869523                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72541.869523                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86243.800349                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86243.800349                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72541.869523                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90381.167213                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 90376.264406                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72541.869523                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90381.167213                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 90376.264406                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs          351                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.358414                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.358414                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.953575                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.953575                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.193079                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.193079                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.953575                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.219698                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.219744                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.953575                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.219698                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.219744                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21214.285714                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21214.285714                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106538.720602                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106538.720602                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 88442.064265                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 88442.064265                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93192.867347                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93192.867347                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 88442.064265                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96698.196809                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 96695.927705                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 88442.064265                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96698.196809                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 96695.927705                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs          541                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                5                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                4                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs    70.200000                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs   135.250000                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.unused_prefetches            58014                       # number of HardPF blocks evicted w/o reference
-system.cpu.l2cache.writebacks::writebacks      1634499                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1634499                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3902                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         3902                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data        45668                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total        45668                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data        49570                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total        49570                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data        49570                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total        49570                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher      1198249                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total      1198249                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            9                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            9                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       976787                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       976787                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1027                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1027                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      2709447                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      2709447                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1027                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      3686234                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      3687261                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1027                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      3686234                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher      1198249                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      4885510                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  73218164638                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  73218164638                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       137500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       137500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  93806338999                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  93806338999                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     68350500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     68350500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 218529981999                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 218529981999                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     68350500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312336320998                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 312404671498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     68350500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312336320998                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  73218164638                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 385622836136                       # number of overall MSHR miss cycles
+system.cpu.l2cache.unused_prefetches            58311                       # number of HardPF blocks evicted w/o reference
+system.cpu.l2cache.writebacks::writebacks      1634049                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1634049                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3931                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         3931                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data        45060                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total        45060                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data        48991                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total        48992                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data        48991                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total        48992                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher      1197394                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total      1197394                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            7                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            7                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       977265                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       977265                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1026                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1026                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      2709455                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      2709455                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1026                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      3686720                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      3687746                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1026                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      3686720                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher      1197394                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      4885140                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  84175133455                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  84175133455                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       106500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       106500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  98289203000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  98289203000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     84580000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     84580000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237438885500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237438885500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     84580000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335728088500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 335812668500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     84580000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335728088500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  84175133455                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 419987801955                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.356810                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.356810                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.954461                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.954461                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.189922                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.189922                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.954461                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216791                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.216837                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.954461                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216791                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.356978                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.356978                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.952646                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.952646                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.189920                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.189920                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.952646                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216816                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.216863                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.952646                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216816                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.287303                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61104.298554                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96035.613700                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96035.613700                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66553.554041                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66553.554041                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80654.828088                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80654.828088                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66553.554041                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84730.465021                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84725.402270                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66553.554041                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84730.465021                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78931.951042                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     34008488                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     17003756                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21185                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops       201663                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops       201662                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.287278                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70298.609693                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70298.609693                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15214.285714                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15214.285714                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100575.793669                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100575.793669                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82436.647173                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82436.647173                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.448609                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.448609                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82436.647173                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91064.167743                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91061.767405                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82436.647173                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91064.167743                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70298.609693                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85972.521147                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests     34008905                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     17003965                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21224                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       200821                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops       200820                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp      14267181                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      6469733                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     12168504                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      3012569                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq      1490485                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp      14267344                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      6459789                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     12178209                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      3013479                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq      1493524                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFResp           11                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            9                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            9                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2737555                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2737555                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         1076                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq     14266107                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2738                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     51010503                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          51013241                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       106368                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   2176436672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2176543040                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     6137564                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic             104608640                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     23142303                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.009630                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.097659                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeReq            7                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp            7                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2737604                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2737604                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         1077                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq     14266268                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2742                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     51011129                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          51013871                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       106560                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   2176463552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2176570112                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     6141063                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic             104579840                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     23146008                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.009594                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.097477                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           22919446     99.04%     99.04% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             222856      0.96%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           22923954     99.04%     99.04% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             222053      0.96%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       23142303                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    34007983525                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          4.4                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy        16538                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       23146008                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    34008401540                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          4.3                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy        16551                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1611000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1614499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   25505500994                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          3.3                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests       9332231                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      4668264                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.respLayer1.occupancy   25505814993                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          3.2                       # Layer utilization (%)
+system.membus.snoop_filter.tot_requests       9333193                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      4668760                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp            3708204                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1634499                       # Transaction distribution
-system.membus.trans_dist::CleanEvict          3012569                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                9                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            976948                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           976948                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       3708206                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     14017383                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               14017383                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    404457664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               404457664                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED 787742202500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp            3708223                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1634049                       # Transaction distribution
+system.membus.trans_dist::CleanEvict          3013479                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq                7                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            977434                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           977434                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       3708224                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     14018850                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               14018850                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    404461184                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               404461184                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           4685163                       # Request fanout histogram
+system.membus.snoop_fanout::samples           4685665                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 4685163    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 4685665    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             4685163                       # Request fanout histogram
-system.membus.reqLayer0.occupancy         17662405597                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        25476549560                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              3.3                       # Layer utilization (%)
+system.membus.snoop_fanout::total             4685665                       # Request fanout histogram
+system.membus.reqLayer0.occupancy         17659262741                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        25448696800                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              3.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
index 5e0a983c6..35828777f 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
@@ -149,7 +149,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -583,7 +583,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -643,7 +643,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -760,6 +760,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -779,29 +780,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -821,6 +829,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -852,9 +861,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout
index 9e68a8154..4b089cf00 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout
@@ -3,11 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:29
-gem5 executing on e108600-lin, pid 4311
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:43
+gem5 executing on e108600-lin, pid 28042
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/minor-timing
 
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -24,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 53344764500 because target called exit()
+122 123 124 Exiting @ tick 53437621500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
index d3e370d8a..2c8dfca63 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.053349                       # Number of seconds simulated
-sim_ticks                                 53349450500                       # Number of ticks simulated
-final_tick                                53349450500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.053438                       # Number of seconds simulated
+sim_ticks                                 53437621500                       # Number of ticks simulated
+final_tick                                53437621500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 273465                       # Simulator instruction rate (inst/s)
-host_op_rate                                   273465                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              158745564                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 258296                       # Number of bytes of host memory used
-host_seconds                                   336.07                       # Real time elapsed on the host
+host_inst_rate                                 247892                       # Simulator instruction rate (inst/s)
+host_op_rate                                   247892                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              144138078                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 256712                       # Number of bytes of host memory used
+host_seconds                                   370.74                       # Real time elapsed on the host
 sim_insts                                    91903089                       # Number of instructions simulated
 sim_ops                                      91903089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  53349450500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED  53437621500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            202880                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            137728                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               340608                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total          202880                       # Nu
 system.physmem.num_reads::cpu.inst               3170                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               2152                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  5322                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3802851                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2581620                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6384471                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3802851                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3802851                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3802851                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2581620                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6384471                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              3796576                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2577360                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6373936                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3796576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3796576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3796576                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2577360                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6373936                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          5322                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        5322                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     53349362500                       # Total gap between requests
+system.physmem.totGap                     53437285500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4932                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       380                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4860                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       449                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          982                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      345.743381                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     213.338865                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.606559                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            303     30.86%     30.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          220     22.40%     53.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           94      9.57%     62.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          105     10.69%     73.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           62      6.31%     79.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           36      3.67%     83.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           29      2.95%     86.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           22      2.24%     88.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          111     11.30%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            982                       # Bytes accessed per row activation
-system.physmem.totQLat                       40016750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 139804250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          981                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      347.009174                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     213.710292                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     326.985210                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            311     31.70%     31.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          198     20.18%     51.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          103     10.50%     62.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          115     11.72%     74.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           57      5.81%     79.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           30      3.06%     82.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           30      3.06%     86.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           26      2.65%     88.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          111     11.31%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            981                       # Bytes accessed per row activation
+system.physmem.totQLat                      132267250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 232054750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     26610000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7519.12                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       24852.92                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26269.12                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           6.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  43602.92                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           6.37                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        6.38                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        6.37                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
@@ -217,49 +217,59 @@ system.physmem.busUtilRead                       0.05                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4333                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4338                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.42                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.51                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     10024307.12                       # Average gap between requests
-system.physmem.pageHitRate                      81.42                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3462480                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1889250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  19843200                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     10040827.79                       # Average gap between requests
+system.physmem.pageHitRate                      81.51                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3348660                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1772265                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  18335520                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3484144560                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             1795262310                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            30431523750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              35736125550                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.920144                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    50622338000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1781260000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       940274500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3923640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2140875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  21247200                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           173328480.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy               64638000                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                9138240                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy         468346770                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy         218747040                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        12435217200                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              13392872175                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              250.626273                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime            53271099000                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE       16953500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF        73680000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    51675337000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN    569631000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        74922500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN   1027097500                       # Time in different power states
+system.physmem_1.actEnergy                    3677100                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1950630                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  19663560                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3484144560                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             1822659075                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            30407483250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              35741598600                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.022916                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    50582866250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1781260000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       980601250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  53349450500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                11450641                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           8210938                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            765018                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              6085190                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5320739                       # Number of BTB hits
+system.physmem_1.refreshEnergy           191767680.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               68393160                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                9924480                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy         510653310                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy         251520000                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        12393371550                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              13451137230                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              251.716611                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime            53261175500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE       18732000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF        81534000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    51486455000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN    654968250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        76126500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN   1119805750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED  53437621500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                11450652                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           8210942                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            765019                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              6085116                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5320742                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             87.437516                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1176674                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             87.438629                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1176677                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                216                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups           26315                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits              24242                       # Number of indirect target hits.
@@ -282,10 +292,10 @@ system.cpu.dtb.data_hits                     26995130                       # DT
 system.cpu.dtb.data_misses                      43659                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_accesses                 27038789                       # DTB accesses
-system.cpu.itb.fetch_hits                    22968614                       # ITB hits
+system.cpu.itb.fetch_hits                    22968644                       # ITB hits
 system.cpu.itb.fetch_misses                        90                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                22968704                       # ITB accesses
+system.cpu.itb.fetch_accesses                22968734                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -299,16 +309,16 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     53349450500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        106698901                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     53437621500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        106875243                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    91903089                       # Number of instructions committed
 system.cpu.committedOps                      91903089                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2191321                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2191333                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.160994                       # CPI: cycles per instruction
-system.cpu.ipc                               0.861331                       # IPC: instructions per cycle
+system.cpu.cpi                               1.162912                       # CPI: cycles per instruction
+system.cpu.ipc                               0.859910                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass             7723353      8.40%      8.40% # Class of committed instruction
 system.cpu.op_class_0::IntAlu                51001454     55.49%     63.90% # Class of committed instruction
 system.cpu.op_class_0::IntMult                 458252      0.50%     64.40% # Class of committed instruction
@@ -344,76 +354,76 @@ system.cpu.op_class_0::MemWrite               6501126      7.07%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                 91903089                       # Class of committed instruction
-system.cpu.tickCycles                       103791781                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         2907120                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  53349450500                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                       103792204                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3083039                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  53437621500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1447.584590                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26572201                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1447.203649                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26572187                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2231                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          11910.444195                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          11910.437920                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1447.584590                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.353414                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.353414                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1447.203649                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.353321                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.353321                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2074                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           44                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          228                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          405                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1379                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.506348                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          53153439                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         53153439                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  53349450500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     20074005                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20074005                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6498196                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6498196                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      26572201                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26572201                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26572201                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26572201                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses          53153435                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         53153435                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  53437621500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     20074003                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20074003                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6498184                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6498184                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      26572187                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26572187                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26572187                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26572187                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          496                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           496                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         2907                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         2907                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         3403                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           3403                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         3403                       # number of overall misses
-system.cpu.dcache.overall_misses::total          3403                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     37687000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     37687000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    223750000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    223750000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    261437000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    261437000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    261437000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    261437000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20074501                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20074501                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data         2919                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         2919                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         3415                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           3415                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         3415                       # number of overall misses
+system.cpu.dcache.overall_misses::total          3415                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     58822000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     58822000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    274731500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    274731500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    333553500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    333553500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    333553500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    333553500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20074499                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20074499                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     26575604                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     26575604                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     26575604                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     26575604                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     26575602                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     26575602                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     26575602                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     26575602                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000025                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000025                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000447                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000447                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000128                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000128                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000128                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000128                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75981.854839                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75981.854839                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76969.384245                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76969.384245                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 76825.448134                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 76825.448134                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 76825.448134                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 76825.448134                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000449                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000449                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000129                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000129                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000129                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000129                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 118592.741935                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 118592.741935                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94118.362453                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 94118.362453                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 97673.060029                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 97673.060029                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 97673.060029                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 97673.060029                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -424,12 +434,12 @@ system.cpu.dcache.writebacks::writebacks          107                       # nu
 system.cpu.dcache.writebacks::total               107                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            8                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total            8                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         1164                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         1164                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         1172                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         1172                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         1172                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         1172                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         1176                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         1176                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         1184                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         1184                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         1184                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         1184                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          488                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          488                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1743                       # number of WriteReq MSHR misses
@@ -438,14 +448,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2231
 system.cpu.dcache.demand_mshr_misses::total         2231                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2231                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2231                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36777500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     36777500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    140150000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    140150000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    176927500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    176927500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    176927500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    176927500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     57888500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     57888500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    165966000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    165966000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    223854500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    223854500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    223854500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    223854500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000268                       # mshr miss rate for WriteReq accesses
@@ -454,70 +464,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75363.729508                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75363.729508                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80407.343660                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80407.343660                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79304.123711                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 79304.123711                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79304.123711                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 79304.123711                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  53349450500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 118623.975410                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 118623.975410                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95218.588640                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95218.588640                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100338.189153                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 100338.189153                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100338.189153                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 100338.189153                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  53437621500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             13865                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1642.701416                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22952783                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1642.239495                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22952813                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             15830                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1449.954706                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1449.956601                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1642.701416                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.802100                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.802100                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1642.239495                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.801875                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.801875                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1965                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          146                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          670                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3          150                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          947                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.959473                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          45953058                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         45953058                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  53349450500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     22952783                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22952783                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      22952783                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22952783                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     22952783                       # number of overall hits
-system.cpu.icache.overall_hits::total        22952783                       # number of overall hits
+system.cpu.icache.tags.tag_accesses          45953118                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45953118                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  53437621500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     22952813                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22952813                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22952813                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22952813                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22952813                       # number of overall hits
+system.cpu.icache.overall_hits::total        22952813                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        15831                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         15831                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        15831                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          15831                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        15831                       # number of overall misses
 system.cpu.icache.overall_misses::total         15831                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    411111000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    411111000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    411111000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    411111000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    411111000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    411111000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22968614                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22968614                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22968614                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22968614                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22968614                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22968614                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    456439000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    456439000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    456439000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    456439000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    456439000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    456439000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22968644                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22968644                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22968644                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22968644                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22968644                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22968644                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000689                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000689                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000689                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000689                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000689                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000689                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25968.732234                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 25968.732234                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 25968.732234                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 25968.732234                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 25968.732234                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 25968.732234                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28831.975238                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28831.975238                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28831.975238                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28831.975238                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28831.975238                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28831.975238                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -532,46 +542,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        15831
 system.cpu.icache.demand_mshr_misses::total        15831                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        15831                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        15831                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    395281000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    395281000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    395281000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    395281000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    395281000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    395281000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    440609000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    440609000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    440609000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    440609000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    440609000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    440609000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000689                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000689                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000689                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000689                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000689                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000689                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24968.795401                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24968.795401                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24968.795401                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 24968.795401                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24968.795401                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 24968.795401                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  53349450500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27832.038406                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27832.038406                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27832.038406                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 27832.038406                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27832.038406                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 27832.038406                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  53437621500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3575.444447                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         3574.446973                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              26761                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             5322                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             5.028373                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2102.450993                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1472.993454                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064162                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.044952                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.109114                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2101.836656                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1472.610316                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064143                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.044941                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.109083                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         5322                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          164                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          920                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          569                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3605                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.162415                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses           261986                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses          261986                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  53349450500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  53437621500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks          107                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total          107                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks        13865                       # number of WritebackClean hits
@@ -600,18 +610,18 @@ system.cpu.l2cache.demand_misses::total          5322                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3170                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         2152                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         5322                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    137262000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    137262000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    238604500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    238604500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     35483000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     35483000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    238604500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    172745000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    411349500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    238604500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    172745000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    411349500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    163078000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    163078000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    283932500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    283932500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     56594000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     56594000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    283932500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    219672000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    503604500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    283932500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    219672000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    503604500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks          107                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total          107                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks        13865                       # number of WritebackClean accesses(hits+misses)
@@ -640,18 +650,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.294668                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200253                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.964590                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.294668                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79942.923704                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79942.923704                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75269.558360                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75269.558360                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81570.114943                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81570.114943                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75269.558360                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80271.840149                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77292.277339                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75269.558360                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80271.840149                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77292.277339                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94978.450786                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94978.450786                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89568.611987                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89568.611987                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 130101.149425                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 130101.149425                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89568.611987                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 102078.066914                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 94626.925968                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89568.611987                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 102078.066914                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 94626.925968                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -670,18 +680,18 @@ system.cpu.l2cache.demand_mshr_misses::total         5322
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3170                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2152                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         5322                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    120092000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    120092000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    206904500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    206904500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31133000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31133000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    206904500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    151225000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    358129500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    206904500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    151225000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    358129500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    145908000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    145908000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    252232500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    252232500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     52244000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     52244000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    252232500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    198152000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    450384500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    252232500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    198152000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    450384500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985083                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985083                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.200253                       # mshr miss rate for ReadCleanReq accesses
@@ -694,25 +704,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.294668
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200253                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964590                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.294668                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69942.923704                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69942.923704                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65269.558360                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65269.558360                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71570.114943                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71570.114943                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65269.558360                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70271.840149                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67292.277339                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65269.558360                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70271.840149                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67292.277339                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84978.450786                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84978.450786                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79568.611987                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79568.611987                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 120101.149425                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 120101.149425                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79568.611987                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92078.066914                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84626.925968                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79568.611987                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92078.066914                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84626.925968                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests        32083                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests        14022                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  53349450500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  53437621500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp         16318                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty          107                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        13865                       # Transaction distribution
@@ -752,7 +762,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  53349450500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED  53437621500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp               3605                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1717                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1717                       # Transaction distribution
@@ -773,9 +783,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                5322                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6421000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             6424500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           28180500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           28175000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index d82573b75..f4beb67d4 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -591,7 +591,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -708,6 +708,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -727,29 +728,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -769,6 +777,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -800,9 +809,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
index 1d7fd9550..e5a3bf839 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:29
-gem5 executing on e108600-lin, pid 4313
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:45
+gem5 executing on e108600-lin, pid 28064
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/o3-timing
 
 Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
@@ -26,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 21909208500 because target called exit()
+122 123 124 Exiting @ tick 21954917500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 720778178..2ed297d74 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,48 +1,48 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.021906                       # Number of seconds simulated
-sim_ticks                                 21906070500                       # Number of ticks simulated
-final_tick                                21906070500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.021955                       # Number of seconds simulated
+sim_ticks                                 21954917500                       # Number of ticks simulated
+final_tick                                21954917500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 201237                       # Simulator instruction rate (inst/s)
-host_op_rate                                   201237                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               52367931                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 260088                       # Number of bytes of host memory used
-host_seconds                                   418.31                       # Real time elapsed on the host
+host_inst_rate                                 181107                       # Simulator instruction rate (inst/s)
+host_op_rate                                   181107                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               47234568                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257228                       # Number of bytes of host memory used
+host_seconds                                   464.81                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            195968                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED  21954917500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            195904                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            138560                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               334528                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       195968                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          195968                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3062                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               334464                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       195904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          195904                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3061                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               2165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5227                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8945831                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              6325187                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15271018                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8945831                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8945831                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8945831                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             6325187                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               15271018                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5227                       # Number of read requests accepted
+system.physmem.num_reads::total                  5226                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              8923012                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              6311115                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15234127                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8923012                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8923012                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8923012                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             6311115                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               15234127                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5226                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5227                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5226                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   334528                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   334464                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    334528                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    334464                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 470                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 469                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 292                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 302                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 523                       # Per bank write bursts
@@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     21905974500                       # Total gap between requests
+system.physmem.totGap                     21954815500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5227                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5226                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -91,11 +91,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3276                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1193                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       513                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       227                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        16                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3223                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1200                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       523                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       260                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -187,105 +187,115 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          862                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      385.707657                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     229.399691                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     360.883028                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            260     30.16%     30.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          179     20.77%     50.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           93     10.79%     61.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           57      6.61%     68.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           30      3.48%     71.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           37      4.29%     76.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           31      3.60%     79.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           50      5.80%     85.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          125     14.50%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            862                       # Bytes accessed per row activation
-system.physmem.totQLat                       40339750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 138346000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26135000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7717.57                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          861                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      385.932636                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     229.340491                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     360.649518                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            261     30.31%     30.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          173     20.09%     50.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           93     10.80%     61.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           57      6.62%     67.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           37      4.30%     72.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           30      3.48%     75.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           47      5.46%     81.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           33      3.83%     84.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          130     15.10%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            861                       # Bytes accessed per row activation
+system.physmem.totQLat                      128746000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 226733500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26130000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       24635.67                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26467.57                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.27                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  43385.67                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          15.23                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       15.27                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       15.23                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.12                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4357                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4356                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.36                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.35                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      4190926.82                       # Average gap between requests
-system.physmem.pageHitRate                      83.36                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3129840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1707750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  19570200                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      4201074.53                       # Average gap between requests
+system.physmem.pageHitRate                      83.35                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3034500                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1593900                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  18099900                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             1430579280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy              905463810                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            12347522250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              14707973130                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.505534                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    20538678250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF       731380000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       632936750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3333960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1819125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  20779200                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           118625520.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy               48811380                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                6176640                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy         312556080                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy         154176960                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy         5001436845                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy               5664547785                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              258.008156                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime            21831003750                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE       11536500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF        50426000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    20744771750                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN    401491250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        61308000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN    685384000                       # Time in different power states
+system.physmem_1.actEnergy                    3177300                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1673595                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  19213740                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             1430579280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy              902236185                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            12350353500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              14709101250                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.557040                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    20543762750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF       731380000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       628284250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                16102243                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11688063                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            931000                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8962915                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7507921                       # Number of BTB hits
+system.physmem_1.refreshEnergy           106332720.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               46621440                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                5256960                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy         301076850                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy         131936160                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy         5018107080                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy               5633395845                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              256.589251                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime            21838957750                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE        9258500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF        45178000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    20835144000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN    343577000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        61468500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN    660291500                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED  21954917500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                16102182                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11688137                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            930988                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8963257                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7508303                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.766509                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1594308                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             83.767575                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1594537                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                466                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups           29379                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits              25730                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses             3649                       # Number of indirect misses.
+system.cpu.branchPred.indirectLookups           29363                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              25724                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             3639                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted          560                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     24059471                       # DTB read hits
-system.cpu.dtb.read_misses                     206747                       # DTB read misses
-system.cpu.dtb.read_acv                             6                       # DTB read access violations
-system.cpu.dtb.read_accesses                 24266218                       # DTB read accesses
-system.cpu.dtb.write_hits                     7167964                       # DTB write hits
-system.cpu.dtb.write_misses                      1190                       # DTB write misses
+system.cpu.dtb.read_hits                     24064359                       # DTB read hits
+system.cpu.dtb.read_misses                     206311                       # DTB read misses
+system.cpu.dtb.read_acv                             4                       # DTB read access violations
+system.cpu.dtb.read_accesses                 24270670                       # DTB read accesses
+system.cpu.dtb.write_hits                     7168837                       # DTB write hits
+system.cpu.dtb.write_misses                      1192                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 7169154                       # DTB write accesses
-system.cpu.dtb.data_hits                     31227435                       # DTB hits
-system.cpu.dtb.data_misses                     207937                       # DTB misses
-system.cpu.dtb.data_acv                             6                       # DTB access violations
-system.cpu.dtb.data_accesses                 31435372                       # DTB accesses
-system.cpu.itb.fetch_hits                    15930202                       # ITB hits
+system.cpu.dtb.write_accesses                 7170029                       # DTB write accesses
+system.cpu.dtb.data_hits                     31233196                       # DTB hits
+system.cpu.dtb.data_misses                     207503                       # DTB misses
+system.cpu.dtb.data_acv                             4                       # DTB access violations
+system.cpu.dtb.data_accesses                 31440699                       # DTB accesses
+system.cpu.itb.fetch_hits                    15932695                       # ITB hits
 system.cpu.itb.fetch_misses                        79                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                15930281                       # ITB accesses
+system.cpu.itb.fetch_accesses                15932774                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -299,140 +309,140 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     21906070500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                         43812142                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     21954917500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                         43909836                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           16640800                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      137955116                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16102243                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9127959                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      25951378                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1939862                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  140                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          2284                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           28                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  15930202                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                367997                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           43564561                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.166682                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.433652                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           16643979                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      137979397                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16102182                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9128564                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      26000321                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1939876                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  155                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          2307                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           30                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  15932695                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                367713                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           43616730                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.163451                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.433365                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 19388904     44.51%     44.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2617971      6.01%     50.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1329653      3.05%     53.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1933242      4.44%     58.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3001866      6.89%     64.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1292154      2.97%     67.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1355153      3.11%     70.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   885983      2.03%     73.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 11759635     26.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 19436456     44.56%     44.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2618537      6.00%     50.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1330059      3.05%     53.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1934096      4.43%     58.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3001834      6.88%     64.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1292274      2.96%     67.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1355703      3.11%     71.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   886638      2.03%     73.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 11761133     26.96%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             43564561                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.367529                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.148787                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 12866207                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               8201064                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19435677                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2103016                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 958597                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2653560                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 11864                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              132121785                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 49799                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 958597                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 13983011                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4637206                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          10599                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  20305280                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3669868                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              128752916                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 70736                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2012785                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1367413                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  56554                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            94580122                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             167299448                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        159747069                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           7552378                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             43616730                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.366710                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.142335                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 12867029                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               8250930                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19434015                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2106147                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 958609                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2654207                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 11848                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              132149793                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 49699                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 958609                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13986200                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4658485                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          10631                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20305693                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3697112                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              128776944                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 70815                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2027533                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1361651                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  79521                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            94599397                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             167333600                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        159779432                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           7554167                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 26152761                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                954                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            949                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   8254781                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26901517                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             8704631                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           3463893                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1634991                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  111837286                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1924                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  99746434                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            118591                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        27659500                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     21091403                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1535                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      43564561                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.289623                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.099110                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 26172036                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                950                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            946                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8272242                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26904484                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             8704450                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3461355                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1614052                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  111855473                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1918                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  99762246                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            119439                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        27677681                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     21095832                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1529                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      43616730                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.287247                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.099564                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            11223672     25.76%     25.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             7655343     17.57%     43.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7467756     17.14%     60.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5704970     13.10%     73.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4467403     10.25%     83.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2981246      6.84%     90.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2039535      4.68%     95.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1169471      2.68%     98.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              855165      1.96%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            11270720     25.84%     25.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             7659760     17.56%     43.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7470187     17.13%     60.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5700495     13.07%     73.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4466514     10.24%     83.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2981046      6.83%     90.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2041941      4.68%     95.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1170841      2.68%     98.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              855226      1.96%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        43564561                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        43616730                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  481664     20.16%     20.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  484010     20.16%     20.16% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     20.16% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                   522      0.02%     20.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   538      0.02%     20.18% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                 34768      1.46%     21.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                12121      0.51%     22.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1011551     42.34%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 688710     28.83%     93.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                159620      6.68%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                 34926      1.45%     21.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                12192      0.51%     22.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1012503     42.17%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 694860     28.94%     93.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                162157      6.75%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              60652801     60.81%     60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               489881      0.49%     61.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              60662676     60.81%     60.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               489936      0.49%     61.30% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2847832      2.86%     64.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp              115342      0.12%     64.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2442782      2.45%     66.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult             314177      0.31%     67.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv              766025      0.77%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2847523      2.85%     64.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              115351      0.12%     64.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2443321      2.45%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             314198      0.31%     67.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              765838      0.77%     67.80% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.80% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.80% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.80% # Type of FU issued
@@ -454,82 +464,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.80% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.80% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.80% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24850091     24.91%     92.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             7267177      7.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24854622     24.91%     92.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7268455      7.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               99746434                       # Type of FU issued
-system.cpu.iq.rate                           2.276685                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2388956                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023950                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          229877287                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         129889935                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     89741335                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            15687689                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            9649325                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      7189295                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               93754597                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 8380786                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1921314                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               99762246                       # Type of FU issued
+system.cpu.iq.rate                           2.271979                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2401186                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.024069                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          229973015                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         129921960                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     89757276                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            15688832                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9653681                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7189481                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               93781523                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 8381902                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1923320                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6905319                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        11494                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        40918                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2203528                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6908286                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11342                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        40947                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2203347                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        42875                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1512                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        42864                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          1503                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 958597                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3610605                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                461685                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           122758059                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            241249                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26901517                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              8704631                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1924                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  38682                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                417297                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          40918                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         531922                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       502439                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1034361                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              98421413                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              24266766                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1325021                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 958609                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3613912                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                479107                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           122779790                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            241415                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              26904484                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              8704450                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1918                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  38391                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                434865                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          40947                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         531949                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       502384                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1034333                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              98436741                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              24271214                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1325505                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      10918849                       # number of nop insts executed
-system.cpu.iew.exec_refs                     31435958                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 12470734                       # Number of branches executed
-system.cpu.iew.exec_stores                    7169192                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.246441                       # Inst execution rate
-system.cpu.iew.wb_sent                       97629714                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      96930630                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  66965531                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  94946242                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       2.212415                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.705299                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        30856710                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                      10922399                       # number of nop insts executed
+system.cpu.iew.exec_refs                     31441282                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 12471732                       # Number of branches executed
+system.cpu.iew.exec_stores                    7170068                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.241792                       # Inst execution rate
+system.cpu.iew.wb_sent                       97645487                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      96946757                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  66976137                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  94960144                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       2.207860                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.705308                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        30878503                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            919666                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     39073158                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.352076                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.920100                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            919659                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     39122931                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.349084                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.919383                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     14677251     37.56%     37.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8528323     21.83%     59.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3880033      9.93%     69.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1914323      4.90%     74.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1374739      3.52%     77.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1034073      2.65%     80.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       692942      1.77%     82.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       727068      1.86%     84.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6244406     15.98%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     14724541     37.64%     37.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8532800     21.81%     59.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3880104      9.92%     69.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1909784      4.88%     74.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1376640      3.52%     77.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1034511      2.64%     80.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       692868      1.77%     82.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       729092      1.86%     84.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6242591     15.96%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     39073158                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     39122931                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
 system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -575,118 +585,118 @@ system.cpu.commit.op_class_0::MemWrite        6501103      7.07%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91903055                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               6244406                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    155587477                       # The number of ROB reads
-system.cpu.rob.rob_writes                   250066312                       # The number of ROB writes
-system.cpu.timesIdled                            4758                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          247581                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               6242591                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    155660858                       # The number of ROB reads
+system.cpu.rob.rob_writes                   250112359                       # The number of ROB writes
+system.cpu.timesIdled                            4774                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          293106                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.520460                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.520460                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.921379                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.921379                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                132984940                       # number of integer regfile reads
-system.cpu.int_regfile_writes                72890464                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   6263699                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  6177982                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                  719169                       # number of misc regfile reads
+system.cpu.cpi                               0.521620                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.521620                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.917104                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.917104                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                133010551                       # number of integer regfile reads
+system.cpu.int_regfile_writes                72904644                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   6263409                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6178123                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  719113                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  21954917500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements               158                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1457.358075                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28585648                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1457.034872                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28588531                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2245                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          12733.028062                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          12734.312249                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1457.358075                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.355800                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.355800                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1457.034872                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.355721                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.355721                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2087                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          543                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1389                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.509521                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          57192649                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         57192649                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     22092545                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22092545                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6492630                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6492630                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data          473                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total          473                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      28585175                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28585175                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28585175                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28585175                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1080                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1080                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8473                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8473                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses          57198427                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         57198427                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  21954917500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     22095438                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22095438                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6492623                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6492623                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data          470                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total          470                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      28588061                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28588061                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28588061                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28588061                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1079                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1079                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8480                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8480                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9553                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9553                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9553                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9553                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     72549500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     72549500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    550211742                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    550211742                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        86000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        86000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    622761242                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    622761242                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    622761242                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    622761242                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22093625                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22093625                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         9559                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9559                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9559                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9559                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     87318000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     87318000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    649645257                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    649645257                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       106000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       106000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    736963257                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    736963257                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    736963257                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    736963257                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22096517                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22096517                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data          474                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total          474                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28594728                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28594728                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28594728                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28594728                       # number of overall (read+write) accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data          471                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total          471                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     28597620                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28597620                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28597620                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28597620                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000049                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000049                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001303                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001303                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002110                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002110                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001304                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001304                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002123                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002123                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000334                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000334                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000334                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000334                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67175.462963                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67175.462963                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64937.063850                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64937.063850                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        86000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        86000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65190.122684                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65190.122684                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65190.122684                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65190.122684                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        33457                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          131                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               396                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    84.487374                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    65.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80924.930491                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 80924.930491                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76609.110495                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 76609.110495                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data       106000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total       106000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 77096.271263                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 77096.271263                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 77096.271263                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 77096.271263                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        43101                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          174                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               350                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               3                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs   123.145714                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           58                       # average number of cycles each access was blocked
 system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
 system.cpu.dcache.writebacks::total               108                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          565                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          565                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6744                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6744                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7309                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7309                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7309                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7309                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          564                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          564                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6751                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6751                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         7315                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7315                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7315                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7315                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          515                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          515                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1729                       # number of WriteReq MSHR misses
@@ -697,232 +707,232 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2244
 system.cpu.dcache.demand_mshr_misses::total         2244                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2244                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2244                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     40822500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     40822500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    136978995                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    136978995                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        85000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        85000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    177801495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    177801495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    177801495                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    177801495                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     47711000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     47711000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    177283495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    177283495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data       105000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total       105000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    224994495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    224994495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    224994495                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    224994495                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000266                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000266                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.002110                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.002110                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.002123                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.002123                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000078                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000078                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79266.990291                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79266.990291                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79224.404280                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79224.404280                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        85000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        85000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79234.177807                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 79234.177807                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79234.177807                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 79234.177807                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements              9515                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1600.893985                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            15915792                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             11453                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1389.661399                       # Average number of references to valid blocks.
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92642.718447                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92642.718447                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102535.277617                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102535.277617                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data       105000                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total       105000                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100264.926471                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 100264.926471                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100264.926471                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 100264.926471                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  21954917500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements              9511                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1600.395362                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            15918262                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             11449                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1390.362652                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1600.893985                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.781687                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.781687                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1600.395362                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.781443                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.781443                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1938                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          753                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          181                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          752                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          943                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          944                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.946289                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          31871855                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         31871855                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     15915792                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        15915792                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      15915792                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         15915792                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     15915792                       # number of overall hits
-system.cpu.icache.overall_hits::total        15915792                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        14409                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         14409                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        14409                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          14409                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        14409                       # number of overall misses
-system.cpu.icache.overall_misses::total         14409                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    447639000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    447639000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    447639000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    447639000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    447639000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    447639000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     15930201                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     15930201                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     15930201                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     15930201                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     15930201                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     15930201                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000905                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000905                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000905                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000905                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000905                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000905                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31066.625026                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 31066.625026                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 31066.625026                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 31066.625026                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 31066.625026                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 31066.625026                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          446                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          31876835                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         31876835                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  21954917500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     15918262                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        15918262                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      15918262                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         15918262                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     15918262                       # number of overall hits
+system.cpu.icache.overall_hits::total        15918262                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        14431                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         14431                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        14431                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          14431                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        14431                       # number of overall misses
+system.cpu.icache.overall_misses::total         14431                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    508617000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    508617000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    508617000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    508617000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    508617000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    508617000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     15932693                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     15932693                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     15932693                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     15932693                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     15932693                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     15932693                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000906                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000906                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000906                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000906                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000906                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000906                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35244.750884                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35244.750884                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35244.750884                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35244.750884                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35244.750884                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35244.750884                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          485                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    89.200000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    80.833333                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks         9515                       # number of writebacks
-system.cpu.icache.writebacks::total              9515                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2955                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2955                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2955                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2955                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2955                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2955                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11454                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        11454                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        11454                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        11454                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        11454                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        11454                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    337628000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    337628000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    337628000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    337628000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    337628000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    337628000                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks         9511                       # number of writebacks
+system.cpu.icache.writebacks::total              9511                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2981                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2981                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2981                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2981                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2981                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2981                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11450                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        11450                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        11450                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        11450                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        11450                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        11450                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    378748000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    378748000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    378748000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    378748000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    378748000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    378748000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000719                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000719                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000719                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000719                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000719                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000719                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29476.863978                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29476.863978                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29476.863978                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 29476.863978                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29476.863978                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 29476.863978                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33078.427948                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33078.427948                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33078.427948                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 33078.427948                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33078.427948                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 33078.427948                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  21954917500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3490.224517                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              18145                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5227                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             3.471399                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         3489.228607                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              18138                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5226                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             3.470723                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2007.515587                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1482.708930                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061265                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.045249                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.106513                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5227                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          263                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1371                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2006.844021                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1482.384585                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061244                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.045239                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.106483                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5226                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          265                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1370                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3517                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.159515                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           192203                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          192203                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.159485                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           192138                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          192138                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  21954917500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks          108                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total          108                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         9515                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         9515                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         9511                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         9511                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8392                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         8392                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8389                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         8389                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data           54                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total           54                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8392                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         8389                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           80                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            8472                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8392                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            8469                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8389                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           80                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           8472                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           8469                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1703                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1703                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3062                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3062                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3061                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3061                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data          462                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total          462                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3062                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         3061                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         2165                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5227                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3062                       # number of overall misses
+system.cpu.l2cache.demand_misses::total          5226                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3061                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         2165                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5227                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    133969500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    133969500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    232023500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    232023500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     39550000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     39550000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    232023500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    173519500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    405543000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    232023500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    173519500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    405543000                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total         5226                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    174274000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    174274000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    273178000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    273178000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     46458500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     46458500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    273178000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    220732500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    493910500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    273178000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    220732500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    493910500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks          108                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total          108                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         9515                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         9515                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         9511                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         9511                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1729                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1729                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        11454                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        11454                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        11450                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        11450                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          516                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          516                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        11454                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        11450                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         2245                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        13699                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        11454                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        13695                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        11450                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         2245                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        13699                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        13695                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.984962                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.984962                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.267330                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.267330                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.267336                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.267336                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.895349                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.895349                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.267330                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.267336                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.964365                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.381561                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.267330                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.381599                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.267336                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.964365                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.381561                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78666.764533                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78666.764533                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75775.146963                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75775.146963                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85606.060606                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85606.060606                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75775.146963                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80147.575058                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77586.187105                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75775.146963                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80147.575058                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77586.187105                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.381599                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102333.529066                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102333.529066                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89244.691277                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89244.691277                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100559.523810                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100559.523810                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89244.691277                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101954.965358                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 94510.237275                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89244.691277                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101954.965358                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 94510.237275                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -931,122 +941,122 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1703                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1703                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3062                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3062                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3061                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3061                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          462                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total          462                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3062                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3061                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         2165                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5227                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3062                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5226                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3061                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2165                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5227                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    116939500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    116939500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    201403500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    201403500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     34930000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     34930000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    201403500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    151869500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    353273000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    201403500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    151869500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    353273000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total         5226                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    157244000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    157244000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    242568000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    242568000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     41838500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     41838500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    242568000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    199082500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    441650500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    242568000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    199082500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    441650500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.984962                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.984962                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.267330                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.267330                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.267336                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.267336                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.895349                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.895349                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.267330                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.267336                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964365                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.381561                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.267330                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.381599                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.267336                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964365                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.381561                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68666.764533                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68666.764533                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65775.146963                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65775.146963                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75606.060606                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75606.060606                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65775.146963                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70147.575058                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67586.187105                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65775.146963                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70147.575058                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67586.187105                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests        23372                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         9673                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.381599                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92333.529066                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92333.529066                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79244.691277                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79244.691277                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90559.523810                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90559.523810                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79244.691277                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91954.965358                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84510.237275                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79244.691277                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91954.965358                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84510.237275                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests        23364                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         9669                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp         11969                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  21954917500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp         11965                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty          108                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         9515                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         9511                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict           50                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1729                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1729                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        11454                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        11450                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          516                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32422                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32410                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4648                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             37070                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1341952                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             37058                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1341440                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150592                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            1492544                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            1492032                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
 system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples        13699                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        13695                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              13699    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              13695    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          13699                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       21309000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          13695                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       21301000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      17179500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      17173500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       3367500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests          5227                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.tot_requests          5226                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp               3524                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED  21954917500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp               3523                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1703                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1703                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3524                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10454                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10454                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  334528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          3523                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10452                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10452                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334464                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  334464                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples              5227                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5226                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5227    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5226    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5227                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6278000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5226                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6271000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           27461750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           27424000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
index cdcb110c1..701cef29f 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
@@ -151,7 +151,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -631,7 +631,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -691,7 +691,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -880,6 +880,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -891,7 +892,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -899,29 +900,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -941,6 +949,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -972,9 +981,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
index 90ea58e8e..862c8292b 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timin
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:40:38
-gem5 executing on e108600-lin, pid 23114
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:49:48
+gem5 executing on e108600-lin, pid 17449
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/arm/linux/minor-timing
 
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav
@@ -26,4 +26,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 132485848500 because target called exit()
+122 123 124 Exiting @ tick 132538562500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
index 9382954d5..26e7200e9 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.132488                       # Number of seconds simulated
-sim_ticks                                132487590500                       # Number of ticks simulated
-final_tick                               132487590500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.132539                       # Number of seconds simulated
+sim_ticks                                132538562500                       # Number of ticks simulated
+final_tick                               132538562500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 200266                       # Simulator instruction rate (inst/s)
-host_op_rate                                   211113                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              153975874                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275560                       # Number of bytes of host memory used
-host_seconds                                   860.44                       # Real time elapsed on the host
+host_inst_rate                                 171463                       # Simulator instruction rate (inst/s)
+host_op_rate                                   180750                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              131881088                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273644                       # Number of bytes of host memory used
+host_seconds                                  1004.99                       # Real time elapsed on the host
 sim_insts                                   172317810                       # Number of instructions simulated
 sim_ops                                     181650743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            138240                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            109312                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               247552                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total          138240                       # Nu
 system.physmem.num_reads::cpu.inst               2160                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               1708                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  3868                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1043418                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               825073                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1868492                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1043418                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1043418                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1043418                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              825073                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1868492                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1043017                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               824756                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1867773                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1043017                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1043017                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1043017                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              824756                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                1867773                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          3868                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        3868                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    132487495500                       # Total gap between requests
+system.physmem.totGap                    132538461500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3626                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       233                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         9                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3621                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       237                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          926                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      265.468683                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.726650                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     275.485307                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            276     29.81%     29.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          359     38.77%     68.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           87      9.40%     77.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           56      6.05%     84.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           31      3.35%     87.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           22      2.38%     89.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           18      1.94%     91.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           16      1.73%     93.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           61      6.59%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            926                       # Bytes accessed per row activation
-system.physmem.totQLat                       28381250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 100906250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          928                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      265.103448                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.439776                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     277.287318                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            274     29.53%     29.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          366     39.44%     68.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           89      9.59%     78.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           57      6.14%     84.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           24      2.59%     87.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           19      2.05%     89.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           18      1.94%     91.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           18      1.94%     93.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           63      6.79%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            928                       # Bytes accessed per row activation
+system.physmem.totQLat                       84421250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 156946250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     19340000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7337.45                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       21825.56                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26087.45                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  40575.56                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.87                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.87                       # Average system read bandwidth in MiByte/s
@@ -217,56 +217,66 @@ system.physmem.busUtilRead                       0.01                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       2936                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       2935                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.90                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   75.88                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     34252196.35                       # Average gap between requests
-system.physmem.pageHitRate                      75.90                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3190320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1740750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  16161600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     34265372.67                       # Average gap between requests
+system.physmem.pageHitRate                      75.88                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    2977380                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1582515                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  14822640                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             8653148400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3615176835                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            76318766250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              88608184155                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.825360                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   126962854750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      4423900000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1098483750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3795120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2070750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  13782600                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           159806400.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy               56564520                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                6779040                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy         507399750                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy         193240800                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        31407910590                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              32351114145                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              244.088313                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           132395468250                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE       11004000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF        67828000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   130780838250                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN    503202000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        62983500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN   1112706750                       # Time in different power states
+system.physmem_1.actEnergy                    3684240                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1939245                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  12794880                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             8653148400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3628387440                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            76307186250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              88608370560                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.826698                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   126942838750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      4423900000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1117460750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                49693795                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          39499605                       # Number of conditional branches predicted
+system.physmem_1.refreshEnergy           142596480.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               50045430                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                5323200                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy         514216380                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy         148467840                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        31429438665                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              32308536150                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              243.767063                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           132414854750                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE        7934000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF        60464000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   130900584250                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN    386668500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        55249000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN   1127662750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                49693791                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          39499604                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           5516746                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             24160974                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups             24160971                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                22899506                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.778903                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1894449                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             94.778914                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1894448                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                142                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups          213843                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits             208090                       # Number of indirect target hits.
 system.cpu.branchPred.indirectMisses             5753                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted        40382                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -296,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -326,7 +336,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -356,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -387,16 +397,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    132487590500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        264975181                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    132538562500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        265077125                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   172317810                       # Number of instructions committed
 system.cpu.committedOps                     181650743                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      11524054                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      11524051                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.537712                       # CPI: cycles per instruction
-system.cpu.ipc                               0.650317                       # IPC: instructions per cycle
+system.cpu.cpi                               1.538304                       # CPI: cycles per instruction
+system.cpu.ipc                               0.650067                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu               138988213     76.51%     76.51% # Class of committed instruction
 system.cpu.op_class_0::IntMult                 908940      0.50%     77.01% # Class of committed instruction
@@ -432,62 +442,62 @@ system.cpu.op_class_0::MemWrite              12644635      6.96%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                181650743                       # Class of committed instruction
-system.cpu.tickCycles                       256731939                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         8243242                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                       256741537                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         8335588                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                42                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1378.670840                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40755401                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1378.587934                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40755397                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              1811                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          22504.362783                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          22504.360574                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1378.670840                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.336590                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.336590                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1378.587934                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.336569                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.336569                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         1769                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           83                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          271                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1359                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.431885                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          81517419                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         81517419                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     28347489                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28347489                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12362636                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12362636                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          81517417                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         81517417                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     28347488                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28347488                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12362633                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12362633                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          462                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           462                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40710125                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40710125                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40710587                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40710587                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data      40710121                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40710121                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40710583                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40710583                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          751                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           751                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1651                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1651                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1654                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1654                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         2402                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2402                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2403                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2403                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     55860000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     55860000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    128578000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    128578000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    184438000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    184438000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    184438000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    184438000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     28348240                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28348240                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         2405                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2405                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2406                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2406                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     64864500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     64864500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    147460000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    147460000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    212324500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    212324500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    212324500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    212324500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     28348239                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28348239                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          463                       # number of SoftPFReq accesses(hits+misses)
@@ -496,10 +506,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407
 system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     40712527                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     40712527                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     40712990                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     40712990                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     40712526                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     40712526                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     40712989                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     40712989                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000026                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000026                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000134                       # miss rate for WriteReq accesses
@@ -510,14 +520,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000059
 system.cpu.dcache.demand_miss_rate::total     0.000059                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000059                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000059                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 76785.179017                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 76753.225135                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86370.838881                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 86370.838881                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89153.567110                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 89153.567110                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 88284.615385                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 88284.615385                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 88247.921862                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 88247.921862                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -528,12 +538,12 @@ system.cpu.dcache.writebacks::writebacks           16                       # nu
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           40                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           40                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          552                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          552                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          592                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          592                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          592                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          592                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          555                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          555                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          595                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          595                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          595                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          595                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          711                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          711                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1099                       # number of WriteReq MSHR misses
@@ -544,16 +554,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         1810
 system.cpu.dcache.demand_mshr_misses::total         1810                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         1811                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         1811                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     52704000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     52704000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     87045000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     87045000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        71000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        71000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    139749000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    139749000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    139820000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    139820000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     61185500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     61185500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    100181500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    100181500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        77000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        77000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    161367000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    161367000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    161444000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    161444000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
@@ -564,72 +574,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000044
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000044                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000044                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        71000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        71000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86055.555556                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86055.555556                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91156.960874                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91156.960874                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        77000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        77000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89153.038674                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 89153.038674                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89146.327996                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 89146.327996                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements              2864                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1424.957423                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            70941364                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1424.889067                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            70941363                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              4663                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          15213.674459                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          15213.674244                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1424.957423                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.695780                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.695780                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1424.889067                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.695747                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.695747                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1799                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           59                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          490                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          130                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          491                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          131                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1069                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.878418                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         141896719                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        141896719                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     70941364                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        70941364                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      70941364                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         70941364                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     70941364                       # number of overall hits
-system.cpu.icache.overall_hits::total        70941364                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         141896717                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        141896717                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     70941363                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        70941363                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      70941363                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         70941363                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     70941363                       # number of overall hits
+system.cpu.icache.overall_hits::total        70941363                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         4664                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          4664                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         4664                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total           4664                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         4664                       # number of overall misses
 system.cpu.icache.overall_misses::total          4664                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    201505000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    201505000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    201505000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    201505000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    201505000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    201505000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     70946028                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     70946028                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     70946028                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     70946028                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     70946028                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     70946028                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    236552500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    236552500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    236552500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    236552500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    236552500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    236552500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     70946027                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     70946027                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     70946027                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     70946027                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     70946027                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     70946027                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000066                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000066                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000066                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000066                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000066                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000066                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 43204.331046                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 43204.331046                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50718.803602                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 50718.803602                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 50718.803602                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 50718.803602                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 50718.803602                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 50718.803602                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -644,46 +654,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         4664
 system.cpu.icache.demand_mshr_misses::total         4664                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         4664                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         4664                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    196842000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    196842000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    196842000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    196842000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    196842000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    196842000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    231889500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    231889500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    231889500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    231889500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    231889500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    231889500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000066                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000066                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49719.018010                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49719.018010                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49719.018010                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 49719.018010                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49719.018010                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 49719.018010                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2835.484229                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         2835.336724                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               5160                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             3868                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             1.334023                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1507.704814                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1327.779416                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.046011                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.040521                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.086532                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1507.638236                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1327.698487                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.046009                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.040518                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.086528                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         3868                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          533                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          366                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          535                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          367                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2841                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.118042                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses            76228                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses           76228                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks           16                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total           16                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks         2534                       # number of WritebackClean hits
@@ -712,18 +722,18 @@ system.cpu.l2cache.demand_misses::total          3885                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2162                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         1723                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         3885                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     85311000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     85311000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    163192000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    163192000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     50782500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     50782500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    163192000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    136093500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    299285500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    163192000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    136093500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    299285500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     98447500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     98447500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    198239500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    198239500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     59270000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     59270000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    198239500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    157717500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    355957000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    198239500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    157717500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    355957000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks           16                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total           16                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks         2534                       # number of WritebackClean accesses(hits+misses)
@@ -752,18 +762,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.600000                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.463551                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.951408                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.600000                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78195.233731                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75481.961147                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80352.056962                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75481.961147                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78986.360998                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77036.164736                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75481.961147                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77036.164736                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90236.021998                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90236.021998                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91692.645698                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91692.645698                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93781.645570                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93781.645570                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91692.645698                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91536.564132                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 91623.423423                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91692.645698                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91536.564132                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 91623.423423                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -792,18 +802,18 @@ system.cpu.l2cache.demand_mshr_misses::total         3869
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2161                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         1708                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         3869                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     74401000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     74401000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    141524500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    141524500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     43559000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     43559000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    141524500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    117960000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    259484500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    141524500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    117960000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    259484500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     87537500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     87537500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    176566000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    176566000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     51432500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     51432500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    176566000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    138970000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    315536000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    176566000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    138970000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    315536000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992721                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992721                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.463336                       # mshr miss rate for ReadCleanReq accesses
@@ -816,25 +826,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.597529
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.463336                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943125                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.597529                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80236.021998                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80236.021998                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81705.691809                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81705.691809                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83358.995138                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83358.995138                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81705.691809                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81364.168618                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81554.923753                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81705.691809                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81364.168618                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81554.923753                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests         9381                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         3042                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          336                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp          5375                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty           16                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean         2864                       # Transaction distribution
@@ -874,7 +884,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 132487590500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp               2777                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1091                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1091                       # Transaction distribution
@@ -895,9 +905,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                3868                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             4519500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             4518000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           20563000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           20568250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 86715fd27..3c414751d 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -172,7 +172,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -534,7 +534,7 @@ pipelined=true
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -813,6 +813,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -824,7 +825,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -832,29 +833,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -874,6 +882,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -905,9 +914,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index 6247d8422..8c06d056d 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -3,11 +3,13 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/s
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:31:02
-gem5 executing on e108600-lin, pid 12562
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:43:01
+gem5 executing on e108600-lin, pid 17342
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/arm/linux/o3-timing
 
+Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -24,4 +26,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 84937723500 because target called exit()
+122 123 124 Exiting @ tick 86053034000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 834ad990c..04ea23c2f 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,67 +1,67 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.085052                       # Number of seconds simulated
-sim_ticks                                 85051506000                       # Number of ticks simulated
-final_tick                                85051506000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.086053                       # Number of seconds simulated
+sim_ticks                                 86053034000                       # Number of ticks simulated
+final_tick                                86053034000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 137318                       # Simulator instruction rate (inst/s)
-host_op_rate                                   144756                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               67782320                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 272616                       # Number of bytes of host memory used
-host_seconds                                  1254.77                       # Real time elapsed on the host
+host_inst_rate                                 114393                       # Simulator instruction rate (inst/s)
+host_op_rate                                   120589                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               57131119                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 270696                       # Number of bytes of host memory used
+host_seconds                                  1506.24                       # Real time elapsed on the host
 sim_insts                                   172303022                       # Number of instructions simulated
 sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            651584                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            192256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher        71040                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               914880                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       651584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          651584                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst              10181                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               3004                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         1110                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 14295                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              7661052                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2260466                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher       835259                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                10756776                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         7661052                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            7661052                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             7661052                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2260466                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher       835259                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               10756776                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         14295                       # Number of read requests accepted
+system.physmem.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            652224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            193472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher        70848                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               916544                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       652224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          652224                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst              10191                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               3023                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         1107                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 14321                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              7579326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2248288                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher       823306                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                10650920                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         7579326                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            7579326                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             7579326                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2248288                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher       823306                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               10650920                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         14321                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                       14295                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       14321                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   914880                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   916544                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    914880                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    916544                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1374                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 495                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5094                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 807                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                2274                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1378                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 501                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5089                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 804                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                2285                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 424                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 384                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 621                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 628                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 270                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 230                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 231                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                354                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                348                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                319                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                321                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                267                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                239                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                795                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                240                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                797                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     85051447500                       # Total gap between requests
+system.physmem.totGap                     86052975500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   14295                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   14321                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -95,18 +95,18 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     12841                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1014                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       173                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        85                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        58                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     12787                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1077                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       178                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        86                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        60                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                        38                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        30                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
@@ -191,86 +191,96 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         8758                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      104.242978                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      83.732821                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     121.093987                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           6415     73.25%     73.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         1879     21.45%     94.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          191      2.18%     96.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           97      1.11%     97.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           35      0.40%     98.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           31      0.35%     98.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           21      0.24%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           17      0.19%     99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           72      0.82%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           8758                       # Bytes accessed per row activation
-system.physmem.totQLat                      205669486                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 473700736                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     71475000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       14387.51                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         8480                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      108.022642                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      86.441459                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     123.287712                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           5899     69.56%     69.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         2101     24.78%     94.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          209      2.46%     96.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           89      1.05%     97.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           41      0.48%     98.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           36      0.42%     98.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           15      0.18%     98.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           13      0.15%     99.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           77      0.91%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           8480                       # Bytes accessed per row activation
+system.physmem.totQLat                     1499260235                       # Total ticks spent queuing
+system.physmem.totMemAccLat                1767778985                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     71605000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                      104689.63                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  33137.51                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          10.76                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                 123439.63                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          10.65                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       10.76                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       10.65                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.08                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.08                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       5530                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       5837                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   38.68                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   40.76                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      5949734.00                       # Average gap between requests
-system.physmem.pageHitRate                      38.68                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   56571480                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   30867375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  89442600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      6008866.39                       # Average gap between requests
+system.physmem.pageHitRate                      40.76                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   51557940                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   27392310                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  82060020                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             5555000880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            17335593540                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            35823020250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              58890496125                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              692.426384                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    59484367239                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2839980000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     22725351261                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    9616320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    5247000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  21801000                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           5180800560.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             1120628550                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              275264640                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       12259963560                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        8345872320                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy         9276913815                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              36622770765                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              425.583720                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime            82871785017                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      531109000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2203210000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    34253599252                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  21734056085                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       445220983                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  26885838680                       # Time in different power states
+system.physmem_1.actEnergy                    9017820                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    4789290                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  20191920                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             5555000880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             4216606920                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            47330903250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              57139175370                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.834595                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    78723898183                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2839980000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      3485604317                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                85633597                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          68181299                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           5935035                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             39958046                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                38197568                       # Number of BTB hits
+system.physmem_1.refreshEnergy           882623040.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy              198112620                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               50847360                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy        1971627720                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        1393669440                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        18810725700                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              23341907430                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              271.250252                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime            85485463257                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      101360000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       375610000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    77532398500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN   3629358146                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        90573993                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN   4323733361                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                85625838                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          68176243                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           5935432                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             39943176                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                38184524                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.594184                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 3683467                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              81914                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups          681978                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits             654112                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses            27866                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted        40296                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             95.597115                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 3683485                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              81916                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups          681521                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             653387                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            28134                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        40344                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -300,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -330,7 +340,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -360,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -391,131 +401,131 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     85051506000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        170103013                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON     86053034000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        172106069                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            5682904                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      347166765                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    85633597                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           42535147                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     157608501                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                11884039                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 2048                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles            5685351                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      347171735                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    85625838                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           42521396                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     158200265                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                11884759                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 4008                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingQuiesceStallCycles           23                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles         3989                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  78333693                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 18018                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          169239484                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.146393                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.050401                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         4307                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  78326471                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 18089                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          169836333                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.138878                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.056220                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 17572638     10.38%     10.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 30072408     17.77%     28.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 31601234     18.67%     46.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 89993204     53.18%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 18169241     10.70%     10.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 30071574     17.71%     28.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 31598899     18.61%     47.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 89996619     52.99%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            169239484                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.503422                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.040921                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17519961                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              17356982                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 121861075                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               6734206                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                5767260                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             11064637                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                189821                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              304987544                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              27243895                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                5767260                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37487022                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8574296                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         598391                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 108353196                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               8459319                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              277412346                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13179472                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3059617                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 843440                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2298708                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  38369                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            27077                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           481431446                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1187749796                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        296450503                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           3005240                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            169836333                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.497518                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.017196                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17522714                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              17948295                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 121866676                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               6730979                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                5767669                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             11064280                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                189793                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              304996623                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              27241409                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                5767669                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37489750                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8834769                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         601523                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 108355832                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               8786790                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              277419061                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              13180458                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3061814                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 846087                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2626546                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  39334                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            27085                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           481448286                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1187772528                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        296460965                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           3003847                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                188454517                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              23636                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          23644                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13356506                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             33916395                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            14406588                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2541453                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1809916                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  263792468                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               45987                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 214404594                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5189732                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        82202501                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    216956580                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            771                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     169239484                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.266871                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.018138                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                188471357                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              23624                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          23625                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13352846                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             33915531                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            14406995                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2538352                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1801972                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  263797881                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               45980                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 214410891                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5187410                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        82207907                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    216953193                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            764                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     169836333                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.262456                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.019138                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            52525006     31.04%     31.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            35947009     21.24%     52.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            65510390     38.71%     90.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            13639375      8.06%     99.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1570056      0.93%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               47432      0.03%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 216      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            53122752     31.28%     31.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            35940807     21.16%     52.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            65514665     38.58%     91.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            13639448      8.03%     99.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1571104      0.93%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               47348      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 209      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       169239484                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       169836333                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                35663808     66.17%     66.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 153282      0.28%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd              1064      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                35657368     66.16%     66.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 153250      0.28%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd              1065      0.00%     66.45% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp             35736      0.07%     66.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt               239      0.00%     66.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              958      0.00%     66.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult            34308      0.06%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               14056089     26.08%     92.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3953676      7.34%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp             35732      0.07%     66.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt               239      0.00%     66.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              954      0.00%     66.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult            34277      0.06%     66.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               14055726     26.08%     92.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3956441      7.34%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             166984371     77.88%     77.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               919276      0.43%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             166991462     77.88%     77.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               919191      0.43%     78.31% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.31% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.31% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.31% # Type of FU issued
@@ -534,91 +544,91 @@ system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.31% # Ty
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.31% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.31% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd           33022      0.02%     78.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           33016      0.02%     78.33% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp          165180      0.08%     78.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt          245718      0.11%     78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         460481      0.21%     78.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult         206631      0.10%     78.87% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          165181      0.08%     78.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          245709      0.11%     78.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         460330      0.21%     78.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         206622      0.10%     78.87% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.90% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt            319      0.00%     78.90% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             31870339     14.86%     93.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            13371616      6.24%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             31869240     14.86%     93.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13372180      6.24%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              214404594                       # Type of FU issued
-system.cpu.iq.rate                           1.260440                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    53899365                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.251391                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          653186184                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         344036614                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    204245973                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             3951585                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            2011286                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1806392                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              266171590                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2132369                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1599233                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              214410891                       # Type of FU issued
+system.cpu.iq.rate                           1.245807                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    53895257                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.251364                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          653788467                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         344049655                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    204252570                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3952315                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2009022                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1806352                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              266172688                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2133460                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1598637                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6020251                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         7425                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         7087                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1761954                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6019387                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7380                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         7051                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1762361                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        25499                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           790                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        25560                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           770                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                5767260                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5621824                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 63176                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           263858489                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                5767669                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5624657                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                173600                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           263863986                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              33916395                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             14406588                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              23579                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3874                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 56135                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           7087                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3147809                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3246868                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              6394677                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             207120469                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              30635063                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7284125                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              33915531                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             14406995                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              23572                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3856                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                166551                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           7051                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3148917                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3246700                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              6395617                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             207126816                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              30634090                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           7284075                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         20034                       # number of nop insts executed
-system.cpu.iew.exec_refs                     43773548                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 44851099                       # Number of branches executed
-system.cpu.iew.exec_stores                   13138485                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.217618                       # Inst execution rate
-system.cpu.iew.wb_sent                      206362307                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     206052365                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 129396792                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 221653711                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.211339                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.583779                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        68665439                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                         20125                       # number of nop insts executed
+system.cpu.iew.exec_refs                     43772682                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 44853086                       # Number of branches executed
+system.cpu.iew.exec_stores                   13138592                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.203484                       # Inst execution rate
+system.cpu.iew.wb_sent                      206368979                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     206058922                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 129395738                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 221650226                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.197279                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.583783                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        68671574                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           5760276                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    157944348                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.150091                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.652266                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           5760722                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    158539716                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.145772                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.650496                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     73354007     46.44%     46.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     41142542     26.05%     72.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     22532573     14.27%     86.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9515365      6.02%     92.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3551587      2.25%     95.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2142504      1.36%     96.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1329210      0.84%     97.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1010049      0.64%     97.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3366511      2.13%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     73944910     46.64%     46.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     41143540     25.95%     72.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     22534900     14.21%     86.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9516225      6.00%     92.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3553894      2.24%     95.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2144247      1.35%     96.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1327660      0.84%     97.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1009164      0.64%     97.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3365176      2.12%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    157944348                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    158539716                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            172317410                       # Number of instructions committed
 system.cpu.commit.committedOps              181650342                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -664,83 +674,83 @@ system.cpu.commit.op_class_0::MemWrite       12644634      6.96%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         181650342                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3366511                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    404888417                       # The number of ROB reads
-system.cpu.rob.rob_writes                   511940612                       # The number of ROB writes
-system.cpu.timesIdled                            9843                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          863529                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               3365176                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    405491255                       # The number of ROB reads
+system.cpu.rob.rob_writes                   511954468                       # The number of ROB writes
+system.cpu.timesIdled                           10012                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         2269736                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   172303022                       # Number of Instructions Simulated
 system.cpu.committedOps                     181635954                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.987232                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.987232                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.012933                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.012933                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                218721236                       # number of integer regfile reads
-system.cpu.int_regfile_writes               114166498                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   2904044                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2441835                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 708181937                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                229500026                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                57441519                       # number of misc regfile reads
+system.cpu.cpi                               0.998857                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.998857                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.001144                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.001144                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                218726711                       # number of integer regfile reads
+system.cpu.int_regfile_writes               114168819                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2904003                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2441695                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 708199076                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                229511616                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                57440558                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements             72593                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.410345                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            41032184                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs             73105                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            561.277396                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         509673500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.410345                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998848                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998848                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements             72579                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.404028                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            41032024                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs             73091                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            561.382715                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         516933500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.404028                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998836                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998836                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          160                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          230                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           44                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          82362697                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         82362697                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     28645946                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28645946                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12341320                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12341320                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          82362375                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         82362375                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     28645802                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28645802                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12341304                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12341304                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          364                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           364                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        22147                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22147                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40987266                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40987266                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40987630                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40987630                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        89269                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89269                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        22967                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        22967                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      40987106                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40987106                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40987470                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40987470                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        89259                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89259                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        22983                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        22983                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data          116                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total          116                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data          260                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total          260                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       112236                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         112236                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       112352                       # number of overall misses
-system.cpu.dcache.overall_misses::total        112352                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1192862000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1192862000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    244207999                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    244207999                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2309000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      2309000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1437069999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1437069999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1437069999                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1437069999                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     28735215                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28735215                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       112242                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         112242                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       112358                       # number of overall misses
+system.cpu.dcache.overall_misses::total        112358                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1986737500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1986737500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    247540999                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    247540999                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2316500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      2316500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   2234278499                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   2234278499                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   2234278499                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   2234278499                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     28735061                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28735061                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          480                       # number of SoftPFReq accesses(hits+misses)
@@ -749,14 +759,14 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407
 system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41099502                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41099502                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     41099982                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     41099982                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003107                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.003107                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001858                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001858                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     41099348                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41099348                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     41099828                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     41099828                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003106                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.003106                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001859                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001859                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.241667                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.241667                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011604                       # miss rate for LoadLockedReq accesses
@@ -765,54 +775,54 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002731
 system.cpu.dcache.demand_miss_rate::total     0.002731                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002734                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002734                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13362.555870                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13362.555870                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10632.995123                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10632.995123                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8880.769231                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8880.769231                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12804.002272                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12804.002272                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12790.782532                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12790.782532                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          168                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        10626                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22258.119629                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22258.119629                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10770.613018                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10770.613018                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8909.615385                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8909.615385                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19905.904198                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19905.904198                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19885.353059                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19885.353059                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          180                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        11288                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             868                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           84                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    12.241935                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks        72593                       # number of writebacks
-system.cpu.dcache.writebacks::total             72593                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24834                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        24834                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14410                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        14410                       # number of WriteReq MSHR hits
+system.cpu.dcache.blocked::no_targets             865                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs           90                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    13.049711                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks        72579                       # number of writebacks
+system.cpu.dcache.writebacks::total             72579                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24837                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        24837                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14427                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        14427                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          260                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total          260                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        39244                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        39244                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        39244                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        39244                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64435                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        64435                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8557                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         8557                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data        39264                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        39264                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        39264                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        39264                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64422                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        64422                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8556                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         8556                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          113                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total          113                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data        72992                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total        72992                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data        73105                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total        73105                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    724757000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    724757000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85765499                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     85765499                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       963000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       963000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    810522499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    810522499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    811485499                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    811485499                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data        72978                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total        72978                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data        73091                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total        73091                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1062843500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1062843500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     87501999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     87501999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       969000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       969000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   1150345499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   1150345499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   1151314499                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   1151314499                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002242                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002242                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000692                       # mshr miss rate for WriteReq accesses
@@ -821,373 +831,374 @@ system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.235417
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.235417                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001776                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.001776                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001779                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.001779                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11247.877706                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11247.877706                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10022.846675                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10022.846675                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8522.123894                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8522.123894                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11104.264837                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11104.264837                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11100.273565                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11100.273565                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements             53637                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.592571                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            78276090                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             54149                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1445.568524                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       84288957500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.592571                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997251                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997251                       # Average percentage of cache occupancy
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001778                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.001778                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16498.145044                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16498.145044                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10226.975105                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10226.975105                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8575.221239                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8575.221239                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15762.907986                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15762.907986                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15751.795693                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15751.795693                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements             53612                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.587809                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            78268729                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             54124                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1446.100233                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       85282294500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.587809                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997242                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997242                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          278                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          277                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           49                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         156721475                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        156721475                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     78276090                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        78276090                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      78276090                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         78276090                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     78276090                       # number of overall hits
-system.cpu.icache.overall_hits::total        78276090                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        57573                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         57573                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        57573                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          57573                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        57573                       # number of overall misses
-system.cpu.icache.overall_misses::total         57573                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1245757924                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1245757924                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1245757924                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1245757924                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1245757924                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1245757924                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     78333663                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     78333663                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     78333663                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     78333663                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     78333663                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     78333663                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000735                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000735                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000735                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000735                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000735                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000735                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21637.884494                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21637.884494                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21637.884494                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21637.884494                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21637.884494                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21637.884494                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        76503                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           31                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              3201                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         156706996                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        156706996                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     78268729                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        78268729                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      78268729                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         78268729                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     78268729                       # number of overall hits
+system.cpu.icache.overall_hits::total        78268729                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        57707                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         57707                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        57707                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          57707                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        57707                       # number of overall misses
+system.cpu.icache.overall_misses::total         57707                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2245995927                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2245995927                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2245995927                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2245995927                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2245995927                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2245995927                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     78326436                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     78326436                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     78326436                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     78326436                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     78326436                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     78326436                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000737                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000737                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000737                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000737                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000737                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000737                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38920.684267                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 38920.684267                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 38920.684267                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 38920.684267                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 38920.684267                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 38920.684267                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        93822                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           55                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              3270                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    23.899719                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    15.500000                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks        53637                       # number of writebacks
-system.cpu.icache.writebacks::total             53637                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3423                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3423                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3423                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3423                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3423                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3423                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54150                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        54150                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        54150                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        54150                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        54150                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        54150                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1124811450                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1124811450                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1124811450                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1124811450                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1124811450                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1124811450                       # number of overall MSHR miss cycles
+system.cpu.icache.avg_blocked_cycles::no_mshrs    28.691743                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    27.500000                       # average number of cycles each access was blocked
+system.cpu.icache.writebacks::writebacks        53612                       # number of writebacks
+system.cpu.icache.writebacks::total             53612                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3582                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3582                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3582                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3582                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3582                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3582                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54125                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        54125                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        54125                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        54125                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        54125                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        54125                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2049967950                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2049967950                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2049967950                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2049967950                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2049967950                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2049967950                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000691                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000691                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000691                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20772.141274                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20772.141274                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20772.141274                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20772.141274                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20772.141274                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20772.141274                       # average overall mshr miss latency
-system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.prefetcher.num_hwpf_issued         9324                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified         9324                       # number of prefetch candidates identified
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37874.696536                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37874.696536                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37874.696536                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 37874.696536                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37874.696536                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 37874.696536                       # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.prefetcher.num_hwpf_issued         9207                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified         9207                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage         1388                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.prefetcher.pfSpanPage         1345                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         1802.479960                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              99008                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             2827                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            35.022285                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         1792.687270                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              99060                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             2834                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            34.954128                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  1726.446772                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    76.033188                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.105374                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.004641                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.110015                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          121                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks  1727.437863                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    65.249406                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.105434                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.003983                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.109417                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          128                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         2706                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           27                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           36                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4           56                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1           26                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           48                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4           54                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          139                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1125                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          199                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          283                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1127                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          200                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4          957                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.007385                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.007812                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.165161                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          4005348                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         4005348                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks        64707                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total        64707                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        51067                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        51067                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         8388                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         8388                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        43964                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        43964                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        61705                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        61705                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        43964                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        70093                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          114057                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        43964                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        70093                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         114057                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data          236                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          236                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        10186                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        10186                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data         2776                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total         2776                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        10186                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         3012                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         13198                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        10186                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         3012                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        13198                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     18599500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     18599500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    782334000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    782334000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    220076500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total    220076500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    782334000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    238676000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1021010000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    782334000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    238676000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1021010000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks        64707                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total        64707                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        51067                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        51067                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         8624                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         8624                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        54150                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        54150                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        64481                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        64481                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        54150                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data        73105                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       127255                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        54150                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data        73105                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       127255                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027365                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.027365                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.188107                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.188107                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043051                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043051                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.188107                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.041201                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.103713                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.188107                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.041201                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.103713                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78811.440678                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78811.440678                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76804.830159                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76804.830159                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79278.278098                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79278.278098                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76804.830159                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79241.699867                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77360.963782                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76804.830159                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79241.699867                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77360.963782                       # average overall miss latency
+system.cpu.l2cache.tags.tag_accesses          4003735                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         4003735                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks        64697                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total        64697                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        51019                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        51019                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         8384                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         8384                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        43929                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        43929                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        61675                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        61675                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        43929                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        70059                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          113988                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        43929                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        70059                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         113988                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data          239                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          239                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        10196                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        10196                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data         2793                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total         2793                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        10196                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         3032                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         13228                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        10196                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         3032                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        13228                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     20303000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     20303000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1707637000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1707637000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    558453500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total    558453500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1707637000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    578756500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   2286393500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1707637000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    578756500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   2286393500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks        64697                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total        64697                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        51019                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        51019                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         8623                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         8623                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        54125                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        54125                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        64468                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        64468                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        54125                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data        73091                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       127216                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        54125                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data        73091                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       127216                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027717                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.027717                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.188379                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.188379                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043324                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043324                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.188379                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.041483                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.103981                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.188379                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.041483                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.103981                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84949.790795                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84949.790795                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167481.071008                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167481.071008                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 199947.547440                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 199947.547440                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167481.071008                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 190882.750660                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 172844.987904                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167481.071008                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 190882.750660                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 172844.987904                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            1                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total            1                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            8                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total            8                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            8                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           13                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            9                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            8                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           13                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         2014                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total         2014                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          236                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          236                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10181                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10181                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         2768                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total         2768                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        10181                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         3004                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        13185                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        10181                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         3004                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         2014                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        15199                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     66910636                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     66910636                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     17183500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     17183500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    720935500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    720935500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    202978500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    202978500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    720935500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    220162000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    941097500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    720935500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    220162000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     66910636                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1008008136                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_hits::cpu.data            9                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         2057                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total         2057                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          238                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          238                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10191                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10191                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         2785                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total         2785                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        10191                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3023                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        13214                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        10191                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         3023                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         2057                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15271                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     97518621                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     97518621                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     18660000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     18660000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1645631000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1645631000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    541204500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    541204500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1645631000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    559864500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   2205495500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1645631000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    559864500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     97518621                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   2303014121                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027365                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027365                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.188015                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.188015                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.042927                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.042927                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.188015                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.041092                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.103611                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.188015                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.041092                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027601                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027601                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.188286                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.188286                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043200                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043200                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.188286                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.041359                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.103871                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.188286                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.041359                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.119437                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33222.758689                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72811.440678                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72811.440678                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70811.855417                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70811.855417                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73330.382948                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73330.382948                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70811.855417                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73289.613848                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71376.374668                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70811.855417                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73289.613848                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66320.687940                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests       253485                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       126250                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10456                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          904                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          903                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.120040                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47408.177443                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78403.361345                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78403.361345                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161478.853891                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161478.853891                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 194328.366248                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 194328.366248                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161478.853891                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185201.620906                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166905.970940                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161478.853891                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185201.620906                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 150809.647109                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests       253407                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       126211                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10475                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          950                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          949                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp        118630                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty        64707                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        61523                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq         2352                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         8624                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         8624                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        54150                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        64481                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       161936                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       218803                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            380739                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6898304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      9324672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           16222976                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                        2352                       # Total snoops (count)
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp        118592                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty        64697                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        61494                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq         2394                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         8623                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         8623                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        54125                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        64468                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       161861                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       218761                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            380622                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6895104                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      9322880                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           16217984                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                        2394                       # Total snoops (count)
 system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples       129607                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.087812                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.283049                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples       129610                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.088311                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.283775                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             118227     91.22%     91.22% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              11379      8.78%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             118165     91.17%     91.17% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              11444      8.83%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         129607                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      252972500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         129610                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      252894500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      81228989                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      81192487                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     109661492                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     109641490                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests         14295                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests        10463                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests         14321                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests        10482                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  85051506000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp              14059                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               236                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              236                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         14059                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        28590                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  28590                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       914880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  914880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp              14082                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               238                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              238                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         14083                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        28641                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  28641                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       916480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  916480                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples             14295                       # Request fanout histogram
+system.membus.snoop_fanout::samples             14321                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   14295    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   14321    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               14295                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            18052130                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               14321                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            18093154                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           77159307                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           77218560                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index 4ca9409ac..8d26638e4 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -179,7 +179,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -552,7 +552,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -756,6 +756,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -767,7 +768,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -775,29 +776,36 @@ width=16
 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -817,6 +825,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -848,9 +857,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index 6416a69a9..99d577e0b 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:17
-gem5 executing on e108600-lin, pid 18548
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:09:02
+gem5 executing on e108600-lin, pid 17639
 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/x86/linux/o3-timing
 
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
@@ -20,7 +20,6 @@ Authors: Carl Sechen, Bill Swartz
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
-  1   2   3   4   5   6   7   8   9  10  11 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
@@ -9804,7 +9803,8 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
- 12  13  14  15 
+info: Increasing stack size by one page.
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
@@ -9812,4 +9812,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 103324153500 because target called exit()
+122 123 124 Exiting @ tick 103189362000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index c2d15923a..f0c12dca0 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,63 +1,63 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.103278                       # Number of seconds simulated
-sim_ticks                                103278421500                       # Number of ticks simulated
-final_tick                               103278421500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.103189                       # Number of seconds simulated
+sim_ticks                                103189362000                       # Number of ticks simulated
+final_tick                               103189362000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  68420                       # Simulator instruction rate (inst/s)
-host_op_rate                                   114678                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               53503682                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309068                       # Number of bytes of host memory used
-host_seconds                                  1930.31                       # Real time elapsed on the host
+host_inst_rate                                  73255                       # Simulator instruction rate (inst/s)
+host_op_rate                                   122783                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               57235650                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 306480                       # Number of bytes of host memory used
+host_seconds                                  1802.89                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            232192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            130496                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               362688                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       232192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          232192                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3628                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2039                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5667                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2248214                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1263536                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3511750                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2248214                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2248214                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2248214                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1263536                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3511750                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5668                       # Number of read requests accepted
+system.physmem.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            232704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            130112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               362816                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       232704                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          232704                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3636                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2033                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5669                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2255116                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1260905                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3516021                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2255116                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2255116                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2255116                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1260905                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3516021                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5669                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5668                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5669                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   362752                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   362816                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    362752                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    362816                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 314                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 385                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 471                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 359                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 360                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 334                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 420                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 393                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 389                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 309                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 384                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 476                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 363                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 357                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 335                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 419                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 395                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 387                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 296                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                257                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                272                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                232                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                487                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                416                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                283                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                260                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                268                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                228                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                486                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                420                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                286                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    103278386000                       # Total gap between requests
+system.physmem.totGap                    103189107000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5668                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5669                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -91,11 +91,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4530                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       947                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       166                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        19                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4455                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       978                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       200                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -187,321 +187,331 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1276                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      283.335423                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     163.570090                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     315.354372                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            562     44.04%     44.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          260     20.38%     64.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          126      9.87%     74.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           65      5.09%     79.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           38      2.98%     82.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           52      4.08%     86.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           32      2.51%     88.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           25      1.96%     90.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          116      9.09%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1276                       # Bytes accessed per row activation
-system.physmem.totQLat                       44968750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 151243750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     28340000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7933.79                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1243                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      291.012068                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     164.006967                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     325.689818                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            565     45.45%     45.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          237     19.07%     64.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           95      7.64%     72.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           65      5.23%     77.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           45      3.62%     81.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           57      4.59%     85.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           29      2.33%     87.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           21      1.69%     89.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          129     10.38%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1243                       # Bytes accessed per row activation
+system.physmem.totQLat                      180648250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 286942000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     28345000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       31865.98                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26683.79                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.51                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  50615.98                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.52                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.51                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.52                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.13                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4387                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4421                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.40                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   77.99                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     18221310.16                       # Average gap between requests
-system.physmem.pageHitRate                      77.40                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5677560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3097875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  23649600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     18202347.33                       # Average gap between requests
+system.physmem.pageHitRate                      77.99                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    5333580                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2823480                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  21691320                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             6745539840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3123252585                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            59226559500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              69127776960                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.342795                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    98524507750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      3448640000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1303957250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3969000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2165625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  20412600                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           286422240.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy               93806610                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy               15765120                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy         717579270                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy         394813440                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        24141432120                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              25679671980                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              248.859682                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           102941166250                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE       30119500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       121808000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   100340787250                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN   1028168000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        94814000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN   1573665250                       # Time in different power states
+system.physmem_1.actEnergy                    3577140                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1893705                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  18785340                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             6745539840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3000772125                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            59333991750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              69106850940                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.140248                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    98704275500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      3448640000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1124404000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                40909998                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          40909998                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6747980                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             35338690                       # Number of BTB lookups
+system.physmem_1.refreshEnergy           224343600.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               72770760                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               12467520                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy         571365720                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy         300199680                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        24277951200                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              25483354665                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              246.957187                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           102997073250                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE       23820000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF        95422000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   100962546500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN    781772000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        72828000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN   1252973500                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                40834752                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          40834752                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6720926                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             35301077                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 3198330                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             606499                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups        35338690                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            9879284                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses         25459406                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted      5040736                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.usedRAS                 3198104                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             606453                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        35301077                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            9875363                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses         25425714                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted      5011557                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    103278421500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        206556844                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    103189362000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        206378725                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           46378865                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      420308215                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    40909998                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           13077614                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     152415438                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                14966481                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        135                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 5953                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         72789                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles          564                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          110                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  41283191                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1528436                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                       4                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          206357094                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.419964                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.660932                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           46270336                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      419359791                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    40834752                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           13073467                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     152339601                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                14895691                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                         89                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 5905                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         73704                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles          808                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          184                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  41191275                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1518616                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       6                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          206138472                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.415591                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.660484                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 99044157     48.00%     48.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  5139433      2.49%     50.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  5380650      2.61%     53.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5336666      2.59%     55.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  6016483      2.92%     58.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5851353      2.84%     61.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5736237      2.78%     64.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4733991      2.29%     66.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 69118124     33.49%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 99063302     48.06%     48.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  5137465      2.49%     50.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  5366260      2.60%     53.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5330020      2.59%     55.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  6010905      2.92%     58.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5824389      2.83%     61.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5722044      2.78%     64.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4745811      2.30%     66.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 68938276     33.44%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            206357094                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.198057                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.034831                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 32325248                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              86371056                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  62511253                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              17666297                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                7483240                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              591444337                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                7483240                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 42110583                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                46566289                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          29410                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  68967744                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              41199828                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              552624215                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1533                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               36277086                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                4842177                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 151976                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           630066400                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1487530571                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        975657611                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          15077279                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            206138472                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.197863                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.031991                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32237214                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              86447407                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  62317142                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              17688864                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                7447845                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              590237823                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                7447845                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 42013779                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                46504501                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          31211                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  68811152                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              41329984                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              551593859                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1410                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               36393589                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                4822156                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 169929                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           628796373                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1484193525                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        973498992                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          15084169                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259429450                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                370636950                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               2363                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           2376                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  89140950                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            128894590                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            45939948                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          77227738                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         25186602                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  490698604                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               59973                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 338566221                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1098463                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       269395193                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    527209931                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          58728                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     206357094                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.640681                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.805896                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                369366923                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2443                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2459                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  89351866                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            128676829                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            45848779                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          77202780                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         25186397                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  489944627                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               61663                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 338268196                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1105632                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       268642906                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    525336348                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          60418                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     206138472                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.640976                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.805234                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            73312584     35.53%     35.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            46573584     22.57%     58.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            32816576     15.90%     74.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            20907210     10.13%     84.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            15065478      7.30%     91.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             8412685      4.08%     95.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             5234413      2.54%     98.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             2370472      1.15%     99.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1664092      0.81%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            73134407     35.48%     35.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            46607709     22.61%     58.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            32815647     15.92%     74.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            20883524     10.13%     84.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            15044203      7.30%     91.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             8407546      4.08%     95.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5216740      2.53%     98.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             2365929      1.15%     99.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1662767      0.81%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       206357094                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       206138472                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  762770     19.47%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2718793     69.40%     88.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                436106     11.13%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  759085     19.35%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2731626     69.64%     88.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                432034     11.01%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1211777      0.36%      0.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             216613901     63.98%     64.34% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               799985      0.24%     64.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               7047582      2.08%     66.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1810682      0.53%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             84424015     24.94%     92.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            26658279      7.87%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1211760      0.36%      0.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             216459489     63.99%     64.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               800418      0.24%     64.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               7047773      2.08%     66.67% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1809637      0.53%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             84315938     24.93%     92.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            26623181      7.87%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              338566221                       # Type of FU issued
-system.cpu.iq.rate                           1.639095                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3917669                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.011571                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          880328489                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         745561228                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    316131833                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             8177179                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           15427221                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      3556889                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              337169115                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 4102998                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18179072                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              338268196                       # Type of FU issued
+system.cpu.iq.rate                           1.639065                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3922745                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.011597                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          879521716                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         744046350                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    315909602                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             8181525                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           15431147                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      3556535                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              336873543                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 4105638                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18155877                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     72245003                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        55572                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       872144                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     25424231                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     72027242                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        55091                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       864575                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     25333062                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        50651                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            53                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        50542                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            27                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                7483240                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                35798970                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                583606                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           490758577                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           1261619                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             128894590                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             45939948                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              21909                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 539997                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 37637                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         872144                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1294345                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      6884684                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8179029                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             326602378                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              80777118                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          11963843                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                7447845                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                35704467                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                582987                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           490006290                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1248239                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             128676829                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             45848779                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              22549                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 539423                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 38394                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         864575                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1296720                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      6850218                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8146938                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             326347367                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              80684613                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          11920829                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    106442155                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 18940356                       # Number of branches executed
-system.cpu.iew.exec_stores                   25665037                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.581174                       # Inst execution rate
-system.cpu.iew.wb_sent                      322715986                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     319688722                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 256576217                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 435723594                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.547703                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.588851                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       269420821                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                    106316260                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 18920718                       # Number of branches executed
+system.cpu.iew.exec_stores                   25631647                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.581303                       # Inst execution rate
+system.cpu.iew.wb_sent                      322480012                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     319466137                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 256417161                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 435540007                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.547961                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.588734                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       268667644                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           6753005                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    163742250                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.351901                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.936120                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6725958                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    163655626                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.352617                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.935975                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     67180478     41.03%     41.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     54846489     33.50%     74.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     13227508      8.08%     82.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     10675855      6.52%     89.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      5434961      3.32%     92.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      3126709      1.91%     94.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1096647      0.67%     95.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1147781      0.70%     95.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      7005822      4.28%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     67077696     40.99%     40.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     54856110     33.52%     74.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13235317      8.09%     82.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     10672053      6.52%     89.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      5439540      3.32%     92.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      3134329      1.92%     94.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1088236      0.66%     95.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1157500      0.71%     95.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6994845      4.27%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    163742250                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    163655626                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
 system.cpu.commit.committedOps              221363384                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -547,469 +557,469 @@ system.cpu.commit.op_class_0::MemWrite       20515717      9.27%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         221363384                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               7005822                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    647520633                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1024585644                       # The number of ROB writes
-system.cpu.timesIdled                            2803                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          199750                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               6994845                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    646691809                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1022946396                       # The number of ROB writes
+system.cpu.timesIdled                            2819                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          240253                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
 system.cpu.committedOps                     221363384                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.563981                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.563981                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.639394                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.639394                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                524858514                       # number of integer regfile reads
-system.cpu.int_regfile_writes               289109549                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   4527972                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  3322072                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 107078976                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 65816113                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               177007720                       # number of misc regfile reads
+system.cpu.cpi                               1.562632                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.562632                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.639946                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.639946                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                524499390                       # number of integer regfile reads
+system.cpu.int_regfile_writes               288922915                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   4524370                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  3323309                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 107020933                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 65779043                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               176790948                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   1689                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements                77                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1524.395872                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            82831685                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              2117                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          39126.917808                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements                81                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1508.634180                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            82760913                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2105                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          39316.348219                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1524.395872                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.372167                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.372167                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         2040                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          411                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1479                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.498047                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         165670739                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        165670739                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     62317357                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        62317357                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20513773                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20513773                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      82831130                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         82831130                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     82831130                       # number of overall hits
-system.cpu.dcache.overall_hits::total        82831130                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1223                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1223                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1958                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1958                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         3181                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           3181                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         3181                       # number of overall misses
-system.cpu.dcache.overall_misses::total          3181                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     77985000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     77985000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    124974000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    124974000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    202959000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    202959000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    202959000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    202959000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     62318580                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     62318580                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data  1508.634180                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.368319                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.368319                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2024                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           98                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          423                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1459                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.494141                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         165529197                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        165529197                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     62246604                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        62246604                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20513664                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20513664                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      82760268                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         82760268                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     82760268                       # number of overall hits
+system.cpu.dcache.overall_hits::total        82760268                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1211                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1211                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         2067                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         2067                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         3278                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           3278                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         3278                       # number of overall misses
+system.cpu.dcache.overall_misses::total          3278                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    109883500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    109883500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    137432000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    137432000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    247315500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    247315500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    247315500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    247315500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     62247815                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     62247815                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     82834311                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     82834311                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     82834311                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     82834311                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000020                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000020                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000095                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000095                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000038                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000038                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000038                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000038                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63765.331153                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63765.331153                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63827.374872                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 63827.374872                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63803.520905                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63803.520905                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63803.520905                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63803.520905                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          403                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           40                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 9                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     82763546                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     82763546                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     82763546                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     82763546                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000019                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000019                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000101                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000101                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000040                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000040                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000040                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000040                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 90737.819983                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 90737.819983                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66488.630866                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 66488.630866                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 75447.071385                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 75447.071385                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 75447.071385                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 75447.071385                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          307                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          143                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    44.777778                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets           20                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    76.750000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    71.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          622                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          622                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data            8                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total            8                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          630                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          630                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          630                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          630                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          601                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          601                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1950                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1950                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2551                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2551                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2551                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2551                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     47286500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     47286500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    122663000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    122663000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    169949500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    169949500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    169949500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    169949500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000095                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000095                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000031                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000031                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000031                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000031                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78679.700499                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78679.700499                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62904.102564                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62904.102564                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66620.736966                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66620.736966                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66620.736966                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66620.736966                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements              6489                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1681.757073                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            41270224                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              8478                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           4867.919792                       # Average number of references to valid blocks.
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          626                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          626                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data            6                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total            6                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          632                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          632                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          632                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          632                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          585                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          585                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2061                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2061                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2646                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2646                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2646                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2646                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     67088500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     67088500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    134984000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    134984000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    202072500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    202072500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    202072500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    202072500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000100                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000100                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 114681.196581                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 114681.196581                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65494.420184                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65494.420184                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76369.047619                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76369.047619                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76369.047619                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76369.047619                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements              6530                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1674.310192                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            41178058                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              8518                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           4834.240197                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1681.757073                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.821170                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.821170                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1989                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          162                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          832                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          147                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          747                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.971191                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          82575282                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         82575282                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     41270227                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        41270227                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      41270227                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         41270227                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     41270227                       # number of overall hits
-system.cpu.icache.overall_hits::total        41270227                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        12961                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         12961                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        12961                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          12961                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        12961                       # number of overall misses
-system.cpu.icache.overall_misses::total         12961                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    483569000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    483569000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    483569000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    483569000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    483569000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    483569000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     41283188                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     41283188                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     41283188                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     41283188                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     41283188                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     41283188                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000314                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000314                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000314                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000314                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000314                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000314                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37309.544017                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 37309.544017                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 37309.544017                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 37309.544017                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 37309.544017                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 37309.544017                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1349                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                25                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    53.960000                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks         6489                       # number of writebacks
-system.cpu.icache.writebacks::total              6489                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4054                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         4054                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         4054                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         4054                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         4054                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         4054                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         8907                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         8907                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         8907                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         8907                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         8907                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         8907                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    345609000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    345609000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    345609000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    345609000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    345609000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    345609000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000216                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000216                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000216                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000216                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000216                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000216                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38801.953520                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38801.953520                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38801.953520                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 38801.953520                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38801.953520                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 38801.953520                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.occ_blocks::cpu.inst  1674.310192                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.817534                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.817534                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1988                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          163                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          841                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          142                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          742                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.970703                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          82391597                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         82391597                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     41178058                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        41178058                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      41178058                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         41178058                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     41178058                       # number of overall hits
+system.cpu.icache.overall_hits::total        41178058                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        13213                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         13213                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        13213                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          13213                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        13213                       # number of overall misses
+system.cpu.icache.overall_misses::total         13213                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    660957500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    660957500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    660957500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    660957500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    660957500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    660957500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     41191271                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     41191271                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     41191271                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     41191271                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     41191271                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     41191271                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000321                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000321                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000321                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000321                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000321                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000321                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50023.272535                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 50023.272535                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 50023.272535                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 50023.272535                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 50023.272535                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 50023.272535                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1885                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          842                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                30                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    62.833333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          842                       # average number of cycles each access was blocked
+system.cpu.icache.writebacks::writebacks         6530                       # number of writebacks
+system.cpu.icache.writebacks::total              6530                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4157                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         4157                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         4157                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         4157                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         4157                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         4157                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         9056                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         9056                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         9056                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         9056                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         9056                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         9056                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    451350000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    451350000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    451350000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    451350000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    451350000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    451350000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000220                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000220                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000220                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000220                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000220                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000220                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49839.885159                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49839.885159                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49839.885159                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 49839.885159                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49839.885159                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 49839.885159                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3906.658043                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              11874                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5667                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.095289                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         3894.223765                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              12041                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5669                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.124008                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2417.494362                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1489.163681                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073776                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.045446                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.119222                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5667                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2411.748228                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1482.475537                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073601                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.045242                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.118842                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5669                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1008                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          510                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3942                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172943                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           146003                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          146003                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          525                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3930                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.173004                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           147349                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          147349                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks           16                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total           16                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         6443                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         6443                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          433                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          433                       # number of UpgradeReq hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         6476                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         6476                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          541                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          541                       # number of UpgradeReq hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            7                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            7                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         4846                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         4846                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data           71                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total           71                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         4846                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           78                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            4924                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         4846                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           78                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           4924                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1512                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1512                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3628                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3628                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          528                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          528                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3628                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         2040                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5668                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3628                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         2040                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5668                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    114827000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    114827000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    280498500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    280498500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     45425000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     45425000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    280498500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    160252000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    440750500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    280498500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    160252000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    440750500                       # number of overall miss cycles
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         4877                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         4877                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data           65                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total           65                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         4877                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           72                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            4949                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         4877                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           72                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           4949                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1515                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1515                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3636                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3636                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          518                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          518                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3636                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         2033                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5669                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3636                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         2033                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5669                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    125752500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    125752500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    385523500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    385523500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     65306000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     65306000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    385523500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    191058500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    576582000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    385523500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    191058500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    576582000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks           16                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total           16                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         6443                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         6443                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          433                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          433                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1519                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1519                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8474                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         8474                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          599                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          599                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         8474                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         2118                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        10592                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         8474                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         2118                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        10592                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.995392                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.995392                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.428133                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.428133                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.881469                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.881469                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.428133                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.963173                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.535121                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.428133                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.963173                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.535121                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75943.783069                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75943.783069                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77314.911797                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77314.911797                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86032.196970                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86032.196970                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77314.911797                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78554.901961                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77761.203246                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77314.911797                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78554.901961                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77761.203246                       # average overall miss latency
+system.cpu.l2cache.WritebackClean_accesses::writebacks         6476                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         6476                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          541                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          541                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1522                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1522                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8513                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         8513                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          583                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          583                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         8513                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         2105                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        10618                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         8513                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         2105                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        10618                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.995401                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.995401                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.427111                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.427111                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.888508                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.888508                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.427111                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.965796                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.533905                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.427111                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.965796                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.533905                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83004.950495                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83004.950495                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106029.565457                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106029.565457                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 126073.359073                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 126073.359073                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106029.565457                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93978.603050                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 101707.884989                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106029.565457                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93978.603050                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 101707.884989                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1512                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1512                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3628                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3628                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          528                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          528                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3628                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         2040                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5668                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3628                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         2040                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5668                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     99707000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     99707000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    244218500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    244218500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     40155000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     40155000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    244218500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    139862000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    384080500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    244218500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    139862000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    384080500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.995392                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.995392                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.428133                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.428133                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.881469                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.881469                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.428133                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963173                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.535121                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.428133                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963173                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.535121                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65943.783069                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65943.783069                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67314.911797                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67314.911797                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76051.136364                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76051.136364                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67314.911797                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68559.803922                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67762.967537                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67314.911797                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68559.803922                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67762.967537                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests        18024                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         7043                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests          478                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1515                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1515                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3636                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3636                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          518                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          518                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3636                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2033                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5669                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3636                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2033                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5669                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    110602500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    110602500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    349163500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    349163500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     60126000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     60126000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    349163500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    170728500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    519892000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    349163500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    170728500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    519892000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.995401                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.995401                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.427111                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.427111                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.888508                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.888508                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.427111                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.965796                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.533905                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.427111                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.965796                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.533905                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73004.950495                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73004.950495                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96029.565457                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96029.565457                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 116073.359073                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 116073.359073                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96029.565457                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83978.603050                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91707.884989                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96029.565457                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83978.603050                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91707.884989                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests        18313                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         7194                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests          597                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp          9504                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp          9638                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         6489                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict           61                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          433                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          433                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1519                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1519                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         8907                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          599                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23869                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5178                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             29047                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       957568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       136512                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            1094080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                         433                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic                 27712                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples        11458                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.082912                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.275760                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackClean         6530                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict           65                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          541                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          541                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1522                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1522                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         9056                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          583                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        24098                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5373                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             29471                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       962688                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       135744                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            1098432                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         543                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic                 34752                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples        11702                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.100496                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.300673                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              10508     91.71%     91.71% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                950      8.29%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              10526     89.95%     89.95% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1176     10.05%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          11458                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       15517998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          11702                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       15702500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      13359000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      13582500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3392501                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3428499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests          5668                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.tot_requests          5669                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 103278421500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp               4155                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1512                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1512                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          4156                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11335                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11335                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  11335                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       362688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total       362688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  362688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED 103189362000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp               4154                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1515                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1515                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          4154                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11338                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11338                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  11338                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       362816                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total       362816                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  362816                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples              5668                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5669                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5668    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5669    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5668                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             7074000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5669                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             7048500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           30060000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           30047500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 3ede85d66..7dde96a20 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -25,7 +25,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:134217727
+mem_ranges=0:134217727:0:0:0:0
 memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
@@ -60,7 +60,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=8796093022208:18446744073709551615
+ranges=8796093022208:18446744073709551615:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -115,7 +115,7 @@ icache_port=system.cpu0.icache.cpu_side
 [system.cpu0.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -166,7 +166,7 @@ size=64
 [system.cpu0.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -268,7 +268,7 @@ icache_port=system.cpu1.icache.cpu_side
 [system.cpu1.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -319,7 +319,7 @@ size=64
 [system.cpu1.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -467,7 +467,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=0:134217727
+addr_ranges=0:134217727:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -513,7 +513,7 @@ size=1024
 [system.l2c]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -611,27 +611,27 @@ system=system
 
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -651,6 +651,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -660,7 +661,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -682,9 +683,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 5e8bf0780..d5fb9a1a9 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -3,14 +3,14 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:25
-gem5 executing on e108600-lin, pid 39587
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:44
+gem5 executing on e108600-lin, pid 28056
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 722572000
-Exiting @ tick 1963612574000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 752919000
+Exiting @ tick 1966741627000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index a66428f0b..de3485335 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,119 +1,119 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.962627                       # Number of seconds simulated
-sim_ticks                                1962626573500                       # Number of ticks simulated
-final_tick                               1962626573500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.966742                       # Number of seconds simulated
+sim_ticks                                1966741627000                       # Number of ticks simulated
+final_tick                               1966741627000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 944250                       # Simulator instruction rate (inst/s)
-host_op_rate                                   944250                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            30421290331                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 338248                       # Number of bytes of host memory used
-host_seconds                                    64.52                       # Real time elapsed on the host
-sim_insts                                    60918166                       # Number of instructions simulated
-sim_ops                                      60918166                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 801704                       # Simulator instruction rate (inst/s)
+host_op_rate                                   801704                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            25865455419                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 334360                       # Number of bytes of host memory used
+host_seconds                                    76.04                       # Real time elapsed on the host
+sim_insts                                    60959478                       # Number of instructions simulated
+sim_ops                                      60959478                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.inst           831680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24730496                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            27968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           420288                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.inst           796480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24829632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            62464                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           430848                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26011392                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       831680                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        27968                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          859648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7700672                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7700672                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             12995                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            386414                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               437                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              6567                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             26120384                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       796480                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        62464                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          858944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7775296                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7775296                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             12445                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            387963                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               976                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              6732                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                406428                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          120323                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               120323                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              423759                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12600714                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               14250                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              214146                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               489                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13253358                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         423759                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          14250                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             438009                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3923656                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3923656                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3923656                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             423759                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12600714                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              14250                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             214146                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              489                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17177014                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        406428                       # Number of read requests accepted
-system.physmem.writeReqs                       120323                       # Number of write requests accepted
-system.physmem.readBursts                      406428                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     120323                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26003904                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7488                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7699456                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26011392                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7700672                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      117                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                408131                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          121489                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               121489                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              404974                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12624755                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               31760                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              219067                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               488                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13281045                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         404974                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          31760                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             436735                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3953390                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3953390                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3953390                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             404974                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12624755                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              31760                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             219067                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              488                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17234435                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        408131                       # Number of read requests accepted
+system.physmem.writeReqs                       121489                       # Number of write requests accepted
+system.physmem.readBursts                      408131                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     121489                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26113216                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7168                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7773568                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26120384                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7775296                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      112                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25480                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25719                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25425                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24952                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               24963                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25448                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25036                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25388                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25382                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25021                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25321                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25245                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              25883                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25960                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25500                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25588                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8093                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7861                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7317                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6760                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6801                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7296                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7054                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7130                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7229                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7212                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7633                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7389                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8081                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8482                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7977                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7989                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               25299                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25599                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25910                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25657                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25586                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25177                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               26012                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25110                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25002                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25326                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25348                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25350                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              25736                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25396                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25673                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25838                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7888                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7973                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7891                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7697                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7528                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7375                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8079                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7030                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7056                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7058                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7243                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7671                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7657                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7555                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7813                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7948                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1962619726500                       # Total gap between requests
+system.physmem.numWrRetry                          71                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1966734334500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  406428                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  408131                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 120323                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    406236                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        62                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 121489                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    407926                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        80                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
@@ -159,195 +159,195 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1824                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5838                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5952                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6657                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6742                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7801                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8946                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7909                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8569                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7650                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6978                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7037                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       48                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65759                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      512.528475                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     309.841182                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     413.690018                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15231     23.16%     23.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        12147     18.47%     41.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5552      8.44%     50.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3316      5.04%     55.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2308      3.51%     58.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1955      2.97%     61.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1491      2.27%     63.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1296      1.97%     65.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22463     34.16%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65759                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5364                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        75.747390                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2879.661653                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5361     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1643                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2752                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5759                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5841                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6396                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6541                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7366                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8415                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6986                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7365                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8033                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7676                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6912                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7040                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5993                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5793                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      415                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      410                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      317                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      250                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      276                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      315                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      340                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      315                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      292                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      356                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      163                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        65984                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      513.560621                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     309.956643                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     413.656575                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15493     23.48%     23.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        12381     18.76%     42.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4640      7.03%     49.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3311      5.02%     54.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3269      4.95%     59.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1542      2.34%     61.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1639      2.48%     64.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1098      1.66%     65.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22611     34.27%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65984                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5405                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        75.487327                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2871.274927                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5402     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5364                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5364                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.428039                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.999012                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       22.364771                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4746     88.48%     88.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              15      0.28%     88.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              16      0.30%     89.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              23      0.43%     89.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             212      3.95%     93.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              26      0.48%     93.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              13      0.24%     94.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               6      0.11%     94.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               2      0.04%     94.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               8      0.15%     94.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               3      0.06%     94.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               8      0.15%     94.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              13      0.24%     94.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.02%     94.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               2      0.04%     94.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               2      0.04%     95.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              18      0.34%     95.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               4      0.07%     95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91              23      0.43%     95.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.06%     95.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             170      3.17%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             3      0.06%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             4      0.07%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.04%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             8      0.15%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             3      0.06%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.02%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             4      0.07%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             2      0.04%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             2      0.04%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207             1      0.02%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.02%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227            12      0.22%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::244-247             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5364                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2137214000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9755545250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2031555000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5260.04                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5405                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5405                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.472155                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.786030                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       24.242091                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4888     90.43%     90.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              28      0.52%     90.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             175      3.24%     94.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47               6      0.11%     94.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55               5      0.09%     94.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              18      0.33%     94.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71               9      0.17%     94.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               2      0.04%     94.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              25      0.46%     95.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               5      0.09%     95.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            152      2.81%     98.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            23      0.43%     98.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             6      0.11%     98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             3      0.06%     98.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             4      0.07%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             5      0.09%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             2      0.04%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             1      0.02%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             1      0.02%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             6      0.11%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             7      0.13%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             9      0.17%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             7      0.13%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             4      0.07%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             1      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             6      0.11%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             3      0.06%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             2      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-343             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5405                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6252046750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               13902403000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2040095000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15322.93                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24010.04                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.25                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.92                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.25                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.92                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  34072.93                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.28                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.95                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.28                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.95                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.34                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     364061                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     96795                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.60                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.45                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3725896.54                       # Average gap between requests
-system.physmem.pageHitRate                      87.51                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  244346760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  133324125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1578805800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                377861760                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           128189159280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            66163184910                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1119537594750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1316224277385                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.644542                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1862206979750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     65536380000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     34882447750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  252791280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  137931750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1590420000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                401708160                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           128189159280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            66247264755                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1119463832250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1316283107475                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.674522                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1862086480750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     65536380000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     35002933000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
+system.physmem.avgWrQLen                        22.83                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     365911                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97586                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.68                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.32                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3713482.00                       # Average gap between requests
+system.physmem.pageHitRate                      87.53                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  236241180                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  125565165                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1459059000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                320826420                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           5643624480.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5139412980                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              370844640                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       13440056220                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        6440902560                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       458973488295                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             492152011950                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              250.237247                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           1954499558250                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      615960500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2400520000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   1908253811750                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  16773151500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      9224451750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  29473731500                       # Time in different power states
+system.physmem_1.actEnergy                  234884580                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  124844115                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1454196660                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                313205220                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           5773313520.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5158429890                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              364374240                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       13818451860                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        6703686720                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       458612092095                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             492560034510                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              250.444709                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           1954406570250                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      598675750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2455572000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   1906713566750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  17457468500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      9212976500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  30303367500                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     7493005                       # DTB read hits
-system.cpu0.dtb.read_misses                      7443                       # DTB read misses
+system.cpu0.dtb.read_hits                     7479115                       # DTB read hits
+system.cpu0.dtb.read_misses                      7764                       # DTB read misses
 system.cpu0.dtb.read_acv                          210                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  490673                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5064687                       # DTB write hits
-system.cpu0.dtb.write_misses                      813                       # DTB write misses
-system.cpu0.dtb.write_acv                         134                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 187452                       # DTB write accesses
-system.cpu0.dtb.data_hits                    12557692                       # DTB hits
-system.cpu0.dtb.data_misses                      8256                       # DTB misses
-system.cpu0.dtb.data_acv                          344                       # DTB access violations
-system.cpu0.dtb.data_accesses                  678125                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3501057                       # ITB hits
-system.cpu0.itb.fetch_misses                     3871                       # ITB misses
+system.cpu0.dtb.read_accesses                  524068                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5079820                       # DTB write hits
+system.cpu0.dtb.write_misses                      909                       # DTB write misses
+system.cpu0.dtb.write_acv                         133                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 202594                       # DTB write accesses
+system.cpu0.dtb.data_hits                    12558935                       # DTB hits
+system.cpu0.dtb.data_misses                      8673                       # DTB misses
+system.cpu0.dtb.data_acv                          343                       # DTB access violations
+system.cpu0.dtb.data_accesses                  726662                       # DTB accesses
+system.cpu0.itb.fetch_hits                    3638634                       # ITB hits
+system.cpu0.itb.fetch_misses                     3984                       # ITB misses
 system.cpu0.itb.fetch_acv                         184                       # ITB acv
-system.cpu0.itb.fetch_accesses                3504928                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3642618                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -360,427 +360,430 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numPwrStateTransitions              13585                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         6793                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    272297667.010158                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   432721655.998866                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         6793    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value       104000                       # Distribution of time spent in the clock gated state
+system.cpu0.numPwrStateTransitions              13588                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         6794                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    272289101.854578                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   432882462.064242                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10         6794    100.00%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value       249000                       # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           6793                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   112908521500                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849718052000                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                      3923838819                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::total           6794                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   116809469000                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849932158000                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                      3933483254                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6793                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    164897                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   56819     40.19%     40.19% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.09%     40.28% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1973      1.40%     41.68% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    423      0.30%     41.98% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  82035     58.02%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              141381                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    56285     49.08%     49.08% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.11%     49.20% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1973      1.72%     50.92% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     423      0.37%     51.29% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   55862     48.71%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               114674                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1900334186500     96.86%     96.86% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               93688500      0.00%     96.87% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              789357000      0.04%     96.91% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              314729500      0.02%     96.92% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            60387418000      3.08%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1961919379500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.990602                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6794                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    163850                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   56218     40.17%     40.17% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.09%     40.26% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1975      1.41%     41.67% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    433      0.31%     41.98% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  81195     58.02%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              139952                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    55706     49.07%     49.07% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     131      0.12%     49.19% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1975      1.74%     50.93% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     433      0.38%     51.31% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   55273     48.69%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               113518                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1903167810000     96.77%     96.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               93266000      0.00%     96.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              790441500      0.04%     96.81% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30              321171500      0.02%     96.83% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            62368212000      3.17%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1966740901000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.990893                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.680953                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.811099                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
-system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
-system.cpu0.kern.syscall::6                        32     14.41%     28.38% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.45%     28.83% # number of syscalls executed
-system.cpu0.kern.syscall::17                        9      4.05%     32.88% # number of syscalls executed
-system.cpu0.kern.syscall::19                       10      4.50%     37.39% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.70%     40.09% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.45%     40.54% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.35%     41.89% # number of syscalls executed
-system.cpu0.kern.syscall::33                        7      3.15%     45.05% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.90%     45.95% # number of syscalls executed
-system.cpu0.kern.syscall::45                       36     16.22%     62.16% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.35%     63.51% # number of syscalls executed
-system.cpu0.kern.syscall::48                       10      4.50%     68.02% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.50%     72.52% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.45%     72.97% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      2.70%     75.68% # number of syscalls executed
-system.cpu0.kern.syscall::71                       23     10.36%     86.04% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.35%     87.39% # number of syscalls executed
-system.cpu0.kern.syscall::74                        6      2.70%     90.09% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.45%     90.54% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      1.35%     91.89% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      4.05%     95.95% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.90%     96.85% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.90%     97.75% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.45%     98.20% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.90%     99.10% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.680744                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.811121                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         8      3.42%      3.42% # number of syscalls executed
+system.cpu0.kern.syscall::3                        20      8.55%     11.97% # number of syscalls executed
+system.cpu0.kern.syscall::4                         4      1.71%     13.68% # number of syscalls executed
+system.cpu0.kern.syscall::6                        33     14.10%     27.78% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.43%     28.21% # number of syscalls executed
+system.cpu0.kern.syscall::17                       10      4.27%     32.48% # number of syscalls executed
+system.cpu0.kern.syscall::19                       10      4.27%     36.75% # number of syscalls executed
+system.cpu0.kern.syscall::20                        6      2.56%     39.32% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.43%     39.74% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.28%     41.03% # number of syscalls executed
+system.cpu0.kern.syscall::33                        8      3.42%     44.44% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.85%     45.30% # number of syscalls executed
+system.cpu0.kern.syscall::45                       39     16.67%     61.97% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.28%     63.25% # number of syscalls executed
+system.cpu0.kern.syscall::48                       10      4.27%     67.52% # number of syscalls executed
+system.cpu0.kern.syscall::54                       10      4.27%     71.79% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.43%     72.22% # number of syscalls executed
+system.cpu0.kern.syscall::59                        6      2.56%     74.79% # number of syscalls executed
+system.cpu0.kern.syscall::71                       27     11.54%     86.32% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.28%     87.61% # number of syscalls executed
+system.cpu0.kern.syscall::74                        7      2.99%     90.60% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.43%     91.03% # number of syscalls executed
+system.cpu0.kern.syscall::90                        3      1.28%     92.31% # number of syscalls executed
+system.cpu0.kern.syscall::92                        9      3.85%     96.15% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.85%     97.01% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.85%     97.86% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.43%     98.29% # number of syscalls executed
+system.cpu0.kern.syscall::144                       2      0.85%     99.15% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.85%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   234                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  504      0.34%      0.34% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.34% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.34% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.34% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3063      2.05%      2.39% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      51      0.03%      2.42% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.42% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               134520     89.85%     92.28% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6699      4.47%     96.75% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.75% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     96.75% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.01%     96.76% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.76% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4333      2.89%     99.65% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 381      0.25%     99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb                     136      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                149713                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6886                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1283                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                  525      0.35%      0.36% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.36% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.36% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.36% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3064      2.07%      2.43% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      51      0.03%      2.46% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.46% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               133000     89.79%     92.25% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6513      4.40%     96.65% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.65% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     4      0.00%     96.65% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.01%     96.66% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.66% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4412      2.98%     99.64% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 394      0.27%     99.91% # number of callpals executed
+system.cpu0.kern.callpal::imb                     139      0.09%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                148125                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             6988                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1369                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1283                      
-system.cpu0.kern.mode_good::user                 1283                      
+system.cpu0.kern.mode_good::kernel               1368                      
+system.cpu0.kern.mode_good::user                 1369                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.186320                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.195764                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.314114                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1958165685500     99.82%     99.82% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3548030000      0.18%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.327510                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1962821824500     99.80%     99.80% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3919074500      0.20%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3064                       # number of times the context was actually changed
-system.cpu0.committedInsts                   47738229                       # Number of instructions committed
-system.cpu0.committedOps                     47738229                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             44272305                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                210363                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1201649                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      5610320                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    44272305                       # number of integer instructions
-system.cpu0.num_fp_insts                       210363                       # number of float instructions
-system.cpu0.num_int_register_reads           60851829                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          32993694                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              102169                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             104020                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     12597866                       # number of memory refs
-system.cpu0.num_load_insts                    7520141                       # Number of load instructions
-system.cpu0.num_store_insts                   5077725                       # Number of store instructions
-system.cpu0.num_idle_cycles              3698103141.291685                       # Number of idle cycles
-system.cpu0.num_busy_cycles              225735677.708315                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.057529                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.942471                       # Percentage of idle cycles
-system.cpu0.Branches                          7202811                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              2726604      5.71%      5.71% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 31424940     65.82%     71.53% # Class of executed instruction
-system.cpu0.op_class::IntMult                   52727      0.11%     71.64% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     71.64% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  25705      0.05%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1656      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7695505     16.12%     87.81% # Class of executed instruction
-system.cpu0.op_class::MemWrite                5083820     10.65%     98.46% # Class of executed instruction
-system.cpu0.op_class::IprAccess                735872      1.54%    100.00% # Class of executed instruction
+system.cpu0.kern.swap_context                    3065                       # number of times the context was actually changed
+system.cpu0.committedInsts                   47690735                       # Number of instructions committed
+system.cpu0.committedOps                     47690735                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             44243506                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                210072                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1190980                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      5607273                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    44243506                       # number of integer instructions
+system.cpu0.num_fp_insts                       210072                       # number of float instructions
+system.cpu0.num_int_register_reads           60857324                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          32955789                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              102653                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             104432                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     12599733                       # number of memory refs
+system.cpu0.num_load_insts                    7506744                       # Number of load instructions
+system.cpu0.num_store_insts                   5092989                       # Number of store instructions
+system.cpu0.num_idle_cycles              3699864315.998118                       # Number of idle cycles
+system.cpu0.num_busy_cycles              233618938.001881                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.059392                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.940608                       # Percentage of idle cycles
+system.cpu0.Branches                          7182999                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              2715471      5.69%      5.69% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 31387897     65.80%     71.50% # Class of executed instruction
+system.cpu0.op_class::IntMult                   52053      0.11%     71.61% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     71.61% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  26676      0.06%     71.66% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1883      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.66% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7680863     16.10%     87.77% # Class of executed instruction
+system.cpu0.op_class::MemWrite                5099104     10.69%     98.46% # Class of executed instruction
+system.cpu0.op_class::IprAccess                735804      1.54%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  47746829                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          1179926                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          505.222517                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           11367443                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1180345                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.630611                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        114940500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.222517                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986763                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.986763                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          419                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          394                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3           25                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.818359                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         51462845                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        51462845                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6409921                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6409921                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4656712                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4656712                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       143926                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       143926                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       147979                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       147979                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11066633                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11066633                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11066633                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11066633                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       937871                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       937871                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       251485                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       251485                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13660                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        13660                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5430                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         5430                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1189356                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1189356                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1189356                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1189356                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  29160615500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  29160615500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10889573000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  10889573000                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    150754500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    150754500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     30482000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     30482000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  40050188500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  40050188500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  40050188500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  40050188500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7347792                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7347792                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4908197                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4908197                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157586                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       157586                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       153409                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       153409                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12255989                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12255989                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12255989                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12255989                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127640                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.127640                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051238                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.051238                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.086683                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.086683                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.035396                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.035396                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.097043                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.097043                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097043                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.097043                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.352253                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.352253                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43301.083564                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 43301.083564                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11036.200586                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11036.200586                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5613.627993                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5613.627993                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33673.844080                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33673.844080                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33673.844080                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33673.844080                       # average overall miss latency
+system.cpu0.op_class::total                  47699751                       # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements          1183172                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          505.236482                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           11369674                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1183684                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.605329                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        121324500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.236482                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986790                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.986790                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         51472726                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        51472726                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6400739                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6400739                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4669408                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       4669408                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       138994                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       138994                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       146309                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       146309                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11070147                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        11070147                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11070147                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       11070147                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       938380                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       938380                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       255338                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       255338                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13584                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        13584                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5728                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         5728                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1193718                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1193718                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1193718                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1193718                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  31213946000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  31213946000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  12660198000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  12660198000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    149666500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    149666500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     31954500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     31954500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  43874144000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  43874144000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  43874144000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  43874144000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7339119                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7339119                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4924746                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4924746                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       152578                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       152578                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       152037                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       152037                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12263865                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12263865                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12263865                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12263865                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127860                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.127860                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051848                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.051848                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.089030                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.089030                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.037675                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.037675                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.097336                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.097336                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097336                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.097336                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.652252                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.652252                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49582.114687                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 49582.114687                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11017.851885                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11017.851885                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5578.648743                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5578.648743                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36754.194877                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 36754.194877                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36754.194877                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 36754.194877                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       679177                       # number of writebacks
-system.cpu0.dcache.writebacks::total           679177                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       937871                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       937871                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       251485                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       251485                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13660                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13660                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5430                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         5430                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1189356                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1189356                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1189356                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1189356                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7110                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7110                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10837                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10837                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17947                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17947                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  28222744500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  28222744500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10638088000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10638088000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    137094500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    137094500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     25052000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     25052000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  38860832500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  38860832500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  38860832500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  38860832500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1578478000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1578478000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1578478000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1578478000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127640                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127640                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051238                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051238                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086683                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086683                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.035396                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.035396                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.097043                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.097043                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.097043                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.097043                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.352253                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.352253                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42301.083564                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42301.083564                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10036.200586                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10036.200586                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4613.627993                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4613.627993                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32673.844080                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32673.844080                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32673.844080                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32673.844080                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222008.157525                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222008.157525                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87952.192567                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87952.192567                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements           698827                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          508.151884                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           47047389                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           699339                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            67.274082                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      42438027500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.151884                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992484                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.992484                       # Average percentage of cache occupancy
+system.cpu0.dcache.writebacks::writebacks       681271                       # number of writebacks
+system.cpu0.dcache.writebacks::total           681271                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       938380                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       938380                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       255338                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       255338                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13584                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13584                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5728                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         5728                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1193718                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1193718                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1193718                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1193718                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7073                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7073                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10752                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10752                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17825                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17825                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  30275566000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  30275566000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  12404860000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12404860000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    136082500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    136082500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     26226500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     26226500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  42680426000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  42680426000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  42680426000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  42680426000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1572135500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1572135500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1572135500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1572135500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127860                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127860                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051848                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051848                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.089030                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.089030                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.037675                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.037675                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.097336                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.097336                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.097336                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.097336                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.652252                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.652252                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48582.114687                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48582.114687                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10017.851885                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10017.851885                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4578.648743                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4578.648743                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35754.194877                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35754.194877                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35754.194877                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35754.194877                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.797964                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.797964                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.345021                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.345021                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements           692001                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          507.922544                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           47007113                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           692513                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            67.879033                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      44813245500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   507.922544                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992036                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.992036                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          349                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3          163                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          435                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         48446269                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        48446269                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     47047389                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       47047389                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     47047389                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        47047389                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     47047389                       # number of overall hits
-system.cpu0.icache.overall_hits::total       47047389                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       699440                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       699440                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       699440                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        699440                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       699440                       # number of overall misses
-system.cpu0.icache.overall_misses::total       699440                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10201863500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  10201863500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  10201863500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  10201863500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  10201863500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  10201863500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     47746829                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     47746829                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     47746829                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     47746829                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     47746829                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     47746829                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014649                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014649                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014649                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014649                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014649                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014649                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14585.759322                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14585.759322                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14585.759322                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14585.759322                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14585.759322                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14585.759322                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         48392391                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        48392391                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst     47007113                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       47007113                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     47007113                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        47007113                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     47007113                       # number of overall hits
+system.cpu0.icache.overall_hits::total       47007113                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       692639                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       692639                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       692639                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        692639                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       692639                       # number of overall misses
+system.cpu0.icache.overall_misses::total       692639                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10340404000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  10340404000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  10340404000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  10340404000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  10340404000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  10340404000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     47699752                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     47699752                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     47699752                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     47699752                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     47699752                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     47699752                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014521                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014521                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014521                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014521                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014521                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014521                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.994758                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.994758                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.994758                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14928.994758                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.994758                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14928.994758                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks       698827                       # number of writebacks
-system.cpu0.icache.writebacks::total           698827                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       699440                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       699440                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       699440                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       699440                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       699440                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       699440                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9502423500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   9502423500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9502423500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   9502423500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9502423500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   9502423500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014649                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014649                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014649                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014649                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014649                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014649                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13585.759322                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13585.759322                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13585.759322                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13585.759322                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13585.759322                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13585.759322                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks       692001                       # number of writebacks
+system.cpu0.icache.writebacks::total           692001                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       692639                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       692639                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       692639                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       692639                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       692639                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       692639                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9647765000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   9647765000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9647765000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   9647765000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9647765000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   9647765000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014521                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014521                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014521                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014521                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014521                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014521                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.994758                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.994758                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.994758                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.994758                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.994758                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.994758                       # average overall mshr miss latency
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2422670                       # DTB read hits
-system.cpu1.dtb.read_misses                      2992                       # DTB read misses
+system.cpu1.dtb.read_hits                     2442522                       # DTB read hits
+system.cpu1.dtb.read_misses                      2621                       # DTB read misses
 system.cpu1.dtb.read_acv                            0                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  239363                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1760134                       # DTB write hits
-system.cpu1.dtb.write_misses                      341                       # DTB write misses
-system.cpu1.dtb.write_acv                          29                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 105247                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4182804                       # DTB hits
-system.cpu1.dtb.data_misses                      3333                       # DTB misses
-system.cpu1.dtb.data_acv                           29                       # DTB access violations
-system.cpu1.dtb.data_accesses                  344610                       # DTB accesses
-system.cpu1.itb.fetch_hits                    1965215                       # ITB hits
-system.cpu1.itb.fetch_misses                     1216                       # ITB misses
+system.cpu1.dtb.read_accesses                  205338                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1749235                       # DTB write hits
+system.cpu1.dtb.write_misses                      236                       # DTB write misses
+system.cpu1.dtb.write_acv                          24                       # DTB write access violations
+system.cpu1.dtb.write_accesses                  89740                       # DTB write accesses
+system.cpu1.dtb.data_hits                     4191757                       # DTB hits
+system.cpu1.dtb.data_misses                      2857                       # DTB misses
+system.cpu1.dtb.data_acv                           24                       # DTB access violations
+system.cpu1.dtb.data_accesses                  295078                       # DTB accesses
+system.cpu1.itb.fetch_hits                    1826928                       # ITB hits
+system.cpu1.itb.fetch_misses                     1064                       # ITB misses
 system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                1966431                       # ITB accesses
+system.cpu1.itb.fetch_accesses                1827992                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -793,389 +796,387 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numPwrStateTransitions               5486                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         2743                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    706502118.118848                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   410575500.110236                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         2743    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value        98500                       # Distribution of time spent in the clock gated state
+system.cpu1.numPwrStateTransitions               5609                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         2805                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    692202308.556150                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   417084374.205506                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10         2805    100.00%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value        82000                       # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::max_value    974673500                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           2743                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON    24691263500                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 1937935310000                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                      3925253147                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::total           2805                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON    25114151500                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941627475500                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                      3931646339                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2743                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     78622                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   26563     38.35%     38.35% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1967      2.84%     41.19% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    504      0.73%     41.91% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  40238     58.09%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               69272                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    25720     48.16%     48.16% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1967      3.68%     51.84% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     504      0.94%     52.79% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   25216     47.21%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                53407                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1909399868000     97.29%     97.29% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              730527500      0.04%     97.33% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              354535500      0.02%     97.34% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            52140917500      2.66%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1962625848500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.968264                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2805                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     79700                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   27196     38.42%     38.42% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1969      2.78%     41.20% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    525      0.74%     41.94% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  41097     58.06%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               70787                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    26331     48.20%     48.20% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1969      3.60%     51.80% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     525      0.96%     52.76% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   25806     47.24%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                54631                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1909855366000     97.15%     97.15% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              731068500      0.04%     97.19% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              371926000      0.02%     97.21% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            54864779000      2.79%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1965823139500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.968194                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.626671                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.770975                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
-system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
-system.cpu1.kern.syscall::17                        6      5.77%     26.92% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      2.88%     29.81% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      2.88%     32.69% # number of syscalls executed
-system.cpu1.kern.syscall::33                        4      3.85%     36.54% # number of syscalls executed
-system.cpu1.kern.syscall::45                       18     17.31%     53.85% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      2.88%     56.73% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      0.96%     57.69% # number of syscalls executed
-system.cpu1.kern.syscall::71                       31     29.81%     87.50% # number of syscalls executed
-system.cpu1.kern.syscall::74                       10      9.62%     97.12% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.627929                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.771766                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3                        10     10.87%     10.87% # number of syscalls executed
+system.cpu1.kern.syscall::6                         9      9.78%     20.65% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      1.09%     21.74% # number of syscalls executed
+system.cpu1.kern.syscall::17                        5      5.43%     27.17% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      3.26%     30.43% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      3.26%     33.70% # number of syscalls executed
+system.cpu1.kern.syscall::33                        3      3.26%     36.96% # number of syscalls executed
+system.cpu1.kern.syscall::45                       15     16.30%     53.26% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      3.26%     56.52% # number of syscalls executed
+system.cpu1.kern.syscall::59                        1      1.09%     57.61% # number of syscalls executed
+system.cpu1.kern.syscall::71                       27     29.35%     86.96% # number of syscalls executed
+system.cpu1.kern.syscall::74                        9      9.78%     96.74% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      3.26%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                    92                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  423      0.59%      0.59% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  433      0.59%      0.59% # number of callpals executed
 system.cpu1.kern.callpal::wrmces                    1      0.00%      0.59% # number of callpals executed
 system.cpu1.kern.callpal::wrfen                     1      0.00%      0.60% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 2001      2.80%      3.39% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.00%      3.40% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      3.41% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                63023     88.06%     91.46% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2145      3.00%     94.46% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.46% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     94.47% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.47% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3777      5.28%     99.75% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 136      0.19%     99.94% # number of callpals executed
-system.cpu1.kern.callpal::imb                      44      0.06%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 2016      2.75%      3.35% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.00%      3.35% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      3.36% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                64567     88.14%     91.50% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2334      3.19%     94.68% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.68% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     3      0.00%     94.69% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.00%     94.69% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3725      5.08%     99.78% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 121      0.17%     99.94% # number of callpals executed
+system.cpu1.kern.callpal::imb                      42      0.06%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 71571                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             2066                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                464                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2880                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                892                      
-system.cpu1.kern.mode_good::user                  464                      
-system.cpu1.kern.mode_good::idle                  428                      
-system.cpu1.kern.mode_switch_good::kernel     0.431752                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 73259                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1964                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                367                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2923                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                816                      
+system.cpu1.kern.mode_good::user                  367                      
+system.cpu1.kern.mode_good::idle                  449                      
+system.cpu1.kern.mode_switch_good::kernel     0.415479                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.148611                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.329760                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       17773252500      0.91%      0.91% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1704242000      0.09%      0.99% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1943148352000     99.01%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    2002                       # number of times the context was actually changed
-system.cpu1.committedInsts                   13179937                       # Number of instructions committed
-system.cpu1.committedOps                     13179937                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             12156604                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                173446                       # Number of float alu accesses
-system.cpu1.num_func_calls                     411985                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1307841                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    12156604                       # number of integer instructions
-system.cpu1.num_fp_insts                       173446                       # number of float instructions
-system.cpu1.num_int_register_reads           16739384                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           8921370                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               90735                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              92616                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      4206400                       # number of memory refs
-system.cpu1.num_load_insts                    2436997                       # Number of load instructions
-system.cpu1.num_store_insts                   1769403                       # Number of store instructions
-system.cpu1.num_idle_cycles              3875870619.998025                       # Number of idle cycles
-system.cpu1.num_busy_cycles              49382527.001975                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.012581                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.987419                       # Percentage of idle cycles
-system.cpu1.Branches                          1874664                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               705658      5.35%      5.35% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  7796168     59.14%     64.49% # Class of executed instruction
-system.cpu1.op_class::IntMult                   21633      0.16%     64.65% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     64.65% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                  14181      0.11%     64.76% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     64.76% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                   1986      0.02%     64.78% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.78% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2508903     19.03%     83.81% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1770394     13.43%     97.24% # Class of executed instruction
-system.cpu1.op_class::IprAccess                364376      2.76%    100.00% # Class of executed instruction
+system.cpu1.kern.mode_switch_good::idle      0.153609                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.310620                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel       18376717500      0.94%      0.94% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1492465500      0.08%      1.01% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1945081083000     98.99%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    2017                       # number of times the context was actually changed
+system.cpu1.committedInsts                   13268743                       # Number of instructions committed
+system.cpu1.committedOps                     13268743                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             12224543                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                175144                       # Number of float alu accesses
+system.cpu1.num_func_calls                     423393                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1315452                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    12224543                       # number of integer instructions
+system.cpu1.num_fp_insts                       175144                       # number of float instructions
+system.cpu1.num_int_register_reads           16795911                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           8988763                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               90944                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              92918                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      4214824                       # number of memory refs
+system.cpu1.num_load_insts                    2456352                       # Number of load instructions
+system.cpu1.num_store_insts                   1758472                       # Number of store instructions
+system.cpu1.num_idle_cycles              3881441492.340690                       # Number of idle cycles
+system.cpu1.num_busy_cycles              50204846.659310                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.012769                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.987231                       # Percentage of idle cycles
+system.cpu1.Branches                          1899015                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               719201      5.42%      5.42% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  7861154     59.23%     64.65% # Class of executed instruction
+system.cpu1.op_class::IntMult                   22602      0.17%     64.82% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     64.82% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                  13252      0.10%     64.92% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     64.92% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     64.92% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     64.92% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                   1759      0.01%     64.94% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.94% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2529811     19.06%     84.00% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1759476     13.26%     97.25% # Class of executed instruction
+system.cpu1.op_class::IprAccess                364369      2.75%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  13183299                       # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements           166569                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          484.920851                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            4014072                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           167081                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            24.024707                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      79208580000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   484.920851                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.947111                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.947111                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          325                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           66                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         16965673                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        16965673                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2258295                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2258295                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1642687                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1642687                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        48217                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        48217                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        50804                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        50804                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      3900982                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         3900982                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      3900982                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        3900982                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       118473                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       118473                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        62672                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        62672                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8931                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         8931                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5870                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         5870                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       181145                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        181145                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       181145                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       181145                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1450679500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1450679500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1216299000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   1216299000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     81854000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     81854000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     32847500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     32847500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   2666978500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   2666978500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   2666978500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   2666978500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2376768                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2376768                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1705359                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1705359                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        57148                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        57148                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        56674                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        56674                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      4082127                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      4082127                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      4082127                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      4082127                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049846                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.049846                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.036750                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.036750                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.156278                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.156278                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103575                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103575                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.044375                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.044375                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044375                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.044375                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12244.811054                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12244.811054                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19407.374904                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 19407.374904                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9165.155078                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9165.155078                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5595.826235                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5595.826235                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14722.893262                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14722.893262                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14722.893262                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14722.893262                       # average overall miss latency
+system.cpu1.op_class::total                  13271624                       # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements           162095                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          484.320037                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            4015175                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           162424                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            24.720331                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      72635663500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   484.320037                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.945938                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.945938                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          329                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3          297                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.642578                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         16996897                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        16996897                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data      2273870                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2273870                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1634166                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1634166                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        51918                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        51918                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        52084                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        52084                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      3908036                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         3908036                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      3908036                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        3908036                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       118670                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       118670                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        58749                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        58749                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         9148                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         9148                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         6116                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         6116                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       177419                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        177419                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       177419                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       177419                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1466187000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   1466187000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1296760000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   1296760000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     84020000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     84020000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     34172000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     34172000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   2762947000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   2762947000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   2762947000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   2762947000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2392540                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2392540                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1692915                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1692915                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        61066                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        61066                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        58200                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        58200                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      4085455                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      4085455                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      4085455                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      4085455                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049600                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.049600                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.034703                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.034703                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.149805                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.149805                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.105086                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105086                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.043427                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.043427                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.043427                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.043427                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12355.161372                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12355.161372                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22072.886347                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22072.886347                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9184.521207                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9184.521207                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5587.311969                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5587.311969                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15573.005146                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15573.005146                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15573.005146                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15573.005146                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks       114559                       # number of writebacks
-system.cpu1.dcache.writebacks::total           114559                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       118473                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       118473                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        62672                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        62672                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         8931                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         8931                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5870                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         5870                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       181145                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       181145                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       181145                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       181145                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data           89                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total           89                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3221                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3221                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3310                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3310                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1332206500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1332206500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1153627000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1153627000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     72923000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     72923000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     26977500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     26977500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2485833500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   2485833500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2485833500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   2485833500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     20174000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     20174000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data     20174000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total     20174000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049846                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049846                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036750                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036750                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.156278                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.156278                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103575                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103575                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.044375                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.044375                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.044375                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.044375                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11244.811054                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11244.811054                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18407.374904                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18407.374904                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8165.155078                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8165.155078                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  4595.826235                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  4595.826235                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13722.893262                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13722.893262                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13722.893262                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13722.893262                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data  6094.864048                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total  6094.864048                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements           316020                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          445.922081                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           12866727                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           316532                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            40.649056                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1960698705500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   445.922081                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.870942                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.870942                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          444                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         13499873                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        13499873                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst     12866727                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       12866727                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     12866727                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        12866727                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     12866727                       # number of overall hits
-system.cpu1.icache.overall_hits::total       12866727                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       316573                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       316573                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       316573                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        316573                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       316573                       # number of overall misses
-system.cpu1.icache.overall_misses::total       316573                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4250508000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4250508000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4250508000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4250508000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4250508000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4250508000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     13183300                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     13183300                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     13183300                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     13183300                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     13183300                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     13183300                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024013                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024013                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024013                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024013                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024013                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024013                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13426.628297                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13426.628297                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13426.628297                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13426.628297                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13426.628297                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13426.628297                       # average overall miss latency
+system.cpu1.dcache.writebacks::writebacks       111600                       # number of writebacks
+system.cpu1.dcache.writebacks::total           111600                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       118670                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       118670                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        58749                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        58749                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9148                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9148                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         6116                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         6116                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       177419                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       177419                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       177419                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       177419                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          125                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total          125                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3371                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3371                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3496                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3496                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1347517000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1347517000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1238011000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1238011000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     74872000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     74872000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     28056000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     28056000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2585528000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   2585528000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2585528000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   2585528000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     26291000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     26291000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data     26291000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total     26291000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049600                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049600                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034703                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.034703                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.149805                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.149805                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.105086                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105086                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043427                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.043427                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043427                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.043427                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11355.161372                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11355.161372                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21072.886347                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21072.886347                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8184.521207                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8184.521207                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  4587.311969                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  4587.311969                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14573.005146                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14573.005146                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14573.005146                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14573.005146                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data       210328                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total       210328                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data  7520.308924                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total  7520.308924                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements           326538                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          445.783445                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           12944535                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           327049                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            39.579803                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1960887554500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   445.783445                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.870671                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.870671                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           75                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3          434                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4            2                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses         13598713                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        13598713                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst     12944535                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       12944535                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     12944535                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        12944535                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     12944535                       # number of overall hits
+system.cpu1.icache.overall_hits::total       12944535                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       327089                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       327089                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       327089                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        327089                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       327089                       # number of overall misses
+system.cpu1.icache.overall_misses::total       327089                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4450039000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4450039000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4450039000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4450039000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4450039000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4450039000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     13271624                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     13271624                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     13271624                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     13271624                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     13271624                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     13271624                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024646                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.024646                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024646                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.024646                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024646                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.024646                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13604.979073                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13604.979073                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13604.979073                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13604.979073                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13604.979073                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13604.979073                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks       316020                       # number of writebacks
-system.cpu1.icache.writebacks::total           316020                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       316573                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       316573                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       316573                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       316573                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       316573                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       316573                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3933935000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3933935000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3933935000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3933935000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3933935000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3933935000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024013                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024013                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024013                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.024013                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024013                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.024013                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12426.628297                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12426.628297                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12426.628297                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 12426.628297                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12426.628297                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 12426.628297                       # average overall mshr miss latency
+system.cpu1.icache.writebacks::writebacks       326538                       # number of writebacks
+system.cpu1.icache.writebacks::total           326538                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       327089                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       327089                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       327089                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       327089                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       327089                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       327089                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4122950000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4122950000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4122950000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4122950000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4122950000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4122950000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024646                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024646                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024646                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.024646                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024646                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.024646                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12604.979073                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12604.979073                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12604.979073                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 12604.979073                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12604.979073                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 12604.979073                       # average overall mshr miss latency
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1188,13 +1189,13 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                 7375                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7375                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               55610                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              55610                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1014                       # Packet count per connected master and slave (bytes)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                 7376                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7376                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               55675                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              55675                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14036                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1010                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
@@ -1202,12 +1203,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        1814
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2474                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        42514                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83456                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83456                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  125970                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        55616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2749                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        42642                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83460                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83460                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  126102                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        56144                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2733                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
@@ -1215,74 +1216,74 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9876                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        81882                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661632                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661632                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2743514                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             14952500                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total        82394                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661648                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total      2661648                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2744042                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             15108500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               763000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               758000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              175000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              174000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            15838000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            15840500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             2459000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6057500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             6051000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               82500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           216134056                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           216235265                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            28456000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            28519000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            41952000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            41956000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                41696                       # number of replacements
-system.iocache.tags.tagsinuse                0.568010                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements                41698                       # number of replacements
+system.iocache.tags.tagsinuse                0.568421                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41712                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                41714                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1756490226000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.568010                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.035501                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.035501                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1760410342000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.568421                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.035526                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.035526                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375552                       # Number of tag accesses
-system.iocache.tags.data_accesses              375552                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               375570                       # Number of tag accesses
+system.iocache.tags.data_accesses              375570                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.iocache.ReadReq_misses::tsunami.ide          178                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              178                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide        41728                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41728                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41728                       # number of overall misses
-system.iocache.overall_misses::total            41728                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     22088883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     22088883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4858687173                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4858687173                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   4880776056                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4880776056                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   4880776056                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4880776056                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide        41730                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41730                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41730                       # number of overall misses
+system.iocache.overall_misses::total            41730                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     22412883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     22412883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4956087382                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4956087382                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   4978500265                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4978500265                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   4978500265                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4978500265                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          178                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41728                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41728                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41728                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41728                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41730                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41730                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41730                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41730                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
@@ -1291,38 +1292,38 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125505.017045                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125505.017045                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116930.284294                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 116930.284294                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 116966.450729                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 116966.450729                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 116966.450729                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 116966.450729                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            16                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125915.073034                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119274.340152                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 119274.340152                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 119302.666307                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 119302.666307                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 119302.666307                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 119302.666307                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs          1665                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   10                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            8                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs   166.500000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
 system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          176                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::tsunami.ide          178                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          178                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41728                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41728                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41728                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41728                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13288883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13288883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2778678942                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2778678942                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   2791967825                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2791967825                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   2791967825                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2791967825                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide        41730                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41730                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41730                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41730                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13512883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13512883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2876027417                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2876027417                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   2889540300                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2889540300                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   2889540300                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2889540300                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1331,196 +1332,196 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75505.017045                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 75505.017045                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66872.327253                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66872.327253                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66908.738137                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 66908.738137                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66908.738137                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 66908.738137                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   341251                       # number of replacements
-system.l2c.tags.tagsinuse                65397.203087                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3991452                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   406774                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     9.812456                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               7305719000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     281.092347                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4857.550126                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    59344.826381                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      110.880269                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      802.853964                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.004289                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.074120                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.905530                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.001692                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.012251                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.997882                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65523                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          485                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          770                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6255                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        57986                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.999802                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 35595123                       # Number of tag accesses
-system.l2c.tags.data_accesses                35595123                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks       793736                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          793736                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       747944                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          747944                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            3115                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            2258                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                5373                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           912                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           927                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              1839                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           126843                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            47590                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               174433                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        686424                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        316124                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1002548                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       663180                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       109254                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           772434                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              686424                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              790023                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              316124                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              156844                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1949415                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             686424                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             790023                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             316124                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             156844                       # number of overall hits
-system.l2c.overall_hits::total                1949415                       # number of overall hits
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69215.138068                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69215.138068                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69243.716751                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 69243.716751                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69243.716751                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 69243.716751                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                   342937                       # number of replacements
+system.l2c.tags.tagsinuse                65389.954388                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3989146                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   408458                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     9.766355                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               7750506000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks     285.827023                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4791.190703                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    59306.187710                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      166.825599                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      839.923352                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.004361                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.073108                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.904941                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.002546                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.012816                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.997772                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65521                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          697                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1597                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6182                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        57022                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.999771                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 35591920                       # Number of tag accesses
+system.l2c.tags.data_accesses                35591920                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks       792871                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          792871                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks       746791                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total          746791                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data            3150                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            2355                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                5505                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           947                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           959                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total              1906                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           128503                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            43274                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               171777                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        680173                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        326101                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total           1006274                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       663284                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       108416                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           771700                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.inst              680173                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              791787                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              326101                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              151690                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1949751                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             680173                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             791787                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             326101                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             151690                       # number of overall hits
+system.l2c.overall_hits::total                1949751                       # number of overall hits
 system.l2c.UpgradeReq_misses::cpu0.data             5                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu1.data             1                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                 6                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         115133                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           6337                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             121470                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        12995                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst          448                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           13443                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       271663                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data          234                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         271897                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst             12995                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            386796                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               448                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data              6571                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                406810                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            12995                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           386796                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              448                       # number of overall misses
-system.l2c.overall_misses::cpu1.data             6571                       # number of overall misses
-system.l2c.overall_misses::total               406810                       # number of overall misses
+system.l2c.ReadExReq_misses::cpu0.data         116830                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           6419                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             123249                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        12445                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst          987                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total           13432                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       271517                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data          340                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         271857                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.inst             12445                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            388347                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst               987                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data              6759                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                408538                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            12445                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           388347                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst              987                       # number of overall misses
+system.l2c.overall_misses::cpu1.data             6759                       # number of overall misses
+system.l2c.overall_misses::total               408538                       # number of overall misses
 system.l2c.UpgradeReq_miss_latency::cpu0.data       300000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data        29500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       329500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   8880064000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    523419000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   9403483000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1061507000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst     36851500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   1098358500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  19897250500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data     18659000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  19915909500                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1061507000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  28777314500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst     36851500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    542078000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     30417751000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1061507000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  28777314500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     36851500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    542078000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    30417751000                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       793736                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       793736                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks       747944                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total       747944                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         3120                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         2259                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            5379                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          912                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          927                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1839                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       241976                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        53927                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           295903                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       699419                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       316572                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total       1015991                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       934843                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       109488                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      1044331                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          699419                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1176819                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          316572                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          163415                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2356225                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         699419                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1176819                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         316572                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         163415                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2356225                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.001603                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.000443                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.001115                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.475803                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.117511                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.410506                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.018580                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.001415                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.013231                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.290597                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.002137                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.260355                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.018580                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.328679                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.001415                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.040211                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.172653                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.018580                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.328679                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.001415                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.040211                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.172653                       # miss rate for overall accesses
+system.l2c.UpgradeReq_miss_latency::cpu1.data        28500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       328500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  10622495500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    657559500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  11280055000                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1281839000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst    101239000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total   1383078000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  21946509000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data     42090000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  21988599000                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   1281839000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  32569004500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    101239000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    699649500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     34651732000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   1281839000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  32569004500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    101239000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    699649500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    34651732000                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks       792871                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       792871                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks       746791                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total       746791                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         3155                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         2356                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            5511                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          947                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          959                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1906                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       245333                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        49693                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           295026                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       692618                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       327088                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total       1019706                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       934801                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       108756                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      1043557                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          692618                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1180134                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          327088                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          158449                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2358289                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         692618                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1180134                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         327088                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         158449                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2358289                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.001585                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.000424                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.001089                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.476210                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.129173                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.417756                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.017968                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.003018                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.013172                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.290454                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.003126                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.260510                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.017968                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.329070                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.003018                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.042657                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.173235                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.017968                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.329070                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.003018                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.042657                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.173235                       # miss rate for overall accesses
 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data        60000                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data        29500                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 54916.666667                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77128.746754                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82597.285782                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 77414.036388                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81685.802232                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82257.812500                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 81704.864985                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73242.401431                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 79739.316239                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 73247.992806                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 81685.802232                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 74399.203973                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 82257.812500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 82495.510577                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 74771.394508                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 81685.802232                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 74399.203973                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 82257.812500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 82495.510577                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 74771.394508                       # average overall miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data        28500                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total        54750                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90922.669691                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102439.554448                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 91522.486998                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 103000.321414                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 102572.441743                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 102968.880286                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80829.226163                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123794.117647                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 80882.960527                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 103000.321414                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 83865.729618                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 102572.441743                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 103513.759432                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 84818.871194                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 103000.321414                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 83865.729618                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 102572.441743                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 103513.759432                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 84818.871194                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks               78803                       # number of writebacks
-system.l2c.writebacks::total                    78803                       # number of writebacks
+system.l2c.writebacks::writebacks               79969                       # number of writebacks
+system.l2c.writebacks::total                    79969                       # number of writebacks
 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           11                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
@@ -1532,231 +1533,231 @@ system.l2c.CleanEvict_mshr_misses::total           10                       # nu
 system.l2c.UpgradeReq_mshr_misses::cpu0.data            5                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu1.data            1                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       115133                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         6337                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        121470                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        12995                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst          437                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        13432                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       271663                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data          234                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       271897                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        12995                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       386796                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst          437                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         6571                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           406799                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        12995                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       386796                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst          437                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data         6571                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          406799                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7110                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data           89                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total         7199                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10837                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3221                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        14058                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17947                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3310                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        21257                       # number of overall MSHR uncacheable misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       116830                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         6419                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        123249                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        12445                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst          976                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total        13421                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       271517                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data          340                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       271857                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        12445                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       388347                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst          976                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         6759                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           408527                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        12445                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       388347                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst          976                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data         6759                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          408527                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7073                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data          125                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total         7198                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10752                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3371                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        14123                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17825                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3496                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        21321                       # number of overall MSHR uncacheable misses
 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       250000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data        19500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       269500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7728734000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    460049000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   8188783000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    931557000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst     31665500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total    963222500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17180620500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     16319000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  17196939500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    931557000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  24909354500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     31665500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    476368000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  26348945000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    931557000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  24909354500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     31665500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    476368000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  26348945000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1489570000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     19061000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1508631000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1489570000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data     19061000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1508631000                       # number of overall MSHR uncacheable cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data        18500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       268500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   9454195500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    593369500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  10047565000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1157389000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst     90609000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   1247998000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  19231339000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     38690000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  19270029000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1157389000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  28685534500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     90609000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    632059500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  30565592000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1157389000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  28685534500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     90609000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    632059500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  30565592000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1483681000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     24728000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1508409000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1483681000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data     24728000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1508409000                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.001603                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.000443                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.001115                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.475803                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.117511                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.410506                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.018580                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.001380                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013221                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.290597                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.002137                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.260355                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018580                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.328679                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.001380                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.040211                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.172649                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018580                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.328679                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.001380                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.040211                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.172649                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.001585                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.000424                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.001089                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.476210                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.129173                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.417756                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.017968                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.002984                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013162                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.290454                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.003126                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.260510                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.017968                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.329070                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.002984                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.042657                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.173230                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.017968                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.329070                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.002984                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.042657                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.173230                       # mshr miss rate for overall accesses
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        50000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        19500                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44916.666667                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67128.746754                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72597.285782                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 67414.036388                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71685.802232                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72461.098398                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71711.025908                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63242.401431                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 69739.316239                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63247.992806                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71685.802232                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64399.203973                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72461.098398                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72495.510577                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 64771.410451                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71685.802232                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64399.203973                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72461.098398                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72495.510577                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 64771.410451                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209503.516174                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209561.189054                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82998.272692                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data  5758.610272                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 70971.021311                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        851905                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       404237                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          411                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        18500                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total        44750                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80922.669691                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92439.554448                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 81522.486998                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 93000.321414                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92837.090164                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92988.450935                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70829.226163                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113794.117647                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70882.960527                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93000.321414                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73865.729618                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92837.090164                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93513.759432                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 74819.025425                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93000.321414                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73865.729618                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92837.090164                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93513.759432                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 74819.025425                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data       197824                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data  7073.226545                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests        856503                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       407142                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          413                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq                7199                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292704                       # Transaction distribution
-system.membus.trans_dist::WriteReq              14058                       # Transaction distribution
-system.membus.trans_dist::WriteResp             14058                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       120323                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261806                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            11056                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           9461                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq                7198                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292654                       # Transaction distribution
+system.membus.trans_dist::WriteReq              14123                       # Transaction distribution
+system.membus.trans_dist::WriteResp             14123                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       121489                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262335                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            11693                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           9938                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            122183                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           121347                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        285505                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            123969                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           123101                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        285456                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42514                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1174875                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1217389                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83439                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83439                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1300828                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        81882                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31053824                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31135706                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42642                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1181120                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1223762                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83443                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        83443                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1307205                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        82394                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31237440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     31319834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33793946                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            21651                       # Total snoops (count)
-system.membus.snoopTraffic                      27136                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            491014                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001340                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.036583                       # Request fanout histogram
+system.membus.pkt_size::total                33978074                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            22774                       # Total snoops (count)
+system.membus.snoopTraffic                      27264                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            493929                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.001371                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.036997                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  490356     99.87%     99.87% # Request fanout histogram
-system.membus.snoop_fanout::1                     658      0.13%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  493252     99.86%     99.86% # Request fanout histogram
+system.membus.snoop_fanout::1                     677      0.14%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              491014                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            40347000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              493929                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            40493000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1314918038                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1323047597                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2173304250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2182313750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy             904117                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy             915117                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      4781747                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2390985                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       355114                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops            992                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops          932                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops           60                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq               7199                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2102308                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             14058                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            14058                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       872539                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1014847                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          815207                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           16306                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         11300                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          27606                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           297851                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          297851                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1016013                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1079098                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq          229                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2097686                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3605272                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       949165                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       535742                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7187865                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     89487744                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    118850496                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     40485888                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     17815770                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              266639898                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          398766                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                   7394432                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          2783305                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.138476                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.345638                       # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests      4789247                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2394847                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       361788                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops            989                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops          928                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops           61                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq               7198                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2106871                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             14123                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            14123                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       872840                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1018539                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          815364                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           17050                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         11844                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          28894                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           297037                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          297037                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1019728                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1079947                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq          246                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2077258                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3616236                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       980715                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       523549                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7197758                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     88615616                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    119196292                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     41832064                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     17309590                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              266953562                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          403246                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                   7576960                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples          2790110                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.141029                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.348296                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                2398113     86.16%     86.16% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 384964     13.83%     99.99% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    227      0.01%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                2396861     85.91%     85.91% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 393013     14.09%     99.99% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    235      0.01%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      1      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            2783305                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4217117493                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            2790110                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4223757496                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           299383                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           302383                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1049361097                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1039141633                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1811830165                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1817975093                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         476124465                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         491872018                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         281628843                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         276251327                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1788,28 +1789,28 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1962626573500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966741627000                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
index b603b455c..fff26b301 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
@@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 38 cycles, load miss latency 162 cycles
+
4096K Bcache detected; load hit latency 38 cycles, load miss latency 175 cycles
 
SMP: 2 CPUs probed -- cpu_present_mask = 3
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index b5a7841a1..7a4d88e30 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -25,7 +25,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:134217727
+mem_ranges=0:134217727:0:0:0:0
 memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
@@ -60,7 +60,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=8796093022208:18446744073709551615
+ranges=8796093022208:18446744073709551615:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -115,7 +115,7 @@ icache_port=system.cpu.icache.cpu_side
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -166,7 +166,7 @@ size=64
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -226,7 +226,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -389,7 +389,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=0:134217727
+addr_ranges=0:134217727:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -434,7 +434,7 @@ size=1024
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -446,7 +446,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -478,29 +478,36 @@ update_data=false
 warn_access=
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -520,6 +527,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -529,7 +537,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -551,9 +559,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index ef6ffb4a6..1d59c0edc 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:24
-gem5 executing on e108600-lin, pid 39578
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:45
+gem5 executing on e108600-lin, pid 28068
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1941275996000 because m5_exit instruction encountered
+Exiting @ tick 1926421414000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 23c45cb03..e8b92466f 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.922415                       # Number of seconds simulated
-sim_ticks                                1922415409000                       # Number of ticks simulated
-final_tick                               1922415409000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.926421                       # Number of seconds simulated
+sim_ticks                                1926421414000                       # Number of ticks simulated
+final_tick                               1926421414000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 933149                       # Simulator instruction rate (inst/s)
-host_op_rate                                   933149                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            31931169584                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 334404                       # Number of bytes of host memory used
-host_seconds                                    60.21                       # Real time elapsed on the host
-sim_insts                                    56180200                       # Number of instructions simulated
-sim_ops                                      56180200                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 779030                       # Simulator instruction rate (inst/s)
+host_op_rate                                   779030                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            26705916367                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 331544                       # Number of bytes of host memory used
+host_seconds                                    72.13                       # Real time elapsed on the host
+sim_insts                                    56195014                       # Number of instructions simulated
+sim_ops                                      56195014                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            844608                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24856576                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            844672                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24856896                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25702144                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       844608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          844608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7408512                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7408512                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13197                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388384                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25702528                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       844672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          844672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7408960                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7408960                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              13198                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388389                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                401596                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115758                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115758                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               439347                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12929867                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               499                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13369714                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          439347                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             439347                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3853752                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3853752                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3853752                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              439347                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12929867                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              499                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17223466                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        401596                       # Number of read requests accepted
-system.physmem.writeReqs                       115758                       # Number of write requests accepted
-system.physmem.readBursts                      401596                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     115758                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25695616                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6528                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7407424                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25702144                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7408512                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      102                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                401602                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115765                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115765                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               438467                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12903146                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               498                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13342111                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          438467                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             438467                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3845971                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3845971                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3845971                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              438467                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12903146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              498                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17188081                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        401602                       # Number of read requests accepted
+system.physmem.writeReqs                       115765                       # Number of write requests accepted
+system.physmem.readBursts                      401602                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     115765                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25695552                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6976                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7408000                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25702528                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7408960                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      109                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25227                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25633                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25570                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25510                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               24963                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24975                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24200                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               25229                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25631                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25563                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25503                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               24978                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24964                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24209                       # Per bank write bursts
 system.physmem.perBankRdBursts::7               24494                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25179                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               24767                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25265                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24877                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24504                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25368                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25180                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               24757                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25269                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24873                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24512                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25367                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              25615                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25347                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7623                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7643                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7871                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7543                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7113                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6990                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6317                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6320                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7316                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6519                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7114                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6905                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7090                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25349                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7626                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7640                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7866                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7539                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7128                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6982                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6324                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6321                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7317                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6511                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7117                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6900                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7101                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7827                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               7864                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7686                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7687                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1922403535500                       # Total gap between requests
+system.physmem.numWrRetry                          65                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1926409540500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  401596                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  401602                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 115758                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    401480                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 115765                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    401479                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
@@ -149,197 +149,192 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1798                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5708                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6441                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7460                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6948                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8317                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6845                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6921                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6031                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5597                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       29                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        63567                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      520.758255                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     315.623593                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     415.134860                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14658     23.06%     23.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11541     18.16%     41.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4861      7.65%     48.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3298      5.19%     54.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2285      3.59%     57.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1919      3.02%     60.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1565      2.46%     63.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1066      1.68%     64.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22374     35.20%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          63567                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5112                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        78.539124                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2951.473216                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5109     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1555                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2761                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5433                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5972                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6087                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6885                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7936                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6558                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6936                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7510                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6518                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6660                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5973                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5861                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5660                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5576                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      497                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      477                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      395                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      374                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      340                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      292                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      316                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      351                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      363                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      332                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      304                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      296                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      281                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      260                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      341                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      335                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      300                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      159                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        63474                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      521.529319                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     315.079750                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     415.298836                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14953     23.56%     23.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11433     18.01%     41.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4319      6.80%     48.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3083      4.86%     53.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3219      5.07%     58.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1509      2.38%     60.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1583      2.49%     63.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          998      1.57%     64.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22377     35.25%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          63474                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5049                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        79.519311                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2969.676150                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5046     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5112                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5112                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.641041                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.167929                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       21.759533                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4475     87.54%     87.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              34      0.67%     88.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              11      0.22%     88.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              14      0.27%     88.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             223      4.36%     93.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              16      0.31%     93.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              14      0.27%     93.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              12      0.23%     93.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               3      0.06%     93.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               7      0.14%     94.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.10%     94.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.04%     94.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              12      0.23%     94.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               2      0.04%     94.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.06%     94.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               1      0.02%     94.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              33      0.65%     95.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.06%     95.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91              18      0.35%     95.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     95.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             174      3.40%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.08%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             4      0.08%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.04%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.04%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             2      0.04%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             4      0.08%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             9      0.18%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             2      0.04%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             2      0.04%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             3      0.06%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.02%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             5      0.10%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-251             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5112                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2082530750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9610543250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2007470000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5186.95                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5049                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5049                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.925332                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.952060                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       24.989890                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4540     89.92%     89.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              33      0.65%     90.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             164      3.25%     93.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47               7      0.14%     93.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55               1      0.02%     93.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              14      0.28%     94.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71               7      0.14%     94.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               4      0.08%     94.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              36      0.71%     95.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               2      0.04%     95.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            139      2.75%     97.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            18      0.36%     98.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            13      0.26%     98.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             3      0.06%     98.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             6      0.12%     98.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             6      0.12%     98.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             3      0.06%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             2      0.04%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            13      0.26%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             4      0.08%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            12      0.24%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199            10      0.20%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             1      0.02%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             1      0.02%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             6      0.12%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             2      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             2      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5049                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6110965000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               13638958750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2007465000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15220.60                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23936.95                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.37                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  33970.60                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.34                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.85                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.37                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.34                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        3.85                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.01                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     359878                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93790                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.63                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.02                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3715837.77                       # Average gap between requests
-system.physmem.pageHitRate                      87.71                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  235297440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  128386500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1564461600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                372081600                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           125562446880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            64706229855                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1096686028500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1289254932375                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.645215                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1824198256500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     64193480000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     34018076000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  245269080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  133827375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1567191600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                377920080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           125562446880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            65408106195                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1096070355750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1289365116960                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.702526                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1823171088500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     64193480000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     35045257750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
+system.physmem.avgWrQLen                        24.93                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     360227                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93542                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.72                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.80                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3723487.47                       # Average gap between requests
+system.physmem.pageHitRate                      87.73                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  220840200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  117379350                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1432076940                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                299763720                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           5519467200.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5038358250                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              366301440                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       13030830420                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        6357713760                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       449603447400                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             481990669050                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              250.200016                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           1914256960750                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      613825000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2347892000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   1869275563500                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  16556600250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      9050884750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  28576648500                       # Time in different power states
+system.physmem_1.actEnergy                  232364160                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  123504480                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1434583080                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                304451280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           5706932400.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5157840510                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              361297920                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       13647845730                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        6595007040                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       449082638955                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             482651277075                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              250.542936                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           1914153639500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      598128250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2427510000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   1867054823500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  17174624250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      9236704750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  29929623250                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9064160                       # DTB read hits
-system.cpu.dtb.read_misses                      10312                       # DTB read misses
+system.cpu.dtb.read_hits                      9066536                       # DTB read hits
+system.cpu.dtb.read_misses                      10331                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_accesses                   728817                       # DTB read accesses
-system.cpu.dtb.write_hits                     6356116                       # DTB write hits
-system.cpu.dtb.write_misses                      1140                       # DTB write misses
+system.cpu.dtb.read_accesses                   728865                       # DTB read accesses
+system.cpu.dtb.write_hits                     6357492                       # DTB write hits
+system.cpu.dtb.write_misses                      1143                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_accesses                  291929                       # DTB write accesses
-system.cpu.dtb.data_hits                     15420276                       # DTB hits
-system.cpu.dtb.data_misses                      11452                       # DTB misses
+system.cpu.dtb.write_accesses                  291932                       # DTB write accesses
+system.cpu.dtb.data_hits                     15424028                       # DTB hits
+system.cpu.dtb.data_misses                      11474                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_accesses                  1020746                       # DTB accesses
-system.cpu.itb.fetch_hits                     4973965                       # ITB hits
-system.cpu.itb.fetch_misses                      4997                       # ITB misses
+system.cpu.dtb.data_accesses                  1020797                       # DTB accesses
+system.cpu.itb.fetch_hits                     4975201                       # ITB hits
+system.cpu.itb.fetch_misses                      5010                       # ITB misses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4978962                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4980211                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -352,43 +347,43 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numPwrStateTransitions               12754                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples          6377                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     281224726.046887                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    439034613.415905                       # Distribution of time spent in the clock gated state
+system.cpu.numPwrStateTransitions               12758                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples          6379                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     281128919.188117                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    439406492.836173                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::underflows            1      0.02%      0.02% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         6376     99.98%    100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10         6378     99.98%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total            6377                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    129045330999                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 1793370078001                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       3844830818                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::total            6379                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    133100038499                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321375501                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       3852842828                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6377                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211971                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74899     40.89%     40.89% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6379                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     212049                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74911     40.89%     40.89% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1932      1.05%     42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  106221     57.99%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183183                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73532     49.31%     49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22                    1934      1.06%     42.01% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  106246     57.99%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               183222                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73544     49.31%     49.31% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1932      1.30%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73532     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149127                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1857710123500     96.63%     96.63% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                93945500      0.00%     96.64% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               769790000      0.04%     96.68% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             63840816000      3.32%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1922414675000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981749                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1934      1.30%     50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73544     49.31%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149153                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1859428695000     96.52%     96.52% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                94503000      0.00%     96.53% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               772442000      0.04%     96.57% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             66125040000      3.43%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1926420680000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981752                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.692255                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814088                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.692205                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814056                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -424,58 +419,58 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4174      2.16%      2.17% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4177      2.16%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175962     91.22%     93.41% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6833      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175997     91.22%     93.41% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6834      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5157      2.67%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5159      2.67%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192906                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5901                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
+system.cpu.kern.callpal::total                 192947                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5906                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1910                      
-system.cpu.kern.mode_good::user                  1741                      
-system.cpu.kern.mode_good::idle                   169                      
-system.cpu.kern.mode_switch_good::kernel     0.323674                       # fraction of useful protection mode switches
+system.cpu.kern.mode_good::kernel                1908                      
+system.cpu.kern.mode_good::user                  1738                      
+system.cpu.kern.mode_good::idle                   170                      
+system.cpu.kern.mode_switch_good::kernel     0.323061                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080630                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.392278                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        46528757000      2.42%      2.42% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5244548000      0.27%      2.69% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1870641368000     97.31%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
-system.cpu.committedInsts                    56180200                       # Number of instructions committed
-system.cpu.committedOps                      56180200                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              52052716                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 324259                       # Number of float alu accesses
-system.cpu.num_func_calls                     1483318                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      6468478                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     52052716                       # number of integer instructions
-system.cpu.num_fp_insts                        324259                       # number of float instructions
-system.cpu.num_int_register_reads            71320481                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38519316                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               163543                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166418                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      15472847                       # number of memory refs
-system.cpu.num_load_insts                     9100978                       # Number of load instructions
-system.cpu.num_store_insts                    6371869                       # Number of store instructions
-system.cpu.num_idle_cycles               3586740156.000134                       # Number of idle cycles
-system.cpu.num_busy_cycles               258090661.999866                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.067127                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.932873                       # Percentage of idle cycles
-system.cpu.Branches                           8422318                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               3200272      5.70%      5.70% # Class of executed instruction
-system.cpu.op_class::IntAlu                  36230015     64.48%     70.17% # Class of executed instruction
-system.cpu.op_class::IntMult                    60990      0.11%     70.28% # Class of executed instruction
+system.cpu.kern.mode_switch_good::idle       0.081107                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.391786                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        47043056000      2.44%      2.44% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           5370301500      0.28%      2.72% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1874007320500     97.28%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
+system.cpu.committedInsts                    56195014                       # Number of instructions committed
+system.cpu.committedOps                      56195014                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              52066552                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
+system.cpu.num_func_calls                     1483758                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      6469897                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     52066552                       # number of integer instructions
+system.cpu.num_fp_insts                        324460                       # number of float instructions
+system.cpu.num_int_register_reads            71340789                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           38530081                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      15476659                       # number of memory refs
+system.cpu.num_load_insts                     9103400                       # Number of load instructions
+system.cpu.num_store_insts                    6373259                       # Number of store instructions
+system.cpu.num_idle_cycles               3586642751.000138                       # Number of idle cycles
+system.cpu.num_busy_cycles               266200076.999862                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.069092                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.930908                       # Percentage of idle cycles
+system.cpu.Branches                           8424278                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               3201027      5.70%      5.70% # Class of executed instruction
+system.cpu.op_class::IntAlu                  36239709     64.48%     70.17% # Class of executed instruction
+system.cpu.op_class::IntMult                    61024      0.11%     70.28% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     70.28% # Class of executed instruction
-system.cpu.op_class::FloatAdd                   38081      0.07%     70.35% # Class of executed instruction
+system.cpu.op_class::FloatAdd                   38087      0.07%     70.35% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     70.35% # Class of executed instruction
 system.cpu.op_class::FloatCvt                       0      0.00%     70.35% # Class of executed instruction
 system.cpu.op_class::FloatMult                      0      0.00%     70.35% # Class of executed instruction
@@ -501,482 +496,482 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     70.35% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     70.35% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     70.35% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::MemRead                  9328048     16.60%     86.95% # Class of executed instruction
-system.cpu.op_class::MemWrite                 6377943     11.35%     98.30% # Class of executed instruction
-system.cpu.op_class::IprAccess                 953034      1.70%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                  9330523     16.60%     86.95% # Class of executed instruction
+system.cpu.op_class::MemWrite                 6379338     11.35%     98.30% # Class of executed instruction
+system.cpu.op_class::IprAccess                 953511      1.70%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   56192019                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           1390892                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.977567                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14047886                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1391404                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             10.096195                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         114940500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.977567                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999956                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999956                       # Average percentage of cache occupancy
+system.cpu.op_class::total                   56206855                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           1390811                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.976541                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            14051752                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1391323                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             10.099561                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         121311500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.976541                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999954                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999954                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          258                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63148569                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63148569                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data      7813455                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7813455                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5852226                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5852226                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       182968                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182968                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199220                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199220                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13665681                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13665681                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13665681                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13665681                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1069828                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069828                       # number of ReadReq misses
+system.cpu.dcache.tags.tag_accesses          63163628                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63163628                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data      7815905                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7815905                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5853570                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5853570                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183002                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183002                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199258                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199258                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13669475                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13669475                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13669475                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13669475                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1069743                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1069743                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       304319                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       304319                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17275                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17275                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1374147                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1374147                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1374147                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1374147                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  30980928500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  30980928500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  11763694500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  11763694500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    230325000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    230325000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  42744623000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  42744623000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  42744623000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  42744623000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      8883283                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8883283                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6156545                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6156545                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200243                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200243                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199220                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199220                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15039828                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15039828                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15039828                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15039828                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120432                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120432                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049430                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049430                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086270                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086270                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.091367                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.091367                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.091367                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.091367                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28958.793843                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28958.793843                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38655.800328                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38655.800328                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13332.850941                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13332.850941                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31106.295760                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31106.295760                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31106.295760                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31106.295760                       # average overall miss latency
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17279                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17279                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1374062                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1374062                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1374062                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1374062                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  33050586500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  33050586500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  13442150000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  13442150000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    232520000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    232520000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  46492736500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  46492736500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  46492736500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  46492736500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      8885648                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      8885648                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6157889                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6157889                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200281                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200281                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199258                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199258                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15043537                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15043537                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15043537                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15043537                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120390                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120390                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049419                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049419                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086274                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086274                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.091339                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.091339                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.091339                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.091339                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.819370                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.819370                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.247934                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.247934                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.797268                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.797268                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.981564                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33835.981564                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.981564                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 33835.981564                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       835265                       # number of writebacks
-system.cpu.dcache.writebacks::total            835265                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069828                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1069828                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       835205                       # number of writebacks
+system.cpu.dcache.writebacks::total            835205                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069743                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1069743                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304319                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       304319                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17275                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17275                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1374147                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1374147                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1374147                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1374147                       # number of overall MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17279                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17279                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1374062                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1374062                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1374062                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1374062                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9650                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9650                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16580                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16580                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29911100500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  29911100500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11459375500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11459375500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    213050000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    213050000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  41370476000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  41370476000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  41370476000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  41370476000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1533911000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1533911000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1533911000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   1533911000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120432                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120432                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049430                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049430                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086270                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086270                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091367                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091367                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091367                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091367                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27958.793843                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27958.793843                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37655.800328                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37655.800328                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12332.850941                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12332.850941                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.295760                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.295760                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.295760                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.295760                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.578644                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.578644                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92515.741858                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92515.741858                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements            928034                       # number of replacements
-system.cpu.icache.tags.tagsinuse           508.064469                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            55263315                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            928545                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             59.516033                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       42160205500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   508.064469                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.992313                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.992313                       # Average percentage of cache occupancy
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9652                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total         9652                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16582                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        16582                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  31980843500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  31980843500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13137831000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  13137831000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    215241000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    215241000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45118674500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  45118674500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45118674500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  45118674500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1533908500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1533908500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1533908500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   1533908500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120390                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120390                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049419                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049419                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086274                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086274                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091339                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091339                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091339                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091339                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.819370                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.819370                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.247934                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.247934                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.797268                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.797268                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.981564                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.981564                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.981564                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.981564                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.217893                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.217893                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92504.432517                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92504.432517                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements            928683                       # number of replacements
+system.cpu.icache.tags.tagsinuse           507.830404                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            55277502                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            929194                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             59.489732                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       44439092500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   507.830404                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.991856                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.991856                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          57120725                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         57120725                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     55263315                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55263315                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      55263315                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55263315                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     55263315                       # number of overall hits
-system.cpu.icache.overall_hits::total        55263315                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       928705                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        928705                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       928705                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         928705                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       928705                       # number of overall misses
-system.cpu.icache.overall_misses::total        928705                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  13023819500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  13023819500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  13023819500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  13023819500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  13023819500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  13023819500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     56192020                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     56192020                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     56192020                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     56192020                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     56192020                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     56192020                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016527                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.016527                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.016527                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.016527                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.016527                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.016527                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14023.634523                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14023.634523                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14023.634523                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14023.634523                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14023.634523                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14023.634523                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          57136210                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         57136210                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     55277502                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        55277502                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      55277502                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         55277502                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     55277502                       # number of overall hits
+system.cpu.icache.overall_hits::total        55277502                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       929354                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        929354                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       929354                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         929354                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       929354                       # number of overall misses
+system.cpu.icache.overall_misses::total        929354                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  13309679000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  13309679000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  13309679000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  13309679000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  13309679000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  13309679000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     56206856                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     56206856                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     56206856                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     56206856                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     56206856                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     56206856                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016535                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.016535                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.016535                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.016535                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.016535                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.016535                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14321.430800                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14321.430800                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14321.430800                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14321.430800                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.430800                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14321.430800                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks       928034                       # number of writebacks
-system.cpu.icache.writebacks::total            928034                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       928705                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       928705                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       928705                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       928705                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       928705                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       928705                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12095114500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12095114500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12095114500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12095114500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12095114500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12095114500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016527                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016527                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016527                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.016527                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016527                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.016527                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13023.634523                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13023.634523                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13023.634523                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13023.634523                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13023.634523                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13023.634523                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           336391                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65395.484463                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4235202                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           401913                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.537609                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       7260348000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   235.775942                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4738.507265                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 60421.201256                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.003598                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072304                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.921954                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997856                       # Average percentage of cache occupancy
+system.cpu.icache.writebacks::writebacks       928683                       # number of writebacks
+system.cpu.icache.writebacks::total            928683                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929354                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       929354                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       929354                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       929354                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       929354                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       929354                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12380325000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12380325000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12380325000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12380325000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12380325000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12380325000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016535                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016535                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016535                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.016535                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016535                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.016535                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.430800                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.430800                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.430800                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.430800                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.430800                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.430800                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           336397                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65387.710851                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4236321                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           401919                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.540236                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       7724199000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   234.658578                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4730.574413                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477860                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.003581                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072183                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.921974                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997737                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          518                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          384                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4753                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        59867                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4685                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        59935                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         37502484                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        37502484                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       835265                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       835265                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       927811                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       927811                       # number of WritebackClean hits
+system.cpu.l2cache.tags.tag_accesses         37511490                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        37511490                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks       835205                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       835205                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       928450                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       928450                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           12                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           12                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187491                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187491                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       915488                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       915488                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       815128                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       815128                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       915488                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1002619                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1918107                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       915488                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1002619                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1918107                       # number of overall hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       187485                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187485                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       916136                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       916136                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       815048                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       815048                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       916136                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1002533                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1918669                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       916136                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1002533                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1918669                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       116811                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       116811                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        13197                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        13197                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       271975                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       271975                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        13197                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       388786                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        401983                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        13197                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       388786                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       401983                       # number of overall misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       116817                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       116817                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        13198                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        13198                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       271974                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       271974                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        13198                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       388791                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        401989                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        13198                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       388791                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       401989                       # number of overall misses
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       246500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total       246500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9030572500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9030572500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1076146500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1076146500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  19920583000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  19920583000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1076146500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  28951155500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  30027302000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1076146500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  28951155500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  30027302000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       835265                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       835265                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       927811                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       927811                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10709040500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  10709040500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1353538000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1353538000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  21993492000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  21993492000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1353538000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  32702532500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  34056070500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1353538000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  32702532500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  34056070500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       835205                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       835205                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       928450                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       928450                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       304302                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       304302                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       928685                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       928685                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1087103                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1087103                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       928685                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1391405                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2320090                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       928685                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1391405                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2320090                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       929334                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       929334                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1087022                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1087022                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       929334                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1391324                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2320658                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       929334                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1391324                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2320658                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.294118                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.294118                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383865                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383865                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014210                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014210                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.250183                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.250183                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014210                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.279420                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.173262                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014210                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.279420                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.173262                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383885                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.383885                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014202                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014202                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.250201                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.250201                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014202                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.279440                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.173222                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014202                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.279440                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.173222                       # miss rate for overall accesses
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        49300                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        49300                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77309.264538                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77309.264538                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81544.782905                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81544.782905                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73244.169501                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73244.169501                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81544.782905                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74465.529880                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74697.939963                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81544.782905                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74465.529880                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74697.939963                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91673.647671                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91673.647671                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102556.296409                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102556.296409                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80866.156324                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80866.156324                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102556.296409                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84113.398973                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 84718.911463                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102556.296409                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84113.398973                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 84718.911463                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        74246                       # number of writebacks
-system.cpu.l2cache.writebacks::total            74246                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        74253                       # number of writebacks
+system.cpu.l2cache.writebacks::total            74253                       # number of writebacks
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116811                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116811                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        13197                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        13197                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       271975                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       271975                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        13197                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       388786                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       401983                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        13197                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       388786                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       401983                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116817                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       116817                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        13198                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        13198                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       271974                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       271974                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        13198                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       388791                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       401989                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        13198                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       388791                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       401989                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9650                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9650                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16580                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16580                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9652                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9652                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16582                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16582                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       196500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       196500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7862462500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7862462500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    944176500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    944176500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  17200833000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  17200833000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    944176500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  25063295500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  26007472000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    944176500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  25063295500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  26007472000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1447255500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1447255500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1447255500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1447255500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9540870500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9540870500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1221558000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1221558000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  19273752000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  19273752000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1221558000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  28814622500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  30036180500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1221558000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  28814622500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  30036180500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1447252500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1447252500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1447252500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1447252500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.294118                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.294118                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383865                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383865                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014210                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014210                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.250183                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.250183                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014210                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279420                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.173262                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014210                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279420                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.173262                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383885                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383885                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014202                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014202                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.250201                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.250201                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014202                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279440                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.173222                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014202                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279440                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.173222                       # mshr miss rate for overall accesses
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        39300                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        39300                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67309.264538                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67309.264538                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71544.782905                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71544.782905                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63244.169501                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63244.169501                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71544.782905                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64465.529880                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64697.939963                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71544.782905                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64465.529880                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64697.939963                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208839.177489                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208839.177489                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87289.234017                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87289.234017                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      4639053                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2319092                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1505                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81673.647671                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81673.647671                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92556.296409                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92556.296409                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70866.156324                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70866.156324                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92556.296409                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74113.398973                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.911463                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92556.296409                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74113.398973                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.911463                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      4640189                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2319660                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1516                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops          884                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops          884                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2022895                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9650                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9650                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       909511                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       928034                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       817772                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2023463                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9652                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9652                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       909458                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       928683                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       817750                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       304302                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       304302                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       928705                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1087263                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       929354                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1087182                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq          219                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2785424                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4207053                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6992477                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    118830016                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142561492                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          261391508                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      336947                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               4763072                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      2673477                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000954                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.030869                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2787371                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4206814                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6994185                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    118913088                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142552484                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          261465572                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      336953                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               4763520                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      2674053                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000958                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.030932                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2670927     99.90%     99.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2550      0.10%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2671492     99.90%     99.90% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2561      0.10%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2673477                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4095940500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2674053                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4097099500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       293383                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1393057500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1394031000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2098871000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2098750500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -990,12 +985,12 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51202                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51202                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5156                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51204                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51204                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5160                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1004,11 +999,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        1812
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33160                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116610                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116614                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20640                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1017,13 +1012,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44564                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44580                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2706172                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              5337500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2706188                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              5344500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               758500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               757500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1031,36 +1026,36 @@ system.iobus.reqLayer6.occupancy                10000                       # La
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer22.occupancy              174000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            15814000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            15813000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             1891500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy             6041500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               82000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy               82500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           216133054                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           216215769                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23510000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23512000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.342865                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.340614                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1756469369000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.342865                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.083929                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.083929                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1760392723000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.340614                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.083788                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.083788                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
@@ -1069,14 +1064,14 @@ system.iocache.demand_misses::tsunami.ide        41725                       # n
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21758883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21758883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4857806171                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4857806171                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   4879565054                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4879565054                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   4879565054                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4879565054                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21848883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21848883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4937126886                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4937126886                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   4958975769                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4958975769                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   4958975769                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4958975769                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1093,19 +1088,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125773.890173                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125773.890173                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116909.081897                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 116909.081897                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 116945.837124                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 116945.837124                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 116945.837124                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 116945.837124                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126294.121387                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118818.032489                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118818.032489                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 118849.029814                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 118849.029814                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 118849.029814                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 118849.029814                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           700                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    4                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          175                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
@@ -1117,14 +1112,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41725
 system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13108883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13108883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2777800981                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2777800981                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   2790909864                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2790909864                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   2790909864                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2790909864                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13198883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13198883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2857073994                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2857073994                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   2870272877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2870272877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   2870272877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2870272877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1133,71 +1128,71 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75773.890173                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 75773.890173                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66851.198041                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66851.198041                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66888.193265                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 66888.193265                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66888.193265                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 66888.193265                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests        821076                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       378187                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68759.000626                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68759.000626                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68790.242708                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68790.242708                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68790.242708                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68790.242708                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests        821141                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       378246                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests          407                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
 system.membus.trans_dist::ReadResp             292275                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9650                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9650                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       115758                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261593                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9652                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9652                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       115765                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261592                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              136                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116680                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116680                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116686                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116686                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq        285345                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33160                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1139235                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1172395                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33164                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1139253                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1172417                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1255820                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44564                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30452928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30497492                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1255842                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44580                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30453760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30498340                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33155220                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33156068                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              431                       # Total snoops (count)
 system.membus.snoopTraffic                      27456                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            460293                       # Request fanout histogram
+system.membus.snoop_fanout::samples            460301                       # Request fanout histogram
 system.membus.snoop_fanout::mean             0.001416                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.037610                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.037609                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  459641     99.86%     99.86% # Request fanout histogram
+system.membus.snoop_fanout::0                  459649     99.86%     99.86% # Request fanout histogram
 system.membus.snoop_fanout::1                     652      0.14%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              460293                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            30118500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              460301                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            30124000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1286935040                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1287045337                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2142767250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2142987750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy             887117                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1229,28 +1224,28 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1922415409000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421414000                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
index 9603a7507..d82c05314 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 38 cycles, load miss latency 263 cycles
+
4096K Bcache detected; load hit latency 38 cycles, load miss latency 175 cycles
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 942d8ed5e..d7e6fcfdf 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -36,7 +36,7 @@ load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -153,7 +153,7 @@ icache_port=system.cpu0.icache.cpu_side
 [system.cpu0.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -250,7 +250,7 @@ port=system.cpu0.toL2Bus.slave[3]
 [system.cpu0.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -382,7 +382,7 @@ port=system.cpu0.toL2Bus.slave[2]
 [system.cpu0.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -531,7 +531,7 @@ icache_port=system.cpu1.icache.cpu_side
 [system.cpu1.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -628,7 +628,7 @@ port=system.cpu1.toL2Bus.slave[3]
 [system.cpu1.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -760,7 +760,7 @@ port=system.cpu1.toL2Bus.slave[2]
 [system.cpu1.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -907,7 +907,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -953,7 +953,7 @@ size=1024
 [system.l2c]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1051,27 +1051,27 @@ system=system
 
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -1091,6 +1091,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -1100,7 +1101,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1122,9 +1123,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -1477,7 +1478,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -1794,6 +1795,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1801,7 +1803,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -2032,6 +2034,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -2039,7 +2042,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index 8023e7aa6..c41a1ac7e 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:10:34
-gem5 executing on e108600-lin, pid 12233
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:54:49
+gem5 executing on e108600-lin, pid 17501
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
 
 Global frequency set at 1000000000000 ticks per second
@@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2869796829000 because m5_exit instruction encountered
+Exiting @ tick 2870822663000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index dc9310742..bd324667f 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,163 +1,159 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.870001                       # Number of seconds simulated
-sim_ticks                                2870000710000                       # Number of ticks simulated
-final_tick                               2870000710000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.870823                       # Number of seconds simulated
+sim_ticks                                2870822663000                       # Number of ticks simulated
+final_tick                               2870822663000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 371570                       # Simulator instruction rate (inst/s)
-host_op_rate                                   449436                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8101953096                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 621024                       # Number of bytes of host memory used
-host_seconds                                   354.24                       # Real time elapsed on the host
-sim_insts                                   131623434                       # Number of instructions simulated
-sim_ops                                     159206188                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 442891                       # Simulator instruction rate (inst/s)
+host_op_rate                                   535691                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9664154143                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 616988                       # Number of bytes of host memory used
+host_seconds                                   297.06                       # Real time elapsed on the host
+sim_insts                                   131564747                       # Number of instructions simulated
+sim_ops                                     159131669                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker          576                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1182180                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1312420                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8596224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           150484                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           578772                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       396096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1180196                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1289828                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8538816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           149012                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           568660                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       388160                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12217776                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1182180                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       150484                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1332664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8789056                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12116336                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1180196                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       149012                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1329208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8714368                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8806620                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8731932                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker            9                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             26925                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             21026                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       134316                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2506                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              9064                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         6189                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             26894                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             20673                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       133419                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2483                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              8906                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         6065                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                200051                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          137329                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                198466                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          136162                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               141720                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           156                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               140553                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           201                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              411909                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              457289                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2995199                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               52433                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              201663                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       138013                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              411100                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              449289                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2974345                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               51906                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              198083                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       135209                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              334                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4257064                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         411909                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          52433                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             464343                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3062388                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6106                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4220510                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         411100                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          51906                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             463006                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3035495                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6104                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3068508                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3062388                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          156                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3041613                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3035495                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          201                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             411909                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             463395                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2995199                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              52433                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             201677                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       138013                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             411100                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             455393                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2974345                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              51906                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             198097                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       135209                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             334                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7325572                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        200051                       # Number of read requests accepted
-system.physmem.writeReqs                       141720                       # Number of write requests accepted
-system.physmem.readBursts                      200051                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     141720                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12793920                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9344                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8819520                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12217776                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8806620                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      146                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::total                7262123                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        198466                       # Number of read requests accepted
+system.physmem.writeReqs                       140553                       # Number of write requests accepted
+system.physmem.readBursts                      198466                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     140553                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12692032                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9792                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8744000                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12116336                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8731932                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      153                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11709                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12160                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12038                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12178                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               20671                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12806                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12086                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12477                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12638                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12504                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11795                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11324                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11594                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11843                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11003                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11079                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8559                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9022                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9017                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8844                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8437                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9230                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8825                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8866                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9056                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8974                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8482                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8329                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8472                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8225                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7833                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7634                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               11821                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11810                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12062                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12027                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               20473                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12098                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12277                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12432                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12179                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12459                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11810                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11367                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11535                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11583                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11073                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11307                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8516                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8730                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8955                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8735                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8248                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8655                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8964                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8852                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8742                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8980                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8644                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8478                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8438                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8004                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7925                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7759                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          37                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2870000192000                       # Total gap between requests
+system.physmem.numWrRetry                          91                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2870821632000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9732                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  190291                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  188706                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 137329                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    139673                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16007                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     10455                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8865                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7050                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      5558                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4708                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3913                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3442                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        97                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       65                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       43                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        6                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 136162                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    135157                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     17197                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     10634                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8782                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7390                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      5915                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5070                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4238                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3688                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       106                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       63                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       39                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -185,164 +181,178 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2714                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6707                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7866                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9954                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8708                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7598                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7446                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      368                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      301                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      249                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      128                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        85925                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      251.537690                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     143.363316                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     306.826134                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          42893     49.92%     49.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18336     21.34%     71.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6281      7.31%     78.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3896      4.53%     83.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2533      2.95%     86.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1590      1.85%     87.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1050      1.22%     89.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          985      1.15%     90.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8361      9.73%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          85925                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6834                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.251244                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      562.918265                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6833     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2427                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4356                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6308                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7021                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9528                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9966                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8517                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8451                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     9511                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7906                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7646                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      714                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      416                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      256                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      247                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      300                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      267                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      236                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        84864                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      252.592006                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     143.738576                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     307.804055                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          42330     49.88%     49.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18020     21.23%     71.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6191      7.30%     78.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3740      4.41%     82.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2680      3.16%     85.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1634      1.93%     87.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          923      1.09%     88.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          980      1.15%     90.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8366      9.86%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          84864                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6753                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.364283                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      566.459907                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6751     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6834                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6834                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.164618                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.651361                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.320527                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5790     84.72%     84.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             323      4.73%     89.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              59      0.86%     90.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              46      0.67%     90.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             267      3.91%     94.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              35      0.51%     95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              21      0.31%     95.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              28      0.41%     96.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              23      0.34%     96.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               7      0.10%     96.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               4      0.06%     96.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              12      0.18%     96.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             155      2.27%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.04%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               5      0.07%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               6      0.09%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              12      0.18%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.03%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.03%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.01%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             6      0.09%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.01%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            11      0.16%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.03%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.01%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.04%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             2      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6834                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4674239132                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8422457882                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    999525000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       23382.30                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6753                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6753                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.231749                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.531627                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.015829                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5781     85.61%     85.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             288      4.26%     89.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              56      0.83%     90.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              54      0.80%     91.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             265      3.92%     95.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              16      0.24%     95.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              17      0.25%     95.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              13      0.19%     96.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              10      0.15%     96.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               4      0.06%     96.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               4      0.06%     96.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              11      0.16%     96.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             146      2.16%     98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.07%     98.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               7      0.10%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               6      0.09%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              12      0.18%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.03%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.01%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               4      0.06%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               4      0.06%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             3      0.04%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             6      0.09%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.01%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.03%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            11      0.16%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             4      0.06%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             3      0.04%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.01%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             4      0.06%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             3      0.04%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             4      0.06%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6753                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     9353740299                       # Total ticks spent queuing
+system.physmem.totMemAccLat               13072109049                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    991565000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       47166.55                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  42132.30                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.46                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.07                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.26                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.07                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  65916.55                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.42                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.05                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.22                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.04                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.74                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     166683                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     85101                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.38                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  61.75                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8397436.27                       # Average gap between requests
-system.physmem.pageHitRate                      74.55                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  335240640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  182919000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 827767200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                458784000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           187454198880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            84698340030                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1647701064750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1921658314500                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.568191                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2740964082488                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95835480000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     33201034512                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  314352360                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  171521625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 731484000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                434192400                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           187454198880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            83981561895                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1648329817500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1921417128660                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.484154                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2742009812705                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95835480000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     32151144795                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.09                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     165583                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     84490                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.50                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  61.83                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8468025.78                       # Average gap between requests
+system.physmem.pageHitRate                      74.66                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  311268300                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  165439230                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 749700000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                363599100                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           6175288080.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5556148530                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              353114880                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       11660360040                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        9231007680                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       675128481165                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             709697287665                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              247.210424                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           2857712170474                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      646078467                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2625372000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   2808102138000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  24039125004                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      9838978559                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  25570970970                       # Time in different power states
+system.physmem_1.actEnergy                  294667800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  156619650                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 666254820                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                349583400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           6182663760.000001                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5620280370                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              353139840                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       11082999060                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        9548118720                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       675230388855                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             709488226485                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              247.137601                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           2857213980946                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      650996744                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2628804000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   2808400306500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  24864927177                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      9973048810                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  24304579769                       # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
@@ -361,9 +371,9 @@ system.realview.nvmem.bw_inst_read::total           24                       # I
 system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
@@ -371,7 +381,7 @@ system.cf0.dma_write_full_pages                   540                       # Nu
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -401,61 +411,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                     7878                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                7878                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1506                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         6372                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples         7878                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           7878    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         7878                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         6484                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12295.265268                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11397.219739                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  5676.180841                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         5980     92.23%     92.23% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767          464      7.16%     99.38% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151           34      0.52%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535            1      0.02%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            2      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687            2      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         6484                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples   1125817500                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0     1125817500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total   1125817500                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5017     77.38%     77.38% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1467     22.62%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6484                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7878                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                     7793                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                7793                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1456                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         6337                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples         7793                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           7793    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         7793                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         6399                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12413.189561                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11268.612574                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 10437.446912                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535         6392     99.89%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071            4      0.06%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607            1      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         6399                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples   1181299500                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     1181299500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total   1181299500                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         4982     77.86%     77.86% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1417     22.14%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6399                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7793                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7878                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6484                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7793                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6399                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6484                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        14362                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6399                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        14192                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    25174501                       # DTB read hits
-system.cpu0.dtb.read_misses                      6776                       # DTB read misses
-system.cpu0.dtb.write_hits                   18763964                       # DTB write hits
-system.cpu0.dtb.write_misses                     1102                       # DTB write misses
+system.cpu0.dtb.read_hits                    25156364                       # DTB read hits
+system.cpu0.dtb.read_misses                      6669                       # DTB read misses
+system.cpu0.dtb.write_hits                   18748845                       # DTB write hits
+system.cpu0.dtb.write_misses                     1124                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3391                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    3378                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1765                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  1745                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                25181277                       # DTB read accesses
-system.cpu0.dtb.write_accesses               18765066                       # DTB write accesses
+system.cpu0.dtb.read_accesses                25163033                       # DTB read accesses
+system.cpu0.dtb.write_accesses               18749969                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         43938465                       # DTB hits
-system.cpu0.dtb.misses                           7878                       # DTB misses
-system.cpu0.dtb.accesses                     43946343                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                         43905209                       # DTB hits
+system.cpu0.dtb.misses                           7793                       # DTB misses
+system.cpu0.dtb.accesses                     43913002                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -485,7 +493,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.cpu0.itb.walker.walks                     3349                       # Table walker walks requested
 system.cpu0.itb.walker.walksShort                3349                       # Table walker walks initiated with short descriptors
 system.cpu0.itb.walker.walksShortTerminationLevel::Level1          299                       # Level at which table walker walks with short descriptors terminate
@@ -494,22 +502,23 @@ system.cpu0.itb.walker.walkWaitTime::samples         3349
 system.cpu0.itb.walker.walkWaitTime::0           3349    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::total         3349                       # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkCompletionTime::samples         2333                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12613.587655                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11778.875659                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  5637.639193                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191          386     16.55%     16.55% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383         1666     71.41%     87.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575          225      9.64%     97.60% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           26      1.11%     98.71% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959           26      1.11%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12610.587227                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11657.853110                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5955.666994                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          437     18.73%     18.73% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383         1604     68.75%     87.48% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575          228      9.77%     97.26% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           34      1.46%     98.71% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959           24      1.03%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151            2      0.09%     99.83% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::49152-57343            1      0.04%     99.87% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-106495            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::122880-131071            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::total         2333                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples   1125441500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     1125441500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total   1125441500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::samples   1180899500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     1180899500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total   1180899500                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walkPageSizes::4K         2034     87.18%     87.18% # Table walker page sizes translated
 system.cpu0.itb.walker.walkPageSizes::1M          299     12.82%    100.00% # Table walker page sizes translated
 system.cpu0.itb.walker.walkPageSizes::total         2333                       # Table walker page sizes translated
@@ -520,7 +529,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2333                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2333                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin::total         5682                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   119077538                       # ITB inst hits
+system.cpu0.itb.inst_hits                   119019454                       # ITB inst hits
 system.cpu0.itb.inst_misses                      3349                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -537,660 +546,663 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               119080887                       # ITB inst accesses
-system.cpu0.itb.hits                        119077538                       # DTB hits
+system.cpu0.itb.inst_accesses               119022803                       # ITB inst accesses
+system.cpu0.itb.hits                        119019454                       # DTB hits
 system.cpu0.itb.misses                           3349                       # DTB misses
-system.cpu0.itb.accesses                    119080887                       # DTB accesses
-system.cpu0.numPwrStateTransitions               3762                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         1881                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    1452265205.015417                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   23608911235.366570                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         1082     57.52%     57.52% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10          794     42.21%     99.73% # Distribution of time spent in the clock gated state
+system.cpu0.itb.accesses                    119022803                       # DTB accesses
+system.cpu0.numPwrStateTransitions               3740                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         1870                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    1460468935.028877                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   23678191319.145061                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         1076     57.54%     57.54% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10          789     42.19%     99.73% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.79% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.21%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 499963656512                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           1881                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   138289859366                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731710850634                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                      5740001420                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 499962822056                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           1870                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   139745754496                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731076908504                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                      5741645326                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1881                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  115412619                       # Number of instructions committed
-system.cpu0.committedOps                    139453859                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            123427491                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  9820                       # Number of float alu accesses
-system.cpu0.num_func_calls                   12678366                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     15706258                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   123427491                       # number of integer instructions
-system.cpu0.num_fp_insts                         9820                       # number of float instructions
-system.cpu0.num_int_register_reads          227200136                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          85767213                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                7560                       # number of times the floating registers were read
+system.cpu0.kern.inst.quiesce                    1870                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  115354991                       # Number of instructions committed
+system.cpu0.committedOps                    139381682                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            123361088                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  9690                       # Number of float alu accesses
+system.cpu0.num_func_calls                   12675511                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     15701045                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   123361088                       # number of integer instructions
+system.cpu0.num_fp_insts                         9690                       # number of float instructions
+system.cpu0.num_int_register_reads          227079516                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          85717450                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                7430                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           505219370                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           52317118                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     45075192                       # number of memory refs
-system.cpu0.num_load_insts                   25426401                       # Number of load instructions
-system.cpu0.num_store_insts                  19648791                       # Number of store instructions
-system.cpu0.num_idle_cycles              5463421701.266096                       # Number of idle cycles
-system.cpu0.num_busy_cycles              276579718.733904                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.048185                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.951815                       # Percentage of idle cycles
-system.cpu0.Branches                         29123439                       # Number of branches fetched
+system.cpu0.num_cc_register_reads           504946337                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           52296035                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     45041487                       # number of memory refs
+system.cpu0.num_load_insts                   25408167                       # Number of load instructions
+system.cpu0.num_store_insts                  19633320                       # Number of store instructions
+system.cpu0.num_idle_cycles              5462153817.006098                       # Number of idle cycles
+system.cpu0.num_busy_cycles              279491508.993903                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.048678                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.951322                       # Percentage of idle cycles
+system.cpu0.Branches                         29114863                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 98023875     68.44%     68.44% # Class of executed instruction
-system.cpu0.op_class::IntMult                  109907      0.08%     68.52% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              8209      0.01%     68.53% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 97984598     68.45%     68.45% # Class of executed instruction
+system.cpu0.op_class::IntMult                  109968      0.08%     68.53% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              8149      0.01%     68.53% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.53% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.53% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.53% # Class of executed instruction
-system.cpu0.op_class::MemRead                25426401     17.75%     86.28% # Class of executed instruction
-system.cpu0.op_class::MemWrite               19648791     13.72%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                25408167     17.75%     86.28% # Class of executed instruction
+system.cpu0.op_class::MemWrite               19633320     13.72%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 143219456                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements           693439                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          491.449824                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           43066582                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           693951                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            62.059975                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       1151827000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   491.449824                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.959863                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.959863                       # Average percentage of cache occupancy
+system.cpu0.op_class::total                 143146475                       # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements           692883                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          489.706194                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           43033783                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           693395                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            62.062436                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       1207347000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   489.706194                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.956457                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.956457                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          328                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           82                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          317                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           94                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88514427                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88514427                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     23911425                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       23911425                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     18032865                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18032865                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       319065                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       319065                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365782                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       365782                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       362736                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       362736                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     41944290                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41944290                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     42263355                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       42263355                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       397667                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       397667                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       324388                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       324388                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       127754                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       127754                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21573                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        21573                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19602                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        19602                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       722055                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        722055                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       849809                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       849809                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5269907000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5269907000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5597938000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   5597938000                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    327322000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    327322000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    460475500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    460475500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1158000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1158000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  10867845000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  10867845000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  10867845000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  10867845000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     24309092                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     24309092                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     18357253                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     18357253                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446819                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       446819                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       387355                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       387355                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       382338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       382338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     42666345                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     42666345                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     43113164                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     43113164                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016359                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.016359                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017671                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.017671                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.285919                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.285919                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055693                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055693                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051269                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051269                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016923                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.016923                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019711                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.019711                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13252.060141                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13252.060141                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17256.920725                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 17256.920725                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15172.762249                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15172.762249                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23491.250893                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23491.250893                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         88447658                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        88447658                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     23895020                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       23895020                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     18016527                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      18016527                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       319201                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       319201                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365698                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       365698                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       362461                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       362461                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     41911547                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        41911547                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     42230748                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       42230748                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       396353                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       396353                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       325830                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       325830                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       127542                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       127542                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21311                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21311                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19654                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        19654                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       722183                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        722183                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       849725                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       849725                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5544958500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5544958500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   6307912000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   6307912000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    337776000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    337776000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    461133500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    461133500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1598000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1598000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  11852870500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  11852870500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  11852870500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  11852870500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     24291373                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     24291373                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     18342357                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     18342357                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446743                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       446743                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       387009                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       387009                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       382115                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       382115                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     42633730                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     42633730                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     43080473                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     43080473                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016317                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.016317                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017764                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.017764                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.285493                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.285493                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055066                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055066                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051435                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051435                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016939                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.016939                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019724                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.019724                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13989.949616                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13989.949616                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19359.518767                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19359.518767                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15849.842804                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15849.842804                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23462.577592                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23462.577592                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15051.270333                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15051.270333                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12788.573668                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 12788.573668                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16412.558174                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16412.558174                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13949.066463                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13949.066463                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       693439                       # number of writebacks
-system.cpu0.dcache.writebacks::total           693439                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25271                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        25271                       # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15260                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15260                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        25271                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        25271                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        25271                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        25271                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       372396                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       372396                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       324388                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       324388                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       100689                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       100689                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6313                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6313                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19602                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        19602                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       696784                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       696784                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       797473                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       797473                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31786                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31786                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28463                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28463                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60249                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60249                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4503432000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4503432000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5273550000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5273550000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1615902000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1615902000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     94571500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     94571500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    440907500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    440907500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1124000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1124000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9776982000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9776982000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  11392884000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  11392884000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6628627500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6628627500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6628627500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6628627500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015319                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015319                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017671                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017671                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225346                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225346                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016298                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016298                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051269                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051269                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016331                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.016331                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018497                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018497                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12093.126672                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12093.126672                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16256.920725                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16256.920725                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16048.446206                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16048.446206                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14980.437193                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14980.437193                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22492.985410                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22492.985410                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       692883                       # number of writebacks
+system.cpu0.dcache.writebacks::total           692883                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25228                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        25228                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data            1                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15026                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15026                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        25229                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        25229                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        25229                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        25229                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       371125                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       371125                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       325829                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       325829                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       100399                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       100399                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6285                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6285                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19654                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        19654                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       696954                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       696954                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       797353                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       797353                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31790                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31790                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28464                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28464                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60254                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60254                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4765649500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4765649500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5981552000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5981552000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1664266000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1664266000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     99162500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     99162500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    441526500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    441526500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1551000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1551000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10747201500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  10747201500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  12411467500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  12411467500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6632422500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6632422500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6632422500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6632422500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015278                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015278                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017764                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017764                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224735                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224735                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016240                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016240                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051435                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051435                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016347                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.016347                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018508                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018508                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.089929                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.089929                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18357.948494                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18357.948494                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16576.519686                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16576.519686                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15777.645187                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15777.645187                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22464.968963                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22464.968963                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14031.582241                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14031.582241                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14286.231634                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14286.231634                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208539.215378                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208539.215378                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110020.539760                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110020.539760                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          1105141                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.449200                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          117971876                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1105653                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           106.698825                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      14058125000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.449200                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998924                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998924                       # Average percentage of cache occupancy
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15420.245095                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15420.245095                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15565.837841                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15565.837841                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208632.352941                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208632.352941                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110074.393401                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110074.393401                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          1103683                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.436898                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          117915250                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1104195                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           106.788430                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      14180312000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.436898                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998900                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998900                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          214                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        239260738                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       239260738                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    117971876                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      117971876                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    117971876                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       117971876                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    117971876                       # number of overall hits
-system.cpu0.icache.overall_hits::total      117971876                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1105662                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1105662                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1105662                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1105662                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1105662                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1105662                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11445416000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  11445416000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  11445416000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  11445416000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  11445416000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  11445416000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    119077538                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    119077538                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    119077538                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    119077538                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    119077538                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    119077538                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009285                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.009285                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009285                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.009285                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009285                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.009285                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10351.640917                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10351.640917                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10351.640917                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10351.640917                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.640917                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10351.640917                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        239143112                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       239143112                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst    117915250                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      117915250                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    117915250                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       117915250                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    117915250                       # number of overall hits
+system.cpu0.icache.overall_hits::total      117915250                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1104204                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1104204                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1104204                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1104204                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1104204                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1104204                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11911095000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  11911095000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  11911095000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  11911095000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  11911095000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  11911095000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    119019454                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    119019454                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    119019454                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    119019454                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    119019454                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    119019454                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009278                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.009278                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009278                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.009278                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009278                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.009278                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10787.042068                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10787.042068                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10787.042068                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10787.042068                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10787.042068                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10787.042068                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      1105141                       # number of writebacks
-system.cpu0.icache.writebacks::total          1105141                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1105662                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1105662                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1105662                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1105662                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1105662                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1105662                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      1103683                       # number of writebacks
+system.cpu0.icache.writebacks::total          1103683                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1104204                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1104204                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1104204                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1104204                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1104204                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1104204                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10892585000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  10892585000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10892585000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  10892585000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10892585000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  10892585000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    811416500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    811416500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    811416500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    811416500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009285                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009285                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009285                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.009285                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009285                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.009285                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9851.640917                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9851.640917                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9851.640917                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9851.640917                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9851.640917                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9851.640917                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1836809                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1836835                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit           22                       # number of redundant prefetches already in prefetch queue
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11358993000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11358993000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11358993000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11358993000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11358993000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11358993000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    863305500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    863305500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    863305500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    863305500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009278                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009278                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009278                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.009278                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009278                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.009278                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10287.042068                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10287.042068                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10287.042068                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10287.042068                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10287.042068                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10287.042068                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1852661                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1852734                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit           64                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       235109                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements          260353                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       15640.705301                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           1686155                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          275976                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.109789                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       236762                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.tags.replacements          259898                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15638.452129                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           1682248                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          275540                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            6.105277                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14471.492082                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.272651                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.132938                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1167.807630                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.883270                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000078                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14455.048208                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.347817                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.124083                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1181.932022                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.882266                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000082                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000008                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.071277                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.954633                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022          311                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15308                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.072139                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.954495                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          340                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15293                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           29                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          131                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          144                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           30                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          149                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          154                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          815                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         6065                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6346                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1905                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.018982                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000244                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.934326                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        61385527                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       61385527                       # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         9987                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4390                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         14377                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks       478787                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total       478787                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      1291925                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      1291925                       # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       226376                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       226376                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1043295                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1043295                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       377938                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       377938                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         9987                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4390                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1043295                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       604314                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1661986                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         9987                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4390                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1043295                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       604314                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1661986                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          261                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          141                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total          402                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55107                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        55107                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19598                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        19598                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        42905                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        42905                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        62367                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total        62367                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101460                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       101460                       # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          261                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          141                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        62367                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       144365                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       207134                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          261                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          141                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        62367                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       144365                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       207134                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      6301500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3315500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total      9617000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data     31218000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total     31218000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data      9500500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total      9500500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1071498                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1071498                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2039769000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   2039769000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2950382000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2950382000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3031048000                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3031048000                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      6301500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3315500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2950382000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   5070817000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   8030816000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      6301500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3315500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2950382000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   5070817000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   8030816000                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        10248                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4531                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total        14779                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks       478787                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total       478787                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      1291925                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      1291925                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55107                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        55107                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19598                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        19598                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269281                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       269281                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1105662                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      1105662                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       479398                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total       479398                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        10248                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4531                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      1105662                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       748679                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      1869120                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        10248                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4531                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1105662                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       748679                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      1869120                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.025468                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.031119                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.027201                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          173                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          821                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         6084                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6238                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1977                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.020752                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.933411                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        61320295                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       61320295                       # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         9508                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4316                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total         13824                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks       476285                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total       476285                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      1292383                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      1292383                       # number of WritebackClean hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       227392                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       227392                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1042059                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      1042059                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       376265                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total       376265                       # number of ReadSharedReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         9508                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4316                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1042059                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data       603657                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        1659540                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         9508                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4316                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1042059                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       603657                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       1659540                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          306                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          159                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total          465                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55222                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        55222                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19651                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        19651                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43215                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total        43215                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        62145                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total        62145                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101544                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       101544                       # number of ReadSharedReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          306                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          159                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        62145                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       144759                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       207369                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          306                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          159                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        62145                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       144759                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       207369                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      8941000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3729500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total     12670500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data     32046500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total     32046500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data      9591500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total      9591500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1480500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1480500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2734835500                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   2734835500                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3426232500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3426232500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3359763500                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3359763500                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      8941000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3729500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3426232500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   6094599000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total   9533502000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      8941000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3729500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3426232500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   6094599000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total   9533502000                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         9814                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4475                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        14289                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks       476285                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total       476285                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      1292383                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      1292383                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55222                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        55222                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19651                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        19651                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       270607                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       270607                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1104204                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1104204                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       477809                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       477809                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         9814                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4475                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1104204                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       748416                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      1866909                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         9814                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4475                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1104204                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       748416                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      1866909                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.031180                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.035531                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.032543                       # miss rate for ReadReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.159332                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.159332                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.056407                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.056407                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.211640                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.211640                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.025468                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.031119                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.056407                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.192826                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.110819                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.025468                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.031119                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.056407                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.192826                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.110819                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24143.678161                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23514.184397                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 23922.885572                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   566.497904                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   566.497904                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   484.768854                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   484.768854                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 267874.500000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 267874.500000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47541.521967                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47541.521967                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 47306.780830                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 47306.780830                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29874.315001                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29874.315001                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24143.678161                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23514.184397                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 47306.780830                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35124.974890                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 38771.114351                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24143.678161                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23514.184397                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 47306.780830                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35124.974890                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 38771.114351                       # average overall miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.159697                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.159697                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.056280                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.056280                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.212520                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.212520                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.031180                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.035531                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.056280                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.193421                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.111076                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.031180                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.035531                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.056280                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.193421                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.111076                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29218.954248                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23455.974843                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27248.387097                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   580.321249                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   580.321249                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   488.092209                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   488.092209                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       493500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       493500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63284.403564                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63284.403564                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 55132.874728                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 55132.874728                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33086.775191                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33086.775191                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29218.954248                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23455.974843                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 55132.874728                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42101.693159                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 45973.612256                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29218.954248                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23455.974843                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 55132.874728                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42101.693159                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 45973.612256                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches           10615                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks       227687                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          227687                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1191                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         1191                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           30                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           30                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1221                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         1221                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1221                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         1221                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          261                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          141                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          402                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       259983                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       259983                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55107                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55107                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19598                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19598                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41714                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        41714                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        62367                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        62367                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       101430                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       101430                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          261                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          141                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        62367                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       143144                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       205913                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          261                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          141                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        62367                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       143144                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       259983                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       465896                       # number of overall MSHR misses
+system.cpu0.l2cache.unused_prefetches           10606                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks       227429                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          227429                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1561                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         1561                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           33                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           33                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1594                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         1594                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1594                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         1594                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          306                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          159                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total          465                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264666                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       264666                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55222                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55222                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19651                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19651                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41654                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        41654                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        62145                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        62145                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       101511                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       101511                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          306                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          159                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        62145                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       143165                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       205775                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          306                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          159                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        62145                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       143165                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       264666                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total       470441                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31786                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40808                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28463                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28463                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31790                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40812                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28464                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28464                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60249                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69271                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      4735500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2469500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      7205000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13869294782                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13869294782                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    942789000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    942789000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    294087500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    294087500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       867498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       867498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1672104500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1672104500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2576180000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2576180000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2417355500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2417355500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      4735500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2469500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2576180000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4089460000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   6672845000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      4735500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2469500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2576180000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4089460000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13869294782                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  20542139782                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    743751500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6373927500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7117679000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    743751500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6373927500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7117679000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.025468                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.031119                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.027201                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60254                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69276                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      7105000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2775500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      9880500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  16752910842                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  16752910842                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    946229000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    946229000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    294413000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    294413000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1198500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1198500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2205065500                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2205065500                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3053362500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3053362500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2745598500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2745598500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      7105000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2775500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3053362500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4950664000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   8013907000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      7105000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2775500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3053362500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4950664000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  16752910842                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  24766817842                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    795640500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6377687500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7173328000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    795640500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6377687500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7173328000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.031180                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.035531                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.032543                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
@@ -1199,118 +1211,118 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.154909                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.154909                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.056407                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.056407                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.211578                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.211578                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.025468                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.031119                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.056407                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.191195                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.110166                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.025468                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.031119                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.056407                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.191195                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.153928                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.153928                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.056280                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.056280                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.212451                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.212451                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.031180                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.035531                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.056280                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.191291                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.110222                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.031180                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.035531                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.056280                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.191291                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.249260                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17922.885572                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53346.929538                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17108.334694                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17108.334694                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15005.995510                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15005.995510                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 216874.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 216874.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40084.971472                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40084.971472                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41306.780830                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41306.780830                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23832.746722                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23832.746722                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41306.780830                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28568.853742                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32406.137544                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41306.780830                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28568.853742                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44091.685230                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200526.253697                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174418.716918                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105793.083703                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102751.209020                       # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests      3740310                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1886004                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        27868                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       209163                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       207471                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         1692                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq         61471                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1694410                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        28463                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        28463                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       706729                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      1319793                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict        79890                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       307615                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        87684                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        41751                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       111919                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           49                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           79                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       288494                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       284839                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1105662                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       565382                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3277                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3334509                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2561453                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10930                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        24498                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          5931390                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    141527480                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     96553100                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        18124                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        40992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         238139696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     885320                       # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic             18675332                       # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples      2797680                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.089870                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.288103                       # Request fanout histogram
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.251989                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21248.387097                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63298.311238                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17135.000543                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17135.000543                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14982.087426                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14982.087426                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       399500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       399500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52937.665050                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52937.665050                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49132.874728                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49132.874728                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27047.300293                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27047.300293                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49132.874728                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34580.127825                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38944.998178                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49132.874728                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34580.127825                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52645.959519                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200619.298522                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175765.167108                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105846.707273                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103547.087014                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests      3736636                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1884055                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        27898                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       214108                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       212409                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         1699                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq         61364                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1691356                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28464                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28464                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       703950                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      1320281                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict        79590                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       311154                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        87625                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        41858                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       112323                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           88                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       289865                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       286282                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1104204                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       563680                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3258                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3330135                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2561187                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10874                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        23944                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          5926140                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    141340856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     96515744                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17900                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        39256                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         237913756                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     888922                       # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic             18673228                       # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples      2798771                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.091578                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.290526                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           2547944     91.07%     91.07% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            248044      8.87%     99.94% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              1692      0.06%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           2544165     90.90%     90.90% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            252907      9.04%     99.94% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              1699      0.06%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       2797680                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    3721587498                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       2798771                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    3717731500                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    113922479                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    114379544                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1667515000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1665328000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1206437474                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1206139485                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu0.toL2Bus.respLayer2.occupancy      6399000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     14255489                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     14135489                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1340,62 +1352,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                     3379                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                3379                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          683                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         2696                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples         3379                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           3379    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         3379                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         2609                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12498.275201                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11540.409783                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  5547.212388                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191          616     23.61%     23.61% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1660     63.63%     87.24% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575          255      9.77%     97.01% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767           67      2.57%     99.58% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959            5      0.19%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151            3      0.11%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-57343            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-106495            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         2609                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  -2073200828                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    -2073200828    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  -2073200828                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1934     74.13%     74.13% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          675     25.87%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2609                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3379                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                     3333                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                3333                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          662                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         2671                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples         3333                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           3333    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         3333                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         2563                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11950.253609                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 10994.949142                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  5354.487249                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-4095            3      0.12%      0.12% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::4096-8191          723     28.21%     28.33% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-12287         1059     41.32%     69.64% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::12288-16383          482     18.81%     88.45% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-20479           76      2.97%     91.42% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::20480-24575          147      5.74%     97.15% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-28671           46      1.79%     98.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::28672-32767           15      0.59%     99.53% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-36863            4      0.16%     99.69% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::36864-40959            3      0.12%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-45055            2      0.08%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-53247            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::53248-57343            2      0.08%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         2563                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -1936423828                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1936423828    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -1936423828                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1909     74.48%     74.48% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          654     25.52%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2563                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3333                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3379                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2609                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3333                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2563                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2609                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total         5988                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2563                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         5896                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3943912                       # DTB read hits
-system.cpu1.dtb.read_misses                      2863                       # DTB read misses
-system.cpu1.dtb.write_hits                    3421052                       # DTB write hits
-system.cpu1.dtb.write_misses                      516                       # DTB write misses
+system.cpu1.dtb.read_hits                     3943012                       # DTB read hits
+system.cpu1.dtb.read_misses                      2827                       # DTB read misses
+system.cpu1.dtb.write_hits                    3420749                       # DTB write hits
+system.cpu1.dtb.write_misses                      506                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1981                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1972                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   312                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   323                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3946775                       # DTB read accesses
-system.cpu1.dtb.write_accesses                3421568                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 3945839                       # DTB read accesses
+system.cpu1.dtb.write_accesses                3421255                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          7364964                       # DTB hits
-system.cpu1.dtb.misses                           3379                       # DTB misses
-system.cpu1.dtb.accesses                      7368343                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                          7363761                       # DTB hits
+system.cpu1.dtb.misses                           3333                       # DTB misses
+system.cpu1.dtb.accesses                      7367094                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1425,7 +1442,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.cpu1.itb.walker.walks                     1746                       # Table walker walks requested
 system.cpu1.itb.walker.walksShort                1746                       # Table walker walks initiated with short descriptors
 system.cpu1.itb.walker.walksShortTerminationLevel::Level1          168                       # Level at which table walker walks with short descriptors terminate
@@ -1434,24 +1451,24 @@ system.cpu1.itb.walker.walkWaitTime::samples         1746
 system.cpu1.itb.walker.walkWaitTime::0           1746    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walkWaitTime::total         1746                       # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walkCompletionTime::samples         1107                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 13079.042457                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 12148.751119                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5740.258970                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          165     14.91%     14.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          593     53.57%     68.47% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          181     16.35%     84.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479           52      4.70%     89.52% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575           63      5.69%     95.21% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           26      2.35%     97.56% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767           17      1.54%     99.10% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863            3      0.27%     99.37% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959            1      0.09%     99.46% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 12715.898826                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11637.572785                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  6041.889650                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          210     18.97%     18.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          573     51.76%     70.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          161     14.54%     85.28% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           52      4.70%     89.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575           52      4.70%     94.67% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           26      2.35%     97.02% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767           21      1.90%     98.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            3      0.27%     99.19% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            3      0.27%     99.46% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::40960-45055            4      0.36%     99.82% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::49152-53247            2      0.18%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::total         1107                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  -2073744828                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    -2073744828    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  -2073744828                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::samples  -1937292828                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1937292828    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1937292828                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walkPageSizes::4K          939     84.82%     84.82% # Table walker page sizes translated
 system.cpu1.itb.walker.walkPageSizes::1M          168     15.18%    100.00% # Table walker page sizes translated
 system.cpu1.itb.walker.walkPageSizes::total         1107                       # Table walker page sizes translated
@@ -1462,7 +1479,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1107                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1107                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin::total         2853                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    16566340                       # ITB inst hits
+system.cpu1.itb.inst_hits                    16565425                       # ITB inst hits
 system.cpu1.itb.inst_misses                      1746                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
@@ -1479,56 +1496,56 @@ system.cpu1.itb.domain_faults                       0                       # Nu
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                16568086                       # ITB inst accesses
-system.cpu1.itb.hits                         16566340                       # DTB hits
+system.cpu1.itb.inst_accesses                16567171                       # ITB inst accesses
+system.cpu1.itb.hits                         16565425                       # DTB hits
 system.cpu1.itb.misses                           1746                       # DTB misses
-system.cpu1.itb.accesses                     16568086                       # DTB accesses
-system.cpu1.numPwrStateTransitions               5497                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         2749                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    1034540641.602037                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   25769735768.471432                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         1960     71.30%     71.30% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10          783     28.48%     99.78% # Distribution of time spent in the clock gated state
+system.cpu1.itb.accesses                     16567171                       # DTB accesses
+system.cpu1.numPwrStateTransitions               5507                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         2754                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    1032876592.840595                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   25746480816.391750                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         1963     71.28%     71.28% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10          785     28.50%     99.78% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::5e+10-1e+11            2      0.07%     99.85% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.04%     99.93% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11            1      0.04%     99.96% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.04%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 929980464320                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           2749                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON    26048486236                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 2843952223764                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                      5739069639                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value 929980503556                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           2754                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON    26280526317                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844542136683                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                      5740713090                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2749                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   16210815                       # Number of instructions committed
-system.cpu1.committedOps                     19752329                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             17813732                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  1857                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1029438                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1815045                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    17813732                       # number of integer instructions
-system.cpu1.num_fp_insts                         1857                       # number of float instructions
-system.cpu1.num_int_register_reads           32326512                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          12493939                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                1341                       # number of times the floating registers were read
+system.cpu1.kern.inst.quiesce                    2754                       # number of quiesce instructions executed
+system.cpu1.committedInsts                   16209756                       # Number of instructions committed
+system.cpu1.committedOps                     19749987                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             17811459                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
+system.cpu1.num_func_calls                    1029227                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1814790                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    17811459                       # number of integer instructions
+system.cpu1.num_fp_insts                         1792                       # number of float instructions
+system.cpu1.num_int_register_reads           32322640                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          12491718                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            72207765                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            6423893                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      7598514                       # number of memory refs
-system.cpu1.num_load_insts                    4055507                       # Number of load instructions
-system.cpu1.num_store_insts                   3543007                       # Number of store instructions
-system.cpu1.num_idle_cycles              5686981123.489185                       # Number of idle cycles
-system.cpu1.num_busy_cycles              52088515.510815                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.009076                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.990924                       # Percentage of idle cycles
-system.cpu1.Branches                          2922923                       # Number of branches fetched
+system.cpu1.num_cc_register_reads            72198073                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            6423445                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      7597281                       # number of memory refs
+system.cpu1.num_load_insts                    4054552                       # Number of load instructions
+system.cpu1.num_store_insts                   3542729                       # Number of store instructions
+system.cpu1.num_idle_cycles              5688160571.384175                       # Number of idle cycles
+system.cpu1.num_busy_cycles              52552518.615825                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.009154                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.990846                       # Percentage of idle cycles
+system.cpu1.Branches                          2922489                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 12474914     62.05%     62.05% # Class of executed instruction
-system.cpu1.op_class::IntMult                   26468      0.13%     62.19% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 12473914     62.06%     62.06% # Class of executed instruction
+system.cpu1.op_class::IntMult                   26414      0.13%     62.19% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     62.19% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                      0      0.00%     62.19% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     62.19% # Class of executed instruction
@@ -1552,583 +1569,584 @@ system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.19% # Cl
 system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.19% # Class of executed instruction
 system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.19% # Class of executed instruction
 system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.19% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              3329      0.02%     62.20% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              3315      0.02%     62.20% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.20% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.20% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.20% # Class of executed instruction
-system.cpu1.op_class::MemRead                 4055507     20.17%     82.38% # Class of executed instruction
-system.cpu1.op_class::MemWrite                3543007     17.62%    100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead                 4054552     20.17%     82.38% # Class of executed instruction
+system.cpu1.op_class::MemWrite                3542729     17.62%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  20103291                       # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements           186972                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          469.131643                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            7097155                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           187306                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            37.890698                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     127531940000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   469.131643                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.916273                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.916273                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          334                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          255                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           79                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.652344                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         14948788                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        14948788                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3631994                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3631994                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      3232351                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       3232351                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48894                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        48894                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78959                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        78959                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70892                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        70892                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      6864345                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         6864345                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      6913239                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        6913239                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       133677                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       133677                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        91948                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        91948                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30343                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        30343                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16973                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        16973                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23209                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23209                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       225625                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        225625                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       255968                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       255968                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2021367000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2021367000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2373794500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   2373794500                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    317489000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    317489000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    544203500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    544203500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1998500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1998500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   4395161500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   4395161500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   4395161500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   4395161500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3765671                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3765671                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      3324299                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      3324299                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79237                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        79237                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        95932                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        95932                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94101                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        94101                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      7089970                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      7089970                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      7169207                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      7169207                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035499                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.035499                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027659                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.027659                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.382940                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.382940                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.176927                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.176927                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.246639                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.246639                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031823                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.031823                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035704                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.035704                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15121.277407                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15121.277407                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25816.706182                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 25816.706182                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18705.532316                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18705.532316                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23447.951226                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23447.951226                       # average StoreCondReq miss latency
+system.cpu1.op_class::total                  20100990                       # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements           186832                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          467.596388                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            7094042                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           187196                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            37.896333                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     105561729000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   467.596388                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.913274                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.913274                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          364                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          276                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           88                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.710938                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         14946466                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        14946466                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3631076                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3631076                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      3232073                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       3232073                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48864                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        48864                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78973                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        78973                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70916                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        70916                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      6863149                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         6863149                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      6912013                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        6912013                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       133685                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       133685                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        91868                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        91868                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30333                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        30333                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17012                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        17012                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23235                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23235                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       225553                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        225553                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       255886                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       255886                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2037941500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2037941500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2527681500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   2527681500                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    319638500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    319638500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    545121500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    545121500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1812500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1812500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   4565623000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   4565623000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   4565623000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   4565623000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3764761                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3764761                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      3323941                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      3323941                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79197                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        79197                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        95985                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        95985                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94151                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        94151                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      7088702                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      7088702                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      7167899                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      7167899                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035510                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.035510                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027638                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.027638                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.383007                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.383007                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.177236                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.177236                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.246784                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.246784                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031819                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.031819                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035699                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.035699                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.354266                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.354266                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27514.275918                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 27514.275918                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18789.001881                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18789.001881                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23461.222294                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23461.222294                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19479.940166                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19479.940166                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17170.745953                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17170.745953                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20241.907667                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20241.907667                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17842.410292                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 17842.410292                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks       186972                       # number of writebacks
-system.cpu1.dcache.writebacks::total           186972                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          283                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          283                       # number of ReadReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12048                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12048                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          283                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          283                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          283                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          283                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       133394                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       133394                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91948                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        91948                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29641                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        29641                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4925                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4925                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23209                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23209                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       225342                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       225342                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       254983                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       254983                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3099                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3099                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2450                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2450                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5549                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5549                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1881488500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1881488500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2281846500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2281846500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    500338500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    500338500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     85063000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     85063000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    521039500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    521039500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1953500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1953500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4163335000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4163335000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4663673500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4663673500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    443787500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    443787500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    443787500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    443787500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035424                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035424                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027659                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027659                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.374080                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.374080                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051338                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051338                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.246639                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.246639                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.writebacks::writebacks       186832                       # number of writebacks
+system.cpu1.dcache.writebacks::total           186832                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          254                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          254                       # number of ReadReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12014                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12014                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          254                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          254                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          254                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          254                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       133431                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       133431                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91868                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        91868                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29599                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        29599                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4998                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4998                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23235                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23235                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       225299                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       225299                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       254898                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       254898                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3096                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3096                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2451                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2451                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5547                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5547                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1895035500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1895035500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2435813500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2435813500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    504348000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    504348000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87440500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87440500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    521927500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    521927500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1771500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1771500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4330849000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4330849000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4835197000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4835197000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    443722000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    443722000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    443722000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    443722000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035442                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035442                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027638                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027638                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.373739                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.373739                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.052071                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.052071                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.246784                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.246784                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031783                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::total     0.031783                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035566                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.035566                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14104.746091                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14104.746091                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24816.706182                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24816.706182                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16879.946695                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16879.946695                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17271.675127                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17271.675127                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22449.890129                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22449.890129                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035561                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035561                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14202.363019                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14202.363019                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26514.275918                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26514.275918                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17039.359438                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17039.359438                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17495.098039                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17495.098039                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22462.986873                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22462.986873                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18475.628156                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18475.628156                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18290.135029                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18290.135029                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143203.452727                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143203.452727                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79976.121824                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79976.121824                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements           505656                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.477037                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           16060167                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           506168                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            31.728926                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      85274966000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.477037                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973588                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.973588                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19222.672981                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19222.672981                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18969.144521                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18969.144521                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143321.059432                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143321.059432                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79993.149450                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79993.149450                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements           505764                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          498.454577                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           16059144                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           506276                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            31.720137                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      85411536000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.454577                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973544                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.973544                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          388                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3          121                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::4            3                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         33638838                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        33638838                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst     16060167                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       16060167                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     16060167                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        16060167                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     16060167                       # number of overall hits
-system.cpu1.icache.overall_hits::total       16060167                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       506168                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       506168                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       506168                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        506168                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       506168                       # number of overall misses
-system.cpu1.icache.overall_misses::total       506168                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4710776500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4710776500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4710776500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4710776500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4710776500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4710776500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     16566335                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     16566335                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     16566335                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     16566335                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     16566335                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     16566335                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030554                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.030554                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030554                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.030554                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030554                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.030554                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9306.744994                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9306.744994                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9306.744994                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9306.744994                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9306.744994                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9306.744994                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         33637116                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        33637116                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst     16059144                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       16059144                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     16059144                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        16059144                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     16059144                       # number of overall hits
+system.cpu1.icache.overall_hits::total       16059144                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       506276                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       506276                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       506276                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        506276                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       506276                       # number of overall misses
+system.cpu1.icache.overall_misses::total       506276                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4773110000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4773110000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4773110000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4773110000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4773110000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4773110000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     16565420                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     16565420                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     16565420                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     16565420                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     16565420                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     16565420                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030562                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.030562                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030562                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.030562                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030562                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.030562                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9427.881235                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9427.881235                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9427.881235                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9427.881235                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9427.881235                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9427.881235                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks       505656                       # number of writebacks
-system.cpu1.icache.writebacks::total           505656                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       506168                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       506168                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       506168                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       506168                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       506168                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       506168                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks       505764                       # number of writebacks
+system.cpu1.icache.writebacks::total           505764                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       506276                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       506276                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       506276                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       506276                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       506276                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       506276                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4457692500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4457692500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4457692500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4457692500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4457692500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4457692500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15627500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15627500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15627500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     15627500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.030554                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.030554                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.030554                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.030554                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.030554                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.030554                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8806.744994                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8806.744994                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8806.744994                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8806.744994                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8806.744994                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8806.744994                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88290.960452                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88290.960452                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       198543                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       198543                       # number of prefetch candidates identified
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4519972000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4519972000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4519972000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4519972000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4519972000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4519972000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     17010500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     17010500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     17010500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     17010500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.030562                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.030562                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.030562                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.030562                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.030562                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.030562                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8927.881235                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8927.881235                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8927.881235                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8927.881235                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8927.881235                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8927.881235                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96104.519774                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96104.519774                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       197759                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       197759                       # number of prefetch candidates identified
 system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        58537                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements           43670                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       14604.323800                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs            603874                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           58010                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           10.409826                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        59073                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.tags.replacements           42341                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       14550.545082                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs            605184                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           56718                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           10.670052                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14211.070638                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.100990                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.057181                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   388.094990                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.867375                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000189                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000126                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.023687                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.891377                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          327                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14000                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           23                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          304                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14134.079332                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.459040                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.079959                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   410.926752                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.862676                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000211                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000127                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.025081                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.888095                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          333                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           17                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14027                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           35                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          296                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          895                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2815                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        10290                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.019958                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.000793                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.854492                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        24332814                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       24332814                       # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3764                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1983                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total          5747                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks       114262                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total       114262                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks       567214                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total       567214                       # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27479                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        27479                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       484841                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       484841                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        98007                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total        98007                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3764                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1983                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       484841                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       125486                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         616074                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3764                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1983                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       484841                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       125486                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        616074                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          441                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          340                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          781                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29645                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29645                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23207                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        23207                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2799                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        10333                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.020325                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001038                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.856140                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        24327160                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       24327160                       # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3447                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1877                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total          5324                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks       114448                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total       114448                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks       567034                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total       567034                       # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27676                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        27676                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       485156                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       485156                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        98414                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total        98414                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3447                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1877                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       485156                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       126090                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         616570                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3447                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1877                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       485156                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       126090                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        616570                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          422                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          327                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          749                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29541                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        29541                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23233                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        23233                       # number of SCUpgradeReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            2                       # number of SCUpgradeFailReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34824                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        34824                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        21327                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        21327                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        69953                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        69953                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          441                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          340                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        21327                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       104777                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       126885                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          441                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          340                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        21327                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       104777                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       126885                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      9030000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      6837500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     15867500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     14606500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total     14606500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     16450500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     16450500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1885500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1885500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1331294000                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1331294000                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    775115000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total    775115000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1573819000                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1573819000                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      9030000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      6837500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    775115000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   2905113000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   3696095500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      9030000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      6837500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    775115000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   2905113000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   3696095500                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         4205                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2323                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total         6528                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks       114262                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total       114262                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks       567214                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total       567214                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29645                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        29645                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23207                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23207                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34651                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        34651                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        21120                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        21120                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        69614                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        69614                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          422                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          327                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        21120                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data       104265                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       126134                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          422                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          327                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        21120                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       104265                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       126134                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      8582000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      6568500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     15150500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     13749500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total     13749500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     16999500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     16999500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1709500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1709500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1487134000                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1487134000                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    835278500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    835278500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1591067500                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1591067500                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      8582000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      6568500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst    835278500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3078201500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   3928630500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      8582000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      6568500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst    835278500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3078201500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   3928630500                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3869                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2204                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total         6073                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks       114448                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total       114448                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks       567034                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total       567034                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29541                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        29541                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23233                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23233                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62303                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        62303                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       506168                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       506168                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       167960                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       167960                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         4205                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2323                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       506168                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       230263                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total       742959                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         4205                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2323                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       506168                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       230263                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       742959                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.104875                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.146362                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.119638                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62327                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        62327                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       506276                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       506276                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       168028                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       168028                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3869                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2204                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       506276                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       230355                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total       742704                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3869                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2204                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       506276                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       230355                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total       742704                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.109072                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.148367                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.123333                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.558946                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.558946                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.042134                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.042134                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.416486                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.416486                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.104875                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.146362                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.042134                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.455032                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.170783                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.104875                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.146362                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.042134                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.455032                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.170783                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20476.190476                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20110.294118                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20316.901408                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   492.713780                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   492.713780                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   708.859396                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   708.859396                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       942750                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       942750                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38229.209740                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38229.209740                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36344.305341                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36344.305341                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22498.234529                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22498.234529                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20476.190476                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20110.294118                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36344.305341                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27726.628936                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 29129.491272                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20476.190476                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20110.294118                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36344.305341                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27726.628936                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 29129.491272                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.555955                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.555955                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.041716                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.041716                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.414300                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.414300                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.109072                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.148367                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.041716                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.452627                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.169831                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.109072                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.148367                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.041716                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.452627                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.169831                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20336.492891                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20087.155963                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20227.636849                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   465.437866                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   465.437866                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   731.696294                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   731.696294                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       854750                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       854750                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42917.491559                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42917.491559                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39549.171402                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39549.171402                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22855.567846                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22855.567846                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20336.492891                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20087.155963                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39549.171402                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29522.864816                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 31146.483105                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20336.492891                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20087.155963                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39549.171402                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29522.864816                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 31146.483105                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches             787                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks        33133                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           33133                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           84                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total           84                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data           84                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total           84                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data           84                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total           84                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          441                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          340                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          781                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        25691                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        25691                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29645                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29645                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23207                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23207                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.unused_prefetches             833                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks        32020                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           32020                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           87                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total           87                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data           87                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total           87                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data           87                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total           87                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          422                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          327                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total          749                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        25249                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        25249                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29541                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29541                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23233                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23233                       # number of SCUpgradeReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34740                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        34740                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        21327                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        21327                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        69953                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        69953                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          441                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          340                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        21327                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       104693                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       126801                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          441                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          340                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        21327                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       104693                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        25691                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       152492                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34564                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        34564                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        21120                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        21120                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        69614                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        69614                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          422                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          327                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        21120                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data       104178                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       126047                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          422                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          327                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        21120                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data       104178                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        25249                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       151296                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3099                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3276                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2450                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2450                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3096                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3273                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2451                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2451                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5549                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5726                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6384000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4797500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     11181500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    812147618                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    812147618                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    453420500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    453420500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    346968500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    346968500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1615500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1615500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1114497500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1114497500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    647153000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    647153000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1154101000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1154101000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6384000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4797500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    647153000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2268598500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   2926933000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6384000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4797500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    647153000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2268598500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    812147618                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   3739080618                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14300000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    418649000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    432949000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14300000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    418649000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    432949000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.104875                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.146362                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.119638                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5547                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5724                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6050000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4606500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     10656500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    879904235                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    879904235                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    451017000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    451017000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    347632000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    347632000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1463500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1463500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1270463000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1270463000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    708558500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    708558500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1173383500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1173383500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6050000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4606500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    708558500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2443846500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3163061500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6050000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4606500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    708558500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2443846500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    879904235                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4042965735                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15683000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    418607000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    434290000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     15683000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    418607000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    434290000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.109072                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.148367                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.123333                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
@@ -2137,118 +2155,118 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.557598                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.557598                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.042134                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042134                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.416486                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.416486                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.104875                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.146362                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.042134                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.454667                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.170670                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.104875                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.146362                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.042134                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.454667                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.554559                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.554559                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.041716                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.041716                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.414300                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.414300                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.109072                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.148367                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.041716                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.452250                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.169714                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.109072                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.148367                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.041716                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.452250                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.205250                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14316.901408                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31612.145031                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15295.007590                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15295.007590                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14951.027707                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14951.027707                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       807750                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       807750                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32081.102476                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32081.102476                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30344.305341                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30344.305341                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16498.234529                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16498.234529                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30344.305341                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21669.056193                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23082.885782                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30344.305341                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21669.056193                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24519.847717                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135091.642465                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132157.814408                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75445.846098                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75611.072302                       # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests      1488311                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests       751924                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        11152                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       112911                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       104591                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         8320                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq         12675                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       724258                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         2450                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         2450                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       148574                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean       578366                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict        28228                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        30717                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        71065                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40939                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        85439                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           36                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           79                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        69452                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        66978                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       506168                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       262948                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq          236                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1518346                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       839098                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5647                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        10280                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2373371                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     64757444                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29422876                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         9292                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        16820                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          94206432                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     332481                       # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic              4905948                       # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples      1059226                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.131024                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.359953                       # Request fanout histogram
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.203710                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14227.636849                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 34849.072637                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15267.492637                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15267.492637                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14962.854560                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.854560                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       731750                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       731750                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36756.827913                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36756.827913                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33549.171402                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33549.171402                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16855.567846                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16855.567846                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33549.171402                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23458.374129                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25094.302125                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33549.171402                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23458.374129                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26722.224877                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135208.979328                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132688.664833                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75465.476834                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75871.767994                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests      1488382                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests       751796                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        11114                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       112776                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       104479                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         8297                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq         12601                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       724485                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2451                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2451                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       147576                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       578148                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        27257                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        30156                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        71390                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40982                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        85466                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           49                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           88                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        69531                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        66980                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       506276                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       263615                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq          248                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1518670                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       839199                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5528                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9873                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2373270                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     64771268                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29426964                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         8816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        15476                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          94222524                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     331491                       # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic              4839132                       # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples      1057684                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.131012                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.359912                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0            928762     87.68%     87.68% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            122144     11.53%     99.21% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              8320      0.79%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0            927412     87.68%     87.68% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            121975     11.53%     99.22% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              8297      0.78%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1059226                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1442372000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1057684                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1442349000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     79594348                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     79817806                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    759429000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    759591000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    376190500                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    376283000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu1.toL2Bus.respLayer2.occupancy      3324000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy      6075998                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy      6005497                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                31015                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31015                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
@@ -2299,27 +2317,27 @@ system.iobus.pkt_size_system.bridge.master::total       162796
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2484068                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             48721500                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             48719500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               321000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               321500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                32000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                16500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                94000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                94500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               622500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               610000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               23000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               48500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
@@ -2333,32 +2351,32 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6160000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6166000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            32045000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            32044000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187728827                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187769062                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                36445                       # number of replacements
-system.iocache.tags.tagsinuse               14.386151                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.383154                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36461                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         289285136000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.386151                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.899134                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.899134                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         289903742000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.383154                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.898947                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.898947                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
 system.iocache.tags.data_accesses              328311                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
@@ -2367,14 +2385,14 @@ system.iocache.demand_misses::realview.ide        36479                       #
 system.iocache.demand_misses::total             36479                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide        36479                       # number of overall misses
 system.iocache.overall_misses::total            36479                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     34821377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     34821377                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4306604450                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4306604450                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   4341425827                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4341425827                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   4341425827                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4341425827                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     40888377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     40888377                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4391190685                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4391190685                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4432079062                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4432079062                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4432079062                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4432079062                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2391,19 +2409,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 136554.419608                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 136554.419608                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118888.152882                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118888.152882                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 119011.645796                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 119011.645796                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 119011.645796                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 119011.645796                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             6                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 160346.576471                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 160346.576471                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121223.241083                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 121223.241083                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 121496.725842                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 121496.725842                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 121496.725842                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 121496.725842                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            70                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   10                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            3                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            7                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
@@ -2415,14 +2433,14 @@ system.iocache.demand_mshr_misses::realview.ide        36479
 system.iocache.demand_mshr_misses::total        36479                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide        36479                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        36479                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     22071377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     22071377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2493082245                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2493082245                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   2515153622                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2515153622                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   2515153622                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2515153622                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     28138377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     28138377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2577641992                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2577641992                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2605780369                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2605780369                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2605780369                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2605780369                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2431,591 +2449,565 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 86554.419608                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 86554.419608                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68824.046074                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.046074                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68947.987116                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68947.987116                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68947.987116                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68947.987116                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   137913                       # number of replacements
-system.l2c.tags.tagsinuse                65077.078827                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     526584                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   203352                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.589520                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             102405123000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks    6467.156176                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.052663                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.040623                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7119.410088                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6998.473757                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.432069                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.004586                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1431.375532                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3211.021288                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2361.112045                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.098681                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000047                       # Average percentage of cache occupancy
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110346.576471                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 110346.576471                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71158.403048                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71158.403048                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 71432.341046                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 71432.341046                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 71432.341046                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 71432.341046                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                   136024                       # number of replacements
+system.l2c.tags.tagsinuse                65074.400284                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     524979                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   201414                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.606467                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle             103030494000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks    6378.541377                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.901261                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.045973                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     7223.294710                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6923.893951                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37646.371687                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1427.225105                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3211.431328                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2259.694892                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.097329                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000060                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.108634                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.106788                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.571982                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.021841                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.048996                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.036028                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.992997                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        34227                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        31208                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          194                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         4904                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        29129                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu0.inst       0.110219                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.105650                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.574438                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.021778                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.049003                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.034480                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.992957                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        34321                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        31064                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1            5                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          178                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         4958                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        29180                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2           96                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         1170                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        29939                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.522263                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.476196                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  6120881                       # Number of tag accesses
-system.l2c.tags.data_accesses                 6120881                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks       260820                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          260820                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data           40104                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            5060                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               45164                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          2347                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          2252                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              4599                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             4026                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             1389                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 5415                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          108                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker           71                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        44456                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        52767                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        45168                       # number of ReadSharedReq hits
+system.l2c.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         1178                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        29816                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.523697                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.473999                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  6089608                       # Number of tag accesses
+system.l2c.tags.data_accesses                 6089608                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks       259449                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          259449                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data           40103                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            4906                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               45009                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          2386                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          2218                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total              4604                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data             4006                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data             1413                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                 5419                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          142                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker           81                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst        44259                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data        52827                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        45774                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           38                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           27                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst        18981                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        11141                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5391                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           178148                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           108                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            71                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               44456                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               56793                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        45168                       # number of demand (read+write) hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker           20                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst        18793                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data        10825                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5311                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           178070                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker           142                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker            81                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst               44259                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data               56833                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher        45774                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.dtb.walker            38                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            27                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               18981                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               12530                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher         5391                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  183563                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          108                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker           71                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              44456                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              56793                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher        45168                       # number of overall hits
+system.l2c.demand_hits::cpu1.itb.walker            20                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst               18793                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               12238                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher         5311                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  183489                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker          142                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker           81                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst              44259                       # number of overall hits
+system.l2c.overall_hits::cpu0.data              56833                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher        45774                       # number of overall hits
 system.l2c.overall_hits::cpu1.dtb.walker           38                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           27                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              18981                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              12530                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher         5391                       # number of overall hits
-system.l2c.overall_hits::total                 183563                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data           439                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           262                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total               701                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          134                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data           80                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             214                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          11600                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           8098                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              19698                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker            7                       # number of ReadSharedReq misses
+system.l2c.overall_hits::cpu1.itb.walker           20                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst              18793                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              12238                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher         5311                       # number of overall hits
+system.l2c.overall_hits::total                 183489                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data           592                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           252                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total               844                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          118                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data           92                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             210                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          11217                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           8015                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              19232                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker            9                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu0.itb.walker            2                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        17911                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         9058                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       134486                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst         2346                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data          949                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6189                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         170949                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker            7                       # number of demand (read+write) misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        17886                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data         9091                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       133589                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst         2327                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data          875                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6065                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         169844                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker            9                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             17911                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             20658                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       134486                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2346                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data              9047                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher         6189                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                190647                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker            7                       # number of overall misses
+system.l2c.demand_misses::cpu0.inst             17886                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             20308                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       133589                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              2327                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data              8890                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher         6065                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                189076                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker            9                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            17911                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            20658                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       134486                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2346                       # number of overall misses
-system.l2c.overall_misses::cpu1.data             9047                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher         6189                       # number of overall misses
-system.l2c.overall_misses::total               190647                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data      8533000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data       947500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      9480500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       549000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       243000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       792000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   1114115000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    666355000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1780470000                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker       613500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       174000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1475165500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data    798074000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  13067739073                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker        89500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst    196303000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data     84484000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    694399123                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  16317041696                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker       613500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker       174000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1475165500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   1912189000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13067739073                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker        89500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    196303000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    750839000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    694399123                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     18097511696                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker       613500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker       174000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1475165500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   1912189000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13067739073                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker        89500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    196303000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    750839000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    694399123                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    18097511696                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       260820                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       260820                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        40543                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5322                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           45865                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         2481                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         2332                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          4813                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data        15626                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data         9487                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            25113                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          115                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           73                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst        62367                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data        61825                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       179654                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           39                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           27                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst        21327                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data        12090                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11580                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       349097                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker          115                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker           73                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           62367                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           77451                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       179654                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker           39                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           27                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           21327                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           21577                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11580                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              374210                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker          115                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           73                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          62367                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          77451                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       179654                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker           39                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           27                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          21327                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          21577                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11580                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             374210                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.010828                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.049230                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.015284                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.054010                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.034305                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.044463                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.742352                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.853589                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.784375                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.060870                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.027397                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.287187                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.146510                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.748583                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.025641                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.110001                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.078495                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.534456                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.489689                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.060870                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.027397                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.287187                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.266723                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.748583                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.025641                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.110001                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.419289                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.534456                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.509465                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.060870                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.027397                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.287187                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.266723                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.748583                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.025641                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.110001                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.419289                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.534456                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.509465                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19437.357631                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3616.412214                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 13524.251070                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4097.014925                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  3037.500000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  3700.934579                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96044.396552                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82286.367004                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 90388.364301                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 87642.857143                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        87000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82360.867623                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88107.087657                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 97168.025467                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker        89500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83675.618073                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89024.236038                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 112198.921150                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 95449.763941                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87642.857143                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        87000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 82360.867623                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 92564.091393                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97168.025467                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        89500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 83675.618073                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 82993.146900                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112198.921150                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 94926.810786                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87642.857143                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        87000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 82360.867623                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 92564.091393                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97168.025467                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        89500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 83675.618073                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 82993.146900                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112198.921150                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 94926.810786                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                12                       # number of cycles access was blocked
+system.l2c.overall_misses::cpu0.inst            17886                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            20308                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       133589                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2327                       # number of overall misses
+system.l2c.overall_misses::cpu1.data             8890                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher         6065                       # number of overall misses
+system.l2c.overall_misses::total               189076                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data      9921500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data       813500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     10735000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       614000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       361000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       975000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   1635531500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    824298500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   2459830000                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      1956500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       180000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1955907500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data   1124374000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  15941458655                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst    261946000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data    108772000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    762939367                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  20157534022                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      1956500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       180000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   1955907500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   2759905500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  15941458655                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    261946000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    933070500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    762939367                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     22617364022                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      1956500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker       180000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   1955907500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   2759905500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  15941458655                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    261946000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    933070500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    762939367                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    22617364022                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks       259449                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       259449                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        40695                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5158                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           45853                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         2504                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         2310                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          4814                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15223                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data         9428                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            24651                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          151                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           83                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        62145                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        61918                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       179363                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           38                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           20                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        21120                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        11700                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11376                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       347914                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          151                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           83                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           62145                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           77141                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       179363                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker           38                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           20                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           21120                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           21128                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11376                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              372565                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          151                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           83                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          62145                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          77141                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       179363                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           38                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           20                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          21120                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          21128                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11376                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             372565                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.014547                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.048856                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.018407                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.047125                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.039827                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.043623                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.736846                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.850127                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.780171                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.059603                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.024096                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.287811                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.146823                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.744797                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.110180                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.074786                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.533140                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.488178                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.059603                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.024096                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.287811                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.263258                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.744797                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.110180                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.420769                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.533140                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.507498                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.059603                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.024096                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.287811                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.263258                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.744797                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.110180                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.420769                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.533140                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.507498                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16759.290541                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3228.174603                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 12719.194313                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5203.389831                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  3923.913043                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  4642.857143                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145808.282072                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102844.479102                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 127902.974210                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 217388.888889                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        90000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109354.103768                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123679.903201                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 112568.113451                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 124310.857143                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 118682.638315                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 217388.888889                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker        90000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 109354.103768                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 135902.378373                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 112568.113451                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 104957.311586                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 119620.491347                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 217388.888889                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        90000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 109354.103768                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 135902.378373                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 112568.113451                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 104957.311586                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 119620.491347                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               873                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        1                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        8                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs            12                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs    109.125000                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks              101139                       # number of writebacks
-system.l2c.writebacks::total                   101139                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            1                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            5                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  6                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 6                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         3904                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         3904                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data          439                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          262                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total          701                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          134                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           80                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total          214                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        11600                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         8098                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         19698                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            7                       # number of ReadSharedReq MSHR misses
+system.l2c.writebacks::writebacks               99972                       # number of writebacks
+system.l2c.writebacks::total                    99972                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            7                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            9                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total           16                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              9                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 16                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             7                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             9                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                16                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         3644                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         3644                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data          592                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          252                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total          844                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          118                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           92                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total          210                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        11217                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         8015                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         19232                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            9                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17910                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9058                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       134486                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2341                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data          949                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6189                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       170943                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17879                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9091                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       133589                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2318                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data          875                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6065                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       169828                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker            9                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        17910                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        20658                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       134486                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2341                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         9047                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6189                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           190641                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker            7                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        17879                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        20308                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       133589                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2318                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         8890                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6065                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           189060                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker            9                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        17910                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        20658                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       134486                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2341                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data         9047                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6189                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          190641                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        17879                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        20308                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       133589                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2318                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data         8890                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6065                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          189060                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31786                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31790                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3096                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        44081                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28463                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2450                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        30913                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3093                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        44082                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28464                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2451                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        30915                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60249                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60254                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5546                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        74994                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     10668500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      5960000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     16628500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      3486500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      1878000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total      5364500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    998115000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    585374501                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1583489501                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker       543500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       154000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1296016500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    707494000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11722877577                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker        79500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    172535500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     74994000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    632508125                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  14607202702                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       543500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       154000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1296016500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   1705609000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11722877577                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        79500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    172535500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    660368501                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    632508125                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16190692203                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       543500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       154000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1296016500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   1705609000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11722877577                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        79500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    172535500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    660368501                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    632508125                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16190692203                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    581355000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5801764501                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11113500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    362869500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6757102501                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    581355000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5801764501                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     11113500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    362869500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   6757102501                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5544                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        74997                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     13698000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      5474500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     19172500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      3092000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2171500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total      5263500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1523361500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    744148500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   2267510000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      1866500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       160000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1775966000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1033464000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14605564664                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    238288500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    100021501                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    702288868                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  18457620033                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1866500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       160000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1775966000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   2556825500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  14605564664                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    238288500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    844170001                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    702288868                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  20725130033                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1866500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       160000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1775966000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   2556825500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14605564664                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    238288500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    844170001                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    702288868                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  20725130033                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    633244000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5805450500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     12497000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    362875500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6814067000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    633244000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5805450500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     12497000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    362875500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   6814067000                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.010828                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.049230                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.015284                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.054010                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.034305                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.044463                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.742352                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.853589                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.784375                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.060870                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.027397                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.287171                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.146510                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.748583                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.025641                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.109767                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.078495                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.534456                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.489672                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.060870                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.027397                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.287171                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.266723                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.748583                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.025641                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.109767                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.419289                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.534456                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.509449                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.060870                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.027397                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.287171                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.266723                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.748583                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.025641                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.109767                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.419289                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.534456                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.509449                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 24301.822323                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22748.091603                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23721.112696                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26018.656716                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        23475                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25067.757009                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86044.396552                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72286.305384                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 80388.338968                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        77000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72362.730318                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78107.087657                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker        79500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73701.623238                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79024.236038                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85450.721597                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        77000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72362.730318                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82564.091393                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        79500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73701.623238                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72993.091743                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 84927.650416                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        77000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72362.730318                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82564.091393                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        79500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73701.623238                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72993.091743                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 84927.650416                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182525.781822                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62788.135593                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117205.910853                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153288.321522                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96296.444771                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62788.135593                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.047962                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 90101.908166                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        504508                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       283356                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.014547                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.048856                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.018407                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.047125                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.039827                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.043623                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.736846                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.850127                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.780171                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.059603                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.024096                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.287698                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.146823                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.744797                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.109754                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.074786                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.533140                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.488132                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.059603                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.024096                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.287698                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.263258                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.744797                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.109754                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.420769                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.533140                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.507455                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.059603                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.024096                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.287698                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.263258                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.744797                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.109754                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.420769                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.533140                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.507455                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23138.513514                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21724.206349                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22716.232227                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26203.389831                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23603.260870                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25064.285714                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135808.282072                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92844.479102                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 117902.974210                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        80000                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99332.513004                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113679.903201                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102799.180328                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 114310.286857                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108684.198324                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        80000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99332.513004                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125902.378373                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102799.180328                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94957.255456                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 109621.972035                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        80000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99332.513004                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125902.378373                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102799.180328                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94957.255456                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 109621.972035                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182618.763762                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117321.532493                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154577.083617                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96349.628240                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65453.733766                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 90857.860981                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests        501880                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       282396                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests          588                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               44081                       # Transaction distribution
-system.membus.trans_dist::ReadResp             215279                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30913                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30913                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       137329                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            16651                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            64792                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          38133                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               44082                       # Transaction distribution
+system.membus.trans_dist::ReadResp             214165                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30915                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30915                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       136162                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            16178                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            65137                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          38197                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             40131                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            19681                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        171198                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             39788                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19211                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        170083                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13736                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       650114                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       771800                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13742                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       645838                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       767530                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72939                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        72939                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 844739                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 840469                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18707276                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18897612                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27484                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18531148                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18721496                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21214732                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           123049                       # Total snoops (count)
+system.membus.pkt_size::total                21038616                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           123440                       # Total snoops (count)
 system.membus.snoopTraffic                      37632                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            425474                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.012172                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.109655                       # Request fanout histogram
+system.membus.snoop_fanout::samples            424426                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.012207                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.109809                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  420295     98.78%     98.78% # Request fanout histogram
-system.membus.snoop_fanout::1                    5179      1.22%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  419245     98.78%     98.78% # Request fanout histogram
+system.membus.snoop_fanout::1                    5181      1.22%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              425474                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            88273000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              424426                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            88263500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11470000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11456000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           976922430                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           968117274                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1118158241                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1108847564                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1366131                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1391627                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -3047,77 +3039,77 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      1015113                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       540228                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       174806                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          29447                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        28379                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops         1068                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq              44084                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            511780                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30913                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30913                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       361959                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          119582                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          109939                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         42732                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         152671                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           79                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           79                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            51282                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           51282                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       467698                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq         4573                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1273273                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       316945                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1590218                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     35272632                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5631700                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               40904332                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          389588                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  15743116                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples           889230                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.395392                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.491385                       # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests      1012066                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       538478                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       175231                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          28833                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        27811                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops         1022                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq              44085                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            510917                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30915                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30915                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       359421                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          118152                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          110125                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         42801                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         152926                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           88                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           88                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50897                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50897                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       466834                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq         4575                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1272193                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       313311                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1585504                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     35206412                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5504908                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               40711320                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          388372                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                  15694348                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples           886366                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.396986                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.491624                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 538704     60.58%     60.58% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 349458     39.30%     99.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                   1068      0.12%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 535513     60.42%     60.42% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 349831     39.47%     99.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                   1022      0.12%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             889230                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          894701567                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             886366                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          892357874                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           360619                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           360373                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         677372101                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         676996738                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         239236747                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         237913566                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 657e88994..5d8ec5a8f 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -36,7 +36,7 @@ load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -153,7 +153,7 @@ icache_port=system.cpu.icache.cpu_side
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -250,7 +250,7 @@ port=system.cpu.toL2Bus.slave[3]
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -382,7 +382,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -499,7 +499,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -544,7 +544,7 @@ size=1024
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -556,7 +556,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -588,29 +588,36 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -630,6 +637,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -639,7 +647,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -661,9 +669,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -1016,7 +1024,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -1333,6 +1341,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1340,7 +1349,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -1571,6 +1580,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1578,7 +1588,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index 6d681649a..03ec36b9d 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:28:47
-gem5 executing on e108600-lin, pid 12530
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:01:25
+gem5 executing on e108600-lin, pid 17555
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2909582799500 because m5_exit instruction encountered
+Exiting @ tick 2905297782500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index dd34564a7..aaea4a10c 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,121 +1,121 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.903737                       # Number of seconds simulated
-sim_ticks                                2903736790500                       # Number of ticks simulated
-final_tick                               2903736790500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.905298                       # Number of seconds simulated
+sim_ticks                                2905297782500                       # Number of ticks simulated
+final_tick                               2905297782500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 515424                       # Simulator instruction rate (inst/s)
-host_op_rate                                   621448                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            13306386787                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 582748                       # Number of bytes of host memory used
-host_seconds                                   218.22                       # Real time elapsed on the host
-sim_insts                                   112476413                       # Number of instructions simulated
-sim_ops                                     135613231                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 483331                       # Simulator instruction rate (inst/s)
+host_op_rate                                   582745                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            12486239543                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 580500                       # Number of bytes of host memory used
+host_seconds                                   232.68                       # Real time elapsed on the host
+sim_insts                                   112461365                       # Number of instructions simulated
+sim_ops                                     135593151                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker          512                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1188964                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9028260                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1184612                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8933156                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10218824                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1188964                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1188964                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7618752                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10119304                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1184612                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1184612                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7531136                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7636276                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker            8                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           7548660                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              27031                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141586                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              26963                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             140100                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                168642                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          119043                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                167087                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117674                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               123424                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            176                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               122055                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            154                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             44                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               409460                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3109187                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              331                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3519198                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          409460                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             409460                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2623775                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6035                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2629810                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2623775                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           176                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               407742                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3074782                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3483052                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          407742                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             407742                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2592208                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6032                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2598240                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2592208                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           154                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            44                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              409460                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3115222                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide             331                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6149008                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        168642                       # Number of read requests accepted
-system.physmem.writeReqs                       123424                       # Number of write requests accepted
-system.physmem.readBursts                      168642                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     123424                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10783744                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9344                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7648256                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10218824                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7636276                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      146                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::cpu.inst              407742                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3080813                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6081292                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        167087                       # Number of read requests accepted
+system.physmem.writeReqs                       122055                       # Number of write requests accepted
+system.physmem.readBursts                      167087                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     122055                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10685312                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8256                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7561344                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10119304                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7548660                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      129                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9943                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9648                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10560                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10245                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18706                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9867                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9999                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10271                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9694                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10419                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9828                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9028                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10140                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10489                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10151                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9508                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7397                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7199                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8385                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7801                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7213                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7134                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7314                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7590                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7388                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8015                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7407                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6899                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7622                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7751                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7507                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6882                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9954                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9813                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10094                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9518                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18811                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10188                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10467                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10858                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9262                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10094                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9505                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9184                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9983                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9847                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9958                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9422                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7103                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7218                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7869                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7374                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7424                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7558                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7579                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7921                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6916                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7516                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7047                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7122                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7779                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7383                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7451                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6886                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2903736355000                       # Total gap between requests
+system.physmem.numWrRetry                          65                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2905297420500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  159070                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  157515                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 119043                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    167708                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       529                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       247                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117674                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    166128                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       554                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       264                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -160,163 +160,178 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2984                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6096                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6034                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6526                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7526                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7572                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8704                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8960                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6955                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       27                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        58618                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      314.441571                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     184.322128                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     334.751512                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          21316     36.36%     36.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14773     25.20%     61.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5607      9.57%     71.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3267      5.57%     76.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2505      4.27%     80.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1471      2.51%     83.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1045      1.78%     85.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1040      1.77%     87.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7594     12.96%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          58618                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5878                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.661279                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      584.674226                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5877     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1886                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2786                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5910                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5857                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5767                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6250                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6643                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8271                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8725                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6628                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6527                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6281                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      401                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      430                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      376                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      256                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      186                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      134                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       78                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      163                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        57323                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      318.311882                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     186.988870                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     336.470779                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          20402     35.59%     35.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14531     25.35%     60.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5716      9.97%     70.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3104      5.41%     76.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2370      4.13%     80.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1421      2.48%     82.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1241      2.16%     85.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          946      1.65%     86.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7592     13.24%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          57323                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5761                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.979865                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      590.542998                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           5760     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5878                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5878                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.330725                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.604611                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.460490                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5095     86.68%     86.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              41      0.70%     87.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              85      1.45%     88.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              37      0.63%     89.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             285      4.85%     94.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              59      1.00%     95.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              13      0.22%     95.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              14      0.24%     95.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               9      0.15%     95.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               4      0.07%     95.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.10%     96.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               8      0.14%     96.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             168      2.86%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.05%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               2      0.03%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               6      0.10%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               7      0.12%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.03%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.03%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             5      0.09%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            11      0.19%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.81% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            5761                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5761                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.507898                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.546505                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       15.055833                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5040     87.48%     87.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              23      0.40%     87.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              68      1.18%     89.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              38      0.66%     89.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             294      5.10%     94.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              33      0.57%     95.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               2      0.03%     95.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               7      0.12%     95.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               6      0.10%     95.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               3      0.05%     95.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               2      0.03%     95.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               5      0.09%     95.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             158      2.74%     98.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.07%     98.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               6      0.10%     98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               3      0.05%     98.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              10      0.17%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.03%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.03%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            11      0.19%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.03%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.05%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             8      0.14%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             7      0.12%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             4      0.07%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             4      0.07%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.02%     99.81% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::148-151             1      0.02%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             6      0.10%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::252-255             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5878                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1493636250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4652936250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    842480000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8864.52                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             3      0.05%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             2      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5761                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4504540500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                7635003000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    834790000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       26980.08                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27614.52                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.71                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.63                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.52                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.63                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  45730.08                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.68                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.60                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.48                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.60                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.41                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     138583                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     90798                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.25                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.96                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9942055.41                       # Average gap between requests
-system.physmem.pageHitRate                      79.64                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  226187640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  123415875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 696064200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                389013840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           189657789360                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            86978464290                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1665943648500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1944014583705                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.487777                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2771286006000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     96962060000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     35486192750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  216964440                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  118383375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 618196800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                385372080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           189657789360                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            85605070095                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1667148388500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1943750164650                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.396712                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2773305848750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     96962060000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     33468782750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
+system.physmem.avgWrQLen                        25.28                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     138094                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     89686                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.71                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.90                       # Row buffer hit rate for writes
+system.physmem.avgGap                     10047995.17                       # Average gap between requests
+system.physmem.pageHitRate                      79.89                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  210115920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  111679260                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 640479420                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                313440120                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           6609223920.000002                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             4735061820                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              414343200                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       13903412640                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        9310120320                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       682719565725                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             718969243965                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              247.468348                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           2893307612500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE      778413000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2810438000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   2839095824500                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  24245244750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      7877734000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  30490128250                       # Time in different power states
+system.physmem_1.actEnergy                  199177440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  105861525                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 551600700                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                303282000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           6621516720.000002                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             4536550200                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              409678080                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       13514783790                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        9490661760                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy       682993594335                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             718728215280                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              247.385386                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           2894278953000                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE      777246000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2816412000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   2839926040500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN  24715420500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      7425105000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  29637558500                       # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -329,9 +344,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst            7
 system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
@@ -339,7 +354,7 @@ system.cf0.dma_write_full_pages                   540                       # Nu
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -369,58 +384,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                      9520                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                 9520                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1         1252                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2         8268                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples         9520                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0            9520    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total         9520                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples         7356                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 10060.290919                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  8514.979061                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  6541.334463                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383         6558     89.15%     89.15% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767          793     10.78%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                      9547                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                 9547                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1         1253                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2         8294                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples         9547                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0            9547    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total         9547                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples         7383                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean  9942.435324                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  8397.692517                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  6587.109188                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-16383         6605     89.46%     89.46% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-32767          773     10.47%     99.93% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::81920-98303            4      0.05%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total         7356                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples    941563500                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0       941563500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total    941563500                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6151     83.62%     83.62% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1205     16.38%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7356                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data         9520                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkCompletionTime::total         7383                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples   1003066500                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0      1003066500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total   1003066500                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6177     83.67%     83.67% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1206     16.33%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7383                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data         9547                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total         9520                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7356                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total         9547                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7383                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7356                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        16876                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7383                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        16930                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24525489                       # DTB read hits
-system.cpu.dtb.read_misses                       8109                       # DTB read misses
-system.cpu.dtb.write_hits                    19608938                       # DTB write hits
-system.cpu.dtb.write_misses                      1411                       # DTB write misses
+system.cpu.dtb.read_hits                     24520121                       # DTB read hits
+system.cpu.dtb.read_misses                       8133                       # DTB read misses
+system.cpu.dtb.write_hits                    19605715                       # DTB write hits
+system.cpu.dtb.write_misses                      1414                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4199                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                     4209                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   1636                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   1628                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24533598                       # DTB read accesses
-system.cpu.dtb.write_accesses                19610349                       # DTB write accesses
+system.cpu.dtb.read_accesses                 24528254                       # DTB read accesses
+system.cpu.dtb.write_accesses                19607129                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44134427                       # DTB hits
-system.cpu.dtb.misses                            9520                       # DTB misses
-system.cpu.dtb.accesses                      44143947                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                          44125836                       # DTB hits
+system.cpu.dtb.misses                            9547                       # DTB misses
+system.cpu.dtb.accesses                      44135383                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -450,39 +465,39 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                      4762                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                 4762                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1          309                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                      4763                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                 4763                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1          310                       # Level at which table walker walks with short descriptors terminate
 system.cpu.itb.walker.walksShortTerminationLevel::Level2         4453                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples         4762                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0            4762    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total         4762                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3107                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 10273.897650                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  8288.299297                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7346.561217                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191         1812     58.32%     58.32% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383          745     23.98%     82.30% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575          548     17.64%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::81920-90111            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::90112-98303            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3107                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples    941232000                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       941232000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total    941232000                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2798     90.05%     90.05% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           309      9.95%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3107                       # Table walker page sizes translated
+system.cpu.itb.walker.walkWaitTime::samples         4763                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0            4763    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total         4763                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3108                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 10156.853282                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  8221.468352                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7284.204444                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         1821     58.59%     58.59% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383          769     24.74%     83.33% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          516     16.60%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::90112-98303            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::98304-106495            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         3108                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples   1002711000                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      1002711000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total   1002711000                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2798     90.03%     90.03% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           310      9.97%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3108                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         4762                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total         4762                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         4763                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total         4763                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3107                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3107                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total         7869                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    115574516                       # ITB inst hits
-system.cpu.itb.inst_misses                       4762                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3108                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3108                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total         7871                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    115559307                       # ITB inst hits
+system.cpu.itb.inst_misses                       4763                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -498,55 +513,55 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                115579278                       # ITB inst accesses
-system.cpu.itb.hits                         115574516                       # DTB hits
-system.cpu.itb.misses                            4762                       # DTB misses
-system.cpu.itb.accesses                     115579278                       # DTB accesses
-system.cpu.numPwrStateTransitions                6062                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples          3031                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     888232478.174860                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    17469824950.226959                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows         2968     97.92%     97.92% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10           57      1.88%     99.80% # Distribution of time spent in the clock gated state
+system.cpu.itb.inst_accesses                115564070                       # ITB inst accesses
+system.cpu.itb.hits                         115559307                       # DTB hits
+system.cpu.itb.misses                            4763                       # DTB misses
+system.cpu.itb.accesses                     115564070                       # DTB accesses
+system.cpu.numPwrStateTransitions                6066                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples          3033                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     887205638.526871                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    17463817933.974155                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows         2968     97.86%     97.86% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10           59      1.95%     99.80% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.03%     99.87% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.03%     99.90% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 499964073052                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total            3031                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    211504149152                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 2692232641348                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       5807473581                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::max_value 499962880972                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total            3033                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    214403080848                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2690894701652                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       5810595565                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3031                       # number of quiesce instructions executed
-system.cpu.committedInsts                   112476413                       # Number of instructions committed
-system.cpu.committedOps                     135613231                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             119916333                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                  11161                       # Number of float alu accesses
-system.cpu.num_func_calls                     9896179                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15232917                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    119916333                       # number of integer instructions
-system.cpu.num_fp_insts                         11161                       # number of float instructions
-system.cpu.num_int_register_reads           218092554                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           82663252                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                 8449                       # number of times the floating registers were read
+system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
+system.cpu.committedInsts                   112461365                       # Number of instructions committed
+system.cpu.committedOps                     135593151                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             119897812                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                  11226                       # Number of float alu accesses
+system.cpu.num_func_calls                     9894928                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     15231225                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    119897812                       # number of integer instructions
+system.cpu.num_fp_insts                         11226                       # number of float instructions
+system.cpu.num_int_register_reads           218061607                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           82648736                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                 8514                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            489835813                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            51902110                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      45414800                       # number of memory refs
-system.cpu.num_load_insts                    24847736                       # Number of load instructions
-system.cpu.num_store_insts                   20567064                       # Number of store instructions
-system.cpu.num_idle_cycles               5384465282.694146                       # Number of idle cycles
-system.cpu.num_busy_cycles               423008298.305854                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.072839                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.927161                       # Percentage of idle cycles
-system.cpu.Branches                          25923023                       # Number of branches fetched
+system.cpu.num_cc_register_reads            489758493                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            51897030                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      45406070                       # number of memory refs
+system.cpu.num_load_insts                    24842315                       # Number of load instructions
+system.cpu.num_store_insts                   20563755                       # Number of store instructions
+system.cpu.num_idle_cycles               5381789403.302147                       # Number of idle cycles
+system.cpu.num_busy_cycles               428806161.697852                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.073797                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.926203                       # Percentage of idle cycles
+system.cpu.Branches                          25920117                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  93194210     67.17%     67.18% # Class of executed instruction
-system.cpu.op_class::IntMult                   114540      0.08%     67.26% # Class of executed instruction
+system.cpu.op_class::IntAlu                  93182494     67.18%     67.18% # Class of executed instruction
+system.cpu.op_class::IntMult                   114558      0.08%     67.26% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     67.26% # Class of executed instruction
@@ -570,502 +585,502 @@ system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.26% # Cl
 system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc               8453      0.01%     67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.26% # Class of executed instruction
-system.cpu.op_class::MemRead                 24847736     17.91%     85.18% # Class of executed instruction
-system.cpu.op_class::MemWrite                20567064     14.82%    100.00% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc               8431      0.01%     67.27% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     67.27% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.27% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.27% # Class of executed instruction
+system.cpu.op_class::MemRead                 24842315     17.91%     85.18% # Class of executed instruction
+system.cpu.op_class::MemWrite                20563755     14.82%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  138734340                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements            819770                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.827215                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            43243016                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            820282                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             52.717256                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1013099500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.827215                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999663                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999663                       # Average percentage of cache occupancy
+system.cpu.op_class::total                  138713890                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements            821351                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.816254                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            43232645                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            821863                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             52.603226                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1078145500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.816254                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999641                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999641                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          366                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           86                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           94                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         177141047                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        177141047                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     23117557                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23117557                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18826251                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18826251                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       392764                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        392764                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       443415                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       443415                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460277                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460277                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41943808                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41943808                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42336572                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42336572                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       400061                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        400061                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       298752                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       298752                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       118460                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       118460                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22645                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22645                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         177108261                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        177108261                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     23111024                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23111024                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18823159                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18823159                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       392414                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        392414                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443071                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443071                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460161                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460161                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41934183                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41934183                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42326597                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42326597                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       401452                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        401452                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       298737                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       298737                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       118712                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       118712                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22861                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22861                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data       698813                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         698813                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       817273                       # number of overall misses
-system.cpu.dcache.overall_misses::total        817273                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5967732500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5967732500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  12596392000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  12596392000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    280149500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    280149500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data       700189                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         700189                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       818901                       # number of overall misses
+system.cpu.dcache.overall_misses::total        818901                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   6440957000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   6440957000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  14361709000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  14361709000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    300793500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    300793500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       166000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       166000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  18564124500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  18564124500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  18564124500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  18564124500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23517618                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23517618                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19125003                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19125003                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       511224                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       511224                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466060                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       466060                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460279                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460279                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42642621                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42642621                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43153845                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43153845                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017011                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.017011                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015621                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015621                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.231718                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.231718                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048588                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048588                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data  20802666000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  20802666000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  20802666000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  20802666000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23512476                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23512476                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19121896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19121896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       511126                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       511126                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465932                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       465932                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460163                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460163                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     42634372                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42634372                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43145498                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43145498                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017074                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.017074                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015623                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015623                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.232256                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.232256                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.049065                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.049065                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.016388                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.016388                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.018939                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.018939                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14917.056399                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14917.056399                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42163.372965                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 42163.372965                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12371.362332                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12371.362332                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.016423                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.016423                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.018980                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.018980                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16044.152227                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16044.152227                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48074.758065                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48074.758065                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13157.495298                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13157.495298                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26565.224888                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26565.224888                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22714.716502                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22714.716502                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29710.072566                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29710.072566                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25403.151297                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25403.151297                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                19                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       683946                       # number of writebacks
-system.cpu.dcache.writebacks::total            683946                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          680                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          680                       # number of ReadReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14146                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        14146                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          680                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          680                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          680                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          680                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       399381                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       399381                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298752                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       298752                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       116429                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       116429                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8499                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8499                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       685561                       # number of writebacks
+system.cpu.dcache.writebacks::total            685561                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          705                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          705                       # number of ReadReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14335                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        14335                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          705                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          705                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          705                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          705                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       400747                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       400747                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298737                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       298737                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       116693                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       116693                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8526                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8526                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       698133                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       698133                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       814562                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       814562                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       699484                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       699484                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       816177                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       816177                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27589                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5555392000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5555392000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12297640000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12297640000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1530002500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1530002500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    108858500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    108858500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6015919500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6015919500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14062972000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  14062972000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1582474000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1582474000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    120274000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    120274000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       164000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       164000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17853032000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17853032000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19383034500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  19383034500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6281205500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6281205500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6281205500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6281205500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016982                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016982                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015621                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015621                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227746                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227746                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018236                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018236                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  20078891500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  20078891500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  21661365500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  21661365500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6284842500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6284842500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6284842500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6284842500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017044                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017044                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015623                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015623                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228306                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228306                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018299                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018299                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016372                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016372                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018876                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.018876                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13910.005734                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13910.005734                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41163.372965                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41163.372965                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13141.077395                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13141.077395                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12808.389222                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12808.389222                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016407                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016407                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018917                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.018917                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15011.764280                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15011.764280                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47074.758065                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47074.758065                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13561.001945                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13561.001945                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14106.732348                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14106.732348                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82000                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25572.537038                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25572.537038                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23795.652756                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23795.652756                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201721.546021                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201721.546021                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.008310                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.008310                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           1698000                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.728664                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           113875998                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1698512                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             67.044565                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       25832791500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.728664                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997517                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997517                       # Average percentage of cache occupancy
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28705.290614                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28705.290614                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26540.034208                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26540.034208                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201838.348642                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201838.348642                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.938938                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.938938                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements           1700003                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.693079                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           113858786                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1700515                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             66.955473                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       26307743500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.693079                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997447                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997447                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          264                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          246                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         117273034                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        117273034                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    113875998                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       113875998                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     113875998                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        113875998                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    113875998                       # number of overall hits
-system.cpu.icache.overall_hits::total       113875998                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1698518                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1698518                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1698518                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1698518                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1698518                       # number of overall misses
-system.cpu.icache.overall_misses::total       1698518                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  23414403500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  23414403500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  23414403500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  23414403500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  23414403500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  23414403500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    115574516                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    115574516                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    115574516                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    115574516                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    115574516                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    115574516                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014696                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014696                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014696                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014696                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014696                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014696                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13785.195977                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13785.195977                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13785.195977                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13785.195977                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13785.195977                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13785.195977                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         117259828                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        117259828                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    113858786                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       113858786                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     113858786                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        113858786                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    113858786                       # number of overall hits
+system.cpu.icache.overall_hits::total       113858786                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1700521                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1700521                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1700521                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1700521                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1700521                       # number of overall misses
+system.cpu.icache.overall_misses::total       1700521                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  24021238000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  24021238000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  24021238000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  24021238000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  24021238000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  24021238000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    115559307                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    115559307                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    115559307                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    115559307                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    115559307                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    115559307                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014716                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014716                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014716                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014716                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014716                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014716                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14125.810854                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14125.810854                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14125.810854                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14125.810854                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14125.810854                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14125.810854                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      1698000                       # number of writebacks
-system.cpu.icache.writebacks::total           1698000                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1698518                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1698518                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1698518                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1698518                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1698518                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1698518                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks      1700003                       # number of writebacks
+system.cpu.icache.writebacks::total           1700003                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1700521                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1700521                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1700521                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1700521                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1700521                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1700521                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  21715885500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  21715885500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  21715885500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  21715885500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  21715885500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  21715885500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    687287000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    687287000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    687287000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    687287000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014696                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014696                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014696                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.014696                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014696                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.014696                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12785.195977                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12785.195977                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12785.195977                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12785.195977                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12785.195977                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12785.195977                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76179.006872                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76179.006872                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements            89464                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65017.694965                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4847707                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           154877                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            31.300367                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     144041988000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.877834                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.040783                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  9524.120186                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 55489.656162                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000059                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  22320717000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  22320717000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22320717000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  22320717000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  22320717000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  22320717000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    745203000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    745203000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    745203000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    745203000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014716                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014716                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014716                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.014716                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014716                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.014716                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13125.810854                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13125.810854                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13125.810854                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13125.810854                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13125.810854                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13125.810854                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82598.426070                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82598.426070                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82598.426070                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82598.426070                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements            88035                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65011.446283                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4854285                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           153426                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            31.639259                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     146352515000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.050747                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.041160                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  9651.725117                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 55356.629260                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000047                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000001                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.145327                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.846705                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992091                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65407                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4600                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        60798                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998032                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         40230644                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        40230644                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         5114                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2743                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           7857                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       683946                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       683946                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1666952                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1666952                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         2730                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         2730                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       166687                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       166687                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1680478                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1680478                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       512210                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       512210                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         5114                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         2743                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1680478                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       678897                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2367232                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         5114                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         2743                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1680478                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       678897                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2367232                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            8                       # number of ReadReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.147274                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.844675                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.991996                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65386                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4355                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        60952                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997711                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         40277345                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        40277345                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         4991                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2669                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           7660                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       685561                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       685561                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1667726                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1667726                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         2795                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         2795                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       168131                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       168131                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1682557                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1682557                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       513829                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       513829                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         4991                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         2669                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst      1682557                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       681960                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2372177                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         4991                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         2669                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      1682557                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       681960                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2372177                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total           10                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           20                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           20                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadReq_misses::total            9                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           19                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           19                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       129315                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       129315                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        18016                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        18016                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        12099                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        12099                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker            8                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       127792                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       127792                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        17948                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        17948                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        12137                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        12137                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        18016                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       141414                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        159440                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker            8                       # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst        17948                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       139929                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        157886                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker            7                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        18016                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       141414                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       159440                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       829500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       168000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total       997500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       581000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       581000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.inst        17948                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       139929                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       157886                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      1154500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       180000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total      1334500                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       555500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       555500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       161000                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       161000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10066469000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10066469000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1464060500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1464060500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1012302000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1012302000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       829500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       168000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1464060500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  11078771000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  12543829000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       829500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       168000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1464060500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  11078771000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  12543829000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         5122                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2745                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         7867                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       683946                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       683946                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1666952                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1666952                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2750                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2750                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  11816022500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  11816022500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2043061500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   2043061500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1517166500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1517166500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      1154500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       180000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   2043061500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  13333189000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  15377585000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      1154500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       180000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   2043061500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  13333189000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  15377585000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         4998                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2671                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         7669                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       685561                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       685561                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1667726                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1667726                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2814                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2814                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       296002                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       296002                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1698494                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1698494                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       524309                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       524309                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         5122                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         2745                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1698494                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       820311                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2526672                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         5122                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         2745                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1698494                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       820311                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2526672                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001562                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000729                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.001271                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.007273                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.007273                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       295923                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       295923                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1700505                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1700505                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       525966                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       525966                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         4998                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         2671                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      1700505                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       821889                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2530063                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         4998                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         2671                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1700505                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       821889                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2530063                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001401                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000749                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.001174                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.006752                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.006752                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.436872                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.436872                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010607                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010607                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.431842                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.431842                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010555                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010555                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.023076                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.023076                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001562                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000729                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010607                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.172391                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.063103                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001562                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000729                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010607                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.172391                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.063103                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103687.500000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        84000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total        99750                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        29050                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        29050                       # average UpgradeReq miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001401                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000749                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010555                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.170253                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.062404                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001401                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000749                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010555                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.170253                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.062404                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164928.571429                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        90000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 148277.777778                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29236.842105                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29236.842105                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77844.557863                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77844.557863                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81264.459369                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81264.459369                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83668.237044                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83668.237044                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103687.500000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        84000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81264.459369                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78342.816129                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78674.291269                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103687.500000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        84000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81264.459369                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78342.816129                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78674.291269                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92462.928039                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92462.928039                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 113832.265433                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 113832.265433                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125003.419296                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125003.419296                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164928.571429                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        90000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 113832.265433                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95285.387589                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 97396.760954                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164928.571429                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        90000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 113832.265433                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95285.387589                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 97396.760954                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        82853                       # number of writebacks
-system.cpu.l2cache.writebacks::total            82853                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            8                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        81484                       # number of writebacks
+system.cpu.l2cache.writebacks::total            81484                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            7                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total           10                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           20                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           20                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total            9                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           19                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           19                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       129315                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       129315                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        18016                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        18016                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        12099                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        12099                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            8                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       127792                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       127792                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        17948                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        17948                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        12137                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        12137                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            7                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        18016                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       141414                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       159440                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            8                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        17948                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       139929                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       157886                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            7                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        18016                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       141414                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       159440                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        17948                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       139929                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       157886                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
@@ -1074,147 +1089,147 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27589
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       749500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       148000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total       897500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       381000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       381000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1084500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       160000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      1244500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       365500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       365500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       141000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       141000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8773319000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8773319000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1283900500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1283900500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    891312000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    891312000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       749500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       148000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1283900500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9664631000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10949429000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       749500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       148000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1283900500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9664631000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10949429000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    574512000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5891860500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6466372500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    574512000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5891860500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6466372500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001562                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000729                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001271                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.007273                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.007273                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  10538102500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  10538102500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1863581500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1863581500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1395796500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1395796500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1084500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       160000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1863581500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11933899000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  13798725000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1084500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       160000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1863581500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11933899000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  13798725000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    632428000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5895497500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6527925500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    632428000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5895497500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6527925500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001401                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000749                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001174                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.006752                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.006752                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.436872                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.436872                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010607                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010607                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.431842                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.431842                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010555                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010555                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.023076                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.023076                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001562                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000729                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010607                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172391                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.063103                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001562                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000729                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010607                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172391                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.063103                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        74000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        89750                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        19050                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        19050                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001401                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000749                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010555                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.170253                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.062404                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001401                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000749                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010555                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.170253                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.062404                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        80000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138277.777778                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19236.842105                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19236.842105                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70500                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67844.557863                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67844.557863                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71264.459369                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71264.459369                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73668.237044                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73668.237044                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        74000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71264.459369                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68342.816129                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68674.291269                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        74000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71264.459369                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68342.816129                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68674.291269                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63679.006872                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189217.692209                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161015.251494                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63679.006872                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100326.263899                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 95446.021343                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      5058492                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2539687                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        38280                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          250                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          250                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82462.928039                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82462.928039                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 103832.265433                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 103832.265433                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115003.419296                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115003.419296                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        80000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 103832.265433                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85285.387589                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87396.760954                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        80000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 103832.265433                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85285.387589                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87396.760954                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.494829                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.945717                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100388.194527                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.566119                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      5065968                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2543576                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        39287                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          219                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          219                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq          67163                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2290209                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq          67217                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2293895                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27589                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27589                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       766799                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1698000                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       142435                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2750                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       767045                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1700003                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       142341                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2814                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2752                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       296002                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       296002                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1698518                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       524530                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq         4455                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5113056                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2583569                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        11960                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        22910                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7731495                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    217411704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96469597                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        10980                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        20488                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          313912769                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      113519                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               5394688                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      2710473                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.021286                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.144336                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2816                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       295923                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       295923                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1700521                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       526163                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq         4351                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5119073                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2588406                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        11887                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        22839                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7742205                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    217668600                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96672157                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        10684                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        19992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          314371433                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      112178                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               5305776                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      2712615                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.021718                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.145761                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2652778     97.87%     97.87% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              57695      2.13%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2653703     97.83%     97.83% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              58912      2.17%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2710473                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4962792000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2712615                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4970051500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       389377                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       347876                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2556799000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2559803500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1276777495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1279174000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy       9215000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy       9216000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      17788000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      17841000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                30159                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30159                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
@@ -1237,9 +1252,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72868                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72868                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178346                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
@@ -1260,22 +1275,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             46334000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2320912                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2320912                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480037                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             46338000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                97000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               338500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               338000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                29500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                15500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                95000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                94500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               642000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               642500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -1297,56 +1312,56 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6273000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6292000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy            36469500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187671849                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187581870                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36692000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.078594                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements                36400                       # number of replacements
+system.iocache.tags.tagsinuse                1.079755                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36416                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         309373303000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.078594                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.067412                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.067412                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         310620847000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.079755                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.067485                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.067485                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
-system.iocache.tags.data_accesses              328122                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               327906                       # Number of tag accesses
+system.iocache.tags.data_accesses              327906                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.iocache.ReadReq_misses::realview.ide          210                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              210                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide        36458                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             36458                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide        36458                       # number of overall misses
-system.iocache.overall_misses::total            36458                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28897377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28897377                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4278807472                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4278807472                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   4307704849                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4307704849                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   4307704849                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4307704849                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide        36434                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36434                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36434                       # number of overall misses
+system.iocache.overall_misses::total            36434                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     34066376                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     34066376                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4367688494                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4367688494                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4401754870                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4401754870                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4401754870                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4401754870                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          210                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            210                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide        36458                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           36458                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide        36458                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          36458                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36434                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36434                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36434                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36434                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1355,14 +1370,14 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 123493.064103                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 123493.064103                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118120.789311                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118120.789311                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 118155.270421                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 118155.270421                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 118155.270421                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 118155.270421                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 162220.838095                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120574.439432                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 120574.439432                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 120814.482901                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 120814.482901                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 120814.482901                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 120814.482901                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1371,22 +1386,22 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide          210                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          210                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide        36458                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        36458                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide        36458                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        36458                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17197377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17197377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2465502723                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2465502723                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   2482700100                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2482700100                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   2482700100                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2482700100                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide        36434                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36434                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36434                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36434                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     23566376                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     23566376                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2554457612                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2554457612                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2578023988                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2578023988                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2578023988                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2578023988                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1395,90 +1410,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73493.064103                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 73493.064103                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68062.685595                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68062.685595                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68097.539635                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68097.539635                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68097.539635                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68097.539635                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests        321817                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       130498                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          482                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70518.374890                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70518.374890                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 70758.741505                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70758.741505                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 70758.741505                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70758.741505                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests        318841                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       128997                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          458                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
-system.membus.trans_dist::ReadResp              70519                       # Transaction distribution
+system.membus.trans_dist::ReadResp              70464                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       119043                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             6845                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       117674                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             6761                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              128                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129207                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129207                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         30359                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            127683                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           127683                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         30304                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       435887                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       543479                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72897                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72897                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 616376                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       431348                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       538940                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72849                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72849                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 611789                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15537980                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15701333                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15350844                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15514197                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18018453                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              498                       # Total snoops (count)
-system.membus.snoopTraffic                      31744                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            263669                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.018793                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.135792                       # Request fanout histogram
+system.membus.pkt_size::total                17831317                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              474                       # Total snoops (count)
+system.membus.snoopTraffic                      30208                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            262090                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.018417                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.134455                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  258714     98.12%     98.12% # Request fanout histogram
-system.membus.snoop_fanout::1                    4955      1.88%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  257263     98.16%     98.16% # Request fanout histogram
+system.membus.snoop_fanout::1                    4827      1.84%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              263669                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            90449000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              262090                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            90471500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1734500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1726500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           828323280                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           819732726                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          954014500                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          945419750                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1219623                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1085624                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1510,28 +1525,28 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
index 6320b231e..fcd6df11a 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
@@ -149,7 +149,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -583,7 +583,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -643,7 +643,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -760,6 +760,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -779,29 +780,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -821,6 +829,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -852,9 +861,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
index 70f465dc7..321da6ba3 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:27
-gem5 executing on e108600-lin, pid 39611
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:43
+gem5 executing on e108600-lin, pid 28041
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 37822000 because target called exit()
+Exiting @ tick 41083000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index 5987fdc63..6227dc2b6 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000038                       # Number of seconds simulated
-sim_ticks                                    38282000                       # Number of ticks simulated
-final_tick                                   38282000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000041                       # Number of seconds simulated
+sim_ticks                                    41083000                       # Number of ticks simulated
+final_tick                                   41083000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 159466                       # Simulator instruction rate (inst/s)
-host_op_rate                                   159415                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              951356890                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253388                       # Number of bytes of host memory used
+host_inst_rate                                 172605                       # Simulator instruction rate (inst/s)
+host_op_rate                                   172547                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1105034404                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251288                       # Number of bytes of host memory used
 host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        6413                       # Number of instructions simulated
 sim_ops                                          6413                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     38282000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             23232                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data             10816                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                34048                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           23232                       # Nu
 system.physmem.num_reads::cpu.inst                363                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                169                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   532                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            606864845                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            282534873                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               889399718                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       606864845                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          606864845                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           606864845                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           282534873                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              889399718                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            565489375                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            263271913                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               828761288                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       565489375                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          565489375                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           565489375                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           263271913                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              828761288                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           532                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         532                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        38177000                       # Total gap between requests
+system.physmem.totGap                        40972000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       446                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        83                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       443                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        85                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -187,83 +187,93 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           83                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      377.831325                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     247.256857                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.629090                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             18     21.69%     21.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           20     24.10%     45.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           11     13.25%     59.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           11     13.25%     72.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            3      3.61%     75.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            4      4.82%     80.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      3.61%     84.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            4      4.82%     89.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            9     10.84%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             83                       # Bytes accessed per row activation
-system.physmem.totQLat                        3252000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13227000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           91                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      363.604396                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     235.588514                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     321.826485                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             22     24.18%     24.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           22     24.18%     48.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           13     14.29%     62.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            8      8.79%     71.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            5      5.49%     76.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            4      4.40%     81.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      3.30%     84.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            8      8.79%     93.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            6      6.59%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             91                       # Bytes accessed per row activation
+system.physmem.totQLat                        6580250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  16555250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2660000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6112.78                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       12368.89                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24862.78                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         889.40                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31118.89                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         828.76                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      889.40                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      828.76                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           6.95                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       6.95                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           6.47                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       6.47                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        437                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        436                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.14                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.95                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        71761.28                       # Average gap between requests
-system.physmem.pageHitRate                      82.14                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     234360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     127875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2020200                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        77015.04                       # Average gap between requests
+system.physmem.pageHitRate                      81.95                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     264180                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     136620                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   1956360                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                2034240                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               21270690                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                 184500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 25871865                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              823.813565                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         196750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF         1040000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        30182000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     347760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     189750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1505400                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           3073200.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                3932430                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  68640                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy          13617300                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy            928800                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                 23977530                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              583.625643                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime               32009500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE          39500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF         1300000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN      2418500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT         7463000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     29862000                       # Time in different power states
+system.physmem_1.actEnergy                     421260                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     208725                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1842120                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                2034240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               20078820                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                1230000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 25385970                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              808.341665                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        2146500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF         1040000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        28481000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     38282000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    2005                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1239                       # Number of conditional branches predicted
+system.physmem_1.refreshEnergy           3073200.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                4022490                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 174720                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy          14292750                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy            178080                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                 24213345                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              589.365503                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime               31744250                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE         288500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF         1300000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN       464250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         7679500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN     31350750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                    2003                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1238                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               379                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1607                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups                 1605                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                     377                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             23.459863                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             23.489097                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     235                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 14                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups             336                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectLookups             335                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits                 13                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses              323                       # Number of indirect misses.
+system.cpu.branchPred.indirectMisses              322                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted          113                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
@@ -299,16 +309,16 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        38282000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            76564                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        41083000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            82166                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6413                       # Number of instructions committed
 system.cpu.committedOps                          6413                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                          1095                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              11.938874                       # CPI: cycles per instruction
-system.cpu.ipc                               0.083760                       # IPC: instructions per cycle
+system.cpu.cpi                              12.812412                       # CPI: cycles per instruction
+system.cpu.ipc                               0.078049                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                  19      0.30%      0.30% # Class of committed instruction
 system.cpu.op_class_0::IntAlu                    4331     67.53%     67.83% # Class of committed instruction
 system.cpu.op_class_0::IntMult                      1      0.02%     67.85% # Class of committed instruction
@@ -344,25 +354,25 @@ system.cpu.op_class_0::MemWrite                   868     13.54%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                     6413                       # Class of committed instruction
-system.cpu.tickCycles                           12651                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           63913                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     38282000                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                           12644                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           69522                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           103.736314                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse           103.984752                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1990                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             11.775148                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   103.736314                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.025326                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025326                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   103.984752                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.025387                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025387                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          147                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          151                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.041260                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              4591                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             4591                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     38282000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data         1250                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1250                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          740                       # number of WriteReq hits
@@ -379,14 +389,14 @@ system.cpu.dcache.demand_misses::cpu.data          221                       # n
 system.cpu.dcache.demand_misses::total            221                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          221                       # number of overall misses
 system.cpu.dcache.overall_misses::total           221                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7713000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7713000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      9281000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      9281000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     16994000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     16994000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     16994000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     16994000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      8545500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      8545500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     10429000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     10429000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     18974500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     18974500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     18974500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     18974500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1346                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1346                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
@@ -403,14 +413,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.099955
 system.cpu.dcache.demand_miss_rate::total     0.099955                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.099955                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.099955                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80343.750000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 80343.750000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        74248                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        74248                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 76895.927602                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 76895.927602                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 76895.927602                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 76895.927602                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        83432                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        83432                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 85857.466063                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 85857.466063                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -431,14 +441,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          169
 system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7617000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7617000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5452500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5452500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13069500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     13069500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13069500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     13069500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8449500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      8449500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6089500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6089500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14539000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     14539000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14539000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     14539000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.071322                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.071322                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
@@ -447,31 +457,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076436
 system.cpu.dcache.demand_mshr_miss_rate::total     0.076436                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076436                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.076436                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79343.750000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79343.750000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74691.780822                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74691.780822                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77334.319527                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77334.319527                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77334.319527                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77334.319527                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     38282000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           174.445567                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           175.153182                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                2322                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               364                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              6.379121                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   174.445567                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.085178                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.085178                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   175.153182                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.085524                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.085524                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          364                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          260                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          271                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.177734                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses              5736                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses             5736                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     38282000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst         2322                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            2322                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          2322                       # number of demand (read+write) hits
@@ -484,12 +494,12 @@ system.cpu.icache.demand_misses::cpu.inst          364                       # n
 system.cpu.icache.demand_misses::total            364                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          364                       # number of overall misses
 system.cpu.icache.overall_misses::total           364                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     28460500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     28460500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     28460500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     28460500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     28460500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     28460500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     30317500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     30317500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     30317500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     30317500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     30317500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     30317500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         2686                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         2686                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         2686                       # number of demand (read+write) accesses
@@ -502,12 +512,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.135517
 system.cpu.icache.demand_miss_rate::total     0.135517                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.135517                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.135517                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78188.186813                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 78188.186813                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 78188.186813                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 78188.186813                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 78188.186813                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 78188.186813                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83289.835165                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 83289.835165                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 83289.835165                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 83289.835165                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 83289.835165                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -520,43 +530,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          364
 system.cpu.icache.demand_mshr_misses::total          364                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          364                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          364                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     28096500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     28096500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     28096500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     28096500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     28096500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     28096500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     29953500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     29953500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     29953500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     29953500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     29953500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     29953500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.135517                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.135517                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.135517                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.135517                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.135517                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.135517                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77188.186813                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77188.186813                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77188.186813                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 77188.186813                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77188.186813                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 77188.186813                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     38282000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          278.242026                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          279.180738                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              532                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.001880                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   174.459359                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   103.782667                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005324                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.003167                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.008491                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   175.152793                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   104.027945                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005345                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.003175                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.008520                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          532                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          407                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          422                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.016235                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4796                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4796                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     38282000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -575,18 +585,18 @@ system.cpu.l2cache.demand_misses::total           532                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          363                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          169                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          532                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5343000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5343000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     27539000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     27539000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7471500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      7471500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     27539000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     12814500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     40353500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     27539000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     12814500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     40353500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5980000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5980000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     29396000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     29396000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      8304000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      8304000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     29396000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     14284000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     43680000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     29396000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     14284000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     43680000                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          364                       # number of ReadCleanReq accesses(hits+misses)
@@ -611,18 +621,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.998124                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.997253                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.998124                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73191.780822                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73191.780822                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75865.013774                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75865.013774                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77828.125000                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77828.125000                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75865.013774                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75825.443787                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75852.443609                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75865.013774                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75825.443787                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75852.443609                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80980.716253                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        86500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        86500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80980.716253                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84520.710059                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82105.263158                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82105.263158                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -641,18 +651,18 @@ system.cpu.l2cache.demand_mshr_misses::total          532
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          363                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          532                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4613000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4613000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     23909000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     23909000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6511500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6511500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23909000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11124500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     35033500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23909000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11124500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     35033500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5250000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5250000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     25766000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     25766000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7344000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      7344000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     25766000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     12594000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     38360000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     25766000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     12594000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     38360000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.997253                       # mshr miss rate for ReadCleanReq accesses
@@ -665,25 +675,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.998124
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.997253                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.998124                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63191.780822                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63191.780822                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65865.013774                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65865.013774                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67828.125000                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67828.125000                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65865.013774                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65825.443787                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65852.443609                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65865.013774                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65825.443787                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65852.443609                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        76500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        76500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests          533                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     38282000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           460                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
@@ -709,18 +719,18 @@ system.cpu.toL2Bus.snoop_fanout::min_value            0                       #
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::total            533                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         266500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
+system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        546000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.4                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization          1.3                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        253500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
 system.membus.snoop_filter.tot_requests           532                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     38282000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                459                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
@@ -741,9 +751,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 532                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              608000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2826500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              7.4                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              607500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2825000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              6.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index 81c1646b5..dc66b2c5c 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -591,7 +591,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -708,6 +708,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -727,29 +728,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -769,6 +777,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -800,9 +809,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
index b4b146baf..27b942df1 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:27
-gem5 executing on e108600-lin, pid 39605
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:49
+gem5 executing on e108600-lin, pid 28099
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 22019000 because target called exit()
+Exiting @ tick 23776000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 1341b2242..518b46438 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000022                       # Number of seconds simulated
-sim_ticks                                    22248000                       # Number of ticks simulated
-final_tick                                   22248000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000024                       # Number of seconds simulated
+sim_ticks                                    23776000                       # Number of ticks simulated
+final_tick                                   23776000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 114507                       # Simulator instruction rate (inst/s)
-host_op_rate                                   114481                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              398824007                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 254412                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  93889                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93856                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              349385939                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 252568                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        6385                       # Number of instructions simulated
 sim_ops                                          6385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     22248000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             19968                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data             11072                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                31040                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           19968                       # Nu
 system.physmem.num_reads::cpu.inst                312                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                173                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   485                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            897518878                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            497662711                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1395181589                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       897518878                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          897518878                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           897518878                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           497662711                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1395181589                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            839838493                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            465679677                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1305518170                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       839838493                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          839838493                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           839838493                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           465679677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1305518170                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           485                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         485                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        22109000                       # Total gap between requests
+system.physmem.totGap                        23381000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,11 +91,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       272                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       135                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        55                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       260                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       141                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        52                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        21                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -187,104 +187,115 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           76                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      352.842105                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     230.159600                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     321.021248                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             18     23.68%     23.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           19     25.00%     48.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            9     11.84%     60.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           11     14.47%     75.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            6      7.89%     82.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            1      1.32%     84.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      2.63%     86.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           10     13.16%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             76                       # Bytes accessed per row activation
-system.physmem.totQLat                        4498250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13592000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           89                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      348.044944                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     230.274346                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     313.082327                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             21     23.60%     23.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           22     24.72%     48.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           15     16.85%     65.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            9     10.11%     75.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            6      6.74%     82.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      3.37%     85.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      2.25%     87.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      1.12%     88.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     11.24%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             89                       # Bytes accessed per row activation
+system.physmem.totQLat                        8009750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  17103500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2425000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9274.74                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       16514.95                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28024.74                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1395.18                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  35264.95                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1305.52                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1395.18                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1305.52                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.90                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.90                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.20                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.20                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.73                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.82                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        394                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        395                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.24                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.44                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        45585.57                       # Average gap between requests
-system.physmem.pageHitRate                      81.24                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     196560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     107250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   1645800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        48208.25                       # Average gap between requests
+system.physmem.pageHitRate                      81.44                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     242760                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     125235                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   1763580                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10785825                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  38250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 13790805                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              871.044055                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE          22500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        15303750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     294840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     160875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1255800                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           1843920.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                3005040                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  47520                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy           7623180                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy            132480                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                 14783715                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              621.784975                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime               16957250                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE          40500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN       344500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT         5900500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     16710500                       # Time in different power states
+system.physmem_1.actEnergy                     399840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     212520                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1699320                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10074465                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 662250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 13465350                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              850.487920                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        1034500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14291750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     22248000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    2853                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1680                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               481                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2201                       # Number of BTB lookups
+system.physmem_1.refreshEnergy           1843920.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                2978250                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 130080                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy           7628310                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy             68160                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                 14960400                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              629.216130                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime               16769000                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE         214000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN       178500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         5875500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN     16728000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                    2854                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1681                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               482                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 2203                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                     713                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             32.394366                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     442                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 41                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups             461                       # Number of indirect predictor lookups.
+system.cpu.branchPred.BTBHitPct             32.364957                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     441                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 42                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups             462                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits                 25                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses              436                       # Number of indirect misses.
+system.cpu.branchPred.indirectMisses              437                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted          123                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         2261                       # DTB read hits
+system.cpu.dtb.read_hits                         2252                       # DTB read hits
 system.cpu.dtb.read_misses                         48                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     2309                       # DTB read accesses
-system.cpu.dtb.write_hits                        1039                       # DTB write hits
+system.cpu.dtb.read_accesses                     2300                       # DTB read accesses
+system.cpu.dtb.write_hits                        1038                       # DTB write hits
 system.cpu.dtb.write_misses                        28                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    1067                       # DTB write accesses
-system.cpu.dtb.data_hits                         3300                       # DTB hits
+system.cpu.dtb.write_accesses                    1066                       # DTB write accesses
+system.cpu.dtb.data_hits                         3290                       # DTB hits
 system.cpu.dtb.data_misses                         76                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     3376                       # DTB accesses
-system.cpu.itb.fetch_hits                        2294                       # ITB hits
+system.cpu.dtb.data_accesses                     3366                       # DTB accesses
+system.cpu.itb.fetch_hits                        2295                       # ITB hits
 system.cpu.itb.fetch_misses                        27                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2321                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2322                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -298,236 +309,236 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        22248000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            44497                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        23776000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            47553                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               8475                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          16557                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2853                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1180                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          5121                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1044                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles               8496                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          16559                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2854                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1179                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          5759                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1046                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   22                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           656                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2294                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   333                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14796                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.119019                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.502117                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      2295                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   335                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              15456                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.071364                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.458774                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11808     79.81%     79.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      299      2.02%     81.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      232      1.57%     83.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      257      1.74%     85.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      292      1.97%     87.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      233      1.57%     88.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      283      1.91%     90.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      144      0.97%     91.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1248      8.43%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    12470     80.68%     80.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      297      1.92%     82.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      230      1.49%     84.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      258      1.67%     85.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      292      1.89%     87.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      234      1.51%     89.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      282      1.82%     90.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      146      0.94%     91.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1247      8.07%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14796                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.064117                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.372093                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8328                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  3356                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2449                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   215                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    448                       # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total                15456                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.060017                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.348222                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8339                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  4008                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2446                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   214                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    449                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  226                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                    75                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  15018                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts                  15004                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   221                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    448                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8488                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    1745                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            620                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2480                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1015                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  14460                       # Number of instructions processed by rename
+system.cpu.rename.SquashCycles                    449                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8498                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    1841                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            655                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2476                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1537                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  14448                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     2                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                     21                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LQFullEvents                     10                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                    949                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               10938                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 17913                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            17904                       # Number of integer rename lookups
+system.cpu.rename.SQFullEvents                   1471                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               10929                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 17896                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            17887                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 8                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4577                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     6361                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     6352                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 28                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             22                       # count of temporary serializing insts renamed
 system.cpu.rename.skidInsts                       585                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2839                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1293                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads                 2834                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1292                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                18                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                6                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      13069                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      13054                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  27                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     10787                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                     10776                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                17                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            6710                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3679                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            6695                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3669                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             10                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14796                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.729048                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.467428                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         15456                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.697205                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.442232                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10757     72.70%     72.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1291      8.73%     81.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 918      6.20%     87.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 680      4.60%     92.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 521      3.52%     95.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 349      2.36%     98.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 197      1.33%     99.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  55      0.37%     99.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  28      0.19%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               11416     73.86%     73.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1297      8.39%     82.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 916      5.93%     88.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 681      4.41%     92.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 517      3.34%     95.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 347      2.25%     98.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 200      1.29%     99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  55      0.36%     99.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  27      0.17%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14796                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           15456                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      21     15.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     82     58.57%     73.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    37     26.43%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      21     14.89%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     83     58.87%     73.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    37     26.24%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7188     66.64%     66.65% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     66.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2482     23.01%     89.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1112     10.31%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7185     66.68%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2475     22.97%     89.69% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1111     10.31%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10787                       # Type of FU issued
-system.cpu.iq.rate                           0.242421                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         140                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012979                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              36506                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             19817                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         9751                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  10776                       # Type of FU issued
+system.cpu.iq.rate                           0.226610                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         141                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013085                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              37145                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             19787                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         9745                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  10914                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  10904                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads              119                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1654                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1649                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            8                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           23                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          428                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          427                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            89                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            78                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    448                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1381                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                   302                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               13180                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                    449                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1429                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   338                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               13165                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts               125                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2839                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1293                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts                  2834                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1292                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 27                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      7                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   295                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   331                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             23                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect            107                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          390                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                  497                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 10303                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2309                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               484                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts                 10290                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2300                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               486                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                            84                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3386                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1643                       # Number of branches executed
-system.cpu.iew.exec_stores                       1077                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.231544                       # Inst execution rate
-system.cpu.iew.wb_sent                           9957                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          9761                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      5150                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7013                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.219363                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.734350                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts            6727                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                         3376                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1642                       # Number of branches executed
+system.cpu.iew.exec_stores                       1076                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.216390                       # Inst execution rate
+system.cpu.iew.wb_sent                           9948                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          9755                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      5155                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      7025                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.205140                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.733808                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts            6712                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               407                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13560                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.472124                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.390428                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               408                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        14219                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.450243                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.361136                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11134     82.11%     82.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1157      8.53%     90.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          469      3.46%     94.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          205      1.51%     95.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          133      0.98%     96.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           85      0.63%     97.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           96      0.71%     97.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           89      0.66%     98.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          192      1.42%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        11792     82.93%     82.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1158      8.14%     91.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          469      3.30%     94.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          205      1.44%     95.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          133      0.94%     96.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           85      0.60%     97.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           97      0.68%     98.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           88      0.62%     98.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          192      1.35%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13560                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        14219                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 6402                       # Number of instructions committed
 system.cpu.commit.committedOps                   6402                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -574,47 +585,47 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              6402                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   192                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        26146                       # The number of ROB reads
-system.cpu.rob.rob_writes                       27511                       # The number of ROB writes
+system.cpu.rob.rob_reads                        26790                       # The number of ROB reads
+system.cpu.rob.rob_writes                       27482                       # The number of ROB writes
 system.cpu.timesIdled                             250                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           29701                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           32097                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        6385                       # Number of Instructions Simulated
 system.cpu.committedOps                          6385                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               6.968990                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.968990                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.143493                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.143493                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    12938                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7444                       # number of integer regfile writes
+system.cpu.cpi                               7.447612                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.447612                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.134271                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.134271                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    12923                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7437                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     22248000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           109.756228                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2407                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           110.182603                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2402                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               173                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.913295                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.884393                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   109.756228                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.026796                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.026796                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   110.182603                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.026900                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.026900                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          173                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          129                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.042236                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              6061                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             6061                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     22248000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data         1899                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1899                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              6051                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             6051                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data         1894                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1894                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          508                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            508                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2407                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2407                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2407                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2407                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          2402                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2402                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2402                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2402                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          180                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           180                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          357                       # number of WriteReq misses
@@ -623,43 +634,43 @@ system.cpu.dcache.demand_misses::cpu.data          537                       # n
 system.cpu.dcache.demand_misses::total            537                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          537                       # number of overall misses
 system.cpu.dcache.overall_misses::total           537                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     12910000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     12910000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     24562475                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     24562475                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     37472475                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     37472475                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     37472475                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     37472475                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2079                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2079                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     13953000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     13953000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     31158482                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     31158482                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     45111482                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     45111482                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     45111482                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     45111482                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         2074                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         2074                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2944                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2944                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2944                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2944                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.086580                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.086580                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2939                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2939                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2939                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2939                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.086789                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.086789                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.412717                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.412717                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.182405                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.182405                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.182405                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.182405                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71722.222222                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71722.222222                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68802.450980                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 68802.450980                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 69781.145251                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69781.145251                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 69781.145251                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69781.145251                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         2459                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.182715                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.182715                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.182715                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.182715                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77516.666667                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 77516.666667                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87278.661064                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 87278.661064                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 84006.484171                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 84006.484171                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 84006.484171                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 84006.484171                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         3098                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                43                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                37                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    57.186047                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    83.729730                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           79                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           79                       # number of ReadReq MSHR hits
@@ -677,138 +688,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          173
 system.cpu.dcache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          173                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8568000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      8568000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6031500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6031500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14599500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     14599500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14599500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     14599500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.048581                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.048581                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      9401500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      9401500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      7013500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      7013500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     16415000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     16415000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     16415000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     16415000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.048698                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.048698                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.058764                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.058764                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.058764                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.058764                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84831.683168                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84831.683168                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83770.833333                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83770.833333                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84390.173410                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 84390.173410                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84390.173410                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 84390.173410                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     22248000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.058864                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.058864                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.058864                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.058864                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93084.158416                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93084.158416                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97409.722222                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97409.722222                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94884.393064                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 94884.393064                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94884.393064                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 94884.393064                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           159.084059                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1838                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           160.538154                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1837                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               313                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.872204                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.869010                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   159.084059                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.077678                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.077678                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   160.538154                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.078388                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.078388                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          313                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          187                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.152832                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4901                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4901                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     22248000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         1838                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1838                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1838                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1838                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1838                       # number of overall hits
-system.cpu.icache.overall_hits::total            1838                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          456                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           456                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          456                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            456                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          456                       # number of overall misses
-system.cpu.icache.overall_misses::total           456                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     32999500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     32999500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     32999500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     32999500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     32999500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     32999500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2294                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2294                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2294                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2294                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2294                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2294                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.198779                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.198779                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.198779                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.198779                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.198779                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.198779                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72367.324561                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72367.324561                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72367.324561                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72367.324561                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72367.324561                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72367.324561                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs           56                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses              4903                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4903                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst         1837                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1837                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1837                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1837                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1837                       # number of overall hits
+system.cpu.icache.overall_hits::total            1837                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          458                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           458                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          458                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            458                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          458                       # number of overall misses
+system.cpu.icache.overall_misses::total           458                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     35507500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     35507500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     35507500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     35507500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     35507500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     35507500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2295                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2295                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2295                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2295                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2295                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2295                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.199564                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.199564                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.199564                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.199564                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.199564                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.199564                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77527.292576                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 77527.292576                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 77527.292576                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 77527.292576                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 77527.292576                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 77527.292576                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs           67                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           56                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           67                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          143                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          143                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          143                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          143                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          143                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          143                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          145                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          145                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          145                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          145                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          145                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          145                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          313                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          313                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          313                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          313                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          313                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          313                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24573000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     24573000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24573000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     24573000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24573000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     24573000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.136443                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.136443                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.136443                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.136443                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.136443                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.136443                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78507.987220                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78507.987220                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78507.987220                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 78507.987220                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78507.987220                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 78507.987220                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     22248000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26275500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     26275500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26275500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     26275500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26275500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     26275500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.136383                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.136383                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.136383                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.136383                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.136383                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.136383                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83947.284345                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83947.284345                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83947.284345                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 83947.284345                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83947.284345                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 83947.284345                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          268.962928                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          270.818986                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              485                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002062                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   159.125052                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   109.837876                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004856                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.003352                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.008208                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.559983                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   110.259003                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004900                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.003365                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.008265                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          485                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          180                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          167                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.014801                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4373                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4373                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     22248000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -827,18 +838,18 @@ system.cpu.l2cache.demand_misses::total           485                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          312                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          173                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          485                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5920500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5920500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     24090000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     24090000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      8408000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      8408000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     24090000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     14328500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     38418500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     24090000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     14328500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     38418500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6902500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6902500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25792500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     25792500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      9241500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      9241500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     25792500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     16144000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     41936500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     25792500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     16144000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     41936500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           72                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           72                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          313                       # number of ReadCleanReq accesses(hits+misses)
@@ -863,18 +874,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.997942                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996805                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997942                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82229.166667                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82229.166667                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77211.538462                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77211.538462                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83247.524752                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83247.524752                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77211.538462                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82823.699422                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79213.402062                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77211.538462                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82823.699422                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79213.402062                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        91500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        91500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -893,18 +904,18 @@ system.cpu.l2cache.demand_mshr_misses::total          485
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          312                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          173                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          485                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5200500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5200500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     20970000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     20970000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7398000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      7398000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     20970000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     12598500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     33568500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     20970000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     12598500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     33568500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      6182500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      6182500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22672500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22672500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      8231500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      8231500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22672500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     14414000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     37086500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22672500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     14414000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     37086500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for ReadCleanReq accesses
@@ -917,25 +928,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.997942
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997942                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72229.166667                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72229.166667                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67211.538462                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67211.538462                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73247.524752                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73247.524752                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67211.538462                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72823.699422                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69213.402062                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67211.538462                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72823.699422                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69213.402062                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        81500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        81500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests          486                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     22248000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           414                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           72                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           72                       # Transaction distribution
@@ -961,18 +972,18 @@ system.cpu.toL2Bus.snoop_fanout::min_value            0                       #
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::total            486                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         243000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
+system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        469500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        259500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
 system.membus.snoop_filter.tot_requests           485                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     22248000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                413                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                72                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               72                       # Transaction distribution
@@ -993,9 +1004,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 485                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              591500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2578750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             11.6                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              595000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2572250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             10.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
index b9631a6d8..067911f85 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -249,10 +270,15 @@ children=directory requestToDir responseFromDir responseFromMemory responseToDir
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=6
 eventq_index=0
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestToDir=system.ruby.dir_cntrl0.requestToDir
 responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -311,6 +337,7 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache
 buffer_size=0
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 enable_prefetch=false
 eventq_index=0
 l1_request_latency=2
@@ -319,6 +346,10 @@ l2_select_num_bits=0
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 number_of_TBEs=256
 optionalQueue=system.ruby.l1_cntrl0.optionalQueue
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 prefetcher=system.ruby.l1_cntrl0.prefetcher
 recycle_latency=10
 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
@@ -447,17 +478,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.L1Dcache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.L1Icache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
@@ -480,10 +516,15 @@ L2cache=system.ruby.l2_cntrl0.L2cache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 l2_request_latency=2
 l2_response_latency=2
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
 responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
@@ -574,18 +615,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
 netifs=
 number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
 ruby_system=system.ruby
 topology=Crossbar
@@ -748,42 +794,216 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers18]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers19]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
 weight=1
 
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11
+power_model=Null
 router_id=0
 virt_nets=3
 
@@ -875,8 +1095,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11
+power_model=Null
 router_id=1
 virt_nets=3
 
@@ -968,8 +1194,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11
+power_model=Null
 router_id=2
 virt_nets=3
 
@@ -1061,8 +1293,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17
+power_model=Null
 router_id=3
 virt_nets=3
 
@@ -1195,9 +1433,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
index 838211534..1a88d47ac 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alp
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 22:00:08
-gem5 started Mar 14 2016 22:01:20
-gem5 executing on phenom, pid 28860
-command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
+gem5 compiled Oct 13 2016 20:28:06
+gem5 started Oct 13 2016 20:28:31
+gem5 executing on e108600-lin, pid 8233
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 121535 because target called exit()
+Exiting @ tick 129075 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
index d17f0dc2a..66e7aabe9 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000122                       # Number of seconds simulated
-sim_ticks                                      121535                       # Number of ticks simulated
-final_tick                                     121535                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000129                       # Number of seconds simulated
+sim_ticks                                      129075                       # Number of ticks simulated
+final_tick                                     129075                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  67126                       # Simulator instruction rate (inst/s)
-host_op_rate                                    67120                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1273887                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 453732                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  59192                       # Simulator instruction rate (inst/s)
+host_op_rate                                    59185                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1192972                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 410988                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        93504                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              93504                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0        17728                       # Number of bytes written to this memory
@@ -22,35 +22,35 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1461                       #
 system.mem_ctrls.num_reads::total                1461                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0          277                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                277                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    769358621                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             769358621                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    145867446                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            145867446                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0    915226067                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total            915226067                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    724416037                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             724416037                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    137346504                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            137346504                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    861762541                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            861762541                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1461                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                        277                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1461                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                      277                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  74240                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   19264                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                    5376                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  74368                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   19136                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                    6400                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   93504                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                17728                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    301                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   163                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    299                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   160                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
 system.mem_ctrls.perBankRdBursts::0               102                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                61                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                90                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                90                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4                94                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5                21                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4               101                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5                22                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::7                 4                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 1                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               84                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               78                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::11               75                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::12               26                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::13              395                       # Per bank write bursts
@@ -60,21 +60,21 @@ system.mem_ctrls.perBankWrBursts::0                 0                       # Pe
 system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4                18                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5                 6                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4                24                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5                 7                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::7                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10                3                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10                7                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::11                0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::12                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               16                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               21                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::14               41                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        121448                       # Total gap between requests
+system.mem_ctrls.totGap                        128982                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                  277                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                    1160                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                    1162                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -151,9 +151,9 @@ system.mem_ctrls.wrQLenPdf::26                      6                       # Wh
 system.mem_ctrls.wrQLenPdf::27                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::28                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::29                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                      5                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
@@ -185,88 +185,99 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          217                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    357.751152                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   214.775071                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   343.064988                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           66     30.41%     30.41% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           51     23.50%     53.92% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           17      7.83%     61.75% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           18      8.29%     70.05% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           15      6.91%     76.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            6      2.76%     79.72% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895           12      5.53%     85.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            4      1.84%     87.10% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           28     12.90%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          217                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples            5                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean     150.400000                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean    107.633945                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev     97.202366                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-23             1     20.00%     20.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::72-79             1     20.00%     40.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::200-207            1     20.00%     60.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::208-215            1     20.00%     80.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::240-247            1     20.00%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total             5                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples            5                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.800000                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.771851                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      1.095445                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16                3     60.00%     60.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                2     40.00%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total             5                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         8011                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   30051                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       5800                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         6.91                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples          215                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    364.055814                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   222.075931                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   347.859995                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           60     27.91%     27.91% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           55     25.58%     53.49% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           24     11.16%     64.65% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           15      6.98%     71.63% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639            8      3.72%     75.35% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            9      4.19%     79.53% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            8      3.72%     83.26% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            5      2.33%     85.58% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           31     14.42%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          215                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples            6                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean     193.166667                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean    134.817545                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev    132.906609                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-31             1     16.67%     16.67% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::64-79             1     16.67%     33.33% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::192-207            1     16.67%     50.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::224-239            1     16.67%     66.67% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::240-255            1     16.67%     83.33% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::384-399            1     16.67%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total             6                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples            6                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.666667                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.640671                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      1.032796                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16                4     66.67%     66.67% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                2     33.33%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total             6                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                        15493                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   37571                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       5810                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        13.33                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   25.91                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       610.85                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                        44.23                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    769.36                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    145.87                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   32.33                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       576.16                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                        49.58                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    724.42                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    137.35                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         5.12                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.77                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    0.35                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         4.89                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     4.50                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    0.39                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      22.41                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      943                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                      78                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 81.29                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                68.42                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         69.88                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    80.14                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   506520                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   281400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 5703360                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                 248832                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              7628400                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             65986164                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy             12347400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               92702076                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            791.986980                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        22788                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF          3900                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         92991                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                  1103760                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   613200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 8236800                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                 622080                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              7628400                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             78402132                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              1456200                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               98062572                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            837.783614                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE         1811                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          3900                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT        111353                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.avgWrQLen                      22.78                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      949                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                      91                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 81.67                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                77.78                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         74.21                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    81.31                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   514080                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   270480                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 5380704                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                 258912                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         9834240.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              8608824                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy               320256                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        37409784                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy         6725376                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy          2906400                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               72229056                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            559.589820                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime               109312                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE          366                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          4166                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF         9809                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN        17514                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         15181                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        82039                       # Time in different power states
+system.mem_ctrls_1.actEnergy                  1071000                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   560280                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 7893984                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 576288                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         9834240.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             12597000                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               372480                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        45058272                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy          640512                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               78604056                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            608.979709                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime               100248                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          270                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          4160                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         1668                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         24165                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        98812                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -301,8 +312,8 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON          121535                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                           121535                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON          129075                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                           129075                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6403                       # Number of instructions committed
@@ -321,7 +332,7 @@ system.cpu.num_mem_refs                          2060                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     121535                       # Number of busy cycles
+system.cpu.num_busy_cycles                     129075                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1056                       # Number of branches fetched
@@ -361,13 +372,13 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       6413                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   9652                       # delay histogram for all message
-system.ruby.delayHist::mean                  0.164525                       # delay histogram for all message
-system.ruby.delayHist::stdev                 1.011525                       # delay histogram for all message
-system.ruby.delayHist                    |        9293     96.28%     96.28% |           0      0.00%     96.28% |         214      2.22%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |         145      1.50%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::mean                  0.163697                       # delay histogram for all message
+system.ruby.delayHist::stdev                 1.010840                       # delay histogram for all message
+system.ruby.delayHist                    |        9297     96.32%     96.32% |           0      0.00%     96.32% |         210      2.18%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |         145      1.50%    100.00% |           0      0.00%    100.00% # delay histogram for all message
 system.ruby.delayHist::total                     9652                       # delay histogram for all message
 system.ruby.outstanding_req_hist_seqr::bucket_size            1                      
 system.ruby.outstanding_req_hist_seqr::max_bucket            9                      
@@ -379,10 +390,10 @@ system.ruby.outstanding_req_hist_seqr::total         8464
 system.ruby.latency_hist_seqr::bucket_size           64                      
 system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples           8463                      
-system.ruby.latency_hist_seqr::mean         13.360747                      
-system.ruby.latency_hist_seqr::gmean         2.097350                      
-system.ruby.latency_hist_seqr::stdev        29.565169                      
-system.ruby.latency_hist_seqr            |        7303     86.29%     86.29% |        1141     13.48%     99.78% |           4      0.05%     99.82% |           1      0.01%     99.83% |           8      0.09%     99.93% |           6      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean         14.251684                      
+system.ruby.latency_hist_seqr::gmean         2.119385                      
+system.ruby.latency_hist_seqr::stdev        32.289040                      
+system.ruby.latency_hist_seqr            |        7301     86.27%     86.27% |        1142     13.49%     99.76% |           3      0.04%     99.80% |           1      0.01%     99.81% |           6      0.07%     99.88% |           9      0.11%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           1      0.01%    100.00%
 system.ruby.latency_hist_seqr::total             8463                      
 system.ruby.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.hit_latency_hist_seqr::max_bucket            9                      
@@ -394,12 +405,12 @@ system.ruby.hit_latency_hist_seqr::total         6972
 system.ruby.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.miss_latency_hist_seqr::samples         1491                      
-system.ruby.miss_latency_hist_seqr::mean    71.160295                      
-system.ruby.miss_latency_hist_seqr::gmean    66.961050                      
-system.ruby.miss_latency_hist_seqr::stdev    30.103565                      
-system.ruby.miss_latency_hist_seqr       |         331     22.20%     22.20% |        1141     76.53%     98.73% |           4      0.27%     98.99% |           1      0.07%     99.06% |           8      0.54%     99.60% |           6      0.40%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    76.217304                      
+system.ruby.miss_latency_hist_seqr::gmean    71.053455                      
+system.ruby.miss_latency_hist_seqr::stdev    35.454362                      
+system.ruby.miss_latency_hist_seqr       |         329     22.07%     22.07% |        1142     76.59%     98.66% |           3      0.20%     98.86% |           1      0.07%     98.93% |           6      0.40%     99.33% |           9      0.60%     99.93% |           0      0.00%     99.93% |           0      0.00%     99.93% |           0      0.00%     99.93% |           1      0.07%    100.00%
 system.ruby.miss_latency_hist_seqr::total         1491                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.L1Dcache.demand_hits         1250                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          800                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2050                       # Number of cache demand accesses
@@ -415,15 +426,15 @@ system.ruby.l1_cntrl0.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
 system.ruby.l2_cntrl0.L2cache.demand_hits           30                       # Number of cache demand hits
 system.ruby.l2_cntrl0.L2cache.demand_misses         1461                       # Number of cache demand misses
 system.ruby.l2_cntrl0.L2cache.demand_accesses         1491                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     4.310281                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     4.058493                      
 system.ruby.network.routers0.msg_count.Control::0         1491                      
 system.ruby.network.routers0.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers0.msg_count.Response_Data::1         1491                      
@@ -440,8 +451,8 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2         6400
 system.ruby.network.routers0.msg_bytes.Writeback_Data::0        10440                      
 system.ruby.network.routers0.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::0         2336                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     8.369194                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     7.880302                      
 system.ruby.network.routers1.msg_count.Control::0         2952                      
 system.ruby.network.routers1.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers1.msg_count.Response_Data::1         3229                      
@@ -458,16 +469,16 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2         6400
 system.ruby.network.routers1.msg_bytes.Writeback_Data::0        10440                      
 system.ruby.network.routers1.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::0         2336                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     4.058913                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     3.821809                      
 system.ruby.network.routers2.msg_count.Control::0         1461                      
 system.ruby.network.routers2.msg_count.Response_Data::1         1738                      
 system.ruby.network.routers2.msg_count.Response_Control::1         2629                      
 system.ruby.network.routers2.msg_bytes.Control::0        11688                      
 system.ruby.network.routers2.msg_bytes.Response_Data::1       125136                      
 system.ruby.network.routers2.msg_bytes.Response_Control::1        21032                      
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized     5.579463                      
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized     5.253535                      
 system.ruby.network.routers3.msg_count.Control::0         2952                      
 system.ruby.network.routers3.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers3.msg_count.Response_Data::1         3229                      
@@ -484,7 +495,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2         6400
 system.ruby.network.routers3.msg_bytes.Writeback_Data::0        10440                      
 system.ruby.network.routers3.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::0         2336                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Control            8856                      
 system.ruby.network.msg_count.Request_Control         3123                      
 system.ruby.network.msg_count.Response_Data         9687                      
@@ -497,15 +508,15 @@ system.ruby.network.msg_byte.Response_Data       697464
 system.ruby.network.msg_byte.Response_Control       114384                      
 system.ruby.network.msg_byte.Writeback_Data        61776                      
 system.ruby.network.msg_byte.Writeback_Control         7008                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED       121535                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     6.128687                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED       129075                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     5.770676                      
 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1         1491                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Control::1          437                      
 system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2         8328                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1       107352                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1         3496                      
-system.ruby.network.routers0.throttle1.link_utilization     2.491875                      
+system.ruby.network.routers0.throttle1.link_utilization     2.346310                      
 system.ruby.network.routers0.throttle1.msg_count.Control::0         1491                      
 system.ruby.network.routers0.throttle1.msg_count.Response_Control::1          900                      
 system.ruby.network.routers0.throttle1.msg_count.Response_Control::2          800                      
@@ -518,7 +529,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2         640
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0        10440                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0         2336                      
-system.ruby.network.routers1.throttle0.link_utilization     8.499198                      
+system.ruby.network.routers1.throttle0.link_utilization     8.002712                      
 system.ruby.network.routers1.throttle0.msg_count.Control::0         1491                      
 system.ruby.network.routers1.throttle0.msg_count.Response_Data::1         1461                      
 system.ruby.network.routers1.throttle0.msg_count.Response_Control::1         2353                      
@@ -533,7 +544,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2         640
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0        10440                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0         2336                      
-system.ruby.network.routers1.throttle1.link_utilization     8.239190                      
+system.ruby.network.routers1.throttle1.link_utilization     7.757893                      
 system.ruby.network.routers1.throttle1.msg_count.Control::0         1461                      
 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::1         1768                      
@@ -542,26 +553,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0        11688
 system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2         8328                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1       127296                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1        12904                      
-system.ruby.network.routers2.throttle0.link_utilization     2.110503                      
+system.ruby.network.routers2.throttle0.link_utilization     1.987217                      
 system.ruby.network.routers2.throttle0.msg_count.Control::0         1461                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::1          277                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Control::1         1176                      
 system.ruby.network.routers2.throttle0.msg_bytes.Control::0        11688                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1        19944                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1         9408                      
-system.ruby.network.routers2.throttle1.link_utilization     6.007323                      
+system.ruby.network.routers2.throttle1.link_utilization     5.656401                      
 system.ruby.network.routers2.throttle1.msg_count.Response_Data::1         1461                      
 system.ruby.network.routers2.throttle1.msg_count.Response_Control::1         1453                      
 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1       105192                      
 system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1        11624                      
-system.ruby.network.routers3.throttle0.link_utilization     6.128687                      
+system.ruby.network.routers3.throttle0.link_utilization     5.770676                      
 system.ruby.network.routers3.throttle0.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Data::1         1491                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Control::1          437                      
 system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2         8328                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1       107352                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1         3496                      
-system.ruby.network.routers3.throttle1.link_utilization     8.499198                      
+system.ruby.network.routers3.throttle1.link_utilization     8.002712                      
 system.ruby.network.routers3.throttle1.msg_count.Control::0         1491                      
 system.ruby.network.routers3.throttle1.msg_count.Response_Data::1         1461                      
 system.ruby.network.routers3.throttle1.msg_count.Response_Control::1         2353                      
@@ -576,7 +587,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2         640
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0        10440                      
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0         2336                      
-system.ruby.network.routers3.throttle2.link_utilization     2.110503                      
+system.ruby.network.routers3.throttle2.link_utilization     1.987217                      
 system.ruby.network.routers3.throttle2.msg_count.Control::0         1461                      
 system.ruby.network.routers3.throttle2.msg_count.Response_Data::1          277                      
 system.ruby.network.routers3.throttle2.msg_count.Response_Control::1         1176                      
@@ -593,9 +604,9 @@ system.ruby.delayVCHist.vnet_0::total            2728                       # de
 system.ruby.delayVCHist.vnet_1::bucket_size            1                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket            9                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::samples          5883                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         0.072752                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        0.374480                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |        5669     96.36%     96.36% |           0      0.00%     96.36% |         214      3.64%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         0.071392                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        0.371094                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |        5673     96.43%     96.43% |           0      0.00%     96.43% |         210      3.57%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::total            5883                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
@@ -605,10 +616,10 @@ system.ruby.delayVCHist.vnet_2::total            1041                       # de
 system.ruby.LD.latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.latency_hist_seqr::samples         1185                      
-system.ruby.LD.latency_hist_seqr::mean      33.565401                      
-system.ruby.LD.latency_hist_seqr::gmean      7.686795                      
-system.ruby.LD.latency_hist_seqr::stdev     38.515936                      
-system.ruby.LD.latency_hist_seqr         |         803     67.76%     67.76% |         378     31.90%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           3      0.25%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      36.416034                      
+system.ruby.LD.latency_hist_seqr::gmean      7.907367                      
+system.ruby.LD.latency_hist_seqr::stdev     46.041898                      
+system.ruby.LD.latency_hist_seqr         |         802     67.68%     67.68% |         375     31.65%     99.32% |           1      0.08%     99.41% |           0      0.00%     99.41% |           3      0.25%     99.66% |           3      0.25%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |           1      0.08%    100.00%
 system.ruby.LD.latency_hist_seqr::total          1185                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
@@ -620,18 +631,18 @@ system.ruby.LD.hit_latency_hist_seqr::total          601
 system.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.miss_latency_hist_seqr::samples          584                      
-system.ruby.LD.miss_latency_hist_seqr::mean    67.078767                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    62.700967                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    28.185747                      
-system.ruby.LD.miss_latency_hist_seqr    |         202     34.59%     34.59% |         378     64.73%     99.32% |           0      0.00%     99.32% |           0      0.00%     99.32% |           3      0.51%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    72.863014                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    66.405671                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    41.005857                      
+system.ruby.LD.miss_latency_hist_seqr    |         201     34.42%     34.42% |         375     64.21%     98.63% |           1      0.17%     98.80% |           0      0.00%     98.80% |           3      0.51%     99.32% |           3      0.51%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           1      0.17%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          584                      
-system.ruby.ST.latency_hist_seqr::bucket_size           64                      
-system.ruby.ST.latency_hist_seqr::max_bucket          639                      
+system.ruby.ST.latency_hist_seqr::bucket_size           16                      
+system.ruby.ST.latency_hist_seqr::max_bucket          159                      
 system.ruby.ST.latency_hist_seqr::samples          865                      
-system.ruby.ST.latency_hist_seqr::mean      15.551445                      
-system.ruby.ST.latency_hist_seqr::gmean      2.706248                      
-system.ruby.ST.latency_hist_seqr::stdev     29.831548                      
-system.ruby.ST.latency_hist_seqr         |         773     89.36%     89.36% |          90     10.40%     99.77% |           0      0.00%     99.77% |           0      0.00%     99.77% |           1      0.12%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::mean      15.646243                      
+system.ruby.ST.latency_hist_seqr::gmean      2.719887                      
+system.ruby.ST.latency_hist_seqr::stdev     27.764380                      
+system.ruby.ST.latency_hist_seqr         |         649     75.03%     75.03% |          12      1.39%     76.42% |         101     11.68%     88.09% |          10      1.16%     89.25% |          36      4.16%     93.41% |          52      6.01%     99.42% |           4      0.46%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist_seqr::total           865                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
@@ -640,21 +651,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean            1
 system.ruby.ST.hit_latency_hist_seqr::gmean            1                      
 system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |         649    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.hit_latency_hist_seqr::total          649                      
-system.ruby.ST.miss_latency_hist_seqr::bucket_size           64                      
-system.ruby.ST.miss_latency_hist_seqr::max_bucket          639                      
+system.ruby.ST.miss_latency_hist_seqr::bucket_size           16                      
+system.ruby.ST.miss_latency_hist_seqr::max_bucket          159                      
 system.ruby.ST.miss_latency_hist_seqr::samples          216                      
-system.ruby.ST.miss_latency_hist_seqr::mean    59.273148                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    53.885554                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    31.884011                      
-system.ruby.ST.miss_latency_hist_seqr    |         124     57.41%     57.41% |          90     41.67%     99.07% |           0      0.00%     99.07% |           0      0.00%     99.07% |           1      0.46%     99.54% |           1      0.46%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean    59.652778                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    54.981344                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    22.464955                      
+system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |          12      5.56%      5.56% |         101     46.76%     52.31% |          10      4.63%     56.94% |          36     16.67%     73.61% |          52     24.07%     97.69% |           4      1.85%     99.54% |           1      0.46%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total          216                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples         6413                      
-system.ruby.IFETCH.latency_hist_seqr::mean     9.331826                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.594079                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    25.833878                      
-system.ruby.IFETCH.latency_hist_seqr     |        5727     89.30%     89.30% |         673     10.49%     99.80% |           4      0.06%     99.86% |           1      0.02%     99.88% |           4      0.06%     99.94% |           4      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     9.968034                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.606700                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    27.770381                      
+system.ruby.IFETCH.latency_hist_seqr     |        5727     89.30%     89.30% |         674     10.51%     99.81% |           2      0.03%     99.84% |           1      0.02%     99.86% |           3      0.05%     99.91% |           6      0.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         6413                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
@@ -666,10 +677,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total         5722
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          691                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    78.325615                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    75.760449                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    29.311514                      
-system.ruby.IFETCH.miss_latency_hist_seqr |           5      0.72%      0.72% |         673     97.40%     98.12% |           4      0.58%     98.70% |           1      0.14%     98.84% |           4      0.58%     99.42% |           4      0.58%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    84.230101                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    81.513388                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    31.252511                      
+system.ruby.IFETCH.miss_latency_hist_seqr |           5      0.72%      0.72% |         674     97.54%     98.26% |           2      0.29%     98.55% |           1      0.14%     98.70% |           3      0.43%     99.13% |           6      0.87%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          691                      
 system.ruby.Directory_Controller.Fetch           1461      0.00%      0.00%
 system.ruby.Directory_Controller.Data             277      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 7127384c1..2e87336b3 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -249,11 +270,16 @@ children=directory forwardFromDir requestToDir responseFromDir responseFromMemor
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=6
 eventq_index=0
 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestToDir=system.ruby.dir_cntrl0.requestToDir
 responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -320,10 +346,15 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache
 buffer_size=0
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 l2_select_num_bits=0
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
 requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache
@@ -433,17 +464,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.L1Dcache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.L1Icache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
@@ -466,8 +502,13 @@ L2cache=system.ruby.l2_cntrl0.L2cache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 request_latency=2
 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
@@ -566,18 +607,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
 netifs=
 number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
 ruby_system=system.ruby
 topology=Crossbar
@@ -740,42 +786,216 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers18]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers19]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
 weight=1
 
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11
+power_model=Null
 router_id=0
 virt_nets=3
 
@@ -867,8 +1087,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11
+power_model=Null
 router_id=1
 virt_nets=3
 
@@ -960,8 +1186,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11
+power_model=Null
 router_id=2
 virt_nets=3
 
@@ -1053,8 +1285,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17
+power_model=Null
 router_id=3
 virt_nets=3
 
@@ -1187,9 +1425,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index c750cc80b..3faf7299f 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hell
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 22:01:23
-gem5 started Mar 14 2016 22:02:29
-gem5 executing on phenom, pid 29128
-command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled Oct 13 2016 20:30:58
+gem5 started Oct 13 2016 20:31:25
+gem5 executing on e108600-lin, pid 17789
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 108878 because target called exit()
+Exiting @ tick 115948 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 99bf8d33d..0d7120e11 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000109                       # Number of seconds simulated
-sim_ticks                                      108878                       # Number of ticks simulated
-final_tick                                     108878                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000116                       # Number of seconds simulated
+sim_ticks                                      115948                       # Number of ticks simulated
+final_tick                                     115948                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66441                       # Simulator instruction rate (inst/s)
-host_op_rate                                    66435                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1129573                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 461124                       # Number of bytes of host memory used
+host_inst_rate                                  62775                       # Simulator instruction rate (inst/s)
+host_op_rate                                    62768                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1136521                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 416956                       # Number of bytes of host memory used
 host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        75712                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              75712                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0        12416                       # Number of bytes written to this memory
@@ -22,29 +22,29 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1183                       #
 system.mem_ctrls.num_reads::total                1183                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0          194                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                194                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    695383824                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             695383824                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    114035893                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            114035893                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0    809419717                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total            809419717                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    652982371                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             652982371                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    107082485                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            107082485                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    760064857                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            760064857                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1183                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                        194                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1183                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                      194                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  64576                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   11136                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                    5504                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  65152                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   10560                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                    5440                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   75712                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                12416                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    174                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                    81                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    165                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                    79                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
 system.mem_ctrls.perBankRdBursts::0                83                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                51                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                81                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                75                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4                94                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4                99                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                18                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 2                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::7                 3                       # Per bank write bursts
@@ -53,15 +53,15 @@ system.mem_ctrls.perBankRdBursts::9                 1                       # Pe
 system.mem_ctrls.perBankRdBursts::10               56                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::11               51                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::12               21                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13              365                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14               67                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13              367                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14               69                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15               41                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::0                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4                18                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5                 6                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4                19                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::7                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
@@ -69,12 +69,12 @@ system.mem_ctrls.perBankWrBursts::9                 0                       # Pe
 system.mem_ctrls.perBankWrBursts::10                3                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::11                0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::12                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               18                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14               41                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               20                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14               43                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        108826                       # Total gap between requests
+system.mem_ctrls.totGap                        115890                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                  194                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                    1009                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                    1018                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -136,21 +136,21 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      4                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      3                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::16                      4                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                      4                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::18                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::19                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::20                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::21                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::22                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                      7                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::24                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::25                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                      5                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::30                      5                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::31                      5                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::32                      5                       # What write queue length does an incoming req see
@@ -185,88 +185,99 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          203                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    334.817734                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   202.715946                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   328.878595                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           65     32.02%     32.02% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           47     23.15%     55.17% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           25     12.32%     67.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           11      5.42%     72.91% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           11      5.42%     78.33% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767           10      4.93%     83.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            5      2.46%     85.71% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            8      3.94%     89.66% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           21     10.34%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          203                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples          208                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    330.153846                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   204.681326                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   325.358480                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           61     29.33%     29.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           54     25.96%     55.29% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           30     14.42%     69.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511            9      4.33%     74.04% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           16      7.69%     81.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            5      2.40%     84.13% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            5      2.40%     86.54% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            4      1.92%     88.46% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           24     11.54%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          208                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples            5                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean     138.600000                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean    101.703151                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev     85.219129                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean     142.600000                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean    108.227176                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev     79.531755                       # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::16-23             1     20.00%     20.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-87             1     20.00%     40.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::168-175            1     20.00%     60.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::192-199            1     20.00%     80.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::128-135            1     20.00%     40.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::136-143            1     20.00%     60.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::200-207            1     20.00%     80.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::216-223            1     20.00%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::total             5                       # Reads before turning the bus around for writes
 system.mem_ctrls.wrPerTurnAround::samples            5                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      17.200000                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     17.171629                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      1.095445                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean             17                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.976446                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev             1                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::16                2     40.00%     40.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                3     60.00%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                1     20.00%     60.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                2     40.00%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total             5                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         7036                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   26207                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       5045                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         6.97                       # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat                        13845                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   33187                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       5090                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        13.60                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   25.97                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       593.10                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                        50.55                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    695.38                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    114.04                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   32.60                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       561.91                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                        46.92                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    652.98                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    107.08                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         5.03                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.63                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    0.39                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         4.76                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     4.39                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    0.37                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      21.05                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      806                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                      80                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 79.88                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                70.80                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         79.03                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    78.97                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   529200                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   294000                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 5004480                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                 248832                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              6611280                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             61961508                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy              6534600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               81183900                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            800.014782                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        16245                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF          3380                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         87571                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                   907200                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   504000                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 6764160                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                 642816                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              6611280                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             67902048                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              1323600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               84655104                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            834.221250                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE         1730                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          3380                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         96382                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.avgWrQLen                      21.83                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      811                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                      78                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 79.67                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                67.83                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         84.16                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    78.46                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   528360                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   278208                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 4706688                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                 158688                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         9219600.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              8177904                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy               299520                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        33992976                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy         6547200                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy          1905360                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               65814504                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            567.620865                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                97183                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE          354                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          3906                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF         5638                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN        17050                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         14454                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        74546                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   999600                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   525504                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 6922944                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 551232                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         8604960.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             10734696                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               319488                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        40821120                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy          789120                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               70268664                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            606.036016                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                91295                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          272                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          3640                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         2055                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         20461                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        89520                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -301,8 +312,8 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON          108878                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                           108878                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON          115948                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                           115948                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6403                       # Number of instructions committed
@@ -321,7 +332,7 @@ system.cpu.num_mem_refs                          2060                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     108878                       # Number of busy cycles
+system.cpu.num_busy_cycles                     115948                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1056                       # Number of branches fetched
@@ -361,7 +372,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       6413                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
 system.ruby.outstanding_req_hist_seqr::bucket_size            1                      
 system.ruby.outstanding_req_hist_seqr::max_bucket            9                      
 system.ruby.outstanding_req_hist_seqr::samples         8464                      
@@ -372,10 +383,10 @@ system.ruby.outstanding_req_hist_seqr::total         8464
 system.ruby.latency_hist_seqr::bucket_size           64                      
 system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples           8463                      
-system.ruby.latency_hist_seqr::mean         11.865178                      
-system.ruby.latency_hist_seqr::gmean         1.973283                      
-system.ruby.latency_hist_seqr::stdev        27.863065                      
-system.ruby.latency_hist_seqr            |        7453     88.07%     88.07% |         995     11.76%     99.82% |           2      0.02%     99.85% |           0      0.00%     99.85% |           9      0.11%     99.95% |           4      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean         12.700579                      
+system.ruby.latency_hist_seqr::gmean         1.992540                      
+system.ruby.latency_hist_seqr::stdev        30.668579                      
+system.ruby.latency_hist_seqr            |        7444     87.96%     87.96% |        1001     11.83%     99.79% |           3      0.04%     99.82% |           0      0.00%     99.82% |           6      0.07%     99.89% |           8      0.09%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           1      0.01%    100.00%
 system.ruby.latency_hist_seqr::total             8463                      
 system.ruby.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.hit_latency_hist_seqr::max_bucket            9                      
@@ -387,27 +398,27 @@ system.ruby.hit_latency_hist_seqr::total         7041
 system.ruby.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.miss_latency_hist_seqr::samples         1422                      
-system.ruby.miss_latency_hist_seqr::mean    65.663854                      
-system.ruby.miss_latency_hist_seqr::gmean    57.123275                      
-system.ruby.miss_latency_hist_seqr::stdev    33.791401                      
-system.ruby.miss_latency_hist_seqr       |         412     28.97%     28.97% |         995     69.97%     98.95% |           2      0.14%     99.09% |           0      0.00%     99.09% |           9      0.63%     99.72% |           4      0.28%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    70.635724                      
+system.ruby.miss_latency_hist_seqr::gmean    60.522119                      
+system.ruby.miss_latency_hist_seqr::stdev    39.545085                      
+system.ruby.miss_latency_hist_seqr       |         403     28.34%     28.34% |        1001     70.39%     98.73% |           3      0.21%     98.95% |           0      0.00%     98.95% |           6      0.42%     99.37% |           8      0.56%     99.93% |           0      0.00%     99.93% |           0      0.00%     99.93% |           0      0.00%     99.93% |           1      0.07%    100.00%
 system.ruby.miss_latency_hist_seqr::total         1422                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.L1Dcache.demand_hits         1274                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          776                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2050                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits         5767                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses          646                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses         6413                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
 system.ruby.l2_cntrl0.L2cache.demand_hits          239                       # Number of cache demand hits
 system.ruby.l2_cntrl0.L2cache.demand_misses         1183                       # Number of cache demand misses
 system.ruby.l2_cntrl0.L2cache.demand_accesses         1422                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     6.929545                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     6.507012                      
 system.ruby.network.routers0.msg_count.Request_Control::0         1422                      
 system.ruby.network.routers0.msg_count.Response_Data::2         1183                      
 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2          239                      
@@ -420,8 +431,8 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2        17208
 system.ruby.network.routers0.msg_bytes.Writeback_Data::2        94248                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::0        21680                      
 system.ruby.network.routers0.msg_bytes.Unblock_Control::2        11744                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized    10.407520                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     9.772915                      
 system.ruby.network.routers1.msg_count.Request_Control::0         1422                      
 system.ruby.network.routers1.msg_count.Request_Control::1         1183                      
 system.ruby.network.routers1.msg_count.Response_Data::2         2366                      
@@ -438,8 +449,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2       108216
 system.ruby.network.routers1.msg_bytes.Writeback_Control::0        21680                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::1         3104                      
 system.ruby.network.routers1.msg_bytes.Unblock_Control::2        21208                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     3.477975                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     3.265904                      
 system.ruby.network.routers2.msg_count.Request_Control::1         1183                      
 system.ruby.network.routers2.msg_count.Response_Data::2         1183                      
 system.ruby.network.routers2.msg_count.Writeback_Data::2          194                      
@@ -450,8 +461,8 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2        85176
 system.ruby.network.routers2.msg_bytes.Writeback_Data::2        13968                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::1         3104                      
 system.ruby.network.routers2.msg_bytes.Unblock_Control::2         9464                      
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized     6.938347                      
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized     6.515277                      
 system.ruby.network.routers3.msg_count.Request_Control::0         1422                      
 system.ruby.network.routers3.msg_count.Request_Control::1         1183                      
 system.ruby.network.routers3.msg_count.Response_Data::2         2366                      
@@ -468,7 +479,7 @@ system.ruby.network.routers3.msg_bytes.Writeback_Data::2       108216
 system.ruby.network.routers3.msg_bytes.Writeback_Control::0        21680                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::1         3104                      
 system.ruby.network.routers3.msg_bytes.Unblock_Control::2        21208                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Request_Control         7815                      
 system.ruby.network.msg_count.Response_Data         7098                      
 system.ruby.network.msg_count.ResponseL2hit_Data          717                      
@@ -481,15 +492,15 @@ system.ruby.network.msg_byte.ResponseL2hit_Data        51624
 system.ruby.network.msg_byte.Writeback_Data       324648                      
 system.ruby.network.msg_byte.Writeback_Control        74352                      
 system.ruby.network.msg_byte.Unblock_Control        63624                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED       108878                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     6.499476                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED       115948                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     6.103167                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2         1183                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2          239                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0         1355                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2        85176                      
 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2        17208                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0        10840                      
-system.ruby.network.routers0.throttle1.link_utilization     7.359614                      
+system.ruby.network.routers0.throttle1.link_utilization     6.910857                      
 system.ruby.network.routers0.throttle1.msg_count.Request_Control::0         1422                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2         1309                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0         1355                      
@@ -498,7 +509,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0        11376
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2        94248                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0        10840                      
 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2        11744                      
-system.ruby.network.routers1.throttle0.link_utilization    12.338122                      
+system.ruby.network.routers1.throttle0.link_utilization    11.585797                      
 system.ruby.network.routers1.throttle0.msg_count.Request_Control::0         1422                      
 system.ruby.network.routers1.throttle0.msg_count.Response_Data::2         1183                      
 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2         1309                      
@@ -511,7 +522,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2        94248
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0        10840                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1         1552                      
 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2        11744                      
-system.ruby.network.routers1.throttle1.link_utilization     8.476919                      
+system.ruby.network.routers1.throttle1.link_utilization     7.960034                      
 system.ruby.network.routers1.throttle1.msg_count.Request_Control::1         1183                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::2         1183                      
 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2          239                      
@@ -526,7 +537,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2        13968
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0        10840                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1         1552                      
 system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2         9464                      
-system.ruby.network.routers2.throttle0.link_utilization     1.977443                      
+system.ruby.network.routers2.throttle0.link_utilization     1.856867                      
 system.ruby.network.routers2.throttle0.msg_count.Request_Control::1         1183                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2          194                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1          194                      
@@ -535,19 +546,19 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1         9464
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2        13968                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1         1552                      
 system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2         9464                      
-system.ruby.network.routers2.throttle1.link_utilization     4.978508                      
+system.ruby.network.routers2.throttle1.link_utilization     4.674940                      
 system.ruby.network.routers2.throttle1.msg_count.Response_Data::2         1183                      
 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1          194                      
 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2        85176                      
 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1         1552                      
-system.ruby.network.routers3.throttle0.link_utilization     6.499476                      
+system.ruby.network.routers3.throttle0.link_utilization     6.103167                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Data::2         1183                      
 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2          239                      
 system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0         1355                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2        85176                      
 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2        17208                      
 system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0        10840                      
-system.ruby.network.routers3.throttle1.link_utilization    12.338122                      
+system.ruby.network.routers3.throttle1.link_utilization    11.585797                      
 system.ruby.network.routers3.throttle1.msg_count.Request_Control::0         1422                      
 system.ruby.network.routers3.throttle1.msg_count.Response_Data::2         1183                      
 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2         1309                      
@@ -560,7 +571,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2        94248
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0        10840                      
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1         1552                      
 system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2        11744                      
-system.ruby.network.routers3.throttle2.link_utilization     1.977443                      
+system.ruby.network.routers3.throttle2.link_utilization     1.856867                      
 system.ruby.network.routers3.throttle2.msg_count.Request_Control::1         1183                      
 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2          194                      
 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1          194                      
@@ -569,13 +580,13 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1         9464
 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2        13968                      
 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1         1552                      
 system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2         9464                      
-system.ruby.LD.latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.latency_hist_seqr::samples         1185                      
-system.ruby.LD.latency_hist_seqr::mean      27.428692                      
-system.ruby.LD.latency_hist_seqr::gmean      5.747000                      
-system.ruby.LD.latency_hist_seqr::stdev     36.091782                      
-system.ruby.LD.latency_hist_seqr         |         775     65.40%     65.40% |          87      7.34%     72.74% |         279     23.54%     96.29% |          40      3.38%     99.66% |           1      0.08%     99.75% |           1      0.08%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           1      0.08%     99.92% |           1      0.08%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      29.289451                      
+system.ruby.LD.latency_hist_seqr::gmean      5.875383                      
+system.ruby.LD.latency_hist_seqr::stdev     39.627102                      
+system.ruby.LD.latency_hist_seqr         |         857     72.32%     72.32% |         323     27.26%     99.58% |           2      0.17%     99.75% |           0      0.00%     99.75% |           1      0.08%     99.83% |           2      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_seqr::total          1185                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
@@ -584,21 +595,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean            1
 system.ruby.LD.hit_latency_hist_seqr::gmean            1                      
 system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |         659    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.hit_latency_hist_seqr::total          659                      
-system.ruby.LD.miss_latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.miss_latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.miss_latency_hist_seqr::samples          526                      
-system.ruby.LD.miss_latency_hist_seqr::mean    60.539924                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    51.393520                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    31.024435                      
-system.ruby.LD.miss_latency_hist_seqr    |         116     22.05%     22.05% |          87     16.54%     38.59% |         279     53.04%     91.63% |          40      7.60%     99.24% |           1      0.19%     99.43% |           1      0.19%     99.62% |           0      0.00%     99.62% |           0      0.00%     99.62% |           1      0.19%     99.81% |           1      0.19%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    64.731939                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    54.016248                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    35.753260                      
+system.ruby.LD.miss_latency_hist_seqr    |         198     37.64%     37.64% |         323     61.41%     99.05% |           2      0.38%     99.43% |           0      0.00%     99.43% |           1      0.19%     99.62% |           2      0.38%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          526                      
 system.ruby.ST.latency_hist_seqr::bucket_size           64                      
 system.ruby.ST.latency_hist_seqr::max_bucket          639                      
 system.ruby.ST.latency_hist_seqr::samples          865                      
-system.ruby.ST.latency_hist_seqr::mean      17.057803                      
-system.ruby.ST.latency_hist_seqr::gmean      3.071194                      
-system.ruby.ST.latency_hist_seqr::stdev     31.094076                      
-system.ruby.ST.latency_hist_seqr         |         753     87.05%     87.05% |         110     12.72%     99.77% |           0      0.00%     99.77% |           0      0.00%     99.77% |           1      0.12%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::mean      17.729480                      
+system.ruby.ST.latency_hist_seqr::gmean      3.104775                      
+system.ruby.ST.latency_hist_seqr::stdev     31.273004                      
+system.ruby.ST.latency_hist_seqr         |         749     86.59%     86.59% |         115     13.29%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist_seqr::total           865                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
@@ -610,18 +621,18 @@ system.ruby.ST.hit_latency_hist_seqr::total          615
 system.ruby.ST.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.ST.miss_latency_hist_seqr::samples          250                      
-system.ruby.ST.miss_latency_hist_seqr::mean    56.560000                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    48.538116                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    33.930333                      
-system.ruby.ST.miss_latency_hist_seqr    |         138     55.20%     55.20% |         110     44.00%     99.20% |           0      0.00%     99.20% |           0      0.00%     99.20% |           1      0.40%     99.60% |           1      0.40%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean    58.884000                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    50.399294                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    31.651062                      
+system.ruby.ST.miss_latency_hist_seqr    |         134     53.60%     53.60% |         115     46.00%     99.60% |           0      0.00%     99.60% |           0      0.00%     99.60% |           0      0.00%     99.60% |           1      0.40%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total          250                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples         6413                      
-system.ruby.IFETCH.latency_hist_seqr::mean     8.288944                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.525778                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    24.342417                      
-system.ruby.IFETCH.latency_hist_seqr     |        5838     91.03%     91.03% |         566      8.83%     99.86% |           0      0.00%     99.86% |           0      0.00%     99.86% |           6      0.09%     99.95% |           3      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     8.956962                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.536905                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    27.408738                      
+system.ruby.IFETCH.latency_hist_seqr     |        5838     91.03%     91.03% |         563      8.78%     99.81% |           1      0.02%     99.83% |           0      0.00%     99.83% |           5      0.08%     99.91% |           5      0.08%     99.98% |           0      0.00%     99.98% |           0      0.00%     99.98% |           0      0.00%     99.98% |           1      0.02%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         6413                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
@@ -633,10 +644,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total         5767
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          646                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    73.359133                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    66.307554                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    34.276818                      
-system.ruby.IFETCH.miss_latency_hist_seqr |          71     10.99%     10.99% |         566     87.62%     98.61% |           0      0.00%     98.61% |           0      0.00%     98.61% |           6      0.93%     99.54% |           3      0.46%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    79.990712                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    71.267502                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    42.993310                      
+system.ruby.IFETCH.miss_latency_hist_seqr |          71     10.99%     10.99% |         563     87.15%     98.14% |           1      0.15%     98.30% |           0      0.00%     98.30% |           5      0.77%     99.07% |           5      0.77%     99.85% |           0      0.00%     99.85% |           0      0.00%     99.85% |           0      0.00%     99.85% |           1      0.15%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          646                      
 system.ruby.Directory_Controller.GETX             198      0.00%      0.00%
 system.ruby.Directory_Controller.GETS             985      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index 072c6d45b..c3c3a350f 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persiste
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=5
 distributed_persistent=true
@@ -258,8 +280,12 @@ eventq_index=0
 fixed_timeout_latency=100
 l2_select_num_bits=0
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir
 persistentToDir=system.ruby.dir_cntrl0.persistentToDir
+power_model=Null
 recycle_latency=10
 reissue_wakeup_latency=10
 requestFromDir=system.ruby.dir_cntrl0.requestFromDir
@@ -361,6 +387,7 @@ N_tokens=2
 buffer_size=0
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 dynamic_timeout_enabled=true
 eventq_index=0
 fixed_timeout_latency=300
@@ -370,8 +397,12 @@ l2_select_num_bits=0
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 no_mig_atomic=true
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache
 persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache
+power_model=Null
 recycle_latency=10
 reissue_wakeup_latency=10
 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
@@ -497,17 +528,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.L1Dcache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.L1Icache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
@@ -524,12 +560,17 @@ N_tokens=2
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 filtering_enabled=true
 l2_request_latency=5
 l2_response_latency=5
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache
+power_model=Null
 recycle_latency=10
 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
 responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
@@ -626,18 +667,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
 netifs=
 number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
 ruby_system=system.ruby
 topology=Crossbar
@@ -926,42 +972,342 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers40]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers41]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers42]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers43]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers44]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers45]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers46]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers47]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers48]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers49]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers50]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers51]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers52]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers53]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers54]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers55]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers56]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers57]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers58]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers59]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers60]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers61]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers62]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers63]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers64]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers65]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers66]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers67]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers68]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers69]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers70]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers71]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
 weight=1
 
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 system.ruby.network.routers0.port_buffers18 system.ruby.network.routers0.port_buffers19 system.ruby.network.routers0.port_buffers20 system.ruby.network.routers0.port_buffers21 system.ruby.network.routers0.port_buffers22 system.ruby.network.routers0.port_buffers23
+power_model=Null
 router_id=0
 virt_nets=6
 
@@ -1137,8 +1483,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 system.ruby.network.routers1.port_buffers18 system.ruby.network.routers1.port_buffers19 system.ruby.network.routers1.port_buffers20 system.ruby.network.routers1.port_buffers21 system.ruby.network.routers1.port_buffers22 system.ruby.network.routers1.port_buffers23
+power_model=Null
 router_id=1
 virt_nets=6
 
@@ -1314,8 +1666,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23
+power_model=Null
 router_id=2
 virt_nets=6
 
@@ -1491,8 +1849,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35
+power_model=Null
 router_id=3
 virt_nets=6
 
@@ -1751,9 +2115,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index f535b9682..57e41dbee 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/al
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 22:02:54
-gem5 started Mar 14 2016 22:04:07
-gem5 executing on phenom, pid 29513
-command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled Oct 13 2016 20:33:48
+gem5 started Oct 13 2016 20:34:16
+gem5 executing on e108600-lin, pid 27525
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 108253 because target called exit()
+Exiting @ tick 113952 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index e5f292184..b89069f53 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000108                       # Number of seconds simulated
-sim_ticks                                      108253                       # Number of ticks simulated
-final_tick                                     108253                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000114                       # Number of seconds simulated
+sim_ticks                                      113952                       # Number of ticks simulated
+final_tick                                     113952                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  94410                       # Simulator instruction rate (inst/s)
-host_op_rate                                    94397                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1595747                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 455808                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  64476                       # Simulator instruction rate (inst/s)
+host_op_rate                                    64460                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1146955                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 412808                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        75456                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              75456                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0        14656                       # Number of bytes written to this memory
@@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1179                       #
 system.mem_ctrls.num_reads::total                1179                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0          229                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                229                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    697033800                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             697033800                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    135386548                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            135386548                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0    832420349                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total            832420349                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    662173547                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             662173547                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    128615557                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            128615557                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    790789104                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            790789104                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1179                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                        229                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1179                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                      229                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  65088                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   10368                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                    6144                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  64256                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   11200                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                    5120                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   75456                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                14656                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    162                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   112                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    175                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   117                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
 system.mem_ctrls.perBankRdBursts::0                86                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                52                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                82                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                77                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4                95                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5                19                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4                92                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5                18                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::7                 3                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 1                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               59                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               51                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::11               53                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::12               22                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13              361                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13              360                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14               61                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15               45                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::0                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4                23                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5                 7                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4                20                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5                 6                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::7                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10                5                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10                2                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::11                0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::12                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               18                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14               43                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               15                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14               37                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        108170                       # Total gap between requests
+system.mem_ctrls.totGap                        113863                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                  229                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                    1017                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                    1004                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -138,10 +138,10 @@ system.mem_ctrls.wrQLenPdf::13                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::15                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::16                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                      7                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                      7                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::21                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::22                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::23                      6                       # What write queue length does an incoming req see
@@ -153,7 +153,7 @@ system.mem_ctrls.wrQLenPdf::28                      6                       # Wh
 system.mem_ctrls.wrQLenPdf::29                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::30                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::31                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                      5                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
@@ -185,87 +185,96 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          203                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    338.916256                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   206.604664                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   325.225174                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           65     32.02%     32.02% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           46     22.66%     54.68% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           21     10.34%     65.02% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           11      5.42%     70.44% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           17      8.37%     78.82% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767           10      4.93%     83.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            8      3.94%     87.68% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            4      1.97%     89.66% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           21     10.34%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          203                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples            6                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean     156.500000                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean    117.084065                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev     90.391924                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-31             1     16.67%     16.67% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-95             1     16.67%     33.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::160-175            1     16.67%     50.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::192-207            1     16.67%     66.67% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::208-223            1     16.67%     83.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::256-271            1     16.67%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total             6                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples            6                       # Writes before turning the bus around for reads
+system.mem_ctrls.bytesPerActivate::samples          201                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    338.149254                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   209.301438                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   329.237418                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           56     27.86%     27.86% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           54     26.87%     54.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           27     13.43%     68.16% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511            9      4.48%     72.64% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           15      7.46%     80.10% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            6      2.99%     83.08% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            6      2.99%     86.07% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            4      1.99%     88.06% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           24     11.94%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          201                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples            5                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean            138                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     99.720637                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev     86.905121                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-23             1     20.00%     20.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::80-87             1     20.00%     40.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::160-167            1     20.00%     60.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::208-215            1     20.00%     80.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::216-223            1     20.00%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total             5                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples            5                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::mean             16                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::gmean     16.000000                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16                6    100.00%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total             6                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         7213                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   26536                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       5085                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         7.09                       # Average queueing delay per DRAM burst
+system.mem_ctrls.wrPerTurnAround::16                5    100.00%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total             5                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                        13296                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   32372                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       5020                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        13.24                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   26.09                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       601.26                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                        56.76                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    697.03                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    135.39                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   32.24                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       563.89                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                        44.93                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    662.17                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    128.62                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         5.14                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.70                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    0.44                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         4.76                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     4.41                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    0.35                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      23.01                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      816                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                      88                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 80.24                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                75.21                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         76.83                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    79.72                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   521640                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   289800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 5104320                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                 311040                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              6611280                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             57840408                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy             10149600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               80828088                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            796.508485                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        21689                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF          3380                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         81532                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                   945000                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   525000                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 6764160                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                 684288                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              6611280                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             67474548                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              1707000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               84711276                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            834.659638                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE         2397                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          3380                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         95729                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.avgWrQLen                      22.60                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      806                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                      73                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 80.28                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                65.18                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         80.87                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    78.76                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   471240                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   255024                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 4695264                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                 217152                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         9219600.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              7578264                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy               292992                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        33706152                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy         7106688                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy          1604640                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               65147016                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            570.509199                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                96809                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE          351                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          3653                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF         4385                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN        18507                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         13139                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        73917                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   992460                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   521640                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 6774432                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 451008                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         8604960.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             10831824                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               319872                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        39423936                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy         1117056                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               69037188                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            605.844461                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                89154                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          259                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          3640                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         2909                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         20688                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        86456                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -300,8 +309,8 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON          108253                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                           108253                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON          113952                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                           113952                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6403                       # Number of instructions committed
@@ -320,7 +329,7 @@ system.cpu.num_mem_refs                          2060                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     108253                       # Number of busy cycles
+system.cpu.num_busy_cycles                     113952                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1056                       # Number of branches fetched
@@ -360,7 +369,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       6413                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
 system.ruby.outstanding_req_hist_seqr::bucket_size            1                      
 system.ruby.outstanding_req_hist_seqr::max_bucket            9                      
 system.ruby.outstanding_req_hist_seqr::samples         8464                      
@@ -371,86 +380,86 @@ system.ruby.outstanding_req_hist_seqr::total         8464
 system.ruby.latency_hist_seqr::bucket_size           64                      
 system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples           8463                      
-system.ruby.latency_hist_seqr::mean         11.791327                      
-system.ruby.latency_hist_seqr::gmean         1.956562                      
-system.ruby.latency_hist_seqr::stdev        27.556143                      
-system.ruby.latency_hist_seqr            |        7446     87.98%     87.98% |         996     11.77%     99.75% |           8      0.09%     99.85% |           4      0.05%     99.89% |           5      0.06%     99.95% |           4      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean         12.464729                      
+system.ruby.latency_hist_seqr::gmean         1.971984                      
+system.ruby.latency_hist_seqr::stdev        29.823065                      
+system.ruby.latency_hist_seqr            |        7459     88.14%     88.14% |         983     11.62%     99.75% |           7      0.08%     99.83% |           3      0.04%     99.87% |           5      0.06%     99.93% |           5      0.06%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           1      0.01%    100.00%
 system.ruby.latency_hist_seqr::total             8463                      
 system.ruby.hit_latency_hist_seqr::bucket_size            8                      
 system.ruby.hit_latency_hist_seqr::max_bucket           79                      
 system.ruby.hit_latency_hist_seqr::samples         7284                      
-system.ruby.hit_latency_hist_seqr::mean      1.635502                      
-system.ruby.hit_latency_hist_seqr::gmean     1.092626                      
-system.ruby.hit_latency_hist_seqr::stdev     3.754063                      
+system.ruby.hit_latency_hist_seqr::mean      1.636052                      
+system.ruby.hit_latency_hist_seqr::gmean     1.092653                      
+system.ruby.hit_latency_hist_seqr::stdev     3.757041                      
 system.ruby.hit_latency_hist_seqr        |        7080     97.20%     97.20% |           0      0.00%     97.20% |          21      0.29%     97.49% |         182      2.50%     99.99% |           0      0.00%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.hit_latency_hist_seqr::total         7284                      
 system.ruby.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.miss_latency_hist_seqr::samples         1179                      
-system.ruby.miss_latency_hist_seqr::mean    74.535199                      
-system.ruby.miss_latency_hist_seqr::gmean    71.564149                      
-system.ruby.miss_latency_hist_seqr::stdev    28.099799                      
-system.ruby.miss_latency_hist_seqr       |         162     13.74%     13.74% |         996     84.48%     98.22% |           8      0.68%     98.90% |           4      0.34%     99.24% |           5      0.42%     99.66% |           4      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    79.365564                      
+system.ruby.miss_latency_hist_seqr::gmean    75.701428                      
+system.ruby.miss_latency_hist_seqr::stdev    33.123085                      
+system.ruby.miss_latency_hist_seqr       |         175     14.84%     14.84% |         983     83.38%     98.22% |           7      0.59%     98.81% |           3      0.25%     99.07% |           5      0.42%     99.49% |           5      0.42%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |           1      0.08%    100.00%
 system.ruby.miss_latency_hist_seqr::total         1179                      
 system.ruby.Directory.incomplete_times_seqr         1178                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.L1Dcache.demand_hits         1313                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          737                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2050                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits         5767                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses          646                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses         6413                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
 system.ruby.l2_cntrl0.L2cache.demand_hits          187                       # Number of cache demand hits
 system.ruby.l2_cntrl0.L2cache.demand_misses         1196                       # Number of cache demand misses
 system.ruby.l2_cntrl0.L2cache.demand_accesses         1383                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     6.022466                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     5.719513                      
 system.ruby.network.routers0.msg_count.Request_Control::1         1383                      
 system.ruby.network.routers0.msg_count.Response_Data::4         1179                      
 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4          204                      
 system.ruby.network.routers0.msg_count.Response_Control::4            1                      
 system.ruby.network.routers0.msg_count.Writeback_Data::4         1355                      
-system.ruby.network.routers0.msg_count.Persistent_Control::3           52                      
+system.ruby.network.routers0.msg_count.Persistent_Control::3           44                      
 system.ruby.network.routers0.msg_bytes.Request_Control::1        11064                      
 system.ruby.network.routers0.msg_bytes.Response_Data::4        84888                      
 system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4        14688                      
 system.ruby.network.routers0.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers0.msg_bytes.Writeback_Data::4        97560                      
-system.ruby.network.routers0.msg_bytes.Persistent_Control::3          416                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     4.541676                      
+system.ruby.network.routers0.msg_bytes.Persistent_Control::3          352                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     4.313658                      
 system.ruby.network.routers1.msg_count.Request_Control::1         1383                      
 system.ruby.network.routers1.msg_count.Request_Control::2         1196                      
 system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4          204                      
 system.ruby.network.routers1.msg_count.Response_Control::4            1                      
 system.ruby.network.routers1.msg_count.Writeback_Data::4         1584                      
 system.ruby.network.routers1.msg_count.Writeback_Control::4          968                      
-system.ruby.network.routers1.msg_count.Persistent_Control::3           26                      
+system.ruby.network.routers1.msg_count.Persistent_Control::3           22                      
 system.ruby.network.routers1.msg_bytes.Request_Control::1        11064                      
 system.ruby.network.routers1.msg_bytes.Request_Control::2         9568                      
 system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4        14688                      
 system.ruby.network.routers1.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers1.msg_bytes.Writeback_Data::4       114048                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::4         7744                      
-system.ruby.network.routers1.msg_bytes.Persistent_Control::3          208                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     3.432237                      
+system.ruby.network.routers1.msg_bytes.Persistent_Control::3          176                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     3.259706                      
 system.ruby.network.routers2.msg_count.Request_Control::2         1196                      
 system.ruby.network.routers2.msg_count.Response_Data::4         1179                      
 system.ruby.network.routers2.msg_count.Writeback_Data::4          229                      
 system.ruby.network.routers2.msg_count.Writeback_Control::4          968                      
-system.ruby.network.routers2.msg_count.Persistent_Control::3           26                      
+system.ruby.network.routers2.msg_count.Persistent_Control::3           22                      
 system.ruby.network.routers2.msg_bytes.Request_Control::2         9568                      
 system.ruby.network.routers2.msg_bytes.Response_Data::4        84888                      
 system.ruby.network.routers2.msg_bytes.Writeback_Data::4        16488                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::4         7744                      
-system.ruby.network.routers2.msg_bytes.Persistent_Control::3          208                      
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized     4.665460                      
+system.ruby.network.routers2.msg_bytes.Persistent_Control::3          176                      
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized     4.430959                      
 system.ruby.network.routers3.msg_count.Request_Control::1         1383                      
 system.ruby.network.routers3.msg_count.Request_Control::2         1196                      
 system.ruby.network.routers3.msg_count.Response_Data::4         1179                      
@@ -458,7 +467,7 @@ system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4          204
 system.ruby.network.routers3.msg_count.Response_Control::4            1                      
 system.ruby.network.routers3.msg_count.Writeback_Data::4         1584                      
 system.ruby.network.routers3.msg_count.Writeback_Control::4          968                      
-system.ruby.network.routers3.msg_count.Persistent_Control::3           52                      
+system.ruby.network.routers3.msg_count.Persistent_Control::3           44                      
 system.ruby.network.routers3.msg_bytes.Request_Control::1        11064                      
 system.ruby.network.routers3.msg_bytes.Request_Control::2         9568                      
 system.ruby.network.routers3.msg_bytes.Response_Data::4        84888                      
@@ -466,47 +475,47 @@ system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4        14688
 system.ruby.network.routers3.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers3.msg_bytes.Writeback_Data::4       114048                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::4         7744                      
-system.ruby.network.routers3.msg_bytes.Persistent_Control::3          416                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.msg_bytes.Persistent_Control::3          352                      
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Request_Control         7737                      
 system.ruby.network.msg_count.Response_Data         3537                      
 system.ruby.network.msg_count.ResponseL2hit_Data          612                      
 system.ruby.network.msg_count.Response_Control            3                      
 system.ruby.network.msg_count.Writeback_Data         4752                      
 system.ruby.network.msg_count.Writeback_Control         2904                      
-system.ruby.network.msg_count.Persistent_Control          156                      
+system.ruby.network.msg_count.Persistent_Control          132                      
 system.ruby.network.msg_byte.Request_Control        61896                      
 system.ruby.network.msg_byte.Response_Data       254664                      
 system.ruby.network.msg_byte.ResponseL2hit_Data        44064                      
 system.ruby.network.msg_byte.Response_Control           24                      
 system.ruby.network.msg_byte.Writeback_Data       342144                      
 system.ruby.network.msg_byte.Writeback_Control        23232                      
-system.ruby.network.msg_byte.Persistent_Control         1248                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED       108253                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     5.761503                      
+system.ruby.network.msg_byte.Persistent_Control         1056                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED       113952                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     5.471602                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1179                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4          204                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Control::4            1                      
-system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3           26                      
+system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3           22                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        84888                      
 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4        14688                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3          208                      
-system.ruby.network.routers0.throttle1.link_utilization     6.283429                      
+system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3          176                      
+system.ruby.network.routers0.throttle1.link_utilization     5.967425                      
 system.ruby.network.routers0.throttle1.msg_count.Request_Control::1         1383                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4         1355                      
-system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3           26                      
+system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3           22                      
 system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1        11064                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4        97560                      
-system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3          208                      
-system.ruby.network.routers1.throttle0.link_utilization     6.283429                      
+system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3          176                      
+system.ruby.network.routers1.throttle0.link_utilization     5.967425                      
 system.ruby.network.routers1.throttle0.msg_count.Request_Control::1         1383                      
 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4         1355                      
-system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3           26                      
+system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3           22                      
 system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1        11064                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4        97560                      
-system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3          208                      
-system.ruby.network.routers1.throttle1.link_utilization     2.799922                      
+system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3          176                      
+system.ruby.network.routers1.throttle1.link_utilization     2.659892                      
 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2         1196                      
 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4          204                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Control::4            1                      
@@ -517,96 +526,96 @@ system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4        14
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4        16488                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4         7744                      
-system.ruby.network.routers2.throttle0.link_utilization     1.963456                      
+system.ruby.network.routers2.throttle0.link_utilization     1.863504                      
 system.ruby.network.routers2.throttle0.msg_count.Request_Control::2         1196                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4          229                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4          968                      
-system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3           26                      
+system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3           22                      
 system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2         9568                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4        16488                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4         7744                      
-system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3          208                      
-system.ruby.network.routers2.throttle1.link_utilization     4.901019                      
+system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3          176                      
+system.ruby.network.routers2.throttle1.link_utilization     4.655908                      
 system.ruby.network.routers2.throttle1.msg_count.Response_Data::4         1179                      
 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4        84888                      
-system.ruby.network.routers3.throttle0.link_utilization     5.749494                      
+system.ruby.network.routers3.throttle0.link_utilization     5.461949                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Data::4         1179                      
 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4          204                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Control::4            1                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4        84888                      
 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4        14688                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers3.throttle1.link_utilization     6.283429                      
+system.ruby.network.routers3.throttle1.link_utilization     5.967425                      
 system.ruby.network.routers3.throttle1.msg_count.Request_Control::1         1383                      
 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4         1355                      
-system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3           26                      
+system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3           22                      
 system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1        11064                      
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4        97560                      
-system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3          208                      
-system.ruby.network.routers3.throttle2.link_utilization     1.963456                      
+system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3          176                      
+system.ruby.network.routers3.throttle2.link_utilization     1.863504                      
 system.ruby.network.routers3.throttle2.msg_count.Request_Control::2         1196                      
 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4          229                      
 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4          968                      
-system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3           26                      
+system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3           22                      
 system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2         9568                      
 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4        16488                      
 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4         7744                      
-system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3          208                      
+system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3          176                      
 system.ruby.LD.latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.latency_hist_seqr::samples         1185                      
-system.ruby.LD.latency_hist_seqr::mean      28.779747                      
-system.ruby.LD.latency_hist_seqr::gmean      6.012520                      
-system.ruby.LD.latency_hist_seqr::stdev     37.360727                      
-system.ruby.LD.latency_hist_seqr         |         843     71.14%     71.14% |         337     28.44%     99.58% |           2      0.17%     99.75% |           0      0.00%     99.75% |           2      0.17%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      29.824473                      
+system.ruby.LD.latency_hist_seqr::gmean      6.089961                      
+system.ruby.LD.latency_hist_seqr::stdev     38.602832                      
+system.ruby.LD.latency_hist_seqr         |         854     72.07%     72.07% |         327     27.59%     99.66% |           2      0.17%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           2      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_seqr::total          1185                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            4                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket           39                      
 system.ruby.LD.hit_latency_hist_seqr::samples          759                      
-system.ruby.LD.hit_latency_hist_seqr::mean     4.030303                      
-system.ruby.LD.hit_latency_hist_seqr::gmean     1.520008                      
-system.ruby.LD.hit_latency_hist_seqr::stdev     7.784219                      
-system.ruby.LD.hit_latency_hist_seqr     |         659     86.82%     86.82% |           0      0.00%     86.82% |           0      0.00%     86.82% |           0      0.00%     86.82% |           0      0.00%     86.82% |           0      0.00%     86.82% |         100     13.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist_seqr::mean     4.025033                      
+system.ruby.LD.hit_latency_hist_seqr::gmean     1.519643                      
+system.ruby.LD.hit_latency_hist_seqr::stdev     7.772026                      
+system.ruby.LD.hit_latency_hist_seqr     |         659     86.82%     86.82% |           0      0.00%     86.82% |           0      0.00%     86.82% |           0      0.00%     86.82% |           0      0.00%     86.82% |           1      0.13%     86.96% |          99     13.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.hit_latency_hist_seqr::total          759                      
 system.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.miss_latency_hist_seqr::samples          426                      
-system.ruby.LD.miss_latency_hist_seqr::mean    72.875587                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    69.678801                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    27.158723                      
-system.ruby.LD.miss_latency_hist_seqr    |          84     19.72%     19.72% |         337     79.11%     98.83% |           2      0.47%     99.30% |           0      0.00%     99.30% |           2      0.47%     99.77% |           1      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    75.791080                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    72.234894                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    27.150058                      
+system.ruby.LD.miss_latency_hist_seqr    |          95     22.30%     22.30% |         327     76.76%     99.06% |           2      0.47%     99.53% |           0      0.00%     99.53% |           0      0.00%     99.53% |           2      0.47%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          426                      
 system.ruby.ST.latency_hist_seqr::bucket_size           32                      
 system.ruby.ST.latency_hist_seqr::max_bucket          319                      
 system.ruby.ST.latency_hist_seqr::samples          865                      
-system.ruby.ST.latency_hist_seqr::mean      13.996532                      
-system.ruby.ST.latency_hist_seqr::gmean      2.581393                      
-system.ruby.ST.latency_hist_seqr::stdev     26.004028                      
-system.ruby.ST.latency_hist_seqr         |         697     80.58%     80.58% |          78      9.02%     89.60% |          85      9.83%     99.42% |           3      0.35%     99.77% |           0      0.00%     99.77% |           1      0.12%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::mean      14.804624                      
+system.ruby.ST.latency_hist_seqr::gmean      2.602855                      
+system.ruby.ST.latency_hist_seqr::stdev     29.163214                      
+system.ruby.ST.latency_hist_seqr         |         697     80.58%     80.58% |          80      9.25%     89.83% |          83      9.60%     99.42% |           2      0.23%     99.65% |           0      0.00%     99.65% |           1      0.12%     99.77% |           0      0.00%     99.77% |           1      0.12%     99.88% |           0      0.00%     99.88% |           1      0.12%    100.00%
 system.ruby.ST.latency_hist_seqr::total           865                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            4                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket           39                      
 system.ruby.ST.hit_latency_hist_seqr::samples          697                      
-system.ruby.ST.hit_latency_hist_seqr::mean     2.305595                      
-system.ruby.ST.hit_latency_hist_seqr::gmean     1.210352                      
-system.ruby.ST.hit_latency_hist_seqr::stdev     5.118132                      
-system.ruby.ST.hit_latency_hist_seqr     |         654     93.83%     93.83% |           0      0.00%     93.83% |           0      0.00%     93.83% |           0      0.00%     93.83% |           0      0.00%     93.83% |          21      3.01%     96.84% |          22      3.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist_seqr::mean     2.317073                      
+system.ruby.ST.hit_latency_hist_seqr::gmean     1.210984                      
+system.ruby.ST.hit_latency_hist_seqr::stdev     5.162159                      
+system.ruby.ST.hit_latency_hist_seqr     |         654     93.83%     93.83% |           0      0.00%     93.83% |           0      0.00%     93.83% |           0      0.00%     93.83% |           0      0.00%     93.83% |          20      2.87%     96.70% |          23      3.30%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.hit_latency_hist_seqr::total          697                      
 system.ruby.ST.miss_latency_hist_seqr::bucket_size           32                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket          319                      
 system.ruby.ST.miss_latency_hist_seqr::samples          168                      
-system.ruby.ST.miss_latency_hist_seqr::mean    62.500000                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    59.782556                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    21.264516                      
-system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |          78     46.43%     46.43% |          85     50.60%     97.02% |           3      1.79%     98.81% |           0      0.00%     98.81% |           1      0.60%     99.40% |           1      0.60%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean    66.613095                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    62.251080                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    30.627944                      
+system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |          80     47.62%     47.62% |          83     49.40%     97.02% |           2      1.19%     98.21% |           0      0.00%     98.21% |           1      0.60%     98.81% |           0      0.00%     98.81% |           1      0.60%     99.40% |           0      0.00%     99.40% |           1      0.60%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total          168                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples         6413                      
-system.ruby.IFETCH.latency_hist_seqr::mean     8.354748                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.531676                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    24.237273                      
-system.ruby.IFETCH.latency_hist_seqr     |        5828     90.88%     90.88% |         571      8.90%     99.78% |           5      0.08%     99.86% |           3      0.05%     99.91% |           3      0.05%     99.95% |           3      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     8.941369                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.542249                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    26.742382                      
+system.ruby.IFETCH.latency_hist_seqr     |        5828     90.88%     90.88% |         571      8.90%     99.78% |           4      0.06%     99.84% |           2      0.03%     99.88% |           4      0.06%     99.94% |           3      0.05%     99.98% |           0      0.00%     99.98% |           0      0.00%     99.98% |           0      0.00%     99.98% |           1      0.02%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         6413                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            8                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket           79                      
@@ -619,10 +628,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total         5828
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          585                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    79.200000                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    76.837583                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    29.345532                      
-system.ruby.IFETCH.miss_latency_hist_seqr |           0      0.00%      0.00% |         571     97.61%     97.61% |           5      0.85%     98.46% |           3      0.51%     98.97% |           3      0.51%     99.49% |           3      0.51%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    85.630769                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    82.856413                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    36.234733                      
+system.ruby.IFETCH.miss_latency_hist_seqr |           0      0.00%      0.00% |         571     97.61%     97.61% |           4      0.68%     98.29% |           2      0.34%     98.63% |           4      0.68%     99.32% |           3      0.51%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           1      0.17%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          585                      
 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket            9                      
@@ -634,18 +643,18 @@ system.ruby.L1Cache.hit_mach_latency_hist_seqr::total         7080
 system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size            8                      
 system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket           79                      
 system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples          204                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean    23.691176                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean    23.640301                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev     1.636324                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean    23.710784                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean    23.661395                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev     1.615711                      
 system.ruby.L2Cache.hit_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |          21     10.29%     10.29% |         182     89.22%     99.51% |           0      0.00%     99.51% |           1      0.49%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L2Cache.hit_mach_latency_hist_seqr::total          204                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::samples         1179                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean    74.535199                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    71.564149                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    28.099799                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |         162     13.74%     13.74% |         996     84.48%     98.22% |           8      0.68%     98.90% |           4      0.34%     99.24% |           5      0.42%     99.66% |           4      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean    79.365564                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    75.701428                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    33.123085                      
+system.ruby.Directory.miss_mach_latency_hist_seqr |         175     14.84%     14.84% |         983     83.38%     98.22% |           7      0.59%     98.81% |           3      0.25%     99.07% |           5      0.42%     99.49% |           5      0.42%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |           1      0.08%    100.00%
 system.ruby.Directory.miss_mach_latency_hist_seqr::total         1179                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket            9                      
@@ -683,17 +692,18 @@ system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total          659
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size            4                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket           39                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples          100                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean           24                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean    24.000000                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         100    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean    23.960000                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean    23.956283                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev     0.400000                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      1.00%      1.00% |          99     99.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total          100                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples          426                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    72.875587                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    69.678801                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    27.158723                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |          84     19.72%     19.72% |         337     79.11%     98.83% |           2      0.47%     99.30% |           0      0.00%     99.30% |           2      0.47%     99.77% |           1      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    75.791080                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    72.234894                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    27.150058                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |          95     22.30%     22.30% |         327     76.76%     99.06% |           2      0.47%     99.53% |           0      0.00%     99.53% |           0      0.00%     99.53% |           2      0.47%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total          426                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
@@ -705,18 +715,18 @@ system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total          654
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size            4                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket           39                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples           43                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean    22.162791                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean    22.076919                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev     1.963115                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          21     48.84%     48.84% |          22     51.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean    22.348837                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean    22.264733                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev     1.938135                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          20     46.51%     46.51% |          23     53.49%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total           43                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          168                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    62.500000                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    59.782556                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    21.264516                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          78     46.43%     46.43% |          85     50.60%     97.02% |           3      1.79%     98.81% |           0      0.00%     98.81% |           1      0.60%     99.40% |           1      0.60%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    66.613095                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    62.251080                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    30.627944                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          80     47.62%     47.62% |          83     49.40%     97.02% |           2      1.19%     98.21% |           0      0.00%     98.21% |           1      0.60%     98.81% |           0      0.00%     98.81% |           1      0.60%     99.40% |           0      0.00%     99.40% |           1      0.60%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          168                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
@@ -736,15 +746,15 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total           61
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples          585                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    79.200000                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    76.837583                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    29.345532                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         571     97.61%     97.61% |           5      0.85%     98.46% |           3      0.51%     98.97% |           3      0.51%     99.49% |           3      0.51%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    85.630769                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    82.856413                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    36.234733                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         571     97.61%     97.61% |           4      0.68%     98.29% |           2      0.34%     98.63% |           4      0.68%     99.32% |           3      0.51%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           1      0.17%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total          585                      
 system.ruby.Directory_Controller.GETX             208      0.00%      0.00%
 system.ruby.Directory_Controller.GETS            1017      0.00%      0.00%
-system.ruby.Directory_Controller.Lockdown           13      0.00%      0.00%
-system.ruby.Directory_Controller.Unlockdown           13      0.00%      0.00%
+system.ruby.Directory_Controller.Lockdown           11      0.00%      0.00%
+system.ruby.Directory_Controller.Unlockdown           11      0.00%      0.00%
 system.ruby.Directory_Controller.Data_Owner            9      0.00%      0.00%
 system.ruby.Directory_Controller.Data_All_Tokens          220      0.00%      0.00%
 system.ruby.Directory_Controller.Ack_Owner           29      0.00%      0.00%
@@ -756,12 +766,11 @@ system.ruby.Directory_Controller.O.GETX           168      0.00%      0.00%
 system.ruby.Directory_Controller.O.GETS          1011      0.00%      0.00%
 system.ruby.Directory_Controller.O.Ack_All_Tokens           34      0.00%      0.00%
 system.ruby.Directory_Controller.NO.GETX           17      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Lockdown            2      0.00%      0.00%
 system.ruby.Directory_Controller.NO.Data_Owner            9      0.00%      0.00%
 system.ruby.Directory_Controller.NO.Data_All_Tokens          220      0.00%      0.00%
 system.ruby.Directory_Controller.NO.Ack_Owner           29      0.00%      0.00%
 system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens          905      0.00%      0.00%
-system.ruby.Directory_Controller.L.Unlockdown           13      0.00%      0.00%
+system.ruby.Directory_Controller.L.Unlockdown           11      0.00%      0.00%
 system.ruby.Directory_Controller.O_W.GETX           23      0.00%      0.00%
 system.ruby.Directory_Controller.O_W.GETS            6      0.00%      0.00%
 system.ruby.Directory_Controller.O_W.Memory_Ack          229      0.00%      0.00%
@@ -775,8 +784,8 @@ system.ruby.L1Cache_Controller.L1_Replacement         1368      0.00%      0.00%
 system.ruby.L1Cache_Controller.Data_Shared          161      0.00%      0.00%
 system.ruby.L1Cache_Controller.Data_All_Tokens         1222      0.00%      0.00%
 system.ruby.L1Cache_Controller.Ack                  1      0.00%      0.00%
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock           26      0.00%      0.00%
-system.ruby.L1Cache_Controller.Request_Timeout           13      0.00%      0.00%
+system.ruby.L1Cache_Controller.Own_Lock_or_Unlock           22      0.00%      0.00%
+system.ruby.L1Cache_Controller.Request_Timeout           11      0.00%      0.00%
 system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers         1221      0.00%      0.00%
 system.ruby.L1Cache_Controller.NP.Load            526      0.00%      0.00%
 system.ruby.L1Cache_Controller.NP.Ifetch          646      0.00%      0.00%
@@ -786,15 +795,15 @@ system.ruby.L1Cache_Controller.S.Ifetch           331      0.00%      0.00%
 system.ruby.L1Cache_Controller.S.Store             20      0.00%      0.00%
 system.ruby.L1Cache_Controller.S.L1_Replacement          141      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.Load             181      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Ifetch          3194      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Ifetch          3196      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.Store             33      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.L1_Replacement          946      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock           13      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock           11      0.00%      0.00%
 system.ruby.L1Cache_Controller.MM.Load            218      0.00%      0.00%
 system.ruby.L1Cache_Controller.MM.Store           265      0.00%      0.00%
 system.ruby.L1Cache_Controller.MM.L1_Replacement          268      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.Load            84      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_W.Ifetch         2242      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_W.Ifetch         2240      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.Store           25      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.L1_Replacement            9      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers          985      0.00%      0.00%
@@ -807,21 +816,21 @@ system.ruby.L1Cache_Controller.IM.Ack               1      0.00%      0.00%
 system.ruby.L1Cache_Controller.SM.Data_All_Tokens           20      0.00%      0.00%
 system.ruby.L1Cache_Controller.IS.Data_Shared          161      0.00%      0.00%
 system.ruby.L1Cache_Controller.IS.Data_All_Tokens         1011      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock           13      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Request_Timeout           13      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock           11      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Request_Timeout           11      0.00%      0.00%
 system.ruby.L2Cache_Controller.L1_GETS           1123      0.00%      0.00%
 system.ruby.L2Cache_Controller.L1_GETS_Last_Token           49      0.00%      0.00%
 system.ruby.L2Cache_Controller.L1_GETX            211      0.00%      0.00%
 system.ruby.L2Cache_Controller.L2_Replacement         1266      0.00%      0.00%
 system.ruby.L2Cache_Controller.Writeback_Shared_Data           84      0.00%      0.00%
 system.ruby.L2Cache_Controller.Writeback_All_Tokens         1271      0.00%      0.00%
-system.ruby.L2Cache_Controller.Persistent_GETS           13      0.00%      0.00%
-system.ruby.L2Cache_Controller.Own_Lock_or_Unlock           13      0.00%      0.00%
+system.ruby.L2Cache_Controller.Persistent_GETS           11      0.00%      0.00%
+system.ruby.L2Cache_Controller.Own_Lock_or_Unlock           11      0.00%      0.00%
 system.ruby.L2Cache_Controller.NP.L1_GETS         1011      0.00%      0.00%
 system.ruby.L2Cache_Controller.NP.L1_GETX          166      0.00%      0.00%
 system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data           81      0.00%      0.00%
 system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens         1193      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock           13      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock           11      0.00%      0.00%
 system.ruby.L2Cache_Controller.I.L1_GETX            1      0.00%      0.00%
 system.ruby.L2Cache_Controller.I.L2_Replacement           69      0.00%      0.00%
 system.ruby.L2Cache_Controller.I.Writeback_Shared_Data            3      0.00%      0.00%
@@ -835,6 +844,6 @@ system.ruby.L2Cache_Controller.O.Writeback_All_Tokens           57      0.00%
 system.ruby.L2Cache_Controller.M.L1_GETS          112      0.00%      0.00%
 system.ruby.L2Cache_Controller.M.L1_GETX           26      0.00%      0.00%
 system.ruby.L2Cache_Controller.M.L2_Replacement         1125      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETS           13      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETS           11      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 2fd013908..293c2e7fd 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
 dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
@@ -257,6 +279,10 @@ forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
 from_memory_controller_latency=2
 full_bit_dir_enabled=false
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeFilter=system.ruby.dir_cntrl0.probeFilter
 probe_filter_enabled=false
 recycle_latency=10
@@ -384,6 +410,7 @@ buffer_size=0
 cache_response_latency=10
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 forwardToCache=system.ruby.l1_cntrl0.forwardToCache
 issue_latency=2
@@ -391,6 +418,10 @@ l2_cache_hit_latency=10
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 no_mig_atomic=true
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestFromCache=system.ruby.l1_cntrl0.requestFromCache
 responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -522,17 +553,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.L1Dcache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.L1Icache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
@@ -560,18 +596,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
 netifs=
 number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
 ruby_system=system.ruby
 topology=Crossbar
@@ -766,32 +807,234 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers40]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers41]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers42]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers43]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers44]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers45]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers46]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers47]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17
+power_model=Null
 router_id=0
 virt_nets=6
 
@@ -925,8 +1168,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17
+power_model=Null
 router_id=1
 virt_nets=6
 
@@ -1060,8 +1309,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23
+power_model=Null
 router_id=2
 virt_nets=6
 
@@ -1236,9 +1491,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index 2d739759e..df46cff97 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 21:55:52
-gem5 started Mar 14 2016 21:57:33
-gem5 executing on phenom, pid 28167
-command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
+gem5 compiled Oct 13 2016 20:24:36
+gem5 started Oct 13 2016 20:24:58
+gem5 executing on e108600-lin, pid 38872
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 86770 because target called exit()
+Exiting @ tick 93323 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 9d52394d3..56d6a64b0 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000087                       # Number of seconds simulated
-sim_ticks                                       86770                       # Number of ticks simulated
-final_tick                                      86770                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000093                       # Number of seconds simulated
+sim_ticks                                       93323                       # Number of ticks simulated
+final_tick                                      93323                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  95809                       # Simulator instruction rate (inst/s)
-host_op_rate                                    95795                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1297998                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 453692                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  48908                       # Simulator instruction rate (inst/s)
+host_op_rate                                    48899                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 712591                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 412484                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        86770                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        93323                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        74240                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              74240                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0        14080                       # Number of bytes written to this memory
@@ -22,29 +22,29 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1160                       #
 system.mem_ctrls.num_reads::total                1160                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0          220                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                220                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    855595252                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             855595252                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    162268065                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            162268065                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   1017863317                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1017863317                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    795516646                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             795516646                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    150873847                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            150873847                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    946390493                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            946390493                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1160                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                        220                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1160                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                      220                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  63744                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   10496                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                    5504                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  63488                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   10752                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                    5248                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   74240                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                14080                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    164                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.servicedByWrQ                    168                       # Number of DRAM read bursts serviced by the write queue
 system.mem_ctrls.mergedWrBursts                   109                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
 system.mem_ctrls.perBankRdBursts::0                86                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                52                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                82                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                77                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4                93                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4                90                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                18                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::7                 3                       # Per bank write bursts
@@ -54,13 +54,13 @@ system.mem_ctrls.perBankRdBursts::10               54                       # Pe
 system.mem_ctrls.perBankRdBursts::11               47                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::12               22                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::13              358                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14               61                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14               60                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15               41                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::0                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4                19                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4                17                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::5                 6                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::7                 0                       # Per bank write bursts
@@ -69,12 +69,12 @@ system.mem_ctrls.perBankWrBursts::9                 0                       # Pe
 system.mem_ctrls.perBankWrBursts::10                2                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::11                0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::12                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               17                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               15                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::14               42                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         86698                       # Total gap between requests
+system.mem_ctrls.totGap                         93245                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                  220                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     996                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                     992                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -136,8 +136,8 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      4                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      4                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      2                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::17                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::18                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::19                      6                       # What write queue length does an incoming req see
@@ -146,10 +146,10 @@ system.mem_ctrls.wrQLenPdf::21                      6                       # Wh
 system.mem_ctrls.wrQLenPdf::22                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::23                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::24                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                      5                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                      6                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::29                      5                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::30                      5                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::31                      5                       # What write queue length does an incoming req see
@@ -185,87 +185,98 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          191                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    358.869110                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   215.937059                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   347.377875                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           57     29.84%     29.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           46     24.08%     53.93% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           20     10.47%     64.40% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           14      7.33%     71.73% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           10      5.24%     76.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            4      2.09%     79.06% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            7      3.66%     82.72% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            8      4.19%     86.91% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           25     13.09%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          191                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples          185                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    364.627027                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   225.304848                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   344.102671                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           47     25.41%     25.41% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           51     27.57%     52.97% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           22     11.89%     64.86% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           11      5.95%     70.81% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           10      5.41%     76.22% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            6      3.24%     79.46% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            6      3.24%     82.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            9      4.86%     87.57% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           23     12.43%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          185                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples            5                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean     143.400000                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean    107.861440                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev     83.476344                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean     135.600000                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean    103.520831                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev     76.774345                       # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::16-23             1     20.00%     20.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::120-127            1     20.00%     40.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::128-135            1     20.00%     60.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::216-223            2     40.00%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::184-191            1     20.00%     80.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::216-223            1     20.00%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::total             5                       # Reads before turning the bus around for writes
 system.mem_ctrls.wrPerTurnAround::samples            5                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      17.200000                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     17.171629                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      1.095445                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16                2     40.00%     40.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                3     60.00%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.400000                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.381380                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.894427                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16                4     80.00%     80.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                1     20.00%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total             5                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         6142                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   25066                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       4980                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         6.17                       # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat                        12811                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   31659                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       4960                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        12.91                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   25.17                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       734.63                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                        63.43                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    855.60                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    162.27                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   31.91                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       680.30                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                        56.23                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    795.52                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    150.87                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         6.23                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     5.74                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    0.50                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         5.75                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     5.31                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    0.44                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      20.55                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      808                       # Number of row buffer hits during reads
+system.mem_ctrls.avgWrQLen                      22.62                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      805                       # Number of row buffer hits during reads
 system.mem_ctrls.writeRowHits                      78                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 81.12                       # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate                 81.15                       # Row buffer hit rate for reads
 system.mem_ctrls.writeRowHitRate                70.27                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         62.82                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    80.04                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   476280                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   264600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 5091840                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                 259200                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              5594160                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             50178924                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy              7527000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               69392004                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            807.766675                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        12759                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF          2860                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         70795                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                   967680                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   537600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 7200960                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                 632448                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              5594160                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             57849984                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy               798000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               73580832                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            856.527274                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE          910                       # Time in different power states
+system.mem_ctrls.avgGap                         67.57                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    80.05                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   449820                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   235704                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 4672416                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                 192096                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         7375680.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              7678128                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy               246528                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        28111488                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy         4554240                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy          1112640                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               54628740                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            585.372738                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                75800                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE          328                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          3126                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF         2335                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN        11860                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         14026                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        61648                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   913920                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   479136                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 6660192                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 492768                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         6761040.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             10312440                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               226560                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        31424328                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy          462720                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               57733104                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            618.637463                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                69937                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          212                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          2860                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         82150                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        86770                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         1205                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         20133                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        68913                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED        93323                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -300,8 +311,8 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON           86770                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            86770                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON           93323                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            93323                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6403                       # Number of instructions committed
@@ -320,7 +331,7 @@ system.cpu.num_mem_refs                          2060                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      86770                       # Number of busy cycles
+system.cpu.num_busy_cycles                      93323                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1056                       # Number of branches fetched
@@ -360,7 +371,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       6413                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        86770                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        93323                       # Cumulative time (in ticks) in various power states
 system.ruby.outstanding_req_hist_seqr::bucket_size            1                      
 system.ruby.outstanding_req_hist_seqr::max_bucket            9                      
 system.ruby.outstanding_req_hist_seqr::samples         8464                      
@@ -371,10 +382,10 @@ system.ruby.outstanding_req_hist_seqr::total         8464
 system.ruby.latency_hist_seqr::bucket_size           64                      
 system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples           8463                      
-system.ruby.latency_hist_seqr::mean          9.252865                      
-system.ruby.latency_hist_seqr::gmean         1.840314                      
-system.ruby.latency_hist_seqr::stdev        22.282539                      
-system.ruby.latency_hist_seqr            |        8231     97.26%     97.26% |         222      2.62%     99.88% |           0      0.00%     99.88% |           1      0.01%     99.89% |           7      0.08%     99.98% |           2      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean         10.027177                      
+system.ruby.latency_hist_seqr::gmean         1.860537                      
+system.ruby.latency_hist_seqr::stdev        25.112208                      
+system.ruby.latency_hist_seqr            |        8219     97.12%     97.12% |         231      2.73%     99.85% |           1      0.01%     99.86% |           1      0.01%     99.87% |           5      0.06%     99.93% |           5      0.06%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           1      0.01%    100.00%
 system.ruby.latency_hist_seqr::total             8463                      
 system.ruby.hit_latency_hist_seqr::bucket_size            2                      
 system.ruby.hit_latency_hist_seqr::max_bucket           19                      
@@ -387,16 +398,16 @@ system.ruby.hit_latency_hist_seqr::total         7303
 system.ruby.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.miss_latency_hist_seqr::samples         1160                      
-system.ruby.miss_latency_hist_seqr::mean    59.460345                      
-system.ruby.miss_latency_hist_seqr::gmean    56.276317                      
-system.ruby.miss_latency_hist_seqr::stdev    26.160126                      
-system.ruby.miss_latency_hist_seqr       |         928     80.00%     80.00% |         222     19.14%     99.14% |           0      0.00%     99.14% |           1      0.09%     99.22% |           7      0.60%     99.83% |           2      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    65.109483                      
+system.ruby.miss_latency_hist_seqr::gmean    60.947221                      
+system.ruby.miss_latency_hist_seqr::stdev    32.683425                      
+system.ruby.miss_latency_hist_seqr       |         916     78.97%     78.97% |         231     19.91%     98.88% |           1      0.09%     98.97% |           1      0.09%     99.05% |           5      0.43%     99.48% |           5      0.43%     99.91% |           0      0.00%     99.91% |           0      0.00%     99.91% |           0      0.00%     99.91% |           1      0.09%    100.00%
 system.ruby.miss_latency_hist_seqr::total         1160                      
 system.ruby.Directory.incomplete_times_seqr         1159                      
 system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
 system.ruby.dir_cntrl0.probeFilter.demand_misses            0                       # Number of cache demand misses
 system.ruby.dir_cntrl0.probeFilter.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        86770                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        93323                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.L1Dcache.demand_hits         1333                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          717                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2050                       # Number of cache demand accesses
@@ -406,12 +417,12 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses         6413
 system.ruby.l1_cntrl0.L2cache.demand_hits          203                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L2cache.demand_misses         1160                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L2cache.demand_accesses         1363                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        86770                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        86770                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        93323                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        93323                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.fully_busy_cycles             7                       # cycles for which number of transistions == max transitions
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        86770                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     5.172295                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        93323                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     4.809104                      
 system.ruby.network.routers0.msg_count.Request_Control::2         1160                      
 system.ruby.network.routers0.msg_count.Response_Data::4         1160                      
 system.ruby.network.routers0.msg_count.Writeback_Data::5          220                      
@@ -426,8 +437,8 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2         9152
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3         9152                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::5         7392                      
 system.ruby.network.routers0.msg_bytes.Unblock_Control::5         9280                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        86770                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     5.172006                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        93323                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     4.808836                      
 system.ruby.network.routers1.msg_count.Request_Control::2         1160                      
 system.ruby.network.routers1.msg_count.Response_Data::4         1160                      
 system.ruby.network.routers1.msg_count.Writeback_Data::5          220                      
@@ -442,8 +453,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2         9152
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3         9152                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::5         7392                      
 system.ruby.network.routers1.msg_bytes.Unblock_Control::5         9272                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        86770                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     5.172295                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        93323                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     4.809104                      
 system.ruby.network.routers2.msg_count.Request_Control::2         1160                      
 system.ruby.network.routers2.msg_count.Response_Data::4         1160                      
 system.ruby.network.routers2.msg_count.Writeback_Data::5          220                      
@@ -458,7 +469,7 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2         9152
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3         9152                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::5         7392                      
 system.ruby.network.routers2.msg_bytes.Unblock_Control::5         9280                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        86770                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        93323                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Request_Control         3480                      
 system.ruby.network.msg_count.Response_Data         3480                      
 system.ruby.network.msg_count.Writeback_Data          660                      
@@ -469,13 +480,13 @@ system.ruby.network.msg_byte.Response_Data       250560
 system.ruby.network.msg_byte.Writeback_Data        47520                      
 system.ruby.network.msg_byte.Writeback_Control        77088                      
 system.ruby.network.msg_byte.Unblock_Control        27832                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        86770                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     6.675118                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        93323                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     6.206401                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1160                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1144                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        83520                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         9152                      
-system.ruby.network.routers0.throttle1.link_utilization     3.669471                      
+system.ruby.network.routers0.throttle1.link_utilization     3.411806                      
 system.ruby.network.routers0.throttle1.msg_count.Request_Control::2         1160                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5          220                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2         1144                      
@@ -486,7 +497,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5        15840
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2         9152                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5         7392                      
 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5         9280                      
-system.ruby.network.routers1.throttle0.link_utilization     3.668895                      
+system.ruby.network.routers1.throttle0.link_utilization     3.411271                      
 system.ruby.network.routers1.throttle0.msg_count.Request_Control::2         1160                      
 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5          220                      
 system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2         1144                      
@@ -497,17 +508,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5        15840
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2         9152                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5         7392                      
 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5         9272                      
-system.ruby.network.routers1.throttle1.link_utilization     6.675118                      
+system.ruby.network.routers1.throttle1.link_utilization     6.206401                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1160                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1144                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        83520                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         9152                      
-system.ruby.network.routers2.throttle0.link_utilization     6.675118                      
+system.ruby.network.routers2.throttle0.link_utilization     6.206401                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1160                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1144                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        83520                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         9152                      
-system.ruby.network.routers2.throttle1.link_utilization     3.669471                      
+system.ruby.network.routers2.throttle1.link_utilization     3.411806                      
 system.ruby.network.routers2.throttle1.msg_count.Request_Control::2         1160                      
 system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5          220                      
 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2         1144                      
@@ -518,13 +529,13 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5        15840
 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2         9152                      
 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5         7392                      
 system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5         9280                      
-system.ruby.LD.latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.latency_hist_seqr::samples         1185                      
-system.ruby.LD.latency_hist_seqr::mean      21.677637                      
-system.ruby.LD.latency_hist_seqr::gmean      5.060853                      
-system.ruby.LD.latency_hist_seqr::stdev     30.245768                      
-system.ruby.LD.latency_hist_seqr         |         853     71.98%     71.98% |         244     20.59%     92.57% |          84      7.09%     99.66% |           1      0.08%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           1      0.08%     99.83% |           2      0.17%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      23.222785                      
+system.ruby.LD.latency_hist_seqr::gmean      5.170883                      
+system.ruby.LD.latency_hist_seqr::stdev     33.395677                      
+system.ruby.LD.latency_hist_seqr         |        1100     92.83%     92.83% |          82      6.92%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           3      0.25%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_seqr::total          1185                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            2                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket           19                      
@@ -534,21 +545,21 @@ system.ruby.LD.hit_latency_hist_seqr::gmean     1.390347
 system.ruby.LD.hit_latency_hist_seqr::stdev     3.445311                      
 system.ruby.LD.hit_latency_hist_seqr     |         659     86.26%     86.26% |           0      0.00%     86.26% |           0      0.00%     86.26% |           0      0.00%     86.26% |           0      0.00%     86.26% |         105     13.74%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.hit_latency_hist_seqr::total          764                      
-system.ruby.LD.miss_latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.miss_latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.miss_latency_hist_seqr::samples          421                      
-system.ruby.LD.miss_latency_hist_seqr::mean    56.707838                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    52.779793                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    25.484779                      
-system.ruby.LD.miss_latency_hist_seqr    |          89     21.14%     21.14% |         244     57.96%     79.10% |          84     19.95%     99.05% |           1      0.24%     99.29% |           0      0.00%     99.29% |           0      0.00%     99.29% |           0      0.00%     99.29% |           0      0.00%     99.29% |           1      0.24%     99.52% |           2      0.48%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    61.057007                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    56.073786                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    29.948950                      
+system.ruby.LD.miss_latency_hist_seqr    |         336     79.81%     79.81% |          82     19.48%     99.29% |           0      0.00%     99.29% |           0      0.00%     99.29% |           0      0.00%     99.29% |           3      0.71%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          421                      
 system.ruby.ST.latency_hist_seqr::bucket_size           16                      
 system.ruby.ST.latency_hist_seqr::max_bucket          159                      
 system.ruby.ST.latency_hist_seqr::samples          865                      
-system.ruby.ST.latency_hist_seqr::mean      10.558382                      
-system.ruby.ST.latency_hist_seqr::gmean      2.225841                      
-system.ruby.ST.latency_hist_seqr::stdev     20.458667                      
-system.ruby.ST.latency_hist_seqr         |         707     81.73%     81.73% |          45      5.20%     86.94% |           0      0.00%     86.94% |          76      8.79%     95.72% |          33      3.82%     99.54% |           4      0.46%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::mean      11.254335                      
+system.ruby.ST.latency_hist_seqr::gmean      2.251088                      
+system.ruby.ST.latency_hist_seqr::stdev     22.172254                      
+system.ruby.ST.latency_hist_seqr         |         707     81.73%     81.73% |          44      5.09%     86.82% |           0      0.00%     86.82% |          73      8.44%     95.26% |          36      4.16%     99.42% |           4      0.46%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist_seqr::total           865                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            2                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket           19                      
@@ -561,18 +572,18 @@ system.ruby.ST.hit_latency_hist_seqr::total          707
 system.ruby.ST.miss_latency_hist_seqr::bucket_size           16                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket          159                      
 system.ruby.ST.miss_latency_hist_seqr::samples          158                      
-system.ruby.ST.miss_latency_hist_seqr::mean    51.240506                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    48.407659                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    15.670342                      
-system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |          45     28.48%     28.48% |           0      0.00%     28.48% |          76     48.10%     76.58% |          33     20.89%     97.47% |           4      2.53%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean    55.050633                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    51.490981                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    17.990372                      
+system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |          44     27.85%     27.85% |           0      0.00%     27.85% |          73     46.20%     74.05% |          36     22.78%     96.84% |           4      2.53%     99.37% |           1      0.63%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total          158                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples         6413                      
-system.ruby.IFETCH.latency_hist_seqr::mean     6.780914                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.487888                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    19.876102                      
-system.ruby.IFETCH.latency_hist_seqr     |        6306     98.33%     98.33% |         100      1.56%     99.89% |           0      0.00%     99.89% |           1      0.02%     99.91% |           4      0.06%     99.97% |           2      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     7.423359                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.501230                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    22.823134                      
+system.ruby.IFETCH.latency_hist_seqr     |        6295     98.16%     98.16% |         108      1.68%     99.84% |           1      0.02%     99.86% |           1      0.02%     99.88% |           5      0.08%     99.95% |           2      0.03%     99.98% |           0      0.00%     99.98% |           0      0.00%     99.98% |           0      0.00%     99.98% |           1      0.02%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         6413                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            2                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket           19                      
@@ -585,10 +596,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total         5832
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          581                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    63.690189                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    61.418649                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    28.087678                      
-system.ruby.IFETCH.miss_latency_hist_seqr |         474     81.58%     81.58% |         100     17.21%     98.80% |           0      0.00%     98.80% |           1      0.17%     98.97% |           4      0.69%     99.66% |           2      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    70.781411                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    67.778682                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    36.410761                      
+system.ruby.IFETCH.miss_latency_hist_seqr |         463     79.69%     79.69% |         108     18.59%     98.28% |           1      0.17%     98.45% |           1      0.17%     98.62% |           5      0.86%     99.48% |           2      0.34%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           1      0.17%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          581                      
 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket            9                      
@@ -607,10 +618,10 @@ system.ruby.L2Cache.hit_mach_latency_hist_seqr::total          203
 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::samples         1160                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean    59.460345                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    56.276317                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    26.160126                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |         928     80.00%     80.00% |         222     19.14%     99.14% |           0      0.00%     99.14% |           1      0.09%     99.22% |           7      0.60%     99.83% |           2      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean    65.109483                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    60.947221                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    32.683425                      
+system.ruby.Directory.miss_mach_latency_hist_seqr |         916     78.97%     78.97% |         231     19.91%     98.88% |           1      0.09%     98.97% |           1      0.09%     99.05% |           5      0.43%     99.48% |           5      0.43%     99.91% |           0      0.00%     99.91% |           0      0.00%     99.91% |           0      0.00%     99.91% |           1      0.09%    100.00%
 system.ruby.Directory.miss_mach_latency_hist_seqr::total         1160                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket            9                      
@@ -652,13 +663,13 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean           11
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean    11.000000                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         105    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total          105                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples          421                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    56.707838                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    52.779793                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    25.484779                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |          89     21.14%     21.14% |         244     57.96%     79.10% |          84     19.95%     99.05% |           1      0.24%     99.29% |           0      0.00%     99.29% |           0      0.00%     99.29% |           0      0.00%     99.29% |           0      0.00%     99.29% |           1      0.24%     99.52% |           2      0.48%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    61.057007                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    56.073786                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    29.948950                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |         336     79.81%     79.81% |          82     19.48%     99.29% |           0      0.00%     99.29% |           0      0.00%     99.29% |           0      0.00%     99.29% |           3      0.71%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total          421                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
@@ -677,10 +688,10 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total           33
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           16                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          159                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          158                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    51.240506                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    48.407659                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    15.670342                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          45     28.48%     28.48% |           0      0.00%     28.48% |          76     48.10%     76.58% |          33     20.89%     97.47% |           4      2.53%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    55.050633                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    51.490981                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    17.990372                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          44     27.85%     27.85% |           0      0.00%     27.85% |          73     46.20%     74.05% |          36     22.78%     96.84% |           4      2.53%     99.37% |           1      0.63%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          158                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
@@ -699,10 +710,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total           65
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples          581                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    63.690189                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    61.418649                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    28.087678                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         474     81.58%     81.58% |         100     17.21%     98.80% |           0      0.00%     98.80% |           1      0.17%     98.97% |           4      0.69%     99.66% |           2      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    70.781411                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    67.778682                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    36.410761                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         463     79.69%     79.69% |         108     18.59%     98.28% |           1      0.17%     98.45% |           1      0.17%     98.62% |           5      0.86%     99.48% |           2      0.34%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           1      0.17%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total          581                      
 system.ruby.Directory_Controller.GETX             185      0.00%      0.00%
 system.ruby.Directory_Controller.GETS            1021      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 2d08f440e..6b91b5d29 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
@@ -256,6 +278,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
 eventq_index=0
 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestToDir=system.ruby.dir_cntrl0.requestToDir
 responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -329,11 +355,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 forwardToCache=system.ruby.l1_cntrl0.forwardToCache
 issue_latency=2
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestFromCache=system.ruby.l1_cntrl0.requestFromCache
 responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -415,17 +446,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.cacheMemory
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.cacheMemory
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
@@ -438,18 +474,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
 netifs=
 number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
 ruby_system=system.ruby
 topology=Crossbar
@@ -616,32 +657,206 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14
+power_model=Null
 router_id=0
 virt_nets=5
 
@@ -754,8 +969,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14
+power_model=Null
 router_id=1
 virt_nets=5
 
@@ -868,8 +1089,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19
+power_model=Null
 router_id=2
 virt_nets=5
 
@@ -1016,9 +1243,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index 9c35f4885..89adb8b85 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 21:54:46
-gem5 started Mar 14 2016 21:55:58
-gem5 executing on phenom, pid 28070
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:45
+gem5 executing on e108600-lin, pid 28066
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 107065 because target called exit()
+Exiting @ tick 112490 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index a33abfe97..06dea8ad2 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000107                       # Number of seconds simulated
-sim_ticks                                      107065                       # Number of ticks simulated
-final_tick                                     107065                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000112                       # Number of seconds simulated
+sim_ticks                                      112490                       # Number of ticks simulated
+final_tick                                     112490                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  58028                       # Simulator instruction rate (inst/s)
-host_op_rate                                    58023                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 970128                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 456600                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  94486                       # Simulator instruction rate (inst/s)
+host_op_rate                                    94411                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1658372                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 414356                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED       107065                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0       110784                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total             110784                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0       110528                       # Number of bytes written to this memory
@@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1731                       #
 system.mem_ctrls.num_reads::total                1731                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0         1727                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total               1727                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0   1034735908                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            1034735908                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0   1032344837                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total           1032344837                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   2067080745                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           2067080745                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    984834207                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             984834207                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    982558450                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            982558450                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   1967392657                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1967392657                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1731                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                       1727                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1731                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                     1727                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  56512                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   54272                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   57856                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  56704                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   54080                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   57088                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                  110784                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys               110528                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    848                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   792                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    845                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   803                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0                85                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1                47                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2                74                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3                68                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4               112                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0                83                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1                50                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2                70                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3                63                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4               108                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                23                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::7                 3                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::9                 1                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               49                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11               33                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12               17                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13              263                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14               79                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15               28                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0                83                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1                47                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2                80                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3                68                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4               133                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5                25                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               55                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11               36                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12               18                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13              270                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14               81                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15               24                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0                82                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1                51                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2                73                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3                60                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4               126                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5                27                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 1                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7                 4                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7                 3                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                 1                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10               46                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11               28                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12               11                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10               50                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11               33                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12               12                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::13              268                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::14               81                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15               28                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15               24                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        106993                       # Total gap between requests
+system.mem_ctrls.totGap                        112412                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                 1727                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     883                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                     886                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -136,15 +136,15 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      9                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                     10                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     50                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     51                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::18                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     60                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     61                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                     60                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     56                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::24                     56                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::25                     56                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::26                     56                       # What write queue length does an incoming req see
@@ -152,9 +152,9 @@ system.mem_ctrls.wrQLenPdf::27                     56                       # Wh
 system.mem_ctrls.wrQLenPdf::28                     56                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::29                     56                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::30                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     55                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     56                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::32                     55                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
@@ -185,90 +185,100 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          275                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    406.341818                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   258.682678                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   357.059585                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           55     20.00%     20.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           74     26.91%     46.91% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           37     13.45%     60.36% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           16      5.82%     66.18% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           18      6.55%     72.73% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767           12      4.36%     77.09% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            8      2.91%     80.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            6      2.18%     82.18% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           49     17.82%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          275                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples          264                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean           424                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   260.079273                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   372.426347                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           66     25.00%     25.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           58     21.97%     46.97% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           27     10.23%     57.20% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           16      6.06%     63.26% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           17      6.44%     69.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            8      3.03%     72.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895           12      4.55%     77.27% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023           10      3.79%     81.06% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           50     18.94%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          264                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples           55                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      15.781818                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     15.596648                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      2.973282                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13             4      7.27%      7.27% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15            25     45.45%     52.73% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            21     38.18%     90.91% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      15.818182                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     15.638991                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      2.938196                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13             3      5.45%      5.45% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15            24     43.64%     49.09% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17            23     41.82%     90.91% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::18-19             4      7.27%     98.18% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::34-35             1      1.82%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::total            55                       # Reads before turning the bus around for writes
 system.mem_ctrls.wrPerTurnAround::samples           55                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.436364                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.408895                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.995613                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               45     81.82%     81.82% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                2      3.64%     85.45% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                2      3.64%     89.09% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                6     10.91%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.218182                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.206001                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.658025                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               49     89.09%     89.09% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                1      1.82%     90.91% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                4      7.27%     98.18% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19                1      1.82%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total            55                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                        10887                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   27664                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       4415                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        12.33                       # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat                        16225                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   33059                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       4430                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        18.31                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   31.33                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       527.83                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       540.38                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   1034.74                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                   1032.34                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   37.31                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       504.08                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       507.49                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    984.83                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    982.56                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         8.35                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.12                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    4.22                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         7.90                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     3.94                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    3.96                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      26.13                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      670                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     835                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 75.88                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                89.30                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         30.94                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    82.78                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   876960                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   487200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 4992000                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                4489344                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              6611280                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             63943740                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy              4795800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               86196324                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            849.408975                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE         8418                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF          3380                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         90483                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                  1156680                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   642600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 5366400                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                4385664                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              6611280                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             65375352                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              3540000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               87077976                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            858.097085                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE         5471                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          3380                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         92641                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED       107065                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.avgWrQLen                      26.10                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      674                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     833                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 76.07                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                90.15                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         32.51                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    83.26                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   735420                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   386400                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 4581024                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                3532896                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         8604960.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             13923048                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy               195072                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        30921360                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy         5237376                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               68117556                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            605.543213                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                81406                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE           88                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          3640                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN        13639                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         27313                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        67810                       # Time in different power states
+system.mem_ctrls_1.actEnergy                  1199520                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   633696                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 5540640                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                3917088                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         8604960.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             12524952                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               314880                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        33139344                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy         4427136                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               70302216                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            624.964139                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                83983                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          260                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          3640                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN        11529                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         24387                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        72674                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -303,8 +313,8 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON          107065                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                           107065                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON          112490                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                           112490                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6403                       # Number of instructions committed
@@ -323,7 +333,7 @@ system.cpu.num_mem_refs                          2060                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     107065                       # Number of busy cycles
+system.cpu.num_busy_cycles                     112490                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1056                       # Number of branches fetched
@@ -363,7 +373,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       6413                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED       107065                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   3458                       # delay histogram for all message
@@ -379,10 +389,10 @@ system.ruby.outstanding_req_hist_seqr::total         8464
 system.ruby.latency_hist_seqr::bucket_size           64                      
 system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples           8463                      
-system.ruby.latency_hist_seqr::mean         11.650951                      
-system.ruby.latency_hist_seqr::gmean         2.202191                      
-system.ruby.latency_hist_seqr::stdev        25.742711                      
-system.ruby.latency_hist_seqr            |        8220     97.13%     97.13% |         190      2.25%     99.37% |          41      0.48%     99.86% |           1      0.01%     99.87% |           6      0.07%     99.94% |           4      0.05%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean         12.291977                      
+system.ruby.latency_hist_seqr::gmean         2.221869                      
+system.ruby.latency_hist_seqr::stdev        27.407806                      
+system.ruby.latency_hist_seqr            |        7608     89.90%     89.90% |         798      9.43%     99.33% |          40      0.47%     99.80% |           5      0.06%     99.86% |           6      0.07%     99.93% |           6      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist_seqr::total             8463                      
 system.ruby.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.hit_latency_hist_seqr::max_bucket            9                      
@@ -394,21 +404,21 @@ system.ruby.hit_latency_hist_seqr::total         6732
 system.ruby.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.miss_latency_hist_seqr::samples         1731                      
-system.ruby.miss_latency_hist_seqr::mean    53.073368                      
-system.ruby.miss_latency_hist_seqr::gmean    47.451096                      
-system.ruby.miss_latency_hist_seqr::stdev    32.911544                      
-system.ruby.miss_latency_hist_seqr       |        1488     85.96%     85.96% |         190     10.98%     96.94% |          41      2.37%     99.31% |           1      0.06%     99.36% |           6      0.35%     99.71% |           4      0.23%     99.94% |           1      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    56.207395                      
+system.ruby.miss_latency_hist_seqr::gmean    49.560362                      
+system.ruby.miss_latency_hist_seqr::stdev    35.333412                      
+system.ruby.miss_latency_hist_seqr       |         876     50.61%     50.61% |         798     46.10%     96.71% |          40      2.31%     99.02% |           5      0.29%     99.31% |           6      0.35%     99.65% |           6      0.35%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist_seqr::total         1731                      
 system.ruby.Directory.incomplete_times_seqr         1730                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED       107065                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         6732                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses         1731                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         8463                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED       107065                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED       107065                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED       107065                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     8.074534                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     7.685128                      
 system.ruby.network.routers0.msg_count.Control::2         1731                      
 system.ruby.network.routers0.msg_count.Data::2         1727                      
 system.ruby.network.routers0.msg_count.Response_Data::4         1731                      
@@ -417,8 +427,8 @@ system.ruby.network.routers0.msg_bytes.Control::2        13848
 system.ruby.network.routers0.msg_bytes.Data::2       124344                      
 system.ruby.network.routers0.msg_bytes.Response_Data::4       124632                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3        13816                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED       107065                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     8.074534                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     7.685128                      
 system.ruby.network.routers1.msg_count.Control::2         1731                      
 system.ruby.network.routers1.msg_count.Data::2         1727                      
 system.ruby.network.routers1.msg_count.Response_Data::4         1731                      
@@ -427,8 +437,8 @@ system.ruby.network.routers1.msg_bytes.Control::2        13848
 system.ruby.network.routers1.msg_bytes.Data::2       124344                      
 system.ruby.network.routers1.msg_bytes.Response_Data::4       124632                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3        13816                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED       107065                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     8.074534                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     7.685128                      
 system.ruby.network.routers2.msg_count.Control::2         1731                      
 system.ruby.network.routers2.msg_count.Data::2         1727                      
 system.ruby.network.routers2.msg_count.Response_Data::4         1731                      
@@ -437,7 +447,7 @@ system.ruby.network.routers2.msg_bytes.Control::2        13848
 system.ruby.network.routers2.msg_bytes.Data::2       124344                      
 system.ruby.network.routers2.msg_bytes.Response_Data::4       124632                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3        13816                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED       107065                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Control            5193                      
 system.ruby.network.msg_count.Data               5181                      
 system.ruby.network.msg_count.Response_Data         5193                      
@@ -446,33 +456,33 @@ system.ruby.network.msg_byte.Control            41544
 system.ruby.network.msg_byte.Data              373032                      
 system.ruby.network.msg_byte.Response_Data       373896                      
 system.ruby.network.msg_byte.Writeback_Control        41448                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED       107065                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     8.082006                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     7.692239                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1731                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1727                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4       124632                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        13816                      
-system.ruby.network.routers0.throttle1.link_utilization     8.067062                      
+system.ruby.network.routers0.throttle1.link_utilization     7.678016                      
 system.ruby.network.routers0.throttle1.msg_count.Control::2         1731                      
 system.ruby.network.routers0.throttle1.msg_count.Data::2         1727                      
 system.ruby.network.routers0.throttle1.msg_bytes.Control::2        13848                      
 system.ruby.network.routers0.throttle1.msg_bytes.Data::2       124344                      
-system.ruby.network.routers1.throttle0.link_utilization     8.067062                      
+system.ruby.network.routers1.throttle0.link_utilization     7.678016                      
 system.ruby.network.routers1.throttle0.msg_count.Control::2         1731                      
 system.ruby.network.routers1.throttle0.msg_count.Data::2         1727                      
 system.ruby.network.routers1.throttle0.msg_bytes.Control::2        13848                      
 system.ruby.network.routers1.throttle0.msg_bytes.Data::2       124344                      
-system.ruby.network.routers1.throttle1.link_utilization     8.082006                      
+system.ruby.network.routers1.throttle1.link_utilization     7.692239                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1731                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1727                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4       124632                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        13816                      
-system.ruby.network.routers2.throttle0.link_utilization     8.082006                      
+system.ruby.network.routers2.throttle0.link_utilization     7.692239                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1731                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1727                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4       124632                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        13816                      
-system.ruby.network.routers2.throttle1.link_utilization     8.067062                      
+system.ruby.network.routers2.throttle1.link_utilization     7.678016                      
 system.ruby.network.routers2.throttle1.msg_count.Control::2         1731                      
 system.ruby.network.routers2.throttle1.msg_count.Data::2         1727                      
 system.ruby.network.routers2.throttle1.msg_bytes.Control::2        13848                      
@@ -490,10 +500,10 @@ system.ruby.delayVCHist.vnet_2::total            1727                       # de
 system.ruby.LD.latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.latency_hist_seqr::samples         1185                      
-system.ruby.LD.latency_hist_seqr::mean      31.532489                      
-system.ruby.LD.latency_hist_seqr::gmean     10.421226                      
-system.ruby.LD.latency_hist_seqr::stdev     34.906160                      
-system.ruby.LD.latency_hist_seqr         |        1091     92.07%     92.07% |          75      6.33%     98.40% |          15      1.27%     99.66% |           0      0.00%     99.66% |           2      0.17%     99.83% |           1      0.08%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      33.356118                      
+system.ruby.LD.latency_hist_seqr::gmean     10.708915                      
+system.ruby.LD.latency_hist_seqr::stdev     36.387225                      
+system.ruby.LD.latency_hist_seqr         |         862     72.74%     72.74% |         301     25.40%     98.14% |          16      1.35%     99.49% |           3      0.25%     99.75% |           1      0.08%     99.83% |           2      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_seqr::total          1185                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
@@ -505,18 +515,18 @@ system.ruby.LD.hit_latency_hist_seqr::total          457
 system.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.miss_latency_hist_seqr::samples          728                      
-system.ruby.LD.miss_latency_hist_seqr::mean    50.699176                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    45.385232                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    32.101179                      
-system.ruby.LD.miss_latency_hist_seqr    |         634     87.09%     87.09% |          75     10.30%     97.39% |          15      2.06%     99.45% |           0      0.00%     99.45% |           2      0.27%     99.73% |           1      0.14%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    53.667582                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    47.442261                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    32.940895                      
+system.ruby.LD.miss_latency_hist_seqr    |         405     55.63%     55.63% |         301     41.35%     96.98% |          16      2.20%     99.18% |           3      0.41%     99.59% |           1      0.14%     99.73% |           2      0.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          728                      
 system.ruby.ST.latency_hist_seqr::bucket_size           32                      
 system.ruby.ST.latency_hist_seqr::max_bucket          319                      
 system.ruby.ST.latency_hist_seqr::samples          865                      
-system.ruby.ST.latency_hist_seqr::mean      16.426590                      
-system.ruby.ST.latency_hist_seqr::gmean      3.318487                      
-system.ruby.ST.latency_hist_seqr::stdev     28.264983                      
-system.ruby.ST.latency_hist_seqr         |         592     68.44%     68.44% |         242     27.98%     96.42% |          21      2.43%     98.84% |           1      0.12%     98.96% |           4      0.46%     99.42% |           4      0.46%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           1      0.12%    100.00%
+system.ruby.ST.latency_hist_seqr::mean      17.479769                      
+system.ruby.ST.latency_hist_seqr::gmean      3.361529                      
+system.ruby.ST.latency_hist_seqr::stdev     31.340829                      
+system.ruby.ST.latency_hist_seqr         |         592     68.44%     68.44% |         160     18.50%     86.94% |         102     11.79%     98.73% |           0      0.00%     98.73% |           4      0.46%     99.19% |           4      0.46%     99.65% |           1      0.12%     99.77% |           0      0.00%     99.77% |           1      0.12%     99.88% |           1      0.12%    100.00%
 system.ruby.ST.latency_hist_seqr::total           865                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
@@ -528,18 +538,18 @@ system.ruby.ST.hit_latency_hist_seqr::total          592
 system.ruby.ST.miss_latency_hist_seqr::bucket_size           32                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket          319                      
 system.ruby.ST.miss_latency_hist_seqr::samples          273                      
-system.ruby.ST.miss_latency_hist_seqr::mean    49.879121                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    44.729882                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    29.942777                      
-system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |         242     88.64%     88.64% |          21      7.69%     96.34% |           1      0.37%     96.70% |           4      1.47%     98.17% |           4      1.47%     99.63% |           0      0.00%     99.63% |           0      0.00%     99.63% |           0      0.00%     99.63% |           1      0.37%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean    53.216117                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    46.594106                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    35.315815                      
+system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |         160     58.61%     58.61% |         102     37.36%     95.97% |           0      0.00%     95.97% |           4      1.47%     97.44% |           4      1.47%     98.90% |           1      0.37%     99.27% |           0      0.00%     99.27% |           1      0.37%     99.63% |           1      0.37%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total          273                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples         6413                      
-system.ruby.IFETCH.latency_hist_seqr::mean     7.333073                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.563492                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    21.145733                      
-system.ruby.IFETCH.latency_hist_seqr     |        6295     98.16%     98.16% |          93      1.45%     99.61% |          18      0.28%     99.89% |           1      0.02%     99.91% |           3      0.05%     99.95% |           3      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     7.699984                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.571280                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    22.534194                      
+system.ruby.IFETCH.latency_hist_seqr     |        5994     93.47%     93.47% |         395      6.16%     99.63% |          16      0.25%     99.88% |           1      0.02%     99.89% |           3      0.05%     99.94% |           4      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         6413                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
@@ -551,18 +561,18 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total         5683
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          730                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    56.635616                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    50.712708                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    34.440483                      
-system.ruby.IFETCH.miss_latency_hist_seqr |         612     83.84%     83.84% |          93     12.74%     96.58% |          18      2.47%     99.04% |           1      0.14%     99.18% |           3      0.41%     99.59% |           3      0.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    59.858904                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    52.975537                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    37.310775                      
+system.ruby.IFETCH.miss_latency_hist_seqr |         311     42.60%     42.60% |         395     54.11%     96.71% |          16      2.19%     98.90% |           1      0.14%     99.04% |           3      0.41%     99.45% |           4      0.55%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          730                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::samples         1731                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean    53.073368                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    47.451096                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    32.911544                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |        1488     85.96%     85.96% |         190     10.98%     96.94% |          41      2.37%     99.31% |           1      0.06%     99.36% |           6      0.35%     99.71% |           4      0.23%     99.94% |           1      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean    56.207395                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    49.560362                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    35.333412                      
+system.ruby.Directory.miss_mach_latency_hist_seqr |         876     50.61%     50.61% |         798     46.10%     96.71% |          40      2.31%     99.02% |           5      0.29%     99.31% |           6      0.35%     99.65% |           6      0.35%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist_seqr::total         1731                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket            9                      
@@ -593,26 +603,26 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples          728                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    50.699176                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    45.385232                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    32.101179                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |         634     87.09%     87.09% |          75     10.30%     97.39% |          15      2.06%     99.45% |           0      0.00%     99.45% |           2      0.27%     99.73% |           1      0.14%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    53.667582                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    47.442261                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    32.940895                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |         405     55.63%     55.63% |         301     41.35%     96.98% |          16      2.20%     99.18% |           3      0.41%     99.59% |           1      0.14%     99.73% |           2      0.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total          728                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          273                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    49.879121                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    44.729882                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    29.942777                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         242     88.64%     88.64% |          21      7.69%     96.34% |           1      0.37%     96.70% |           4      1.47%     98.17% |           4      1.47%     99.63% |           0      0.00%     99.63% |           0      0.00%     99.63% |           0      0.00%     99.63% |           1      0.37%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    53.216117                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    46.594106                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    35.315815                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         160     58.61%     58.61% |         102     37.36%     95.97% |           0      0.00%     95.97% |           4      1.47%     97.44% |           4      1.47%     98.90% |           1      0.37%     99.27% |           0      0.00%     99.27% |           1      0.37%     99.63% |           1      0.37%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          273                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples          730                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    56.635616                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    50.712708                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    34.440483                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         612     83.84%     83.84% |          93     12.74%     96.58% |          18      2.47%     99.04% |           1      0.14%     99.18% |           3      0.41%     99.59% |           3      0.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    59.858904                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    52.975537                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    37.310775                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         311     42.60%     42.60% |         395     54.11%     96.71% |          16      2.19%     98.90% |           1      0.14%     99.04% |           3      0.41%     99.45% |           4      0.55%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total          730                      
 system.ruby.Directory_Controller.GETX            1731      0.00%      0.00%
 system.ruby.Directory_Controller.PUTX            1727      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
index ccd9350bc..220cfeeae 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
@@ -149,7 +149,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -583,7 +583,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -643,7 +643,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -760,6 +760,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -779,29 +780,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -821,6 +829,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -852,9 +861,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout
index 115f46689..fff19a530 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:24
-gem5 executing on e108600-lin, pid 39579
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:45
+gem5 executing on e108600-lin, pid 28071
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 20329000 because target called exit()
+Exiting @ tick 22083000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
index 95775a988..a6e87b576 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000021                       # Number of seconds simulated
-sim_ticks                                    20616000                       # Number of ticks simulated
-final_tick                                   20616000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000022                       # Number of seconds simulated
+sim_ticks                                    22083000                       # Number of ticks simulated
+final_tick                                   22083000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  91304                       # Simulator instruction rate (inst/s)
-host_op_rate                                    91266                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              727585147                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252076                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                 143746                       # Simulator instruction rate (inst/s)
+host_op_rate                                   143654                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1226490189                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251004                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        2585                       # Number of instructions simulated
 sim_ops                                          2585                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     20616000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED     22083000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             14400                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              5440                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                19840                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           14400                       # Nu
 system.physmem.num_reads::cpu.inst                225                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   310                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            698486612                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            263872720                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               962359333                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       698486612                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          698486612                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           698486612                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           263872720                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              962359333                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            652085314                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            246343341                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               898428656                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       652085314                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          652085314                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           652085314                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           246343341                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              898428656                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           310                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         310                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        20527500                       # Total gap between requests
+system.physmem.totGap                        21988500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,8 +91,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       246                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       245                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        62                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -188,77 +188,87 @@ system.physmem.wrQLenPdf::61                        0                       # Wh
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples           41                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      424.585366                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     277.937119                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     331.553388                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      429.268293                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     281.212133                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.776868                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::0-127             10     24.39%     24.39% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::128-255            6     14.63%     39.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            5     12.20%     51.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            2      4.88%     56.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            6     14.63%     70.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      4.88%     75.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            4      9.76%     85.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            3      7.32%     92.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            6     14.63%     53.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            2      4.88%     58.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      7.32%     65.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      4.88%     70.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            7     17.07%     87.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      4.88%     92.68% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            3      7.32%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             41                       # Bytes accessed per row activation
-system.physmem.totQLat                        1590750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   7403250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        3615250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   9427750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1550000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5131.45                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       11662.10                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23881.45                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         962.36                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30412.10                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         898.43                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      962.36                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      898.43                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           7.52                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.52                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           7.02                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.24                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.26                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        260                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.87                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        66217.74                       # Average gap between requests
+system.physmem.avgGap                        70930.65                       # Average gap between requests
 system.physmem.pageHitRate                      83.87                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                      83160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                      45375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                    787800                       # Energy for read commands per rank (pJ)
+system.physmem_0.actEnergy                     114240                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                      45540                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                    885360                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10790100                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  34500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 12758055                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              805.814306                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         727750                       # Time in different power states
+system.physmem_0.refreshEnergy           1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                1636470                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  32160                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy           7529700                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy            729120                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                 12201870                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              552.527084                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime               18356500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE          27500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        15310750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     189000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     103125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1162200                       # Energy for read commands per rank (pJ)
+system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN      1898500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT         3124750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     16512250                       # Time in different power states
+system.physmem_1.actEnergy                     242760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     110055                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1328040                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10417320                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 361500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 13250265                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              836.902890                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         560000                       # Time in different power states
+system.physmem_1.refreshEnergy           1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                2565570                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 217440                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy           7221900                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy             20640                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                 12935685                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              585.755816                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime               15168500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE         498000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14766250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     20616000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                     794                       # Number of BP lookups
-system.cpu.branchPred.condPredicted               394                       # Number of conditional branches predicted
+system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN        53000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         5182750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN     15829250                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     22083000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                     793                       # Number of BP lookups
+system.cpu.branchPred.condPredicted               395                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               170                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                  562                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups                  561                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                      54                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct              9.608541                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct              9.625668                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     144                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  2                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups              83                       # Number of indirect predictor lookups.
@@ -282,10 +292,10 @@ system.cpu.dtb.data_hits                          813                       # DT
 system.cpu.dtb.data_misses                         12                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_accesses                      825                       # DTB accesses
-system.cpu.itb.fetch_hits                         979                       # ITB hits
+system.cpu.itb.fetch_hits                         980                       # ITB hits
 system.cpu.itb.fetch_misses                        13                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                     992                       # ITB accesses
+system.cpu.itb.fetch_accesses                     993                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -299,16 +309,16 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        20616000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            41232                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        22083000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            44166                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2585                       # Number of instructions committed
 system.cpu.committedOps                          2585                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                           573                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              15.950484                       # CPI: cycles per instruction
-system.cpu.ipc                               0.062694                       # IPC: instructions per cycle
+system.cpu.cpi                              17.085493                       # CPI: cycles per instruction
+system.cpu.ipc                               0.058529                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                 189      7.31%      7.31% # Class of committed instruction
 system.cpu.op_class_0::IntAlu                    1678     64.91%     72.22% # Class of committed instruction
 system.cpu.op_class_0::IntMult                      1      0.04%     72.26% # Class of committed instruction
@@ -344,25 +354,25 @@ system.cpu.op_class_0::MemWrite                   298     11.53%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                     2585                       # Class of committed instruction
-system.cpu.tickCycles                            5423                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           35809                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     20616000                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                            5429                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           38737                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     22083000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            48.342284                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            48.291787                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                 692                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              8.141176                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    48.342284                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.011802                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011802                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    48.291787                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011790                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011790                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           54                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              1673                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             1673                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     20616000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     22083000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data          441                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             441                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          251                       # number of WriteReq hits
@@ -379,14 +389,14 @@ system.cpu.dcache.demand_misses::cpu.data          102                       # n
 system.cpu.dcache.demand_misses::total            102                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          102                       # number of overall misses
 system.cpu.dcache.overall_misses::total           102                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4617500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4617500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      3301000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      3301000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      7918500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7918500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      7918500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7918500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      5143500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      5143500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      3553000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      3553000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      8696500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      8696500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      8696500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      8696500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data          500                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total          500                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
@@ -403,14 +413,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.128463
 system.cpu.dcache.demand_miss_rate::total     0.128463                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.128463                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.128463                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78262.711864                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 78262.711864                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76767.441860                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76767.441860                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 77632.352941                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 77632.352941                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 77632.352941                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 77632.352941                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87177.966102                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 87177.966102                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82627.906977                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 82627.906977                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 85259.803922                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 85259.803922                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 85259.803922                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 85259.803922                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -433,14 +443,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data           85
 system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4487000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4487000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2044500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2044500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6531500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6531500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6531500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6531500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5007000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5007000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2203500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2203500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7210500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7210500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7210500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7210500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.116000                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.116000                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.091837                       # mshr miss rate for WriteReq accesses
@@ -449,67 +459,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.107053
 system.cpu.dcache.demand_mshr_miss_rate::total     0.107053                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.107053                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.107053                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77362.068966                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77362.068966                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75722.222222                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75722.222222                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76841.176471                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76841.176471                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76841.176471                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76841.176471                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     20616000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86327.586207                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86327.586207                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81611.111111                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81611.111111                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84829.411765                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 84829.411765                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84829.411765                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 84829.411765                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     22083000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           119.307121                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 754                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           118.973491                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 755                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               225                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              3.351111                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.355556                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   119.307121                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.058255                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.058255                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   118.973491                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.058093                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.058093                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          225                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.109863                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              2183                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             2183                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     20616000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst          754                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             754                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           754                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              754                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          754                       # number of overall hits
-system.cpu.icache.overall_hits::total             754                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              2185                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             2185                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     22083000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst          755                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             755                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           755                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              755                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          755                       # number of overall hits
+system.cpu.icache.overall_hits::total             755                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          225                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           225                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          225                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            225                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          225                       # number of overall misses
 system.cpu.icache.overall_misses::total           225                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     17383000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     17383000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     17383000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     17383000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     17383000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     17383000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst          979                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total          979                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst          979                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total          979                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst          979                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total          979                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.229826                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.229826                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.229826                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.229826                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.229826                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.229826                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77257.777778                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 77257.777778                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 77257.777778                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 77257.777778                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 77257.777778                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 77257.777778                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     18729500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     18729500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     18729500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     18729500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     18729500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     18729500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          980                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          980                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          980                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          980                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          980                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          980                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.229592                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.229592                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.229592                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.229592                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.229592                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.229592                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83242.222222                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 83242.222222                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 83242.222222                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 83242.222222                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 83242.222222                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 83242.222222                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -522,43 +532,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          225
 system.cpu.icache.demand_mshr_misses::total          225                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          225                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          225                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     17158000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     17158000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     17158000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     17158000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     17158000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     17158000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.229826                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.229826                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.229826                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.229826                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.229826                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.229826                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76257.777778                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76257.777778                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 76257.777778                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 76257.777778                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     20616000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     18504500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     18504500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     18504500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     18504500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     18504500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     18504500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.229592                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.229592                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.229592                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.229592                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.229592                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.229592                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82242.222222                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82242.222222                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82242.222222                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 82242.222222                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82242.222222                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 82242.222222                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     22083000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          167.807293                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          167.412677                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              310                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   119.421716                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    48.385576                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003644                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001477                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005121                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   119.080474                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    48.332203                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003634                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001475                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005109                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          310                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          189                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.009460                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             2790                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            2790                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     20616000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     22083000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.ReadExReq_misses::cpu.data           27                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           27                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          225                       # number of ReadCleanReq misses
@@ -571,18 +581,18 @@ system.cpu.l2cache.demand_misses::total           310                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          225                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data           85                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          310                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2004000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2004000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     16820500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     16820500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4399000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      4399000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     16820500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      6403000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     23223500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     16820500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      6403000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     23223500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2163000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2163000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     18167000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     18167000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4919000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      4919000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     18167000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7082000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     25249000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     18167000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7082000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     25249000                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           27                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           27                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          225                       # number of ReadCleanReq accesses(hits+misses)
@@ -607,18 +617,18 @@ system.cpu.l2cache.demand_miss_rate::total            1                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74222.222222                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74222.222222                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74757.777778                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74757.777778                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75844.827586                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75844.827586                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74757.777778                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75329.411765                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74914.516129                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74757.777778                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75329.411765                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74914.516129                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80111.111111                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80111.111111                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80742.222222                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80742.222222                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84810.344828                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84810.344828                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80742.222222                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83317.647059                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81448.387097                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80742.222222                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83317.647059                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81448.387097                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -637,18 +647,18 @@ system.cpu.l2cache.demand_mshr_misses::total          310
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          225                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          310                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1734000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1734000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     14570500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     14570500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      3819000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      3819000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     14570500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5553000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     20123500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     14570500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5553000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     20123500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1893000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1893000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     15917000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     15917000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4339000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4339000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15917000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6232000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     22149000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15917000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6232000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     22149000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
@@ -661,25 +671,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total            1
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64222.222222                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64222.222222                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64757.777778                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64757.777778                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65844.827586                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65844.827586                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64757.777778                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65329.411765                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64914.516129                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64757.777778                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65329.411765                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64914.516129                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70111.111111                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70111.111111                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70742.222222                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70742.222222                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74810.344828                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74810.344828                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70742.222222                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73317.647059                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71448.387097                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70742.222222                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73317.647059                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71448.387097                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests          310                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     20616000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     22083000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           283                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           27                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           27                       # Transaction distribution
@@ -705,9 +715,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value            0                       #
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::total            310                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         155000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
+system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        337500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.6                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        127500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
 system.membus.snoop_filter.tot_requests           310                       # Total number of requests made to the snoop filter.
@@ -716,7 +726,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     20616000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     22083000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                283                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                27                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               27                       # Transaction distribution
@@ -737,9 +747,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 310                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              363000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.8                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              362500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.6                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            1648750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              8.0                       # Layer utilization (%)
+system.membus.respLayer1.utilization              7.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 39c72e110..ff6825b17 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -591,7 +591,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -708,6 +708,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -727,29 +728,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -769,6 +777,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -800,9 +809,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
index 5515360ee..35f169b23 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:24
-gem5 executing on e108600-lin, pid 39577
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:49
+gem5 executing on e108600-lin, pid 28097
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 12409500 because target called exit()
+Exiting @ tick 13358500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index cdae5e837..cecea8f6e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000013                       # Number of seconds simulated
-sim_ticks                                    12542500                       # Number of ticks simulated
-final_tick                                   12542500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    13358500                       # Number of ticks simulated
+final_tick                                   13358500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60996                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60977                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              320317516                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253100                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                  53089                       # Simulator instruction rate (inst/s)
+host_op_rate                                    53060                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              296795260                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251260                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     12542500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED     13358500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             11968                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              5440                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                17408                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           11968                       # Nu
 system.physmem.num_reads::cpu.inst                187                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   272                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            954195735                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            433725334                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1387921068                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       954195735                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          954195735                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           954195735                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           433725334                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1387921068                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            895908972                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            407231351                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1303140323                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       895908972                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          895908972                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           895908972                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           407231351                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1303140323                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           272                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         272                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        12445000                       # Total gap between requests
+system.physmem.totGap                        13255000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,10 +91,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       157                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       155                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                        80                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -188,81 +188,91 @@ system.physmem.wrQLenPdf::61                        0                       # Wh
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples           36                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      394.666667                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     235.952583                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     357.320824                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean             384                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     235.532687                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     344.140835                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::0-127             12     33.33%     33.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255            5     13.89%     47.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            3      8.33%     55.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            3      8.33%     63.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            3      8.33%     72.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      5.56%     77.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      5.56%     83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255            4     11.11%     44.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            4     11.11%     55.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            6     16.67%     72.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      5.56%     77.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      2.78%     80.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      2.78%     83.33% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023            1      2.78%     86.11% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            5     13.89%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             36                       # Bytes accessed per row activation
-system.physmem.totQLat                        1866000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   6966000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        3364250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   8464250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1360000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6860.29                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       12368.57                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25610.29                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1387.92                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31118.57                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1303.14                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1387.92                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1303.14                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.84                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.84                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.18                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.18                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.70                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.73                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        226                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        224                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.09                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   82.35                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        45753.68                       # Average gap between requests
-system.physmem.pageHitRate                      83.09                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                      68040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                      37125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                    585000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        48731.62                       # Average gap between requests
+system.physmem.pageHitRate                      82.35                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                      99960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                      37950                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                    756840                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                 508560                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy                5478840                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  21750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                  6699315                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              832.600901                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE          22500                       # Time in different power states
+system.physmem_0.refreshEnergy           614640.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                1355460                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  21600                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy           4583370                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy            107040                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                  7576860                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              567.183307                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime               10278500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE          28500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          260000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT         7777500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     128520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                      70125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                    787800                       # Energy for read commands per rank (pJ)
+system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN       279000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT         2735250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     10055750                       # Time in different power states
+system.physmem_1.actEnergy                     242760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                      98670                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1185240                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                 508560                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy                5198400                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 267750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                  6961155                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              865.142768                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         432500                       # Time in different power states
+system.physmem_1.refreshEnergy           614640.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                1822290                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 183840                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy           4050420                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy               480                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                  8198340                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              613.705624                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime                8246250                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE         450500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          260000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT         7367500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     12542500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    1001                       # Number of BP lookups
-system.cpu.branchPred.condPredicted               492                       # Number of conditional branches predicted
+system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN         1250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         3767500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN      8879250                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     13358500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                     994                       # Number of BP lookups
+system.cpu.branchPred.condPredicted               488                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               213                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                  687                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     176                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups                  684                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     175                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             25.618632                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     220                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             25.584795                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     218                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 18                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups             100                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits                  3                       # Number of indirect target hits.
+system.cpu.branchPred.indirectLookups              99                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits                  2                       # Number of indirect target hits.
 system.cpu.branchPred.indirectMisses               97                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted           33                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -270,22 +280,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                          712                       # DTB read hits
-system.cpu.dtb.read_misses                         13                       # DTB read misses
+system.cpu.dtb.read_hits                          705                       # DTB read hits
+system.cpu.dtb.read_misses                         10                       # DTB read misses
 system.cpu.dtb.read_acv                             1                       # DTB read access violations
-system.cpu.dtb.read_accesses                      725                       # DTB read accesses
+system.cpu.dtb.read_accesses                      715                       # DTB read accesses
 system.cpu.dtb.write_hits                         349                       # DTB write hits
-system.cpu.dtb.write_misses                        17                       # DTB write misses
+system.cpu.dtb.write_misses                        16                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     366                       # DTB write accesses
-system.cpu.dtb.data_hits                         1061                       # DTB hits
-system.cpu.dtb.data_misses                         30                       # DTB misses
+system.cpu.dtb.write_accesses                     365                       # DTB write accesses
+system.cpu.dtb.data_hits                         1054                       # DTB hits
+system.cpu.dtb.data_misses                         26                       # DTB misses
 system.cpu.dtb.data_acv                             1                       # DTB access violations
-system.cpu.dtb.data_accesses                     1091                       # DTB accesses
-system.cpu.itb.fetch_hits                         877                       # ITB hits
+system.cpu.dtb.data_accesses                     1080                       # DTB accesses
+system.cpu.itb.fetch_hits                         872                       # ITB hits
 system.cpu.itb.fetch_misses                        32                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                     909                       # ITB accesses
+system.cpu.itb.fetch_accesses                     904                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -299,193 +309,193 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        12542500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            25086                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        13358500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            26718                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               4377                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                           6059                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        1001                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                399                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          1174                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.icacheStallCycles               4379                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                           6026                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                         994                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                395                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          1172                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                     472                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   18                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1154                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles          1202                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                       877                       # Number of cache lines fetched
+system.cpu.fetch.CacheLines                       872                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   147                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples               6970                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.869297                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.271813                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples               7018                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.858649                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.260497                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     5938     85.19%     85.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                       27      0.39%     85.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      100      1.43%     87.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                       87      1.25%     88.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      141      2.02%     90.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                       81      1.16%     91.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       45      0.65%     92.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                       76      1.09%     93.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      475      6.81%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     5993     85.39%     85.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                       27      0.38%     85.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                       97      1.38%     87.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                       87      1.24%     88.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      140      1.99%     90.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                       81      1.15%     91.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                       45      0.64%     92.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                       75      1.07%     93.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      473      6.74%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                 6970                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.039903                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.241529                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     5221                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                   627                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                       919                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    40                       # Number of cycles decode is unblocking
+system.cpu.fetch.rateDist::total                 7018                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.037203                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.225541                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     5261                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                   642                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                       913                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    39                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                    163                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  145                       # Number of times decode resolved a branch
+system.cpu.decode.BranchResolved                  144                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                    75                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                   5274                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts                   5228                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   263                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    163                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     5296                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     329                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            290                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                       881                       # Number of cycles rename is running
+system.cpu.rename.IdleCycles                     5336                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     333                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            302                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                       873                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles                    11                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                   5069                       # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts                   5015                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     1                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                      2                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RenamedOperands                3638                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                  5669                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups             5662                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands                3598                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                  5603                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups             5596                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 6                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  1768                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     1870                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     1830                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                  8                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts              6                       # count of temporary serializing insts renamed
 system.cpu.rename.skidInsts                        62                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                  846                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                 428                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
+system.cpu.memDep0.insertedLoads                  838                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                 424                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 0                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       4387                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                       4336                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                   6                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      3758                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                28                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            2005                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         1025                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      3724                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                19                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            1954                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined          987                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples          6970                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.539168                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.278867                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples          7018                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.530636                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.266302                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                5524     79.25%     79.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                 467      6.70%     85.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 343      4.92%     90.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 254      3.64%     94.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 193      2.77%     97.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 103      1.48%     98.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                  56      0.80%     99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  20      0.29%     99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  10      0.14%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                5580     79.51%     79.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 466      6.64%     86.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 341      4.86%     91.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 254      3.62%     94.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 190      2.71%     97.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 104      1.48%     98.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  55      0.78%     99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  20      0.28%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                   8      0.11%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total            6970                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total            7018                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       6      9.84%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     31     50.82%     60.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    24     39.34%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       6     10.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     30     50.00%     60.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    24     40.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  2627     69.90%     69.90% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.03%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                  757     20.14%     90.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                 373      9.93%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  2606     69.98%     69.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.03%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                  745     20.01%     90.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                 372      9.99%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   3758                       # Type of FU issued
-system.cpu.iq.rate                           0.149805                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                          61                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.016232                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              14562                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes              6395                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         3419                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   3724                       # Type of FU issued
+system.cpu.iq.rate                           0.139382                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                          60                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.016112                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              14532                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes              6293                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         3394                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  13                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  6                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            6                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   3812                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   3777                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       7                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               33                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               32                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads          431                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads          423                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            4                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          134                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          130                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            56                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            42                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles                    163                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     299                       # Number of cycles IEW is blocking
+system.cpu.iew.iewBlockCycles                     304                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                     3                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts                4700                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts                4648                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                46                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                   846                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                  428                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts                   838                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                  424                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                  6                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
@@ -493,41 +503,41 @@ system.cpu.iew.memOrderViolationEvents              4                       # Nu
 system.cpu.iew.predictedTakenIncorrect             33                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          132                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                  165                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  3634                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                   727                       # Number of load instructions executed
+system.cpu.iew.iewExecutedInsts                  3600                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                   717                       # Number of load instructions executed
 system.cpu.iew.iewExecSquashedInsts               124                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                           307                       # number of nop insts executed
-system.cpu.iew.exec_refs                         1093                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                      599                       # Number of branches executed
-system.cpu.iew.exec_stores                        366                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.144862                       # Inst execution rate
-system.cpu.iew.wb_sent                           3483                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          3425                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      1633                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      2097                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.136530                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.778732                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts            2122                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                           306                       # number of nop insts executed
+system.cpu.iew.exec_refs                         1082                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                      595                       # Number of branches executed
+system.cpu.iew.exec_stores                        365                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.134741                       # Inst execution rate
+system.cpu.iew.wb_sent                           3453                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          3400                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      1619                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      2076                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.127255                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.779865                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts            2070                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls               4                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               140                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples         6555                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.392982                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.248476                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples         6610                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.389713                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.245121                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         5684     86.71%     86.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          198      3.02%     89.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          318      4.85%     94.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          118      1.80%     96.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4           63      0.96%     97.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           53      0.81%     98.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           37      0.56%     98.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           23      0.35%     99.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           61      0.93%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         5740     86.84%     86.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          197      2.98%     89.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          319      4.83%     94.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          117      1.77%     96.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4           63      0.95%     97.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           53      0.80%     98.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           36      0.54%     98.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           23      0.35%     99.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           62      0.94%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total         6555                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total         6610                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 2576                       # Number of instructions committed
 system.cpu.commit.committedOps                   2576                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -573,47 +583,47 @@ system.cpu.commit.op_class_0::MemWrite            294     11.41%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              2576                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                    61                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        10945                       # The number of ROB reads
-system.cpu.rob.rob_writes                        9815                       # The number of ROB writes
+system.cpu.commit.bw_lim_events                    62                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        10947                       # The number of ROB reads
+system.cpu.rob.rob_writes                        9704                       # The number of ROB writes
 system.cpu.timesIdled                             154                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           18116                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           19700                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
 system.cpu.committedOps                          2387                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                              10.509426                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                        10.509426                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.095153                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.095153                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     4383                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    2640                       # number of integer regfile writes
+system.cpu.cpi                              11.193129                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                        11.193129                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.089341                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.089341                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     4344                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    2618                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     12542500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     13358500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            45.419736                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 735                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            45.378002                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 743                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.647059                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.741176                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    45.419736                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.011089                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011089                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    45.378002                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011079                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011079                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              1919                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             1919                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     12542500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data          522                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             522                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              1935                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             1935                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     13358500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data          530                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             530                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          213                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            213                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data           735                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total              735                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data          735                       # number of overall hits
-system.cpu.dcache.overall_hits::total             735                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data           743                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              743                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data          743                       # number of overall hits
+system.cpu.dcache.overall_hits::total             743                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          101                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           101                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           81                       # number of WriteReq misses
@@ -622,43 +632,43 @@ system.cpu.dcache.demand_misses::cpu.data          182                       # n
 system.cpu.dcache.demand_misses::total            182                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          182                       # number of overall misses
 system.cpu.dcache.overall_misses::total           182                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      6754500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      6754500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5744000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5744000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     12498500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     12498500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     12498500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     12498500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data          623                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          623                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7124500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7124500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      6134000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      6134000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     13258500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     13258500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     13258500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     13258500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          631                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          631                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data          917                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total          917                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data          917                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total          917                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.162119                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.162119                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data          925                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          925                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data          925                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          925                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.160063                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.160063                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.275510                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.275510                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.198473                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.198473                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.198473                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.198473                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66876.237624                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66876.237624                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70913.580247                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70913.580247                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 68673.076923                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 68673.076923                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 68673.076923                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 68673.076923                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          260                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.196757                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.196757                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.196757                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.196757                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70539.603960                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 70539.603960                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75728.395062                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 75728.395062                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72848.901099                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72848.901099                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72848.901099                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72848.901099                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          269                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    43.333333                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    67.250000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           40                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           40                       # number of ReadReq MSHR hits
@@ -676,138 +686,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data           85
 system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4858000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4858000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1875000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1875000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6733000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6733000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6733000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6733000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.097913                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.097913                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5157500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5157500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2004000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2004000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7161500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7161500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7161500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7161500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.096672                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.096672                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081633                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081633                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.092694                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.092694                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.092694                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.092694                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79639.344262                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79639.344262                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        78125                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        78125                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79211.764706                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 79211.764706                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79211.764706                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 79211.764706                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     12542500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091892                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091892                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091892                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091892                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84549.180328                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84549.180328                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        83500                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        83500                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84252.941176                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 84252.941176                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84252.941176                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 84252.941176                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     13358500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse            90.302659                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 624                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse            89.996713                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 618                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               187                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              3.336898                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.304813                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    90.302659                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.044093                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.044093                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst    89.996713                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.043944                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.043944                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          187                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          150                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           37                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.091309                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              1941                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             1941                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     12542500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst          624                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             624                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           624                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              624                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          624                       # number of overall hits
-system.cpu.icache.overall_hits::total             624                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          253                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           253                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          253                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            253                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          253                       # number of overall misses
-system.cpu.icache.overall_misses::total           253                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     19081499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     19081499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     19081499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     19081499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     19081499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     19081499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst          877                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total          877                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst          877                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total          877                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst          877                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total          877                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.288483                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.288483                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.288483                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.288483                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.288483                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.288483                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75420.944664                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75420.944664                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75420.944664                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75420.944664                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75420.944664                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75420.944664                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          127                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses              1931                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             1931                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     13358500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst          618                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             618                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           618                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              618                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          618                       # number of overall hits
+system.cpu.icache.overall_hits::total             618                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          254                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           254                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          254                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            254                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          254                       # number of overall misses
+system.cpu.icache.overall_misses::total           254                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     20808999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     20808999                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     20808999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     20808999                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     20808999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     20808999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          872                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          872                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          872                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          872                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          872                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          872                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.291284                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.291284                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.291284                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.291284                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.291284                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.291284                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81925.192913                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 81925.192913                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 81925.192913                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 81925.192913                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 81925.192913                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 81925.192913                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          131                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    63.500000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    65.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           66                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           66                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           66                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           66                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           66                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           66                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           67                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           67                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           67                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           67                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           67                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           67                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          187                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          187                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          187                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          187                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          187                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          187                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14560999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     14560999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14560999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     14560999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14560999                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     14560999                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.213227                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.213227                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.213227                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.213227                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.213227                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.213227                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77866.304813                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77866.304813                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77866.304813                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 77866.304813                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77866.304813                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 77866.304813                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     12542500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15635499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     15635499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15635499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     15635499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15635499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     15635499                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.214450                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.214450                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.214450                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.214450                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.214450                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.214450                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83612.294118                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83612.294118                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83612.294118                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 83612.294118                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83612.294118                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 83612.294118                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     13358500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          135.950101                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          135.588512                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              272                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    90.459206                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    45.490894                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002761                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001388                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004149                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    90.143699                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    45.444813                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002751                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001387                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004138                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          272                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          217                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           55                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          207                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.008301                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             2448                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            2448                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     12542500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     13358500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.ReadExReq_misses::cpu.data           24                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           24                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          187                       # number of ReadCleanReq misses
@@ -820,18 +830,18 @@ system.cpu.l2cache.demand_misses::total           272                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          187                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data           85                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          272                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1837500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      1837500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     14279500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     14279500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4766500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      4766500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     14279500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      6604000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     20883500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     14279500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      6604000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     20883500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1966500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1966500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     15354000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     15354000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5066000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      5066000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     15354000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7032500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     22386500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     15354000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7032500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     22386500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           24                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           24                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          187                       # number of ReadCleanReq accesses(hits+misses)
@@ -856,18 +866,18 @@ system.cpu.l2cache.demand_miss_rate::total            1                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76562.500000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76562.500000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76360.962567                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76360.962567                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78139.344262                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78139.344262                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76360.962567                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77694.117647                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76777.573529                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76360.962567                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77694.117647                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76777.573529                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81937.500000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81937.500000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82106.951872                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82106.951872                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83049.180328                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83049.180328                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82106.951872                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82735.294118                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82303.308824                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82106.951872                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82735.294118                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82303.308824                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -886,18 +896,18 @@ system.cpu.l2cache.demand_mshr_misses::total          272
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          187                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          272                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1597500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1597500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     12409500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     12409500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4156500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4156500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12409500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5754000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     18163500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12409500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5754000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     18163500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1726500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1726500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     13484000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     13484000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4456000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4456000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     13484000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6182500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     19666500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     13484000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6182500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     19666500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
@@ -910,25 +920,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total            1
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66562.500000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66562.500000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66360.962567                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66360.962567                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68139.344262                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68139.344262                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66360.962567                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67694.117647                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66777.573529                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66360.962567                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67694.117647                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66777.573529                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71937.500000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71937.500000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72106.951872                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72106.951872                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73049.180328                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73049.180328                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72106.951872                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72735.294118                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72303.308824                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72106.951872                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72735.294118                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72303.308824                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests          272                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     12542500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     13358500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           248                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           24                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           24                       # Transaction distribution
@@ -954,9 +964,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value            0                       #
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::total            272                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         136000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
+system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        280500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization          2.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        127500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
 system.membus.snoop_filter.tot_requests           272                       # Total number of requests made to the snoop filter.
@@ -965,7 +975,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     12542500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     13358500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                248                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                24                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               24                       # Transaction distribution
@@ -987,8 +997,8 @@ system.membus.snoop_fanout::min_value               0                       # Re
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 272                       # Request fanout histogram
 system.membus.reqLayer0.occupancy              337500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            1440000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             11.5                       # Layer utilization (%)
+system.membus.reqLayer0.utilization               2.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            1437500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             10.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
index 214f11946..41209dc7f 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -249,10 +270,15 @@ children=directory requestToDir responseFromDir responseFromMemory responseToDir
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=6
 eventq_index=0
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestToDir=system.ruby.dir_cntrl0.requestToDir
 responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -311,6 +337,7 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache
 buffer_size=0
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 enable_prefetch=false
 eventq_index=0
 l1_request_latency=2
@@ -319,6 +346,10 @@ l2_select_num_bits=0
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 number_of_TBEs=256
 optionalQueue=system.ruby.l1_cntrl0.optionalQueue
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 prefetcher=system.ruby.l1_cntrl0.prefetcher
 recycle_latency=10
 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
@@ -447,17 +478,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.L1Dcache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.L1Icache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
@@ -480,10 +516,15 @@ L2cache=system.ruby.l2_cntrl0.L2cache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 l2_request_latency=2
 l2_response_latency=2
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
 responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
@@ -574,18 +615,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
 netifs=
 number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
 ruby_system=system.ruby
 topology=Crossbar
@@ -748,42 +794,216 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers18]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers19]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
 weight=1
 
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11
+power_model=Null
 router_id=0
 virt_nets=3
 
@@ -875,8 +1095,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11
+power_model=Null
 router_id=1
 virt_nets=3
 
@@ -968,8 +1194,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11
+power_model=Null
 router_id=2
 virt_nets=3
 
@@ -1061,8 +1293,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17
+power_model=Null
 router_id=3
 virt_nets=3
 
@@ -1195,9 +1433,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
index 1c18978fa..63982fce4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
@@ -4,9 +4,8 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
 warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
index 321d1816d..fcadeb2be 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
+Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:01:33
-gem5 started Jan 21 2016 14:02:10
-gem5 executing on zizzer, pid 44711
-command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level
+gem5 compiled Oct 13 2016 20:28:06
+gem5 started Oct 13 2016 20:28:32
+gem5 executing on e108600-lin, pid 8237
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 45733 because target called exit()
+Exiting @ tick 48659 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
index 5ca935512..d4dee56c3 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000046                       # Number of seconds simulated
-sim_ticks                                       45733                       # Number of ticks simulated
-final_tick                                      45733                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000049                       # Number of seconds simulated
+sim_ticks                                       48659                       # Number of ticks simulated
+final_tick                                      48659                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  61876                       # Simulator instruction rate (inst/s)
-host_op_rate                                    61863                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1097622                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 452416                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                  43978                       # Simulator instruction rate (inst/s)
+host_op_rate                                    43962                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 829814                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 410700                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        35008                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              35008                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0         6592                       # Number of bytes written to this memory
@@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0          547                       #
 system.mem_ctrls.num_reads::total                 547                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0          103                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                103                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    765486629                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             765486629                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    144140992                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            144140992                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0    909627621                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total            909627621                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    719455805                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             719455805                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    135473396                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            135473396                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    854929201                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            854929201                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                         547                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                        103                       # Number of write requests accepted
 system.mem_ctrls.readBursts                       547                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                1                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         45654                       # Total gap between requests
+system.mem_ctrls.totGap                         48574                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -185,20 +185,20 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples           74                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    358.054054                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   233.275053                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   307.922241                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           18     24.32%     24.32% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           18     24.32%     48.65% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383            8     10.81%     59.46% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511            4      5.41%     64.86% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639            9     12.16%     77.03% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            7      9.46%     86.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            3      4.05%     90.54% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            1      1.35%     91.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151            6      8.11%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total           74                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples           83                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    339.277108                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   221.785975                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   292.728223                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           23     27.71%     27.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           19     22.89%     50.60% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383            6      7.23%     57.83% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           10     12.05%     69.88% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           11     13.25%     83.13% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            4      4.82%     87.95% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            3      3.61%     91.57% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            3      3.61%     95.18% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151            4      4.82%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total           83                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples            1                       # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::mean            268                       # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::gmean    268.000000                       # Reads before turning the bus around for writes
@@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean     16.000000                       # Wr
 system.mem_ctrls.wrPerTurnAround::stdev           nan                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::16                1    100.00%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total             1                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         2733                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   11055                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totQLat                         5659                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   13981                       # Total ticks spent from burst creation until serviced by the DRAM
 system.mem_ctrls.totBusLat                       2190                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         6.24                       # Average queueing delay per DRAM burst
+system.mem_ctrls.avgQLat                        12.92                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   25.24                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       612.95                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                        22.39                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    765.49                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    144.14                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   31.92                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       576.09                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                        21.04                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    719.46                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    135.47                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         4.96                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.79                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    0.17                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         4.67                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     4.50                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    0.16                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
 system.mem_ctrls.avgWrQLen                      22.48                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      356                       # Number of row buffer hits during reads
+system.mem_ctrls.readRowHits                      349                       # Number of row buffer hits during reads
 system.mem_ctrls.writeRowHits                      15                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 81.28                       # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate                 79.68                       # Row buffer hit rate for reads
 system.mem_ctrls.writeRowHitRate                32.61                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         70.24                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    76.65                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   143640                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                    79800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 1797120                       # Energy for read commands per rank (pJ)
+system.mem_ctrls.avgGap                         74.73                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    75.21                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   199920                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                    92736                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 2124864                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              2542800                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             26498844                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy               269400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               31331604                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            799.479561                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE          528                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF          1300                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         37581                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                   362880                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   201600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 2882880                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                 165888                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              2542800                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             26204040                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy               528000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               32888088                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            839.195917                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE          754                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          1300                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         37150                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls_0.refreshEnergy         3687840.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              3071616                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy                85248                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        18833256                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy          153600                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               28249080                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            580.552005                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                41659                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE           54                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          1560                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN          400                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT          5344                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        41301                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   442680                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   227976                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 2878848                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 133632                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         3687840.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy              4289136                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               272256                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        17021568                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy          466944                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               29420880                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            604.633881                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                37647                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          541                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          1560                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         1216                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT          8014                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        37328                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -296,8 +306,8 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON           45733                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            45733                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON           48659                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            48659                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2577                       # Number of instructions committed
@@ -316,7 +326,7 @@ system.cpu.num_mem_refs                           717                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      45733                       # Number of busy cycles
+system.cpu.num_busy_cycles                      48659                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
@@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       2585                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   3612                       # delay histogram for all message
@@ -374,10 +384,10 @@ system.ruby.outstanding_req_hist_seqr::total         3295
 system.ruby.latency_hist_seqr::bucket_size           64                      
 system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples           3294                      
-system.ruby.latency_hist_seqr::mean         12.883728                      
-system.ruby.latency_hist_seqr::gmean         2.062291                      
-system.ruby.latency_hist_seqr::stdev        28.863704                      
-system.ruby.latency_hist_seqr            |        2856     86.70%     86.70% |         432     13.11%     99.82% |           1      0.03%     99.85% |           0      0.00%     99.85% |           1      0.03%     99.88% |           4      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean         13.772010                      
+system.ruby.latency_hist_seqr::gmean         2.084389                      
+system.ruby.latency_hist_seqr::stdev        31.264017                      
+system.ruby.latency_hist_seqr            |        2856     86.70%     86.70% |         431     13.08%     99.79% |           1      0.03%     99.82% |           0      0.00%     99.82% |           2      0.06%     99.88% |           4      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist_seqr::total             3294                      
 system.ruby.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.hit_latency_hist_seqr::max_bucket            9                      
@@ -389,12 +399,12 @@ system.ruby.hit_latency_hist_seqr::total         2722
 system.ruby.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.miss_latency_hist_seqr::samples          572                      
-system.ruby.miss_latency_hist_seqr::mean    69.435315                      
-system.ruby.miss_latency_hist_seqr::gmean    64.604000                      
-system.ruby.miss_latency_hist_seqr::stdev    30.458568                      
-system.ruby.miss_latency_hist_seqr       |         134     23.43%     23.43% |         432     75.52%     98.95% |           1      0.17%     99.13% |           0      0.00%     99.13% |           1      0.17%     99.30% |           4      0.70%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    74.550699                      
+system.ruby.miss_latency_hist_seqr::gmean    68.693513                      
+system.ruby.miss_latency_hist_seqr::stdev    34.041428                      
+system.ruby.miss_latency_hist_seqr       |         134     23.43%     23.43% |         431     75.35%     98.78% |           1      0.17%     98.95% |           0      0.00%     98.95% |           2      0.35%     99.30% |           4      0.70%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist_seqr::total          572                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.L1Dcache.demand_hits          437                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          272                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
@@ -410,15 +420,15 @@ system.ruby.l1_cntrl0.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
 system.ruby.l2_cntrl0.L2cache.demand_hits           25                       # Number of cache demand hits
 system.ruby.l2_cntrl0.L2cache.demand_misses          547                       # Number of cache demand misses
 system.ruby.l2_cntrl0.L2cache.demand_accesses          572                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     4.350250                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     4.088658                      
 system.ruby.network.routers0.msg_count.Control::0          572                      
 system.ruby.network.routers0.msg_count.Request_Control::2          431                      
 system.ruby.network.routers0.msg_count.Response_Data::1          572                      
@@ -435,8 +445,8 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2         2176
 system.ruby.network.routers0.msg_bytes.Writeback_Data::0         3240                      
 system.ruby.network.routers0.msg_bytes.Writeback_Data::1         4464                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::0          632                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     8.380163                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     7.876241                      
 system.ruby.network.routers1.msg_count.Control::0         1119                      
 system.ruby.network.routers1.msg_count.Request_Control::2          431                      
 system.ruby.network.routers1.msg_count.Response_Data::1         1222                      
@@ -453,16 +463,16 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2         2176
 system.ruby.network.routers1.msg_bytes.Writeback_Data::0         3240                      
 system.ruby.network.routers1.msg_bytes.Writeback_Data::1         4464                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::0          632                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     4.029913                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     3.787583                      
 system.ruby.network.routers2.msg_count.Control::0          547                      
 system.ruby.network.routers2.msg_count.Response_Data::1          650                      
 system.ruby.network.routers2.msg_count.Response_Control::1          975                      
 system.ruby.network.routers2.msg_bytes.Control::0         4376                      
 system.ruby.network.routers2.msg_bytes.Response_Data::1        46800                      
 system.ruby.network.routers2.msg_bytes.Response_Control::1         7800                      
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized     5.586775                      
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized     5.250827                      
 system.ruby.network.routers3.msg_count.Control::0         1119                      
 system.ruby.network.routers3.msg_count.Request_Control::2          431                      
 system.ruby.network.routers3.msg_count.Response_Data::1         1222                      
@@ -479,7 +489,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2         2176
 system.ruby.network.routers3.msg_bytes.Writeback_Data::0         3240                      
 system.ruby.network.routers3.msg_bytes.Writeback_Data::1         4464                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::0          632                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Control            3357                      
 system.ruby.network.msg_count.Request_Control         1293                      
 system.ruby.network.msg_count.Response_Data         3666                      
@@ -492,15 +502,15 @@ system.ruby.network.msg_byte.Response_Data       263952
 system.ruby.network.msg_byte.Response_Control        41760                      
 system.ruby.network.msg_byte.Writeback_Data        23112                      
 system.ruby.network.msg_byte.Writeback_Control         1896                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        45733                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     6.235104                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        48659                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     5.860170                      
 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2          431                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1          572                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Control::1          124                      
 system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2         3448                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1        41184                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1          992                      
-system.ruby.network.routers0.throttle1.link_utilization     2.465397                      
+system.ruby.network.routers0.throttle1.link_utilization     2.317146                      
 system.ruby.network.routers0.throttle1.msg_count.Control::0          572                      
 system.ruby.network.routers0.throttle1.msg_count.Response_Control::1          369                      
 system.ruby.network.routers0.throttle1.msg_count.Response_Control::2          272                      
@@ -513,7 +523,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2         217
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0         3240                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1         4464                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0          632                      
-system.ruby.network.routers1.throttle0.link_utilization     8.437015                      
+system.ruby.network.routers1.throttle0.link_utilization     7.929674                      
 system.ruby.network.routers1.throttle0.msg_count.Control::0          572                      
 system.ruby.network.routers1.throttle0.msg_count.Response_Data::1          547                      
 system.ruby.network.routers1.throttle0.msg_count.Response_Control::1          908                      
@@ -528,7 +538,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2         217
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0         3240                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1         4464                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0          632                      
-system.ruby.network.routers1.throttle1.link_utilization     8.323311                      
+system.ruby.network.routers1.throttle1.link_utilization     7.822808                      
 system.ruby.network.routers1.throttle1.msg_count.Control::0          547                      
 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2          431                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::1          675                      
@@ -537,26 +547,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0         4376
 system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2         3448                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1        48600                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1         4480                      
-system.ruby.network.routers2.throttle0.link_utilization     2.088208                      
+system.ruby.network.routers2.throttle0.link_utilization     1.962638                      
 system.ruby.network.routers2.throttle0.msg_count.Control::0          547                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::1          103                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Control::1          436                      
 system.ruby.network.routers2.throttle0.msg_bytes.Control::0         4376                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1         7416                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1         3488                      
-system.ruby.network.routers2.throttle1.link_utilization     5.971618                      
+system.ruby.network.routers2.throttle1.link_utilization     5.612528                      
 system.ruby.network.routers2.throttle1.msg_count.Response_Data::1          547                      
 system.ruby.network.routers2.throttle1.msg_count.Response_Control::1          539                      
 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1        39384                      
 system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1         4312                      
-system.ruby.network.routers3.throttle0.link_utilization     6.235104                      
+system.ruby.network.routers3.throttle0.link_utilization     5.860170                      
 system.ruby.network.routers3.throttle0.msg_count.Request_Control::2          431                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Data::1          572                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Control::1          124                      
 system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2         3448                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1        41184                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1          992                      
-system.ruby.network.routers3.throttle1.link_utilization     8.437015                      
+system.ruby.network.routers3.throttle1.link_utilization     7.929674                      
 system.ruby.network.routers3.throttle1.msg_count.Control::0          572                      
 system.ruby.network.routers3.throttle1.msg_count.Response_Data::1          547                      
 system.ruby.network.routers3.throttle1.msg_count.Response_Control::1          908                      
@@ -571,7 +581,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2         217
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0         3240                      
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1         4464                      
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0          632                      
-system.ruby.network.routers3.throttle2.link_utilization     2.088208                      
+system.ruby.network.routers3.throttle2.link_utilization     1.962638                      
 system.ruby.network.routers3.throttle2.msg_count.Control::0          547                      
 system.ruby.network.routers3.throttle2.msg_count.Response_Data::1          103                      
 system.ruby.network.routers3.throttle2.msg_count.Response_Control::1          436                      
@@ -597,13 +607,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket            9                       #
 system.ruby.delayVCHist.vnet_2::samples           431                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2           |         431    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::total             431                       # delay histogram for vnet_2
-system.ruby.LD.latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.latency_hist_seqr::samples          415                      
-system.ruby.LD.latency_hist_seqr::mean      31.356627                      
-system.ruby.LD.latency_hist_seqr::gmean      7.342788                      
-system.ruby.LD.latency_hist_seqr::stdev     35.995277                      
-system.ruby.LD.latency_hist_seqr         |         223     53.73%     53.73% |          75     18.07%     71.81% |         106     25.54%     97.35% |          10      2.41%     99.76% |           0      0.00%     99.76% |           0      0.00%     99.76% |           0      0.00%     99.76% |           0      0.00%     99.76% |           0      0.00%     99.76% |           1      0.24%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      33.824096                      
+system.ruby.LD.latency_hist_seqr::gmean      7.531942                      
+system.ruby.LD.latency_hist_seqr::stdev     41.807535                      
+system.ruby.LD.latency_hist_seqr         |         298     71.81%     71.81% |         115     27.71%     99.52% |           0      0.00%     99.52% |           0      0.00%     99.52% |           0      0.00%     99.52% |           2      0.48%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_seqr::total           415                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
@@ -612,21 +622,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean            1
 system.ruby.LD.hit_latency_hist_seqr::gmean            1                      
 system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |         211    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.hit_latency_hist_seqr::total          211                      
-system.ruby.LD.miss_latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.miss_latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.miss_latency_hist_seqr::samples          204                      
-system.ruby.LD.miss_latency_hist_seqr::mean    62.754902                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    57.734169                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    26.340677                      
-system.ruby.LD.miss_latency_hist_seqr    |          12      5.88%      5.88% |          75     36.76%     42.65% |         106     51.96%     94.61% |          10      4.90%     99.51% |           0      0.00%     99.51% |           0      0.00%     99.51% |           0      0.00%     99.51% |           0      0.00%     99.51% |           0      0.00%     99.51% |           1      0.49%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    67.774510                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    60.800044                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    35.866860                      
+system.ruby.LD.miss_latency_hist_seqr    |          87     42.65%     42.65% |         115     56.37%     99.02% |           0      0.00%     99.02% |           0      0.00%     99.02% |           0      0.00%     99.02% |           2      0.98%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          204                      
-system.ruby.ST.latency_hist_seqr::bucket_size           64                      
-system.ruby.ST.latency_hist_seqr::max_bucket          639                      
+system.ruby.ST.latency_hist_seqr::bucket_size           16                      
+system.ruby.ST.latency_hist_seqr::max_bucket          159                      
 system.ruby.ST.latency_hist_seqr::samples          294                      
-system.ruby.ST.latency_hist_seqr::mean      14.789116                      
-system.ruby.ST.latency_hist_seqr::gmean      2.517478                      
-system.ruby.ST.latency_hist_seqr::stdev     31.573573                      
-system.ruby.ST.latency_hist_seqr         |         264     89.80%     89.80% |          29      9.86%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           1      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::mean      14.469388                      
+system.ruby.ST.latency_hist_seqr::gmean      2.523301                      
+system.ruby.ST.latency_hist_seqr::stdev     26.779037                      
+system.ruby.ST.latency_hist_seqr         |         226     76.87%     76.87% |           4      1.36%     78.23% |          33     11.22%     89.46% |           1      0.34%     89.80% |          14      4.76%     94.56% |          14      4.76%     99.32% |           2      0.68%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist_seqr::total           294                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
@@ -635,21 +645,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean            1
 system.ruby.ST.hit_latency_hist_seqr::gmean            1                      
 system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |         226    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.hit_latency_hist_seqr::total          226                      
-system.ruby.ST.miss_latency_hist_seqr::bucket_size           64                      
-system.ruby.ST.miss_latency_hist_seqr::max_bucket          639                      
+system.ruby.ST.miss_latency_hist_seqr::bucket_size           16                      
+system.ruby.ST.miss_latency_hist_seqr::max_bucket          159                      
 system.ruby.ST.miss_latency_hist_seqr::samples           68                      
-system.ruby.ST.miss_latency_hist_seqr::mean    60.617647                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    54.148546                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    39.831747                      
-system.ruby.ST.miss_latency_hist_seqr    |          38     55.88%     55.88% |          29     42.65%     98.53% |           0      0.00%     98.53% |           0      0.00%     98.53% |           0      0.00%     98.53% |           1      1.47%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean    59.235294                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    54.692111                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    22.140068                      
+system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |           4      5.88%      5.88% |          33     48.53%     54.41% |           1      1.47%     55.88% |          14     20.59%     76.47% |          14     20.59%     97.06% |           2      2.94%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total           68                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples         2585                      
-system.ruby.IFETCH.latency_hist_seqr::mean     9.701354                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.644214                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    25.994801                      
-system.ruby.IFETCH.latency_hist_seqr     |        2294     88.74%     88.74% |         287     11.10%     99.85% |           1      0.04%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           3      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean    10.473501                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.659469                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    28.438724                      
+system.ruby.IFETCH.latency_hist_seqr     |        2294     88.74%     88.74% |         286     11.06%     99.81% |           1      0.04%     99.85% |           0      0.00%     99.85% |           2      0.08%     99.92% |           2      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         2585                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
@@ -661,10 +671,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total         2285
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          300                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    75.976667                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    72.583942                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    29.223784                      
-system.ruby.IFETCH.miss_latency_hist_seqr |           9      3.00%      3.00% |         287     95.67%     98.67% |           1      0.33%     99.00% |           0      0.00%     99.00% |           0      0.00%     99.00% |           3      1.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    82.630000                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    78.596235                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    32.857141                      
+system.ruby.IFETCH.miss_latency_hist_seqr |           9      3.00%      3.00% |         286     95.33%     98.33% |           1      0.33%     98.67% |           0      0.00%     98.67% |           2      0.67%     99.33% |           2      0.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          300                      
 system.ruby.Directory_Controller.Fetch            547      0.00%      0.00%
 system.ruby.Directory_Controller.Data             103      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 2ad2eb8ea..70212c16a 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -249,11 +270,16 @@ children=directory forwardFromDir requestToDir responseFromDir responseFromMemor
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=6
 eventq_index=0
 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestToDir=system.ruby.dir_cntrl0.requestToDir
 responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -320,10 +346,15 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache
 buffer_size=0
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 l2_select_num_bits=0
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
 requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache
@@ -433,17 +464,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.L1Dcache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.L1Icache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
@@ -466,8 +502,13 @@ L2cache=system.ruby.l2_cntrl0.L2cache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 request_latency=2
 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
@@ -566,18 +607,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
 netifs=
 number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
 ruby_system=system.ruby
 topology=Crossbar
@@ -740,42 +786,216 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers18]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers19]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
 weight=1
 
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11
+power_model=Null
 router_id=0
 virt_nets=3
 
@@ -867,8 +1087,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11
+power_model=Null
 router_id=1
 virt_nets=3
 
@@ -960,8 +1186,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11
+power_model=Null
 router_id=2
 virt_nets=3
 
@@ -1053,8 +1285,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17
+power_model=Null
 router_id=3
 virt_nets=3
 
@@ -1187,9 +1425,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
index 1c18978fa..63982fce4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -4,9 +4,8 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
 warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index 28c1f1cb8..42fdb4cc6 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:06:59
-gem5 started Jan 21 2016 14:07:35
-gem5 executing on zizzer, pid 50069
-command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled Oct 13 2016 20:30:58
+gem5 started Oct 13 2016 20:31:25
+gem5 executing on e108600-lin, pid 17791
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 41712 because target called exit()
+Exiting @ tick 44230 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 1d68008a1..9bed4b569 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000042                       # Number of seconds simulated
-sim_ticks                                       41712                       # Number of ticks simulated
-final_tick                                      41712                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000044                       # Number of seconds simulated
+sim_ticks                                       44230                       # Number of ticks simulated
+final_tick                                      44230                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  62826                       # Simulator instruction rate (inst/s)
-host_op_rate                                    62813                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1016484                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 457644                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                  44627                       # Simulator instruction rate (inst/s)
+host_op_rate                                    44610                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 765394                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 414624                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        29696                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              29696                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0         4992                       # Number of bytes written to this memory
@@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0          464                       #
 system.mem_ctrls.num_reads::total                 464                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0           78                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                 78                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    711929421                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             711929421                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    119677791                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            119677791                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0    831607211                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total            831607211                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    671399503                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             671399503                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    112864572                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            112864572                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    784264074                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            784264074                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                         464                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                         78                       # Number of write requests accepted
 system.mem_ctrls.readBursts                       464                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                1                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         41632                       # Total gap between requests
+system.mem_ctrls.totGap                         44144                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -185,20 +185,20 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples           72                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean           336                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   226.772547                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   284.954160                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           17     23.61%     23.61% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           17     23.61%     47.22% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           12     16.67%     63.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511            5      6.94%     70.83% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639            7      9.72%     80.56% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            6      8.33%     88.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            2      2.78%     91.67% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            3      4.17%     95.83% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151            3      4.17%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total           72                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples           75                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    308.906667                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   203.362375                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   281.413861                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           21     28.00%     28.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           20     26.67%     54.67% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383            8     10.67%     65.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511            8     10.67%     76.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639            6      8.00%     84.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            3      4.00%     88.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            4      5.33%     93.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            1      1.33%     94.67% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151            4      5.33%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total           75                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples            1                       # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::mean            248                       # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::gmean    248.000000                       # Reads before turning the bus around for writes
@@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean     16.000000                       # Wr
 system.mem_ctrls.wrPerTurnAround::stdev           nan                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::16                1    100.00%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total             1                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         2393                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                    9689                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totQLat                         4911                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   12207                       # Total ticks spent from burst creation until serviced by the DRAM
 system.mem_ctrls.totBusLat                       1920                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         6.23                       # Average queueing delay per DRAM burst
+system.mem_ctrls.avgQLat                        12.79                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   25.23                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       589.18                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                        24.55                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    711.93                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    119.68                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   31.79                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       555.64                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                        23.15                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    671.40                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    112.86                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         4.79                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.60                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    0.19                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         4.52                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     4.34                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    0.18                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      21.63                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      305                       # Number of row buffer hits during reads
+system.mem_ctrls.avgWrQLen                      21.61                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      302                       # Number of row buffer hits during reads
 system.mem_ctrls.writeRowHits                      15                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 79.43                       # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate                 78.65                       # Row buffer hit rate for reads
 system.mem_ctrls.writeRowHitRate                32.61                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         76.81                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    74.42                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   158760                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                    88200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 1809600                       # Energy for read commands per rank (pJ)
+system.mem_ctrls.avgGap                         81.45                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    73.72                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   178500                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                    81144                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 1793568                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              2542800                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             24398280                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy              2114400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               31112040                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            793.795989                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE         3488                       # Time in different power states
+system.mem_ctrls_0.refreshEnergy         3073200.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              2736456                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy                72192                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        16199400                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy          966144                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               25100604                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            567.501786                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                37998                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE           48                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          1300                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         34510                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                   385560                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   214200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 2708160                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                 165888                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              2542800                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             26293644                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy               449400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               32759652                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            835.918653                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE          623                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN         2516                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT          4841                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        35525                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   414120                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   208656                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 2593248                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 133632                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         3073200.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy              3830856                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               258048                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        15964560                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy           56448                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               26532768                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            599.881709                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                34371                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          532                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          1300                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         37281                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN          147                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT          7241                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        35010                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -296,8 +306,8 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON           41712                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            41712                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON           44230                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            44230                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2577                       # Number of instructions committed
@@ -316,7 +326,7 @@ system.cpu.num_mem_refs                           717                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      41712                       # Number of busy cycles
+system.cpu.num_busy_cycles                      44230                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
@@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       2585                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
 system.ruby.outstanding_req_hist_seqr::bucket_size            1                      
 system.ruby.outstanding_req_hist_seqr::max_bucket            9                      
 system.ruby.outstanding_req_hist_seqr::samples         3295                      
@@ -364,13 +374,13 @@ system.ruby.outstanding_req_hist_seqr::mean            1
 system.ruby.outstanding_req_hist_seqr::gmean            1                      
 system.ruby.outstanding_req_hist_seqr    |           0      0.00%      0.00% |        3295    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.outstanding_req_hist_seqr::total         3295                      
-system.ruby.latency_hist_seqr::bucket_size           32                      
-system.ruby.latency_hist_seqr::max_bucket          319                      
+system.ruby.latency_hist_seqr::bucket_size           64                      
+system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples           3294                      
-system.ruby.latency_hist_seqr::mean         11.663024                      
-system.ruby.latency_hist_seqr::gmean         1.954156                      
-system.ruby.latency_hist_seqr::stdev        27.142816                      
-system.ruby.latency_hist_seqr            |        2830     85.91%     85.91% |          80      2.43%     88.34% |         359     10.90%     99.24% |          18      0.55%     99.79% |           2      0.06%     99.85% |           0      0.00%     99.85% |           1      0.03%     99.88% |           0      0.00%     99.88% |           1      0.03%     99.91% |           3      0.09%    100.00%
+system.ruby.latency_hist_seqr::mean         12.427444                      
+system.ruby.latency_hist_seqr::gmean         1.971908                      
+system.ruby.latency_hist_seqr::stdev        29.452789                      
+system.ruby.latency_hist_seqr            |        2910     88.34%     88.34% |         377     11.45%     99.79% |           2      0.06%     99.85% |           0      0.00%     99.85% |           3      0.09%     99.94% |           2      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist_seqr::total             3294                      
 system.ruby.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.hit_latency_hist_seqr::max_bucket            9                      
@@ -379,30 +389,30 @@ system.ruby.hit_latency_hist_seqr::mean             1
 system.ruby.hit_latency_hist_seqr::gmean            1                      
 system.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |        2750    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.hit_latency_hist_seqr::total         2750                      
-system.ruby.miss_latency_hist_seqr::bucket_size           32                      
-system.ruby.miss_latency_hist_seqr::max_bucket          319                      
+system.ruby.miss_latency_hist_seqr::bucket_size           64                      
+system.ruby.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.miss_latency_hist_seqr::samples          544                      
-system.ruby.miss_latency_hist_seqr::mean    65.566176                      
-system.ruby.miss_latency_hist_seqr::gmean    57.783054                      
-system.ruby.miss_latency_hist_seqr::stdev    31.323348                      
-system.ruby.miss_latency_hist_seqr       |          80     14.71%     14.71% |          80     14.71%     29.41% |         359     65.99%     95.40% |          18      3.31%     98.71% |           2      0.37%     99.08% |           0      0.00%     99.08% |           1      0.18%     99.26% |           0      0.00%     99.26% |           1      0.18%     99.45% |           3      0.55%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    70.194853                      
+system.ruby.miss_latency_hist_seqr::gmean    61.035379                      
+system.ruby.miss_latency_hist_seqr::stdev    35.442152                      
+system.ruby.miss_latency_hist_seqr       |         160     29.41%     29.41% |         377     69.30%     98.71% |           2      0.37%     99.08% |           0      0.00%     99.08% |           3      0.55%     99.63% |           2      0.37%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist_seqr::total          544                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.L1Dcache.demand_hits          435                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          274                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits         2315                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses          270                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses         2585                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
 system.ruby.l2_cntrl0.L2cache.demand_hits           80                       # Number of cache demand hits
 system.ruby.l2_cntrl0.L2cache.demand_misses          464                       # Number of cache demand misses
 system.ruby.l2_cntrl0.L2cache.demand_accesses          544                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     6.800201                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     6.413068                      
 system.ruby.network.routers0.msg_count.Request_Control::0          544                      
 system.ruby.network.routers0.msg_count.Response_Data::2          464                      
 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2           80                      
@@ -415,8 +425,8 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2         5760
 system.ruby.network.routers0.msg_bytes.Writeback_Data::2        34704                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::0         8032                      
 system.ruby.network.routers0.msg_bytes.Unblock_Control::2         4512                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized    10.372914                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     9.782388                      
 system.ruby.network.routers1.msg_count.Request_Control::0          544                      
 system.ruby.network.routers1.msg_count.Request_Control::1          464                      
 system.ruby.network.routers1.msg_count.Response_Data::2          928                      
@@ -433,8 +443,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2        40320
 system.ruby.network.routers1.msg_bytes.Writeback_Control::0         8032                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::1         1248                      
 system.ruby.network.routers1.msg_bytes.Unblock_Control::2         8216                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     3.572713                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     3.369319                      
 system.ruby.network.routers2.msg_count.Request_Control::1          464                      
 system.ruby.network.routers2.msg_count.Response_Data::2          464                      
 system.ruby.network.routers2.msg_count.Writeback_Data::2           78                      
@@ -445,8 +455,8 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2        33408
 system.ruby.network.routers2.msg_bytes.Writeback_Data::2         5616                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::1         1248                      
 system.ruby.network.routers2.msg_bytes.Unblock_Control::2         3704                      
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized     6.915276                      
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized     6.521592                      
 system.ruby.network.routers3.msg_count.Request_Control::0          544                      
 system.ruby.network.routers3.msg_count.Request_Control::1          464                      
 system.ruby.network.routers3.msg_count.Response_Data::2          928                      
@@ -463,7 +473,7 @@ system.ruby.network.routers3.msg_bytes.Writeback_Data::2        40320
 system.ruby.network.routers3.msg_bytes.Writeback_Control::0         8032                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::1         1248                      
 system.ruby.network.routers3.msg_bytes.Unblock_Control::2         8216                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Request_Control         3024                      
 system.ruby.network.msg_count.Response_Data         2784                      
 system.ruby.network.msg_count.ResponseL2hit_Data          240                      
@@ -476,15 +486,15 @@ system.ruby.network.msg_byte.ResponseL2hit_Data        17280
 system.ruby.network.msg_byte.Writeback_Data       120960                      
 system.ruby.network.msg_byte.Writeback_Control        27840                      
 system.ruby.network.msg_byte.Unblock_Control        24648                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        41712                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     6.470560                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        44230                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     6.102193                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2          464                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2           80                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0          502                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2        33408                      
 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2         5760                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0         4016                      
-system.ruby.network.routers0.throttle1.link_utilization     7.129843                      
+system.ruby.network.routers0.throttle1.link_utilization     6.723943                      
 system.ruby.network.routers0.throttle1.msg_count.Request_Control::0          544                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2          482                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0          502                      
@@ -493,7 +503,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0         4352
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2        34704                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0         4016                      
 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2         4512                      
-system.ruby.network.routers1.throttle0.link_utilization    12.229095                      
+system.ruby.network.routers1.throttle0.link_utilization    11.532896                      
 system.ruby.network.routers1.throttle0.msg_count.Request_Control::0          544                      
 system.ruby.network.routers1.throttle0.msg_count.Response_Data::2          464                      
 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2          482                      
@@ -506,7 +516,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2        34704
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0         4016                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1          624                      
 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2         4512                      
-system.ruby.network.routers1.throttle1.link_utilization     8.516734                      
+system.ruby.network.routers1.throttle1.link_utilization     8.031879                      
 system.ruby.network.routers1.throttle1.msg_count.Request_Control::1          464                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::2          464                      
 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2           80                      
@@ -521,7 +531,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2         5616
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0         4016                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1          624                      
 system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2         3704                      
-system.ruby.network.routers2.throttle0.link_utilization     2.046174                      
+system.ruby.network.routers2.throttle0.link_utilization     1.929686                      
 system.ruby.network.routers2.throttle0.msg_count.Request_Control::1          464                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2           78                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1           78                      
@@ -530,19 +540,19 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1         3712
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2         5616                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1          624                      
 system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2         3704                      
-system.ruby.network.routers2.throttle1.link_utilization     5.099252                      
+system.ruby.network.routers2.throttle1.link_utilization     4.808953                      
 system.ruby.network.routers2.throttle1.msg_count.Response_Data::2          464                      
 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1           78                      
 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2        33408                      
 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1          624                      
-system.ruby.network.routers3.throttle0.link_utilization     6.470560                      
+system.ruby.network.routers3.throttle0.link_utilization     6.102193                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Data::2          464                      
 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2           80                      
 system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0          502                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2        33408                      
 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2         5760                      
 system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0         4016                      
-system.ruby.network.routers3.throttle1.link_utilization    12.229095                      
+system.ruby.network.routers3.throttle1.link_utilization    11.532896                      
 system.ruby.network.routers3.throttle1.msg_count.Request_Control::0          544                      
 system.ruby.network.routers3.throttle1.msg_count.Response_Data::2          464                      
 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2          482                      
@@ -555,7 +565,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2        34704
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0         4016                      
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1          624                      
 system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2         4512                      
-system.ruby.network.routers3.throttle2.link_utilization     2.046174                      
+system.ruby.network.routers3.throttle2.link_utilization     1.929686                      
 system.ruby.network.routers3.throttle2.msg_count.Request_Control::1          464                      
 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2           78                      
 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1           78                      
@@ -564,13 +574,13 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1         3712
 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2         5616                      
 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1          624                      
 system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2         3704                      
-system.ruby.LD.latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.latency_hist_seqr::samples          415                      
-system.ruby.LD.latency_hist_seqr::mean      25.657831                      
-system.ruby.LD.latency_hist_seqr::gmean      5.487426                      
-system.ruby.LD.latency_hist_seqr::stdev     34.035908                      
-system.ruby.LD.latency_hist_seqr         |         275     66.27%     66.27% |          45     10.84%     77.11% |          85     20.48%     97.59% |           8      1.93%     99.52% |           1      0.24%     99.76% |           0      0.00%     99.76% |           1      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      27.790361                      
+system.ruby.LD.latency_hist_seqr::gmean      5.600782                      
+system.ruby.LD.latency_hist_seqr::stdev     40.269706                      
+system.ruby.LD.latency_hist_seqr         |         320     77.11%     77.11% |          92     22.17%     99.28% |           1      0.24%     99.52% |           0      0.00%     99.52% |           1      0.24%     99.76% |           1      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_seqr::total           415                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
@@ -579,21 +589,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean            1
 system.ruby.LD.hit_latency_hist_seqr::gmean            1                      
 system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |         233    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.hit_latency_hist_seqr::total          233                      
-system.ruby.LD.miss_latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.miss_latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.miss_latency_hist_seqr::samples          182                      
-system.ruby.LD.miss_latency_hist_seqr::mean    57.225275                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    48.520263                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    29.410954                      
-system.ruby.LD.miss_latency_hist_seqr    |          42     23.08%     23.08% |          45     24.73%     47.80% |          85     46.70%     94.51% |           8      4.40%     98.90% |           1      0.55%     99.45% |           0      0.00%     99.45% |           1      0.55%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    62.087912                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    50.836003                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    40.030554                      
+system.ruby.LD.miss_latency_hist_seqr    |          87     47.80%     47.80% |          92     50.55%     98.35% |           1      0.55%     98.90% |           0      0.00%     98.90% |           1      0.55%     99.45% |           1      0.55%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          182                      
 system.ruby.ST.latency_hist_seqr::bucket_size           16                      
 system.ruby.ST.latency_hist_seqr::max_bucket          159                      
 system.ruby.ST.latency_hist_seqr::samples          294                      
-system.ruby.ST.latency_hist_seqr::mean      18.809524                      
-system.ruby.ST.latency_hist_seqr::gmean      3.456048                      
-system.ruby.ST.latency_hist_seqr::stdev     29.072895                      
-system.ruby.ST.latency_hist_seqr         |         202     68.71%     68.71% |          12      4.08%     72.79% |          34     11.56%     84.35% |           1      0.34%     84.69% |          38     12.93%     97.62% |           6      2.04%     99.66% |           1      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::mean      19.755102                      
+system.ruby.ST.latency_hist_seqr::gmean      3.497030                      
+system.ruby.ST.latency_hist_seqr::stdev     31.010753                      
+system.ruby.ST.latency_hist_seqr         |         202     68.71%     68.71% |          12      4.08%     72.79% |          34     11.56%     84.35% |           1      0.34%     84.69% |           0      0.00%     84.69% |          44     14.97%     99.66% |           1      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist_seqr::total           294                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
@@ -605,18 +615,18 @@ system.ruby.ST.hit_latency_hist_seqr::total          202
 system.ruby.ST.miss_latency_hist_seqr::bucket_size           16                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket          159                      
 system.ruby.ST.miss_latency_hist_seqr::samples           92                      
-system.ruby.ST.miss_latency_hist_seqr::mean    57.913043                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    52.615480                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    21.714254                      
-system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |          12     13.04%     13.04% |          34     36.96%     50.00% |           1      1.09%     51.09% |          38     41.30%     92.39% |           6      6.52%     98.91% |           1      1.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean    60.934783                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    54.635401                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    24.518127                      
+system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |          12     13.04%     13.04% |          34     36.96%     50.00% |           1      1.09%     51.09% |           0      0.00%     51.09% |          44     47.83%     98.91% |           1      1.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total           92                      
-system.ruby.IFETCH.latency_hist_seqr::bucket_size           32                      
-system.ruby.IFETCH.latency_hist_seqr::max_bucket          319                      
+system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
+system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples         2585                      
-system.ruby.IFETCH.latency_hist_seqr::mean     8.603482                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.551701                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    24.714457                      
-system.ruby.IFETCH.latency_hist_seqr     |        2341     90.56%     90.56% |           0      0.00%     90.56% |         230      8.90%     99.46% |           9      0.35%     99.81% |           1      0.04%     99.85% |           0      0.00%     99.85% |           0      0.00%     99.85% |           0      0.00%     99.85% |           1      0.04%     99.88% |           3      0.12%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     9.127660                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.562445                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    26.109704                      
+system.ruby.IFETCH.latency_hist_seqr     |        2341     90.56%     90.56% |         240      9.28%     99.85% |           1      0.04%     99.88% |           0      0.00%     99.88% |           2      0.08%     99.96% |           1      0.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         2585                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
@@ -625,13 +635,13 @@ system.ruby.IFETCH.hit_latency_hist_seqr::mean            1
 system.ruby.IFETCH.hit_latency_hist_seqr::gmean            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |        2315    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.hit_latency_hist_seqr::total         2315                      
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           32                      
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          319                      
+system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
+system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          270                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    73.796296                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    67.113694                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    33.225253                      
-system.ruby.IFETCH.miss_latency_hist_seqr |          26      9.63%      9.63% |           0      0.00%      9.63% |         230     85.19%     94.81% |           9      3.33%     98.15% |           1      0.37%     98.52% |           0      0.00%     98.52% |           0      0.00%     98.52% |           0      0.00%     98.52% |           1      0.37%     98.89% |           3      1.11%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    78.814815                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    71.697206                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    33.251813                      
+system.ruby.IFETCH.miss_latency_hist_seqr |          26      9.63%      9.63% |         240     88.89%     98.52% |           1      0.37%     98.89% |           0      0.00%     98.89% |           2      0.74%     99.63% |           1      0.37%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          270                      
 system.ruby.Directory_Controller.GETX              80      0.00%      0.00%
 system.ruby.Directory_Controller.GETS             384      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index c78531ccf..cf25b799b 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persiste
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=5
 distributed_persistent=true
@@ -258,8 +280,12 @@ eventq_index=0
 fixed_timeout_latency=100
 l2_select_num_bits=0
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir
 persistentToDir=system.ruby.dir_cntrl0.persistentToDir
+power_model=Null
 recycle_latency=10
 reissue_wakeup_latency=10
 requestFromDir=system.ruby.dir_cntrl0.requestFromDir
@@ -361,6 +387,7 @@ N_tokens=2
 buffer_size=0
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 dynamic_timeout_enabled=true
 eventq_index=0
 fixed_timeout_latency=300
@@ -370,8 +397,12 @@ l2_select_num_bits=0
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 no_mig_atomic=true
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache
 persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache
+power_model=Null
 recycle_latency=10
 reissue_wakeup_latency=10
 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
@@ -497,17 +528,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.L1Dcache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.L1Icache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
@@ -524,12 +560,17 @@ N_tokens=2
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 filtering_enabled=true
 l2_request_latency=5
 l2_response_latency=5
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache
+power_model=Null
 recycle_latency=10
 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
 responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
@@ -626,18 +667,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
 netifs=
 number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
 ruby_system=system.ruby
 topology=Crossbar
@@ -926,42 +972,342 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers40]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers41]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers42]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers43]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers44]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers45]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers46]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers47]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers48]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers49]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers50]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers51]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers52]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers53]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers54]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers55]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers56]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers57]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers58]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers59]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers60]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers61]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers62]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers63]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers64]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers65]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers66]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers67]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers68]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers69]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers70]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers71]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
 weight=1
 
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 system.ruby.network.routers0.port_buffers18 system.ruby.network.routers0.port_buffers19 system.ruby.network.routers0.port_buffers20 system.ruby.network.routers0.port_buffers21 system.ruby.network.routers0.port_buffers22 system.ruby.network.routers0.port_buffers23
+power_model=Null
 router_id=0
 virt_nets=6
 
@@ -1137,8 +1483,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 system.ruby.network.routers1.port_buffers18 system.ruby.network.routers1.port_buffers19 system.ruby.network.routers1.port_buffers20 system.ruby.network.routers1.port_buffers21 system.ruby.network.routers1.port_buffers22 system.ruby.network.routers1.port_buffers23
+power_model=Null
 router_id=1
 virt_nets=6
 
@@ -1314,8 +1666,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23
+power_model=Null
 router_id=2
 virt_nets=6
 
@@ -1491,8 +1849,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35
+power_model=Null
 router_id=3
 virt_nets=6
 
@@ -1751,9 +2115,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
index 1c18978fa..63982fce4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -4,9 +4,8 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
 warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index 9a1a80ba2..57e88573f 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:12:23
-gem5 started Jan 21 2016 14:13:00
-gem5 executing on zizzer, pid 55410
-command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled Oct 13 2016 20:33:48
+gem5 started Oct 13 2016 20:34:16
+gem5 executing on e108600-lin, pid 27527
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 40527 because target called exit()
+Exiting @ tick 42756 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 20325d4b9..0254766b0 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000041                       # Number of seconds simulated
-sim_ticks                                       40527                       # Number of ticks simulated
-final_tick                                      40527                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000043                       # Number of seconds simulated
+sim_ticks                                       42756                       # Number of ticks simulated
+final_tick                                      42756                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  89328                       # Simulator instruction rate (inst/s)
-host_op_rate                                    89293                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1403832                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 454496                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                  50628                       # Simulator instruction rate (inst/s)
+host_op_rate                                    50604                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 839232                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 411504                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        28672                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              28672                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0         5376                       # Number of bytes written to this memory
@@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0          448                       #
 system.mem_ctrls.num_reads::total                 448                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0           84                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                 84                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    707478965                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             707478965                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    132652306                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            132652306                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0    840131271                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total            840131271                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    670595940                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             670595940                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    125736739                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            125736739                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    796332678                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            796332678                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                         448                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                         84                       # Number of write requests accepted
 system.mem_ctrls.readBursts                       448                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                1                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         40452                       # Total gap between requests
+system.mem_ctrls.totGap                         42675                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -185,20 +185,20 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples           73                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    334.027397                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   221.884458                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   291.386817                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           19     26.03%     26.03% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           15     20.55%     46.58% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           13     17.81%     64.38% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511            6      8.22%     72.60% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639            7      9.59%     82.19% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            5      6.85%     89.04% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            1      1.37%     90.41% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            2      2.74%     93.15% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151            5      6.85%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total           73                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples           72                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    326.222222                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   214.888456                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   283.209683                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           20     27.78%     27.78% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           16     22.22%     50.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           10     13.89%     63.89% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511            5      6.94%     70.83% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639            9     12.50%     83.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            2      2.78%     86.11% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            6      8.33%     94.44% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            2      2.78%     97.22% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151            2      2.78%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total           72                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples            1                       # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::mean            245                       # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::gmean    245.000000                       # Reads before turning the bus around for writes
@@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean     16.000000                       # Wr
 system.mem_ctrls.wrPerTurnAround::stdev           nan                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::16                1    100.00%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total             1                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         2601                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                    9726                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totQLat                         4832                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   11957                       # Total ticks spent from burst creation until serviced by the DRAM
 system.mem_ctrls.totBusLat                       1875                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         6.94                       # Average queueing delay per DRAM burst
+system.mem_ctrls.avgQLat                        12.89                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   25.94                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       592.20                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                        25.27                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    707.48                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    132.65                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   31.89                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       561.32                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                        23.95                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    670.60                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    125.74                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         4.82                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.63                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    0.20                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         4.57                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     4.39                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    0.19                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      21.86                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      297                       # Number of row buffer hits during reads
+system.mem_ctrls.avgWrQLen                      21.84                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      296                       # Number of row buffer hits during reads
 system.mem_ctrls.writeRowHits                      15                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 79.20                       # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate                 78.93                       # Row buffer hit rate for reads
 system.mem_ctrls.writeRowHitRate                32.61                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         76.04                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    74.11                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   158760                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                    88200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 1896960                       # Energy for read commands per rank (pJ)
+system.mem_ctrls.avgGap                         80.22                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    73.87                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   178500                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                    81144                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 1816416                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              2542800                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             25074756                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy              1518600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               31280076                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            798.164736                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE         2492                       # Time in different power states
+system.mem_ctrls_0.refreshEnergy         3073200.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              2612424                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy                73344                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        15837336                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy          808320                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               24480684                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            572.567219                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                36801                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE           51                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          1300                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         35499                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                   393120                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   218400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 2658240                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                 165888                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              2542800                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             26158212                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy               568200                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               32704860                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            834.520541                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE          821                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN         2105                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT          4569                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        34731                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   392700                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   197064                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 2467584                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 133632                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         3073200.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy              3542208                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               293376                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        15524520                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy           68736                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               25693020                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            600.921976                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                33391                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          512                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          1300                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         37083                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN          179                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT          6720                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        34045                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -296,8 +306,8 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON           40527                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            40527                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON           42756                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            42756                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2577                       # Number of instructions committed
@@ -316,7 +326,7 @@ system.cpu.num_mem_refs                           717                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      40527                       # Number of busy cycles
+system.cpu.num_busy_cycles                      42756                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
@@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       2585                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
 system.ruby.outstanding_req_hist_seqr::bucket_size            1                      
 system.ruby.outstanding_req_hist_seqr::max_bucket            9                      
 system.ruby.outstanding_req_hist_seqr::samples         3295                      
@@ -367,44 +377,44 @@ system.ruby.outstanding_req_hist_seqr::total         3295
 system.ruby.latency_hist_seqr::bucket_size           64                      
 system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples           3294                      
-system.ruby.latency_hist_seqr::mean         11.303279                      
-system.ruby.latency_hist_seqr::gmean         1.905847                      
-system.ruby.latency_hist_seqr::stdev        27.108694                      
-system.ruby.latency_hist_seqr            |        2919     88.62%     88.62% |         368     11.17%     99.79% |           2      0.06%     99.85% |           0      0.00%     99.85% |           3      0.09%     99.94% |           2      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean         11.979964                      
+system.ruby.latency_hist_seqr::gmean         1.922311                      
+system.ruby.latency_hist_seqr::stdev        28.863148                      
+system.ruby.latency_hist_seqr            |        2919     88.62%     88.62% |         368     11.17%     99.79% |           2      0.06%     99.85% |           1      0.03%     99.88% |           0      0.00%     99.88% |           4      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist_seqr::total             3294                      
 system.ruby.hit_latency_hist_seqr::bucket_size            4                      
 system.ruby.hit_latency_hist_seqr::max_bucket           39                      
 system.ruby.hit_latency_hist_seqr::samples         2846                      
-system.ruby.hit_latency_hist_seqr::mean      1.554814                      
-system.ruby.hit_latency_hist_seqr::gmean     1.080771                      
-system.ruby.hit_latency_hist_seqr::stdev     3.499483                      
-system.ruby.hit_latency_hist_seqr        |        2776     97.54%     97.54% |           0      0.00%     97.54% |           0      0.00%     97.54% |           0      0.00%     97.54% |           0      0.00%     97.54% |           9      0.32%     97.86% |          61      2.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist_seqr::mean      1.555868                      
+system.ruby.hit_latency_hist_seqr::gmean     1.080822                      
+system.ruby.hit_latency_hist_seqr::stdev     3.505788                      
+system.ruby.hit_latency_hist_seqr        |        2776     97.54%     97.54% |           0      0.00%     97.54% |           0      0.00%     97.54% |           0      0.00%     97.54% |           0      0.00%     97.54% |           8      0.28%     97.82% |          62      2.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.hit_latency_hist_seqr::total         2846                      
 system.ruby.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.miss_latency_hist_seqr::samples          448                      
-system.ruby.miss_latency_hist_seqr::mean    73.232143                      
-system.ruby.miss_latency_hist_seqr::gmean    69.999992                      
-system.ruby.miss_latency_hist_seqr::stdev    29.782878                      
-system.ruby.miss_latency_hist_seqr       |          73     16.29%     16.29% |         368     82.14%     98.44% |           2      0.45%     98.88% |           0      0.00%     98.88% |           3      0.67%     99.55% |           2      0.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    78.200893                      
+system.ruby.miss_latency_hist_seqr::gmean    74.547837                      
+system.ruby.miss_latency_hist_seqr::stdev    31.179064                      
+system.ruby.miss_latency_hist_seqr       |          73     16.29%     16.29% |         368     82.14%     98.44% |           2      0.45%     98.88% |           1      0.22%     99.11% |           0      0.00%     99.11% |           4      0.89%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist_seqr::total          448                      
 system.ruby.Directory.incomplete_times_seqr          447                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.L1Dcache.demand_hits          461                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          248                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits         2315                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses          270                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses         2585                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
 system.ruby.l2_cntrl0.L2cache.demand_hits           64                       # Number of cache demand hits
 system.ruby.l2_cntrl0.L2cache.demand_misses          454                       # Number of cache demand misses
 system.ruby.l2_cntrl0.L2cache.demand_accesses          518                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     5.992918                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     5.680489                      
 system.ruby.network.routers0.msg_count.Request_Control::1          518                      
 system.ruby.network.routers0.msg_count.Response_Data::4          448                      
 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4           70                      
@@ -417,8 +427,8 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4         5040
 system.ruby.network.routers0.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers0.msg_bytes.Writeback_Data::4        36144                      
 system.ruby.network.routers0.msg_bytes.Persistent_Control::3          128                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     4.472327                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     4.239171                      
 system.ruby.network.routers1.msg_count.Request_Control::1          518                      
 system.ruby.network.routers1.msg_count.Request_Control::2          454                      
 system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4           70                      
@@ -433,8 +443,8 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4            8
 system.ruby.network.routers1.msg_bytes.Writeback_Data::4        42192                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::4         2920                      
 system.ruby.network.routers1.msg_bytes.Persistent_Control::3           64                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     3.463740                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     3.283165                      
 system.ruby.network.routers2.msg_count.Request_Control::2          454                      
 system.ruby.network.routers2.msg_count.Response_Data::4          448                      
 system.ruby.network.routers2.msg_count.Writeback_Data::4           84                      
@@ -445,8 +455,8 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4        32256
 system.ruby.network.routers2.msg_bytes.Writeback_Data::4         6048                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::4         2920                      
 system.ruby.network.routers2.msg_bytes.Persistent_Control::3           64                      
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized     4.642995                      
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized     4.400942                      
 system.ruby.network.routers3.msg_count.Request_Control::1          518                      
 system.ruby.network.routers3.msg_count.Request_Control::2          454                      
 system.ruby.network.routers3.msg_count.Response_Data::4          448                      
@@ -463,7 +473,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::4            8
 system.ruby.network.routers3.msg_bytes.Writeback_Data::4        42192                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::4         2920                      
 system.ruby.network.routers3.msg_bytes.Persistent_Control::3          128                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Request_Control         2916                      
 system.ruby.network.msg_count.Response_Data         1344                      
 system.ruby.network.msg_count.ResponseL2hit_Data          210                      
@@ -478,8 +488,8 @@ system.ruby.network.msg_byte.Response_Control           24
 system.ruby.network.msg_byte.Writeback_Data       126576                      
 system.ruby.network.msg_byte.Writeback_Control         8760                      
 system.ruby.network.msg_byte.Persistent_Control          384                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        40527                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     5.762825                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        42756                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     5.462391                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          448                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4           70                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Control::4            1                      
@@ -488,21 +498,21 @@ system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        32256
 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4         5040                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3           64                      
-system.ruby.network.routers0.throttle1.link_utilization     6.223012                      
+system.ruby.network.routers0.throttle1.link_utilization     5.898587                      
 system.ruby.network.routers0.throttle1.msg_count.Request_Control::1          518                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4          502                      
 system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3            8                      
 system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1         4144                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4        36144                      
 system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3           64                      
-system.ruby.network.routers1.throttle0.link_utilization     6.223012                      
+system.ruby.network.routers1.throttle0.link_utilization     5.898587                      
 system.ruby.network.routers1.throttle0.msg_count.Request_Control::1          518                      
 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4          502                      
 system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3            8                      
 system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1         4144                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4        36144                      
 system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3           64                      
-system.ruby.network.routers1.throttle1.link_utilization     2.721642                      
+system.ruby.network.routers1.throttle1.link_utilization     2.579755                      
 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2          454                      
 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4           70                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Control::4            1                      
@@ -513,7 +523,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4         5
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4         6048                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4         2920                      
-system.ruby.network.routers2.throttle0.link_utilization     1.953019                      
+system.ruby.network.routers2.throttle0.link_utilization     1.851202                      
 system.ruby.network.routers2.throttle0.msg_count.Request_Control::2          454                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4           84                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4          365                      
@@ -522,24 +532,24 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2         3632
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4         6048                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4         2920                      
 system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3           64                      
-system.ruby.network.routers2.throttle1.link_utilization     4.974461                      
+system.ruby.network.routers2.throttle1.link_utilization     4.715128                      
 system.ruby.network.routers2.throttle1.msg_count.Response_Data::4          448                      
 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4        32256                      
-system.ruby.network.routers3.throttle0.link_utilization     5.752955                      
+system.ruby.network.routers3.throttle0.link_utilization     5.453036                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Data::4          448                      
 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4           70                      
 system.ruby.network.routers3.throttle0.msg_count.Response_Control::4            1                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4        32256                      
 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4         5040                      
 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers3.throttle1.link_utilization     6.223012                      
+system.ruby.network.routers3.throttle1.link_utilization     5.898587                      
 system.ruby.network.routers3.throttle1.msg_count.Request_Control::1          518                      
 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4          502                      
 system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3            8                      
 system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1         4144                      
 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4        36144                      
 system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3           64                      
-system.ruby.network.routers3.throttle2.link_utilization     1.953019                      
+system.ruby.network.routers3.throttle2.link_utilization     1.851202                      
 system.ruby.network.routers3.throttle2.msg_count.Request_Control::2          454                      
 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4           84                      
 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4          365                      
@@ -548,36 +558,36 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2         3632
 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4         6048                      
 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4         2920                      
 system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3           64                      
-system.ruby.LD.latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.latency_hist_seqr::bucket_size           16                      
+system.ruby.LD.latency_hist_seqr::max_bucket          159                      
 system.ruby.LD.latency_hist_seqr::samples          415                      
-system.ruby.LD.latency_hist_seqr::mean      27.009639                      
-system.ruby.LD.latency_hist_seqr::gmean      5.745092                      
-system.ruby.LD.latency_hist_seqr::stdev     35.695436                      
-system.ruby.LD.latency_hist_seqr         |         266     64.10%     64.10% |          50     12.05%     76.14% |          86     20.72%     96.87% |          10      2.41%     99.28% |           2      0.48%     99.76% |           0      0.00%     99.76% |           0      0.00%     99.76% |           0      0.00%     99.76% |           0      0.00%     99.76% |           1      0.24%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      27.997590                      
+system.ruby.LD.latency_hist_seqr::gmean      5.837138                      
+system.ruby.LD.latency_hist_seqr::stdev     35.585408                      
+system.ruby.LD.latency_hist_seqr         |         233     56.14%     56.14% |          33      7.95%     64.10% |          48     11.57%     75.66% |           2      0.48%     76.14% |          68     16.39%     92.53% |          18      4.34%     96.87% |          10      2.41%     99.28% |           1      0.24%     99.52% |           0      0.00%     99.52% |           2      0.48%    100.00%
 system.ruby.LD.latency_hist_seqr::total           415                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            4                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket           39                      
 system.ruby.LD.hit_latency_hist_seqr::samples          266                      
-system.ruby.LD.hit_latency_hist_seqr::mean     3.834586                      
-system.ruby.LD.hit_latency_hist_seqr::gmean     1.482071                      
-system.ruby.LD.hit_latency_hist_seqr::stdev     7.549265                      
-system.ruby.LD.hit_latency_hist_seqr     |         233     87.59%     87.59% |           0      0.00%     87.59% |           0      0.00%     87.59% |           0      0.00%     87.59% |           0      0.00%     87.59% |           2      0.75%     88.35% |          31     11.65%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist_seqr::mean     3.845865                      
+system.ruby.LD.hit_latency_hist_seqr::gmean     1.482816                      
+system.ruby.LD.hit_latency_hist_seqr::stdev     7.577195                      
+system.ruby.LD.hit_latency_hist_seqr     |         233     87.59%     87.59% |           0      0.00%     87.59% |           0      0.00%     87.59% |           0      0.00%     87.59% |           0      0.00%     87.59% |           1      0.38%     87.97% |          32     12.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.hit_latency_hist_seqr::total          266                      
-system.ruby.LD.miss_latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.miss_latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.miss_latency_hist_seqr::bucket_size           16                      
+system.ruby.LD.miss_latency_hist_seqr::max_bucket          159                      
 system.ruby.LD.miss_latency_hist_seqr::samples          149                      
-system.ruby.LD.miss_latency_hist_seqr::mean    68.382550                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    64.532565                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    27.813471                      
-system.ruby.LD.miss_latency_hist_seqr    |           0      0.00%      0.00% |          50     33.56%     33.56% |          86     57.72%     91.28% |          10      6.71%     97.99% |           2      1.34%     99.33% |           0      0.00%     99.33% |           0      0.00%     99.33% |           0      0.00%     99.33% |           0      0.00%     99.33% |           1      0.67%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    71.114094                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    67.393219                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    22.792700                      
+system.ruby.LD.miss_latency_hist_seqr    |           0      0.00%      0.00% |           0      0.00%      0.00% |          48     32.21%     32.21% |           2      1.34%     33.56% |          68     45.64%     79.19% |          18     12.08%     91.28% |          10      6.71%     97.99% |           1      0.67%     98.66% |           0      0.00%     98.66% |           2      1.34%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          149                      
 system.ruby.ST.latency_hist_seqr::bucket_size           16                      
 system.ruby.ST.latency_hist_seqr::max_bucket          159                      
 system.ruby.ST.latency_hist_seqr::samples          294                      
-system.ruby.ST.latency_hist_seqr::mean      12.595238                      
-system.ruby.ST.latency_hist_seqr::gmean      2.381363                      
-system.ruby.ST.latency_hist_seqr::stdev     23.818056                      
+system.ruby.ST.latency_hist_seqr::mean      13.153061                      
+system.ruby.ST.latency_hist_seqr::gmean      2.398410                      
+system.ruby.ST.latency_hist_seqr::stdev     25.296880                      
 system.ruby.ST.latency_hist_seqr         |         228     77.55%     77.55% |          14      4.76%     82.31% |          20      6.80%     89.12% |           3      1.02%     90.14% |          23      7.82%     97.96% |           6      2.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist_seqr::total           294                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            4                      
@@ -591,18 +601,18 @@ system.ruby.ST.hit_latency_hist_seqr::total          242
 system.ruby.ST.miss_latency_hist_seqr::bucket_size           16                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket          159                      
 system.ruby.ST.miss_latency_hist_seqr::samples           52                      
-system.ruby.ST.miss_latency_hist_seqr::mean    60.865385                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    58.719474                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    16.012286                      
+system.ruby.ST.miss_latency_hist_seqr::mean    64.019231                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    61.135942                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    18.838311                      
 system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |           0      0.00%      0.00% |          20     38.46%     38.46% |           3      5.77%     44.23% |          23     44.23%     88.46% |           6     11.54%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total           52                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples         2585                      
-system.ruby.IFETCH.latency_hist_seqr::mean     8.634816                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.556513                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    24.922226                      
-system.ruby.IFETCH.latency_hist_seqr     |        2338     90.44%     90.44% |         243      9.40%     99.85% |           0      0.00%     99.85% |           0      0.00%     99.85% |           2      0.08%     99.92% |           2      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     9.275048                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.568384                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    27.157574                      
+system.ruby.IFETCH.latency_hist_seqr     |        2338     90.44%     90.44% |         242      9.36%     99.81% |           0      0.00%     99.81% |           1      0.04%     99.85% |           0      0.00%     99.85% |           4      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         2585                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            4                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket           39                      
@@ -615,10 +625,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total         2338
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          247                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    78.761134                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    76.290474                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    31.873920                      
-system.ruby.IFETCH.miss_latency_hist_seqr |           0      0.00%      0.00% |         243     98.38%     98.38% |           0      0.00%     98.38% |           0      0.00%     98.38% |           2      0.81%     99.19% |           2      0.81%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    85.461538                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    82.604305                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    35.418255                      
+system.ruby.IFETCH.miss_latency_hist_seqr |           0      0.00%      0.00% |         242     97.98%     97.98% |           0      0.00%     97.98% |           1      0.40%     98.38% |           0      0.00%     98.38% |           4      1.62%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          247                      
 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket            9                      
@@ -630,18 +640,18 @@ system.ruby.L1Cache.hit_mach_latency_hist_seqr::total         2776
 system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size            4                      
 system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket           39                      
 system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples           70                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean    23.557143                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean    23.524270                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev     1.199465                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           9     12.86%     12.86% |          61     87.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean    23.600000                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean    23.569187                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev     1.159710                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           8     11.43%     11.43% |          62     88.57%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L2Cache.hit_mach_latency_hist_seqr::total           70                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::samples          448                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean    73.232143                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    69.999992                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    29.782878                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |          73     16.29%     16.29% |         368     82.14%     98.44% |           2      0.45%     98.88% |           0      0.00%     98.88% |           3      0.67%     99.55% |           2      0.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean    78.200893                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    74.547837                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    31.179064                      
+system.ruby.Directory.miss_mach_latency_hist_seqr |          73     16.29%     16.29% |         368     82.14%     98.44% |           2      0.45%     98.88% |           1      0.22%     99.11% |           0      0.00%     99.11% |           4      0.89%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist_seqr::total          448                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket            9                      
@@ -679,18 +689,18 @@ system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total          233
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size            4                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket           39                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples           33                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean    23.848485                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean    23.840140                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev     0.618527                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2      6.06%      6.06% |          31     93.94%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean    23.939394                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean    23.936802                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev     0.348155                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      3.03%      3.03% |          32     96.97%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total           33                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           16                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          159                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples          149                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    68.382550                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    64.532565                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    27.813471                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          50     33.56%     33.56% |          86     57.72%     91.28% |          10      6.71%     97.99% |           2      1.34%     99.33% |           0      0.00%     99.33% |           0      0.00%     99.33% |           0      0.00%     99.33% |           0      0.00%     99.33% |           1      0.67%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    71.114094                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    67.393219                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    22.792700                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |          48     32.21%     32.21% |           2      1.34%     33.56% |          68     45.64%     79.19% |          18     12.08%     91.28% |          10      6.71%     97.99% |           1      0.67%     98.66% |           0      0.00%     98.66% |           2      1.34%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total          149                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
@@ -710,9 +720,9 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total           14
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           16                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          159                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples           52                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    60.865385                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    58.719474                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    16.012286                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    64.019231                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    61.135942                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    18.838311                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |          20     38.46%     38.46% |           3      5.77%     44.23% |          23     44.23%     88.46% |           6     11.54%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total           52                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
@@ -732,10 +742,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total           23
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples          247                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    78.761134                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    76.290474                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    31.873920                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         243     98.38%     98.38% |           0      0.00%     98.38% |           0      0.00%     98.38% |           2      0.81%     99.19% |           2      0.81%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    85.461538                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    82.604305                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    35.418255                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         242     97.98%     97.98% |           0      0.00%     97.98% |           1      0.40%     98.38% |           0      0.00%     98.38% |           4      1.62%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total          247                      
 system.ruby.Directory_Controller.GETX              61      0.00%      0.00%
 system.ruby.Directory_Controller.GETS             398      0.00%      0.00%
@@ -752,6 +762,7 @@ system.ruby.Directory_Controller.O.GETX            52      0.00%      0.00%
 system.ruby.Directory_Controller.O.GETS           396      0.00%      0.00%
 system.ruby.Directory_Controller.O.Ack_All_Tokens           15      0.00%      0.00%
 system.ruby.Directory_Controller.NO.GETX            6      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Lockdown            1      0.00%      0.00%
 system.ruby.Directory_Controller.NO.Data_Owner            3      0.00%      0.00%
 system.ruby.Directory_Controller.NO.Data_All_Tokens           81      0.00%      0.00%
 system.ruby.Directory_Controller.NO.Ack_Owner           16      0.00%      0.00%
@@ -760,9 +771,9 @@ system.ruby.Directory_Controller.L.Unlockdown            4      0.00%      0.00%
 system.ruby.Directory_Controller.O_W.GETX            3      0.00%      0.00%
 system.ruby.Directory_Controller.O_W.GETS            2      0.00%      0.00%
 system.ruby.Directory_Controller.O_W.Memory_Ack           84      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.Memory_Data            4      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown            4      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data          444      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.Memory_Data            3      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Lockdown            3      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Memory_Data          445      0.00%      0.00%
 system.ruby.L1Cache_Controller.Load               415      0.00%      0.00%
 system.ruby.L1Cache_Controller.Ifetch            2585      0.00%      0.00%
 system.ruby.L1Cache_Controller.Store              294      0.00%      0.00%
@@ -781,7 +792,7 @@ system.ruby.L1Cache_Controller.S.Ifetch           158      0.00%      0.00%
 system.ruby.L1Cache_Controller.S.Store              8      0.00%      0.00%
 system.ruby.L1Cache_Controller.S.L1_Replacement           48      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.Load              66      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Ifetch          1099      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Ifetch          1098      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.Store             29      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.L1_Replacement          358      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock            4      0.00%      0.00%
@@ -789,7 +800,7 @@ system.ruby.L1Cache_Controller.MM.Load             96      0.00%      0.00%
 system.ruby.L1Cache_Controller.MM.Store           103      0.00%      0.00%
 system.ruby.L1Cache_Controller.MM.L1_Replacement           96      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.Load            36      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_W.Ifetch         1058      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_W.Ifetch         1059      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.Store            3      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.L1_Replacement            1      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers          392      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index 18d7c2ab4..8207d6ac7 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
 dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
@@ -257,6 +279,10 @@ forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
 from_memory_controller_latency=2
 full_bit_dir_enabled=false
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeFilter=system.ruby.dir_cntrl0.probeFilter
 probe_filter_enabled=false
 recycle_latency=10
@@ -384,6 +410,7 @@ buffer_size=0
 cache_response_latency=10
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 forwardToCache=system.ruby.l1_cntrl0.forwardToCache
 issue_latency=2
@@ -391,6 +418,10 @@ l2_cache_hit_latency=10
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 no_mig_atomic=true
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestFromCache=system.ruby.l1_cntrl0.requestFromCache
 responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -522,17 +553,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.L1Dcache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.L1Icache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
@@ -560,18 +596,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
 netifs=
 number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
 ruby_system=system.ruby
 topology=Crossbar
@@ -766,32 +807,234 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers40]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers41]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers42]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers43]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers44]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers45]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers46]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers47]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17
+power_model=Null
 router_id=0
 virt_nets=6
 
@@ -925,8 +1168,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17
+power_model=Null
 router_id=1
 virt_nets=6
 
@@ -1060,8 +1309,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23
+power_model=Null
 router_id=2
 virt_nets=6
 
@@ -1236,9 +1491,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
index 1c18978fa..63982fce4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
@@ -4,9 +4,8 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
 warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index 2cf0cc885..35b481dda 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:56:08
-gem5 started Jan 21 2016 13:56:42
-gem5 executing on zizzer, pid 39363
-command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
+gem5 compiled Oct 13 2016 20:24:36
+gem5 started Oct 13 2016 20:24:58
+gem5 executing on e108600-lin, pid 38874
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 32936 because target called exit()
+Exiting @ tick 35056 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index 71e93d920..4d9201d35 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000033                       # Number of seconds simulated
-sim_ticks                                       32936                       # Number of ticks simulated
-final_tick                                      32936                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000035                       # Number of seconds simulated
+sim_ticks                                       35056                       # Number of ticks simulated
+final_tick                                      35056                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  91605                       # Simulator instruction rate (inst/s)
-host_op_rate                                    91573                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1170024                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 453424                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                  50934                       # Simulator instruction rate (inst/s)
+host_op_rate                                    50910                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 692254                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 411180                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        32936                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        35056                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        28224                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              28224                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0         5184                       # Number of bytes written to this memory
@@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0          441                       #
 system.mem_ctrls.num_reads::total                 441                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0           81                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                 81                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    856934661                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             856934661                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    157396162                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            157396162                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   1014330823                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1014330823                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    805111821                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             805111821                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    147877681                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            147877681                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0    952989503                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            952989503                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                         441                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                         81                       # Number of write requests accepted
 system.mem_ctrls.readBursts                       441                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                1                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         32872                       # Total gap between requests
+system.mem_ctrls.totGap                         34986                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -186,17 +186,17 @@ system.mem_ctrls.wrQLenPdf::61                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.bytesPerActivate::samples           67                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    358.208955                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   229.774303                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   311.560906                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           18     26.87%     26.87% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           13     19.40%     46.27% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383            8     11.94%     58.21% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511            7     10.45%     68.66% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639            5      7.46%     76.12% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            6      8.96%     85.07% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            2      2.99%     88.06% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            4      5.97%     94.03% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    356.298507                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   230.035457                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   306.978482                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           19     28.36%     28.36% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           11     16.42%     44.78% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           10     14.93%     59.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511            7     10.45%     70.15% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639            6      8.96%     79.10% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            4      5.97%     85.07% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            3      4.48%     89.55% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            3      4.48%     94.03% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::1024-1151            4      5.97%    100.00% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::total           67                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples            1                       # Reads before turning the bus around for writes
@@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean     16.000000                       # Wr
 system.mem_ctrls.wrPerTurnAround::stdev           nan                       # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::16                1    100.00%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total             1                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         2381                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                    9506                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totQLat                         4501                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   11626                       # Total ticks spent from burst creation until serviced by the DRAM
 system.mem_ctrls.totBusLat                       1875                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         6.35                       # Average queueing delay per DRAM burst
+system.mem_ctrls.avgQLat                        12.00                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   25.35                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       728.69                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                        31.09                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    856.93                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    157.40                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   31.00                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       684.62                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                        29.21                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    805.11                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    147.88                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         5.94                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     5.69                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    0.24                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         5.58                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     5.35                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    0.23                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      21.54                       # Average write queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      21.49                       # Average write queue length when enqueuing
 system.mem_ctrls.readRowHits                      302                       # Number of row buffer hits during reads
 system.mem_ctrls.writeRowHits                      15                       # Number of row buffer hits during writes
 system.mem_ctrls.readRowHitRate                 80.53                       # Row buffer hit rate for reads
 system.mem_ctrls.writeRowHitRate                32.61                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         62.97                       # Average gap between requests
+system.mem_ctrls.avgGap                         67.02                       # Average gap between requests
 system.mem_ctrls.pageHitRate                    75.30                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   151200                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                    84000                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 1859520                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.actEnergy                   164220                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                    77280                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 1839264                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              2034240                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             21272400                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy               182400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               25583760                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            814.665648                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE          206                       # Time in different power states
+system.mem_ctrls_0.refreshEnergy         2458560.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              2689032                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy                56064                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        13011960                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy          183552                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               20479932                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            584.206184                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                29013                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE           34                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          1040                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         30172                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                   355320                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   197400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 2620800                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                 165888                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              2034240                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             20904408                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy               505200                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               26783256                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            852.861292                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE         1046                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN          478                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT          4969                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        28535                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   364140                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   181608                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 2444736                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 133632                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         2458560.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy              3405408                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               211968                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        12011952                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy          266496                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               21478500                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            612.691123                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                26306                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          440                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          1040                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         29634                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        32936                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN          694                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT          6540                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        26342                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED        35056                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -296,8 +306,8 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON           32936                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            32936                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON           35056                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            35056                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2577                       # Number of instructions committed
@@ -316,7 +326,7 @@ system.cpu.num_mem_refs                           717                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      32936                       # Number of busy cycles
+system.cpu.num_busy_cycles                      35056                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
@@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       2585                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        32936                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        35056                       # Cumulative time (in ticks) in various power states
 system.ruby.outstanding_req_hist_seqr::bucket_size            1                      
 system.ruby.outstanding_req_hist_seqr::max_bucket            9                      
 system.ruby.outstanding_req_hist_seqr::samples         3295                      
@@ -364,13 +374,13 @@ system.ruby.outstanding_req_hist_seqr::mean            1
 system.ruby.outstanding_req_hist_seqr::gmean            1                      
 system.ruby.outstanding_req_hist_seqr    |           0      0.00%      0.00% |        3295    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.outstanding_req_hist_seqr::total         3295                      
-system.ruby.latency_hist_seqr::bucket_size           64                      
-system.ruby.latency_hist_seqr::max_bucket          639                      
+system.ruby.latency_hist_seqr::bucket_size           32                      
+system.ruby.latency_hist_seqr::max_bucket          319                      
 system.ruby.latency_hist_seqr::samples           3294                      
-system.ruby.latency_hist_seqr::mean          8.998786                      
-system.ruby.latency_hist_seqr::gmean         1.800750                      
-system.ruby.latency_hist_seqr::stdev        22.386902                      
-system.ruby.latency_hist_seqr            |        3204     97.27%     97.27% |          86      2.61%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           2      0.06%     99.94% |           2      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean          9.642380                      
+system.ruby.latency_hist_seqr::gmean         1.819734                      
+system.ruby.latency_hist_seqr::stdev        23.663336                      
+system.ruby.latency_hist_seqr            |        2910     88.34%     88.34% |         293      8.89%     97.24% |          85      2.58%     99.82% |           2      0.06%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           4      0.12%    100.00%
 system.ruby.latency_hist_seqr::total             3294                      
 system.ruby.hit_latency_hist_seqr::bucket_size            2                      
 system.ruby.hit_latency_hist_seqr::max_bucket           19                      
@@ -380,19 +390,19 @@ system.ruby.hit_latency_hist_seqr::gmean     1.059708
 system.ruby.hit_latency_hist_seqr::stdev     1.536503                      
 system.ruby.hit_latency_hist_seqr        |        2784     97.58%     97.58% |           0      0.00%     97.58% |           0      0.00%     97.58% |           0      0.00%     97.58% |           0      0.00%     97.58% |          69      2.42%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.hit_latency_hist_seqr::total         2853                      
-system.ruby.miss_latency_hist_seqr::bucket_size           64                      
-system.ruby.miss_latency_hist_seqr::max_bucket          639                      
+system.ruby.miss_latency_hist_seqr::bucket_size           32                      
+system.ruby.miss_latency_hist_seqr::max_bucket          319                      
 system.ruby.miss_latency_hist_seqr::samples          441                      
-system.ruby.miss_latency_hist_seqr::mean    59.181406                      
-system.ruby.miss_latency_hist_seqr::gmean    55.608631                      
-system.ruby.miss_latency_hist_seqr::stdev    28.659343                      
-system.ruby.miss_latency_hist_seqr       |         351     79.59%     79.59% |          86     19.50%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           2      0.45%     99.55% |           2      0.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    63.988662                      
+system.ruby.miss_latency_hist_seqr::gmean    60.139666                      
+system.ruby.miss_latency_hist_seqr::stdev    27.525151                      
+system.ruby.miss_latency_hist_seqr       |          57     12.93%     12.93% |         293     66.44%     79.37% |          85     19.27%     98.64% |           2      0.45%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           4      0.91%    100.00%
 system.ruby.miss_latency_hist_seqr::total          441                      
 system.ruby.Directory.incomplete_times_seqr          440                      
 system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
 system.ruby.dir_cntrl0.probeFilter.demand_misses            0                       # Number of cache demand misses
 system.ruby.dir_cntrl0.probeFilter.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        32936                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        35056                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.L1Dcache.demand_hits          469                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          240                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
@@ -402,12 +412,12 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses         2585
 system.ruby.l1_cntrl0.L2cache.demand_hits           69                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L2cache.demand_misses          441                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L2cache.demand_accesses          510                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        32936                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        32936                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        35056                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        35056                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.fully_busy_cycles             5                       # cycles for which number of transistions == max transitions
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        32936                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     5.141031                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        35056                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     4.830129                      
 system.ruby.network.routers0.msg_count.Request_Control::2          441                      
 system.ruby.network.routers0.msg_count.Response_Data::4          441                      
 system.ruby.network.routers0.msg_count.Writeback_Data::5           81                      
@@ -422,8 +432,8 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2         3400
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3         3400                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::5         2752                      
 system.ruby.network.routers0.msg_bytes.Unblock_Control::5         3520                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        32936                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     5.141031                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        35056                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     4.830129                      
 system.ruby.network.routers1.msg_count.Request_Control::2          441                      
 system.ruby.network.routers1.msg_count.Response_Data::4          441                      
 system.ruby.network.routers1.msg_count.Writeback_Data::5           81                      
@@ -438,8 +448,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2         3400
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3         3400                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::5         2752                      
 system.ruby.network.routers1.msg_bytes.Unblock_Control::5         3520                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        32936                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     5.141031                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        35056                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     4.830129                      
 system.ruby.network.routers2.msg_count.Request_Control::2          441                      
 system.ruby.network.routers2.msg_count.Response_Data::4          441                      
 system.ruby.network.routers2.msg_count.Writeback_Data::5           81                      
@@ -454,7 +464,7 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2         3400
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3         3400                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::5         2752                      
 system.ruby.network.routers2.msg_bytes.Unblock_Control::5         3520                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        32936                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        35056                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Request_Control         1323                      
 system.ruby.network.msg_count.Response_Data         1323                      
 system.ruby.network.msg_count.Writeback_Data          243                      
@@ -465,13 +475,13 @@ system.ruby.network.msg_byte.Response_Data        95256
 system.ruby.network.msg_byte.Writeback_Data        17496                      
 system.ruby.network.msg_byte.Writeback_Control        28656                      
 system.ruby.network.msg_byte.Unblock_Control        10560                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        32936                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     6.670513                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        35056                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     6.267115                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          441                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          425                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        31752                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         3400                      
-system.ruby.network.routers0.throttle1.link_utilization     3.611550                      
+system.ruby.network.routers0.throttle1.link_utilization     3.393142                      
 system.ruby.network.routers0.throttle1.msg_count.Request_Control::2          441                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5           81                      
 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2          425                      
@@ -482,7 +492,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5         5832
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2         3400                      
 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5         2752                      
 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5         3520                      
-system.ruby.network.routers1.throttle0.link_utilization     3.611550                      
+system.ruby.network.routers1.throttle0.link_utilization     3.393142                      
 system.ruby.network.routers1.throttle0.msg_count.Request_Control::2          441                      
 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5           81                      
 system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2          425                      
@@ -493,17 +503,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5         5832
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2         3400                      
 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5         2752                      
 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5         3520                      
-system.ruby.network.routers1.throttle1.link_utilization     6.670513                      
+system.ruby.network.routers1.throttle1.link_utilization     6.267115                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          441                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          425                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        31752                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         3400                      
-system.ruby.network.routers2.throttle0.link_utilization     6.670513                      
+system.ruby.network.routers2.throttle0.link_utilization     6.267115                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          441                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          425                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        31752                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         3400                      
-system.ruby.network.routers2.throttle1.link_utilization     3.611550                      
+system.ruby.network.routers2.throttle1.link_utilization     3.393142                      
 system.ruby.network.routers2.throttle1.msg_count.Request_Control::2          441                      
 system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5           81                      
 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2          425                      
@@ -517,10 +527,10 @@ system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5         3520
 system.ruby.LD.latency_hist_seqr::bucket_size           16                      
 system.ruby.LD.latency_hist_seqr::max_bucket          159                      
 system.ruby.LD.latency_hist_seqr::samples          415                      
-system.ruby.LD.latency_hist_seqr::mean      19.850602                      
-system.ruby.LD.latency_hist_seqr::gmean      4.833066                      
-system.ruby.LD.latency_hist_seqr::stdev     26.151303                      
-system.ruby.LD.latency_hist_seqr         |         269     64.82%     64.82% |          42     10.12%     74.94% |           3      0.72%     75.66% |          70     16.87%     92.53% |          20      4.82%     97.35% |          11      2.65%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      21.354217                      
+system.ruby.LD.latency_hist_seqr::gmean      4.945859                      
+system.ruby.LD.latency_hist_seqr::stdev     28.670834                      
+system.ruby.LD.latency_hist_seqr         |         269     64.82%     64.82% |          42     10.12%     74.94% |           3      0.72%     75.66% |          69     16.63%     92.29% |          18      4.34%     96.63% |          14      3.37%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_seqr::total           415                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            2                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket           19                      
@@ -533,18 +543,18 @@ system.ruby.LD.hit_latency_hist_seqr::total          269
 system.ruby.LD.miss_latency_hist_seqr::bucket_size           16                      
 system.ruby.LD.miss_latency_hist_seqr::max_bucket          159                      
 system.ruby.LD.miss_latency_hist_seqr::samples          146                      
-system.ruby.LD.miss_latency_hist_seqr::mean    52.116438                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    48.763829                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    17.717519                      
-system.ruby.LD.miss_latency_hist_seqr    |           0      0.00%      0.00% |          42     28.77%     28.77% |           3      2.05%     30.82% |          70     47.95%     78.77% |          20     13.70%     92.47% |          11      7.53%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    56.390411                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    52.068669                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    20.461022                      
+system.ruby.LD.miss_latency_hist_seqr    |           0      0.00%      0.00% |          42     28.77%     28.77% |           3      2.05%     30.82% |          69     47.26%     78.08% |          18     12.33%     90.41% |          14      9.59%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          146                      
-system.ruby.ST.latency_hist_seqr::bucket_size           32                      
-system.ruby.ST.latency_hist_seqr::max_bucket          319                      
+system.ruby.ST.latency_hist_seqr::bucket_size            8                      
+system.ruby.ST.latency_hist_seqr::max_bucket           79                      
 system.ruby.ST.latency_hist_seqr::samples          294                      
-system.ruby.ST.latency_hist_seqr::mean      10.064626                      
-system.ruby.ST.latency_hist_seqr::gmean      2.035894                      
-system.ruby.ST.latency_hist_seqr::stdev     25.936505                      
-system.ruby.ST.latency_hist_seqr         |         262     89.12%     89.12% |          22      7.48%     96.60% |           9      3.06%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           1      0.34%    100.00%
+system.ruby.ST.latency_hist_seqr::mean       9.778912                      
+system.ruby.ST.latency_hist_seqr::gmean      2.043604                      
+system.ruby.ST.latency_hist_seqr::stdev     20.538869                      
+system.ruby.ST.latency_hist_seqr         |         236     80.27%     80.27% |          11      3.74%     84.01% |           0      0.00%     84.01% |          15      5.10%     89.12% |           0      0.00%     89.12% |           0      0.00%     89.12% |           0      0.00%     89.12% |          22      7.48%     96.60% |           5      1.70%     98.30% |           5      1.70%    100.00%
 system.ruby.ST.latency_hist_seqr::total           294                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            2                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket           19                      
@@ -554,21 +564,21 @@ system.ruby.ST.hit_latency_hist_seqr::gmean     1.112699
 system.ruby.ST.hit_latency_hist_seqr::stdev     2.066980                      
 system.ruby.ST.hit_latency_hist_seqr     |         236     95.55%     95.55% |           0      0.00%     95.55% |           0      0.00%     95.55% |           0      0.00%     95.55% |           0      0.00%     95.55% |          11      4.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.hit_latency_hist_seqr::total          247                      
-system.ruby.ST.miss_latency_hist_seqr::bucket_size           32                      
-system.ruby.ST.miss_latency_hist_seqr::max_bucket          319                      
+system.ruby.ST.miss_latency_hist_seqr::bucket_size            8                      
+system.ruby.ST.miss_latency_hist_seqr::max_bucket           79                      
 system.ruby.ST.miss_latency_hist_seqr::samples           47                      
-system.ruby.ST.miss_latency_hist_seqr::mean    55.361702                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    48.711518                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    42.031265                      
-system.ruby.ST.miss_latency_hist_seqr    |          15     31.91%     31.91% |          22     46.81%     78.72% |           9     19.15%     97.87% |           0      0.00%     97.87% |           0      0.00%     97.87% |           0      0.00%     97.87% |           0      0.00%     97.87% |           0      0.00%     97.87% |           0      0.00%     97.87% |           1      2.13%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean    53.574468                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    49.876949                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    18.206240                      
+system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          15     31.91%     31.91% |           0      0.00%     31.91% |           0      0.00%     31.91% |           0      0.00%     31.91% |          22     46.81%     78.72% |           5     10.64%     89.36% |           5     10.64%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total           47                      
-system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
-system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
+system.ruby.IFETCH.latency_hist_seqr::bucket_size           32                      
+system.ruby.IFETCH.latency_hist_seqr::max_bucket          319                      
 system.ruby.IFETCH.latency_hist_seqr::samples         2585                      
-system.ruby.IFETCH.latency_hist_seqr::mean     7.135397                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.515500                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    20.744191                      
-system.ruby.IFETCH.latency_hist_seqr     |        2536     98.10%     98.10% |          46      1.78%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           1      0.04%     99.92% |           2      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     7.746615                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.529553                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    22.548460                      
+system.ruby.IFETCH.latency_hist_seqr     |        2337     90.41%     90.41% |         199      7.70%     98.10% |          43      1.66%     99.77% |           2      0.08%     99.85% |           0      0.00%     99.85% |           0      0.00%     99.85% |           0      0.00%     99.85% |           0      0.00%     99.85% |           0      0.00%     99.85% |           4      0.15%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         2585                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            2                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket           19                      
@@ -578,13 +588,13 @@ system.ruby.IFETCH.hit_latency_hist_seqr::gmean     1.022830
 system.ruby.IFETCH.hit_latency_hist_seqr::stdev     0.965875                      
 system.ruby.IFETCH.hit_latency_hist_seqr |        2315     99.06%     99.06% |           0      0.00%     99.06% |           0      0.00%     99.06% |           0      0.00%     99.06% |           0      0.00%     99.06% |          22      0.94%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.hit_latency_hist_seqr::total         2337                      
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
+system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           32                      
+system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          319                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          248                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    64.064516                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    61.606137                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    29.893804                      
-system.ruby.IFETCH.miss_latency_hist_seqr |         199     80.24%     80.24% |          46     18.55%     98.79% |           0      0.00%     98.79% |           0      0.00%     98.79% |           1      0.40%     99.19% |           2      0.81%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    70.435484                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    67.827440                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    30.751253                      
+system.ruby.IFETCH.miss_latency_hist_seqr |           0      0.00%      0.00% |         199     80.24%     80.24% |          43     17.34%     97.58% |           2      0.81%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           4      1.61%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          248                      
 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket            9                      
@@ -600,13 +610,13 @@ system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean           11
 system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean    11.000000                      
 system.ruby.L2Cache.hit_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          69    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L2Cache.hit_mach_latency_hist_seqr::total           69                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           64                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          639                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           32                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          319                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::samples          441                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean    59.181406                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    55.608631                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    28.659343                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |         351     79.59%     79.59% |          86     19.50%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           2      0.45%     99.55% |           2      0.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean    63.988662                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    60.139666                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    27.525151                      
+system.ruby.Directory.miss_mach_latency_hist_seqr |          57     12.93%     12.93% |         293     66.44%     79.37% |          85     19.27%     98.64% |           2      0.45%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           4      0.91%    100.00%
 system.ruby.Directory.miss_mach_latency_hist_seqr::total          441                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket            9                      
@@ -651,10 +661,10 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total           36
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           16                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          159                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples          146                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    52.116438                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    48.763829                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    17.717519                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          42     28.77%     28.77% |           3      2.05%     30.82% |          70     47.95%     78.77% |          20     13.70%     92.47% |          11      7.53%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    56.390411                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    52.068669                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    20.461022                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          42     28.77%     28.77% |           3      2.05%     30.82% |          69     47.26%     78.08% |          18     12.33%     90.41% |          14      9.59%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total          146                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
@@ -670,13 +680,13 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean           11
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean    11.000000                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          11    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total           11                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size            8                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket           79                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples           47                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    55.361702                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    48.711518                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    42.031265                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |          15     31.91%     31.91% |          22     46.81%     78.72% |           9     19.15%     97.87% |           0      0.00%     97.87% |           0      0.00%     97.87% |           0      0.00%     97.87% |           0      0.00%     97.87% |           0      0.00%     97.87% |           0      0.00%     97.87% |           1      2.13%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    53.574468                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    49.876949                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    18.206240                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          15     31.91%     31.91% |           0      0.00%     31.91% |           0      0.00%     31.91% |           0      0.00%     31.91% |          22     46.81%     78.72% |           5     10.64%     89.36% |           5     10.64%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total           47                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
@@ -692,13 +702,13 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean           11
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean    11.000000                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          22    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total           22                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples          248                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    64.064516                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    61.606137                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    29.893804                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         199     80.24%     80.24% |          46     18.55%     98.79% |           0      0.00%     98.79% |           0      0.00%     98.79% |           1      0.40%     99.19% |           2      0.81%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    70.435484                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    67.827440                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    30.751253                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         199     80.24%     80.24% |          43     17.34%     97.58% |           2      0.81%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           4      1.61%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total          248                      
 system.ruby.Directory_Controller.GETX              51      0.00%      0.00%
 system.ruby.Directory_Controller.GETS             410      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 538bb6cd3..7199cc5b0 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
@@ -256,6 +278,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
 eventq_index=0
 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestToDir=system.ruby.dir_cntrl0.requestToDir
 responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -329,11 +355,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 forwardToCache=system.ruby.l1_cntrl0.forwardToCache
 issue_latency=2
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestFromCache=system.ruby.l1_cntrl0.requestFromCache
 responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -415,17 +446,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.cacheMemory
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.cacheMemory
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
@@ -438,18 +474,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
 netifs=
 number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
 ruby_system=system.ruby
 topology=Crossbar
@@ -616,32 +657,206 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14
+power_model=Null
 router_id=0
 virt_nets=5
 
@@ -754,8 +969,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14
+power_model=Null
 router_id=1
 virt_nets=5
 
@@ -868,8 +1089,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19
+power_model=Null
 router_id=2
 virt_nets=5
 
@@ -1016,9 +1243,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
index 1c18978fa..63982fce4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
@@ -4,9 +4,8 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
 warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 98025cd1e..d4c6f5ba8 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:26
-gem5 executing on zizzer, pid 34072
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:46
+gem5 executing on e108600-lin, pid 28078
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 41659 because target called exit()
+Exiting @ tick 43520 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index f97a14626..535942f10 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000042                       # Number of seconds simulated
-sim_ticks                                       41659                       # Number of ticks simulated
-final_tick                                      41659                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000044                       # Number of seconds simulated
+sim_ticks                                       43520                       # Number of ticks simulated
+final_tick                                      43520                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  54027                       # Simulator instruction rate (inst/s)
-host_op_rate                                    54016                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 873053                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 453224                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  93431                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93392                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1576605                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 411000                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        41659                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        43520                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        40064                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              40064                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0        39808                       # Number of bytes written to this memory
@@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0          626                       #
 system.mem_ctrls.num_reads::total                 626                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0          622                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total                622                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    961712955                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             961712955                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    955567824                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            955567824                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   1917280780                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1917280780                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    920588235                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             920588235                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    914705882                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            914705882                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   1835294118                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1835294118                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                         626                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                        622                       # Number of write requests accepted
 system.mem_ctrls.readBursts                       626                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                      622                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  24960                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   15104                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   24000                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  24512                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   15552                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   23424                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   40064                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                39808                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    236                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   219                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    243                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   231                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
 system.mem_ctrls.perBankRdBursts::0                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                30                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4                23                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4                24                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                 0                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6                58                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7                62                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8                63                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9                 4                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               24                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11               15                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12               32                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13               66                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6                53                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7                53                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8                68                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9                 5                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               25                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11               14                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12               30                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13               68                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14               10                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                1                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::0                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::1                 1                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 1                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3                31                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4                22                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3                32                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4                23                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::5                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6                54                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7                57                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8                65                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9                 3                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10               21                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6                48                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7                43                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8                68                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9                 5                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10               23                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::11               15                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::12               31                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               63                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               65                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::14               10                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                1                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         41626                       # Total gap between requests
+system.mem_ctrls.totGap                         43487                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                  622                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     390                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                     383                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -136,24 +136,24 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      3                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      3                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     18                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                     25                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     27                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     27                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                     25                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     25                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     24                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                     24                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     24                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                     24                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     24                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                     23                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     23                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     23                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     23                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     23                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      7                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     17                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                     23                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     23                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                     26                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                     28                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     24                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     23                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                     23                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                     22                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                     22                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                     22                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                     22                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     22                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                     22                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     22                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                     22                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
@@ -185,89 +185,98 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          105                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    455.923810                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   317.170384                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   344.729986                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           11     10.48%     10.48% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           29     27.62%     38.10% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           10      9.52%     47.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           10      9.52%     57.14% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           14     13.33%     70.48% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            5      4.76%     75.24% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            4      3.81%     79.05% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            5      4.76%     83.81% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           17     16.19%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          105                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples           23                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      16.434783                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     16.058223                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      4.388270                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13             3     13.04%     13.04% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15            10     43.48%     56.52% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17             5     21.74%     78.26% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             4     17.39%     95.65% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35             1      4.35%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total            23                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples           23                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.304348                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.283756                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.875670                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               20     86.96%     86.96% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                1      4.35%     91.30% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                2      8.70%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total            23                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         4371                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   11781                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       1950                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        11.21                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples          113                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    404.389381                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   273.588270                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   327.373952                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           20     17.70%     17.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           26     23.01%     40.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           16     14.16%     54.87% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           15     13.27%     68.14% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639            5      4.42%     72.57% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            6      5.31%     77.88% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            8      7.08%     84.96% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            5      4.42%     89.38% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           12     10.62%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          113                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples           22                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean             17                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     16.662586                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      4.253850                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15             8     36.36%     36.36% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17             8     36.36%     72.73% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19             5     22.73%     95.45% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35             1      4.55%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total            22                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples           22                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.636364                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.596436                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      1.216766                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               17     77.27%     77.27% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                1      4.55%     81.82% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19                4     18.18%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total            22                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                         6435                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   13712                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       1915                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        16.80                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   30.21                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       599.15                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       576.11                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    961.71                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    955.57                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   35.80                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       563.24                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       538.24                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    920.59                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    914.71                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         9.18                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.68                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    4.50                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         8.61                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     4.40                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    4.20                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      24.82                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      298                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     355                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 76.41                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                88.09                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         33.35                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    82.35                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   234360                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   130200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 1971840                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                1555200                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              2542800                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             26028252                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy               682200                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               33144852                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            845.747691                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE         1011                       # Time in different power states
+system.mem_ctrls.avgWrQLen                      24.70                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      286                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     342                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 74.67                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                87.47                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         34.85                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    81.14                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   264180                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   127512                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 1850688                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                1236096                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         3073200.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              3917040                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy                69120                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        15256848                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy          496128                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               26290812                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            604.108732                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                34684                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE           40                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          1300                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         36893                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                   536760                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   298200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 2608320                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                2166912                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              2542800                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             26345628                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy               403800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               34902420                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            890.595050                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE          832                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN         1292                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT          7430                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        33458                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   599760                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   309120                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 2524704                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                1820736                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         3073200.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy              5746968                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               231168                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        13781232                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy           35712                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               28122600                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            646.199449                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                29649                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          448                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF          1300                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         37357                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        41659                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN           93                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         11457                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        30222                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED        43520                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -302,8 +311,8 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON           41659                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            41659                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON           43520                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            43520                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2577                       # Number of instructions committed
@@ -322,7 +331,7 @@ system.cpu.num_mem_refs                           717                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      41659                       # Number of busy cycles
+system.cpu.num_busy_cycles                      43520                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               396                       # Number of branches fetched
@@ -362,7 +371,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       2585                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        41659                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        43520                       # Cumulative time (in ticks) in various power states
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   1248                       # delay histogram for all message
@@ -378,10 +387,10 @@ system.ruby.outstanding_req_hist_seqr::total         3295
 system.ruby.latency_hist_seqr::bucket_size           64                      
 system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples           3294                      
-system.ruby.latency_hist_seqr::mean         11.646934                      
-system.ruby.latency_hist_seqr::gmean         2.114776                      
-system.ruby.latency_hist_seqr::stdev        26.263922                      
-system.ruby.latency_hist_seqr            |        3185     96.69%     96.69% |          90      2.73%     99.42% |          14      0.43%     99.85% |           0      0.00%     99.85% |           2      0.06%     99.91% |           3      0.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean         12.211900                      
+system.ruby.latency_hist_seqr::gmean         2.131468                      
+system.ruby.latency_hist_seqr::stdev        27.594720                      
+system.ruby.latency_hist_seqr            |        2924     88.77%     88.77% |         353     10.72%     99.48% |          12      0.36%     99.85% |           0      0.00%     99.85% |           2      0.06%     99.91% |           3      0.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist_seqr::total             3294                      
 system.ruby.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.hit_latency_hist_seqr::max_bucket            9                      
@@ -393,21 +402,21 @@ system.ruby.hit_latency_hist_seqr::total         2668
 system.ruby.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.miss_latency_hist_seqr::samples          626                      
-system.ruby.miss_latency_hist_seqr::mean    57.023962                      
-system.ruby.miss_latency_hist_seqr::gmean    51.467697                      
-system.ruby.miss_latency_hist_seqr::stdev    32.986607                      
-system.ruby.miss_latency_hist_seqr       |         517     82.59%     82.59% |          90     14.38%     96.96% |          14      2.24%     99.20% |           0      0.00%     99.20% |           2      0.32%     99.52% |           3      0.48%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    59.996805                      
+system.ruby.miss_latency_hist_seqr::gmean    53.641558                      
+system.ruby.miss_latency_hist_seqr::stdev    34.472574                      
+system.ruby.miss_latency_hist_seqr       |         256     40.89%     40.89% |         353     56.39%     97.28% |          12      1.92%     99.20% |           0      0.00%     99.20% |           2      0.32%     99.52% |           3      0.48%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist_seqr::total          626                      
 system.ruby.Directory.incomplete_times_seqr          625                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        41659                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        43520                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         2668                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses          626                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         3294                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        41659                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        41659                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        43520                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        43520                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        41659                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     7.489378                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        43520                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     7.169118                      
 system.ruby.network.routers0.msg_count.Control::2          626                      
 system.ruby.network.routers0.msg_count.Data::2          622                      
 system.ruby.network.routers0.msg_count.Response_Data::4          626                      
@@ -416,8 +425,8 @@ system.ruby.network.routers0.msg_bytes.Control::2         5008
 system.ruby.network.routers0.msg_bytes.Data::2        44784                      
 system.ruby.network.routers0.msg_bytes.Response_Data::4        45072                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        41659                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     7.489378                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        43520                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     7.169118                      
 system.ruby.network.routers1.msg_count.Control::2          626                      
 system.ruby.network.routers1.msg_count.Data::2          622                      
 system.ruby.network.routers1.msg_count.Response_Data::4          626                      
@@ -426,8 +435,8 @@ system.ruby.network.routers1.msg_bytes.Control::2         5008
 system.ruby.network.routers1.msg_bytes.Data::2        44784                      
 system.ruby.network.routers1.msg_bytes.Response_Data::4        45072                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        41659                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     7.489378                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        43520                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     7.169118                      
 system.ruby.network.routers2.msg_count.Control::2          626                      
 system.ruby.network.routers2.msg_count.Data::2          622                      
 system.ruby.network.routers2.msg_count.Response_Data::4          626                      
@@ -436,7 +445,7 @@ system.ruby.network.routers2.msg_bytes.Control::2         5008
 system.ruby.network.routers2.msg_bytes.Data::2        44784                      
 system.ruby.network.routers2.msg_bytes.Response_Data::4        45072                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        41659                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        43520                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Control            1878                      
 system.ruby.network.msg_count.Data               1866                      
 system.ruby.network.msg_count.Response_Data         1878                      
@@ -445,33 +454,33 @@ system.ruby.network.msg_byte.Control            15024
 system.ruby.network.msg_byte.Data              134352                      
 system.ruby.network.msg_byte.Response_Data       135216                      
 system.ruby.network.msg_byte.Writeback_Control        14928                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        41659                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     7.508582                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        43520                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     7.187500                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          626                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          622                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        45072                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.routers0.throttle1.link_utilization     7.470175                      
+system.ruby.network.routers0.throttle1.link_utilization     7.150735                      
 system.ruby.network.routers0.throttle1.msg_count.Control::2          626                      
 system.ruby.network.routers0.throttle1.msg_count.Data::2          622                      
 system.ruby.network.routers0.throttle1.msg_bytes.Control::2         5008                      
 system.ruby.network.routers0.throttle1.msg_bytes.Data::2        44784                      
-system.ruby.network.routers1.throttle0.link_utilization     7.470175                      
+system.ruby.network.routers1.throttle0.link_utilization     7.150735                      
 system.ruby.network.routers1.throttle0.msg_count.Control::2          626                      
 system.ruby.network.routers1.throttle0.msg_count.Data::2          622                      
 system.ruby.network.routers1.throttle0.msg_bytes.Control::2         5008                      
 system.ruby.network.routers1.throttle0.msg_bytes.Data::2        44784                      
-system.ruby.network.routers1.throttle1.link_utilization     7.508582                      
+system.ruby.network.routers1.throttle1.link_utilization     7.187500                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          626                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          622                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        45072                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.routers2.throttle0.link_utilization     7.508582                      
+system.ruby.network.routers2.throttle0.link_utilization     7.187500                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          626                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          622                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        45072                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.routers2.throttle1.link_utilization     7.470175                      
+system.ruby.network.routers2.throttle1.link_utilization     7.150735                      
 system.ruby.network.routers2.throttle1.msg_count.Control::2          626                      
 system.ruby.network.routers2.throttle1.msg_count.Data::2          622                      
 system.ruby.network.routers2.throttle1.msg_bytes.Control::2         5008                      
@@ -486,13 +495,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket            9                       #
 system.ruby.delayVCHist.vnet_2::samples           622                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2           |         622    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::total             622                       # delay histogram for vnet_2
-system.ruby.LD.latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.latency_hist_seqr::samples          415                      
-system.ruby.LD.latency_hist_seqr::mean      30.537349                      
-system.ruby.LD.latency_hist_seqr::gmean      9.686440                      
-system.ruby.LD.latency_hist_seqr::stdev     30.265140                      
-system.ruby.LD.latency_hist_seqr         |         170     40.96%     40.96% |         203     48.92%     89.88% |          35      8.43%     98.31% |           3      0.72%     99.04% |           3      0.72%     99.76% |           1      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      33.354217                      
+system.ruby.LD.latency_hist_seqr::gmean      9.992707                      
+system.ruby.LD.latency_hist_seqr::stdev     38.395820                      
+system.ruby.LD.latency_hist_seqr         |         297     71.57%     71.57% |         114     27.47%     99.04% |           2      0.48%     99.52% |           0      0.00%     99.52% |           0      0.00%     99.52% |           2      0.48%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_seqr::total           415                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
@@ -501,21 +510,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean            1
 system.ruby.LD.hit_latency_hist_seqr::gmean            1                      
 system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |         170    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.hit_latency_hist_seqr::total          170                      
-system.ruby.LD.miss_latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.miss_latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.miss_latency_hist_seqr::samples          245                      
-system.ruby.LD.miss_latency_hist_seqr::mean    51.032653                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    46.821080                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    22.902478                      
-system.ruby.LD.miss_latency_hist_seqr    |           0      0.00%      0.00% |         203     82.86%     82.86% |          35     14.29%     97.14% |           3      1.22%     98.37% |           3      1.22%     99.59% |           1      0.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    55.804082                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    49.356103                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    35.580698                      
+system.ruby.LD.miss_latency_hist_seqr    |         127     51.84%     51.84% |         114     46.53%     98.37% |           2      0.82%     99.18% |           0      0.00%     99.18% |           0      0.00%     99.18% |           2      0.82%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          245                      
-system.ruby.ST.latency_hist_seqr::bucket_size           64                      
-system.ruby.ST.latency_hist_seqr::max_bucket          639                      
+system.ruby.ST.latency_hist_seqr::bucket_size           32                      
+system.ruby.ST.latency_hist_seqr::max_bucket          319                      
 system.ruby.ST.latency_hist_seqr::samples          294                      
-system.ruby.ST.latency_hist_seqr::mean      16.663265                      
-system.ruby.ST.latency_hist_seqr::gmean      3.036238                      
-system.ruby.ST.latency_hist_seqr::stdev     32.952425                      
-system.ruby.ST.latency_hist_seqr         |         283     96.26%     96.26% |           6      2.04%     98.30% |           4      1.36%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           1      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::mean      16.173469                      
+system.ruby.ST.latency_hist_seqr::gmean      3.033104                      
+system.ruby.ST.latency_hist_seqr::stdev     28.208400                      
+system.ruby.ST.latency_hist_seqr         |         210     71.43%     71.43% |          44     14.97%     86.39% |          36     12.24%     98.64% |           1      0.34%     98.98% |           2      0.68%     99.66% |           1      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist_seqr::total           294                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
@@ -524,21 +533,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean            1
 system.ruby.ST.hit_latency_hist_seqr::gmean            1                      
 system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |         210    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.hit_latency_hist_seqr::total          210                      
-system.ruby.ST.miss_latency_hist_seqr::bucket_size           64                      
-system.ruby.ST.miss_latency_hist_seqr::max_bucket          639                      
+system.ruby.ST.miss_latency_hist_seqr::bucket_size           32                      
+system.ruby.ST.miss_latency_hist_seqr::max_bucket          319                      
 system.ruby.ST.miss_latency_hist_seqr::samples           84                      
-system.ruby.ST.miss_latency_hist_seqr::mean    55.821429                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    48.772534                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    40.751129                      
-system.ruby.ST.miss_latency_hist_seqr    |          73     86.90%     86.90% |           6      7.14%     94.05% |           4      4.76%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           1      1.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean    54.107143                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    48.596564                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    27.751487                      
+system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |          44     52.38%     52.38% |          36     42.86%     95.24% |           1      1.19%     96.43% |           2      2.38%     98.81% |           1      1.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total           84                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples         2585                      
-system.ruby.IFETCH.latency_hist_seqr::mean     8.043714                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.589638                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    23.152025                      
-system.ruby.IFETCH.latency_hist_seqr     |        2529     97.83%     97.83% |          46      1.78%     99.61% |           6      0.23%     99.85% |           0      0.00%     99.85% |           2      0.08%     99.92% |           2      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     8.367118                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.597827                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    23.571466                      
+system.ruby.IFETCH.latency_hist_seqr     |        2373     91.80%     91.80% |         202      7.81%     99.61% |           7      0.27%     99.88% |           0      0.00%     99.88% |           2      0.08%     99.96% |           1      0.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         2585                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
@@ -550,18 +559,18 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total         2288
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          297                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    62.306397                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    56.498895                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    36.624977                      
-system.ruby.IFETCH.miss_latency_hist_seqr |         241     81.14%     81.14% |          46     15.49%     96.63% |           6      2.02%     98.65% |           0      0.00%     98.65% |           2      0.67%     99.33% |           2      0.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    65.121212                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    59.083052                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    34.625488                      
+system.ruby.IFETCH.miss_latency_hist_seqr |          85     28.62%     28.62% |         202     68.01%     96.63% |           7      2.36%     98.99% |           0      0.00%     98.99% |           2      0.67%     99.66% |           1      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          297                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::samples          626                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean    57.023962                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    51.467697                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    32.986607                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |         517     82.59%     82.59% |          90     14.38%     96.96% |          14      2.24%     99.20% |           0      0.00%     99.20% |           2      0.32%     99.52% |           3      0.48%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean    59.996805                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    53.641558                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    34.472574                      
+system.ruby.Directory.miss_mach_latency_hist_seqr |         256     40.89%     40.89% |         353     56.39%     97.28% |          12      1.92%     99.20% |           0      0.00%     99.20% |           2      0.32%     99.52% |           3      0.48%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist_seqr::total          626                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket            9                      
@@ -589,29 +598,29 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean
 system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev          nan                      
 system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
 system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total            1                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples          245                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    51.032653                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    46.821080                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    22.902478                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         203     82.86%     82.86% |          35     14.29%     97.14% |           3      1.22%     98.37% |           3      1.22%     99.59% |           1      0.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    55.804082                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    49.356103                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    35.580698                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |         127     51.84%     51.84% |         114     46.53%     98.37% |           2      0.82%     99.18% |           0      0.00%     99.18% |           0      0.00%     99.18% |           2      0.82%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total          245                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples           84                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    55.821429                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    48.772534                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    40.751129                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |          73     86.90%     86.90% |           6      7.14%     94.05% |           4      4.76%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |           1      1.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    54.107143                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    48.596564                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    27.751487                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          44     52.38%     52.38% |          36     42.86%     95.24% |           1      1.19%     96.43% |           2      2.38%     98.81% |           1      1.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total           84                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples          297                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    62.306397                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    56.498895                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    36.624977                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         241     81.14%     81.14% |          46     15.49%     96.63% |           6      2.02%     98.65% |           0      0.00%     98.65% |           2      0.67%     99.33% |           2      0.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    65.121212                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    59.083052                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    34.625488                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |          85     28.62%     28.62% |         202     68.01%     96.63% |           7      2.36%     98.99% |           0      0.00%     98.99% |           2      0.67%     99.66% |           1      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total          297                      
 system.ruby.Directory_Controller.GETX             626      0.00%      0.00%
 system.ruby.Directory_Controller.PUTX             622      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
index a47bafcf6..fc8ce75af 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
@@ -151,7 +151,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -631,7 +631,7 @@ opClass=InstPrefetch
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -691,7 +691,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -880,6 +880,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -891,7 +892,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -899,29 +900,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -941,6 +949,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -972,9 +981,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout
index 21abd8071..6a285f351 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:38:22
-gem5 executing on e108600-lin, pid 23083
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:42:59
+gem5 executing on e108600-lin, pid 17319
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/minor-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 30083500 because target called exit()
+Exiting @ tick 32719500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index 9ca1ab172..48cd9ae26 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000030                       # Number of seconds simulated
-sim_ticks                                    30404500                       # Number of ticks simulated
-final_tick                                   30404500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000033                       # Number of seconds simulated
+sim_ticks                                    32719500                       # Number of ticks simulated
+final_tick                                   32719500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  82707                       # Simulator instruction rate (inst/s)
-host_op_rate                                    96800                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              545818868                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269760                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                 127457                       # Simulator instruction rate (inst/s)
+host_op_rate                                   149152                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              904929733                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267332                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        4605                       # Number of instructions simulated
 sim_ops                                          5391                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             19520                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              7424                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                26944                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           19520                       # Nu
 system.physmem.num_reads::cpu.inst                305                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                116                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   421                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            642010229                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            244174382                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               886184611                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       642010229                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          642010229                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           642010229                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           244174382                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              886184611                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            596586134                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            226898333                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               823484466                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       596586134                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          596586134                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           596586134                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           226898333                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              823484466                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           421                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         421                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        30312500                       # Total gap between requests
+system.physmem.totGap                        32621500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       344                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       343                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                        70                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -187,86 +187,96 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           63                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      402.285714                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     286.546821                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.800854                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127              7     11.11%     11.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           19     30.16%     41.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           13     20.63%     61.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            6      9.52%     71.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      3.17%     74.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            3      4.76%     79.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      4.76%     84.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      1.59%     85.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            9     14.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             63                       # Bytes accessed per row activation
-system.physmem.totQLat                        2201250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10095000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           70                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      374.857143                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     257.842659                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     316.227871                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             12     17.14%     17.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           20     28.57%     45.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           11     15.71%     61.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            9     12.86%     74.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      2.86%     77.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      4.29%     81.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            4      5.71%     87.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      2.86%     90.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            7     10.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             70                       # Bytes accessed per row activation
+system.physmem.totQLat                        5175000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13068750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2105000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5228.62                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       12292.16                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23978.62                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         886.18                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31042.16                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         823.48                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      886.18                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      823.48                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           6.92                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       6.92                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           6.43                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       6.43                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.23                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        349                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        347                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.90                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   82.42                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        72001.19                       # Average gap between requests
-system.physmem.pageHitRate                      82.90                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     272160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     148500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   1942200                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        77485.75                       # Average gap between requests
+system.physmem.pageHitRate                      82.42                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     349860                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     174570                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2263380                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               16099650                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  48750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 20036940                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              848.348875                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE          12000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        22840500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     128520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                      70125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                    694200                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           2458560.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                4410090                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  59520                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy          10437840                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy              1440                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                 20155260                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              615.992054                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime               22842000                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE          30000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF         1040000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN         3750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT         8749750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     22896000                       # Time in different power states
+system.physmem_1.actEnergy                     178500                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                      91080                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                    742560                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               15442155                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 625500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 18486180                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              782.690871                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        2431750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        21880250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.physmem_1.refreshEnergy           2458560.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                1743060                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                  96480                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy          12022440                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy            876000                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                 18208680                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              556.500000                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime               28380000                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE         141000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF         1040000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN      2280750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         2887500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN     26370250                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups                    1968                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1178                       # Number of conditional branches predicted
+system.cpu.branchPred.condPredicted              1177                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               351                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1660                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups                 1659                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                     322                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             19.397590                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     220                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             19.409283                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     221                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 16                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups             135                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits                  8                       # Number of indirect target hits.
 system.cpu.branchPred.indirectMisses              127                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted           62                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -296,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -326,7 +336,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -356,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -387,16 +397,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        30404500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            60809                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        32719500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            65439                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4605                       # Number of instructions committed
 system.cpu.committedOps                          5391                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                          1193                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              13.204995                       # CPI: cycles per instruction
-system.cpu.ipc                               0.075729                       # IPC: instructions per cycle
+system.cpu.cpi                              14.210423                       # CPI: cycles per instruction
+system.cpu.ipc                               0.070371                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu                    3419     63.42%     63.42% # Class of committed instruction
 system.cpu.op_class_0::IntMult                      4      0.07%     63.49% # Class of committed instruction
@@ -432,25 +442,25 @@ system.cpu.op_class_0::MemWrite                   938     17.40%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                     5391                       # Class of committed instruction
-system.cpu.tickCycles                           10721                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           50088                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                           10731                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           54708                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            86.589882                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            86.904844                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1918                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             13.136986                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    86.589882                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021140                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021140                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    86.904844                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021217                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021217                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          110                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              4334                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             4334                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data         1050                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1050                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          846                       # number of WriteReq hits
@@ -471,14 +481,14 @@ system.cpu.dcache.demand_misses::cpu.data          176                       # n
 system.cpu.dcache.demand_misses::total            176                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          176                       # number of overall misses
 system.cpu.dcache.overall_misses::total           176                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      6774500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      6774500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5069500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5069500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     11844000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     11844000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     11844000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     11844000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7434500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7434500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5464500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5464500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     12899000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     12899000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     12899000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     12899000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1159                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1159                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
@@ -499,14 +509,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.084942
 system.cpu.dcache.demand_miss_rate::total     0.084942                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.084942                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.084942                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62151.376147                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62151.376147                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75664.179104                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 75664.179104                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 67295.454545                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67295.454545                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67295.454545                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67295.454545                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68206.422018                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68206.422018                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81559.701493                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 81559.701493                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 73289.772727                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73289.772727                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73289.772727                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73289.772727                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -529,14 +539,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          146
 system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6419000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6419000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3231000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3231000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9650000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9650000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9650000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9650000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7061000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7061000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3488000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3488000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10549000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10549000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10549000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10549000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.088870                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088870                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
@@ -545,67 +555,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.070463
 system.cpu.dcache.demand_mshr_miss_rate::total     0.070463                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.070463                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.070463                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62320.388350                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62320.388350                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75139.534884                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75139.534884                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66095.890411                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66095.890411                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66095.890411                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66095.890411                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68553.398058                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68553.398058                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81116.279070                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81116.279070                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72253.424658                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72253.424658                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72253.424658                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72253.424658                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 4                       # number of replacements
-system.cpu.icache.tags.tagsinuse           162.072741                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1963                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           162.619345                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1965                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               322                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.096273                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.102484                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   162.072741                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.079137                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.079137                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   162.619345                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.079404                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.079404                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          318                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          215                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          220                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.155273                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4892                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4892                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         1963                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1963                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1963                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1963                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1963                       # number of overall hits
-system.cpu.icache.overall_hits::total            1963                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              4896                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4896                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst         1965                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1965                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1965                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1965                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1965                       # number of overall hits
+system.cpu.icache.overall_hits::total            1965                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          322                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           322                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          322                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            322                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          322                       # number of overall misses
 system.cpu.icache.overall_misses::total           322                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     23964000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     23964000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     23964000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     23964000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     23964000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     23964000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2285                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2285                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2285                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2285                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2285                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2285                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.140919                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.140919                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.140919                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.140919                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.140919                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.140919                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74422.360248                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 74422.360248                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 74422.360248                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 74422.360248                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 74422.360248                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 74422.360248                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     26079500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     26079500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     26079500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     26079500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     26079500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     26079500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2287                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2287                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2287                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2287                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2287                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2287                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.140796                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.140796                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.140796                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.140796                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.140796                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.140796                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80992.236025                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 80992.236025                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 80992.236025                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 80992.236025                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 80992.236025                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 80992.236025                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -620,43 +630,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          322
 system.cpu.icache.demand_mshr_misses::total          322                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          322                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          322                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23642000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     23642000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23642000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     23642000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23642000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     23642000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.140919                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.140919                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.140919                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.140919                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.140919                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.140919                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73422.360248                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73422.360248                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73422.360248                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 73422.360248                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73422.360248                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 73422.360248                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25757500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     25757500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25757500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     25757500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25757500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     25757500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.140796                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.140796                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.140796                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.140796                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.140796                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.140796                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79992.236025                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79992.236025                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79992.236025                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 79992.236025                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79992.236025                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 79992.236025                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          223.657376                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          224.400944                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 42                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              421                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.099762                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   154.975765                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    68.681611                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004729                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.002096                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006825                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   155.496620                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    68.904325                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004745                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.002103                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006848                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          421                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          308                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012848                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4189                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4189                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackClean_hits::writebacks            3                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total            3                       # number of WritebackClean hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           17                       # number of ReadCleanReq hits
@@ -681,18 +691,18 @@ system.cpu.l2cache.demand_misses::total           429                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          305                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          124                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          429                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3166500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3166500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     22963500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     22963500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      6005000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      6005000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     22963500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9171500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     32135000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     22963500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9171500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     32135000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3423500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3423500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25079000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     25079000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      6647000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      6647000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     25079000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10070500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     35149500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     25079000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10070500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     35149500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackClean_accesses::writebacks            3                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total            3                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           43                       # number of ReadExReq accesses(hits+misses)
@@ -719,18 +729,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.916667                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.947205                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.849315                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.916667                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73639.534884                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73639.534884                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75290.163934                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75290.163934                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 74135.802469                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 74135.802469                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75290.163934                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73963.709677                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74906.759907                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75290.163934                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73963.709677                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74906.759907                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79616.279070                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79616.279070                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82226.229508                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82226.229508                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82061.728395                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82061.728395                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82226.229508                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81213.709677                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81933.566434                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82226.229508                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81213.709677                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81933.566434                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -755,18 +765,18 @@ system.cpu.l2cache.demand_mshr_misses::total          421
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          305                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          116                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          421                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2736500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2736500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19913500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19913500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4721000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4721000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19913500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7457500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     27371000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19913500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7457500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     27371000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2993500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2993500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22029000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22029000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5321000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      5321000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22029000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8314500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     30343500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22029000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8314500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     30343500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for ReadCleanReq accesses
@@ -779,25 +789,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.899573
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.794521                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.899573                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63639.534884                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63639.534884                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65290.163934                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65290.163934                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64671.232877                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64671.232877                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65290.163934                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64288.793103                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65014.251781                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65290.163934                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64288.793103                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65014.251781                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69616.279070                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69616.279070                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72226.229508                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72226.229508                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72890.410959                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72890.410959                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72226.229508                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71676.724138                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72074.821853                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72226.229508                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71676.724138                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72074.821853                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests          472                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests           50                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           425                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            4                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
@@ -824,9 +834,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value            0                       #
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::total            468                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         240000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
+system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        483000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.6                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        222992                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
 system.membus.snoop_filter.tot_requests           421                       # Total number of requests made to the snoop filter.
@@ -835,7 +845,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     30404500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     32719500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                378                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
@@ -856,9 +866,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 421                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              490000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2238500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              7.4                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              489500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2238250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              6.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 69978e99c..ff436d924 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -352,7 +352,7 @@ eventq_index=0
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -756,7 +756,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -888,7 +888,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1005,6 +1005,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -1016,7 +1017,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -1024,29 +1025,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -1066,6 +1074,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -1075,7 +1084,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1097,9 +1106,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index 09d4a73db..e9b447feb 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:27:25
-gem5 executing on e108600-lin, pid 12519
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:42:58
+gem5 executing on e108600-lin, pid 17311
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 17232500 because target called exit()
+Exiting @ tick 18422500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 012901358..bf47005a8 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000017                       # Number of seconds simulated
-sim_ticks                                    17458500                       # Number of ticks simulated
-final_tick                                   17458500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000018                       # Number of seconds simulated
+sim_ticks                                    18422500                       # Number of ticks simulated
+final_tick                                   18422500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  52261                       # Simulator instruction rate (inst/s)
-host_op_rate                                    61197                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              198636102                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269760                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  65137                       # Simulator instruction rate (inst/s)
+host_op_rate                                    76274                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              261240377                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 268360                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             17664                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              7744                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                25408                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           17664                       # Nu
 system.physmem.num_reads::cpu.inst                276                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                121                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   397                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1011770771                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            443566171                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1455336942                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1011770771                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1011770771                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1011770771                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           443566171                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1455336942                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            958827521                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            420355543                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1379183064                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       958827521                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          958827521                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           958827521                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           420355543                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1379183064                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           397                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         397                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        17373000                       # Total gap between requests
+system.physmem.totGap                        18337000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,12 +91,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       209                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        50                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        16                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       202                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       121                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        54                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -187,86 +187,96 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           61                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      398.688525                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     264.215339                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     341.944807                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             12     19.67%     19.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           15     24.59%     44.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            9     14.75%     59.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            7     11.48%     70.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            3      4.92%     75.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      3.28%     78.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      3.28%     81.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      3.28%     85.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            9     14.75%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             61                       # Bytes accessed per row activation
-system.physmem.totQLat                        3455750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10899500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           59                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      407.864407                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     273.934367                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     344.219630                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             10     16.95%     16.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           17     28.81%     45.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            8     13.56%     59.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            7     11.86%     71.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            1      1.69%     72.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      3.39%     76.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      5.08%     81.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      5.08%     86.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            8     13.56%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             59                       # Bytes accessed per row activation
+system.physmem.totQLat                        5196750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  12640500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1985000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8704.66                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       13090.05                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27454.66                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1455.34                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31840.05                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1379.18                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1455.34                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1379.18                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.37                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.37                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.77                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.77                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.88                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.90                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        330                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.12                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43760.71                       # Average gap between requests
+system.physmem.avgGap                        46188.92                       # Average gap between requests
 system.physmem.pageHitRate                      83.12                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     294840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     160875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2051400                       # Energy for read commands per rank (pJ)
+system.physmem_0.actEnergy                     314160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     151800                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2084880                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10792665                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  32250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 14349150                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              906.309806                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE          11500                       # Time in different power states
+system.physmem_0.refreshEnergy           1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                3077430                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  36000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy           5255970                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy             20640                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                 12170160                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              660.613923                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime               11420000                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE          23500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        15314750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     143640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                      78375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                    748800                       # Energy for read commands per rank (pJ)
+system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN        53500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT         6303750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     11521750                       # Time in different power states
+system.physmem_1.actEnergy                     164220                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                      72105                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                    749700                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10299330                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 466500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 12753765                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              805.416167                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         734500                       # Time in different power states
+system.physmem_1.refreshEnergy           1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                1466040                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                  65760                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy           6124080                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy            616800                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                 10487985                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              569.303026                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime               14986000                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE         116000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14593500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    2836                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1744                       # Number of conditional branches predicted
+system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN      1605250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         2751250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN     13430000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                    2844                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1749                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               464                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2400                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     864                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups                 2408                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     867                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             36.000000                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             36.004983                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     314                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 70                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups             265                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits                 14                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses              251                       # Number of indirect misses.
+system.cpu.branchPred.indirectLookups             266                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits                 13                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses              253                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted           63                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -296,7 +306,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.checker.dtb.walker.walks                 0                       # Table walker walks requested
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -326,7 +336,7 @@ system.cpu.checker.dtb.inst_accesses                0                       # IT
 system.cpu.checker.dtb.hits                         0                       # DTB hits
 system.cpu.checker.dtb.misses                       0                       # DTB misses
 system.cpu.checker.dtb.accesses                     0                       # DTB accesses
-system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -356,7 +366,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.checker.itb.walker.walks                 0                       # Table walker walks requested
 system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -387,11 +397,11 @@ system.cpu.checker.itb.hits                         0                       # DT
 system.cpu.checker.itb.misses                       0                       # DTB misses
 system.cpu.checker.itb.accesses                     0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.checker.pwrStateResidencyTicks::ON     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.pwrStateResidencyTicks::ON     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.checker.numCycles                     5391                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -421,7 +431,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -451,7 +461,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -481,7 +491,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -511,237 +521,237 @@ system.cpu.itb.inst_accesses                        0                       # IT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.pwrStateResidencyTicks::ON        17458500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            34918                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        18422500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            36846                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               7601                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          12293                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2836                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1192                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4902                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.icacheStallCycles               7661                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12314                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2844                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1194                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          5108                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                     977                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           248                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles           260                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           17                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      1960                       # Number of cache lines fetched
+system.cpu.fetch.CacheLines                      1962                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   282                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13257                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.116542                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.478893                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              13535                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.094422                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.458272                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10565     79.69%     79.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      264      1.99%     81.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      184      1.39%     83.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      203      1.53%     84.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      282      2.13%     86.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      396      2.99%     89.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      139      1.05%     90.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      173      1.30%     92.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1051      7.93%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10839     80.08%     80.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      264      1.95%     82.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      185      1.37%     83.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      204      1.51%     84.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      283      2.09%     87.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      398      2.94%     89.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      139      1.03%     90.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      173      1.28%     92.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1050      7.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13257                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.081219                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.352053                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6292                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  4354                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2143                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   134                       # Number of cycles decode is unblocking
+system.cpu.fetch.rateDist::total                13535                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.077186                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.334202                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     6279                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  4644                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2146                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   132                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                    334                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  431                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   160                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  12137                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts                  12150                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   489                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    334                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     6521                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     773                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           2325                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2036                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1268                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11426                       # Number of instructions processed by rename
+system.cpu.rename.IdleCycles                     6511                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     826                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           2470                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2033                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1361                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11433                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     4                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                    168                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                    132                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                   1090                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               11634                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 52309                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            12345                       # Number of integer rename lookups
+system.cpu.rename.IQFullEvents                    178                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                    144                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                   1169                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               11641                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 52345                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            12355                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               199                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5494                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     6140                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     6147                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 40                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             34                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       441                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2200                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1540                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                32                       # Number of conflicting loads.
+system.cpu.rename.skidInsts                       446                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2197                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1543                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                33                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores               22                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      10163                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  43                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8100                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                40                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4828                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        12342                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved              6                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13257                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.610998                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.340069                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      10169                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  44                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                      8096                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                37                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            4835                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        12334                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved              7                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         13535                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.598153                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.329974                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10033     75.68%     75.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1170      8.83%     84.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 770      5.81%     90.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 479      3.61%     93.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 341      2.57%     96.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 274      2.07%     98.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 121      0.91%     99.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  59      0.45%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  10      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10320     76.25%     76.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1163      8.59%     84.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 763      5.64%     90.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 482      3.56%     94.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 344      2.54%     96.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 273      2.02%     98.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 120      0.89%     99.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  60      0.44%     99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  10      0.07%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13257                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13535                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       9      6.16%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     65     44.52%     50.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    72     49.32%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       9      6.12%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     66     44.90%     51.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    72     48.98%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5026     62.05%     62.05% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    7      0.09%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.14% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5023     62.04%     62.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    7      0.09%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     62.17% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.17% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.17% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1881     23.22%     85.40% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1183     14.60%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1876     23.17%     85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1187     14.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8100                       # Type of FU issued
-system.cpu.iq.rate                           0.231972                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         146                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.018025                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              29552                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             14921                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         7399                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   8096                       # Type of FU issued
+system.cpu.iq.rate                           0.219725                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         147                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.018157                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              29820                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             14935                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7404                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  91                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                132                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           32                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8203                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8200                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      43                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               23                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1173                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1170                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           19                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          602                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          605                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           31                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads           29                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             4                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles                    334                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     684                       # Number of cycles IEW is blocking
+system.cpu.iew.iewBlockCycles                     696                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    18                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10215                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               130                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2200                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1540                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 31                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispatchedInsts               10222                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               131                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2197                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1543                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 32                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                     13                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     4                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             19                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect             94                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          263                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  357                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  7807                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1773                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               293                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect          262                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  356                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  7806                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1768                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               290                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             9                       # number of nop insts executed
-system.cpu.iew.exec_refs                         2920                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1492                       # Number of branches executed
-system.cpu.iew.exec_stores                       1147                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.223581                       # Inst execution rate
-system.cpu.iew.wb_sent                           7528                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          7431                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      3502                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6830                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.212813                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.512738                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts            4836                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                         2921                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1491                       # Number of branches executed
+system.cpu.iew.exec_stores                       1153                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.211855                       # Inst execution rate
+system.cpu.iew.wb_sent                           7533                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7436                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      3503                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6835                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.201813                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.512509                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts            4843                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               310                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12404                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.433570                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.278209                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        12682                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.424066                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.266213                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        10353     83.47%     83.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          884      7.13%     90.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          420      3.39%     93.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          217      1.75%     95.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          107      0.86%     96.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          220      1.77%     98.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           55      0.44%     98.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           39      0.31%     99.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          109      0.88%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10636     83.87%     83.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          879      6.93%     90.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          416      3.28%     94.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          218      1.72%     95.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          111      0.88%     96.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          220      1.73%     98.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           54      0.43%     98.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           39      0.31%     99.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          109      0.86%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12404                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12682                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4592                       # Number of instructions committed
 system.cpu.commit.committedOps                   5378                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -788,52 +798,52 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5378                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   109                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        22352                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21294                       # The number of ROB writes
+system.cpu.rob.rob_reads                        22637                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21308                       # The number of ROB writes
 system.cpu.timesIdled                             191                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           21661                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           23311                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4592                       # Number of Instructions Simulated
 system.cpu.committedOps                          5378                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.604094                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.604094                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.131508                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.131508                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     7649                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    4266                       # number of integer regfile writes
+system.cpu.cpi                               8.023955                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         8.023955                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.124627                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.124627                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     7656                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    4268                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        32                       # number of floating regfile reads
 system.cpu.cc_regfile_reads                     27780                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                     3273                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                    2976                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                    2974                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            88.222961                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2096                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            88.014551                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2093                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               147                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             14.258503                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             14.238095                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    88.222961                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021539                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021539                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    88.014551                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021488                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021488                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          147                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035889                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5341                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5341                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data         1478                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1478                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              5335                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5335                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data         1475                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1475                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          597                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            597                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           10                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           10                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          2075                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2075                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2075                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2075                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          2072                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2072                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2072                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2072                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          183                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           183                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          316                       # number of WriteReq misses
@@ -844,53 +854,53 @@ system.cpu.dcache.demand_misses::cpu.data          499                       # n
 system.cpu.dcache.demand_misses::total            499                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          499                       # number of overall misses
 system.cpu.dcache.overall_misses::total           499                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     10847000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     10847000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     22859500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     22859500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       144000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       144000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     33706500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     33706500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     33706500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     33706500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1661                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1661                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11345000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11345000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     24463500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     24463500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       156000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       156000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     35808500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     35808500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     35808500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     35808500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1658                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1658                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           12                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           12                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2574                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2574                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2574                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2574                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.110175                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.110175                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2571                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2571                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2571                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2571                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.110374                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.110374                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.346112                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.346112                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.166667                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.166667                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.193862                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.193862                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.193862                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.193862                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59273.224044                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 59273.224044                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72340.189873                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72340.189873                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        72000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        72000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 67548.096192                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67548.096192                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67548.096192                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67548.096192                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          147                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.194088                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.194088                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.194088                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.194088                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61994.535519                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 61994.535519                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77416.139241                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 77416.139241                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        78000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        78000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 71760.521042                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 71760.521042                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 71760.521042                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 71760.521042                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          159                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           49                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs           53                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           78                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           78                       # number of ReadReq MSHR hits
@@ -910,140 +920,140 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          147
 system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7089000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7089000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3440000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3440000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10529000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10529000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10529000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10529000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.063215                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.063215                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7355500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7355500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3668000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3668000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11023500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     11023500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11023500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     11023500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.063329                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.063329                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046002                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057110                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.057110                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.057110                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.057110                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67514.285714                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67514.285714                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81904.761905                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81904.761905                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71625.850340                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71625.850340                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71625.850340                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71625.850340                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057176                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.057176                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.057176                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.057176                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70052.380952                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70052.380952                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74989.795918                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74989.795918                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74989.795918                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74989.795918                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 2                       # number of replacements
-system.cpu.icache.tags.tagsinuse           149.958367                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1576                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           149.507349                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1577                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               294                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.360544                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.363946                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   149.958367                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.073222                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.073222                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   149.507349                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.073002                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.073002                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          292                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          166                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          126                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.142578                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4214                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4214                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         1576                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1576                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1576                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1576                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1576                       # number of overall hits
-system.cpu.icache.overall_hits::total            1576                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          384                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           384                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          384                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            384                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          384                       # number of overall misses
-system.cpu.icache.overall_misses::total           384                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     27225000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     27225000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     27225000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     27225000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     27225000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     27225000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1960                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1960                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1960                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1960                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1960                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1960                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.195918                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.195918                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.195918                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.195918                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.195918                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.195918                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70898.437500                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70898.437500                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70898.437500                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70898.437500                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70898.437500                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70898.437500                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          433                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses              4218                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4218                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst         1577                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1577                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1577                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1577                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1577                       # number of overall hits
+system.cpu.icache.overall_hits::total            1577                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          385                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           385                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          385                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            385                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          385                       # number of overall misses
+system.cpu.icache.overall_misses::total           385                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     28997500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     28997500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     28997500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     28997500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     28997500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     28997500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1962                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1962                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1962                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1962                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1962                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1962                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.196228                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.196228                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.196228                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.196228                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.196228                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.196228                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75318.181818                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 75318.181818                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 75318.181818                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 75318.181818                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 75318.181818                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 75318.181818                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          493                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    86.600000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    98.600000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.writebacks::writebacks            2                       # number of writebacks
 system.cpu.icache.writebacks::total                 2                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           90                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           90                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           90                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           90                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           90                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           90                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           91                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           91                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           91                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           91                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           91                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           91                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          294                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          294                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          294                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          294                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          294                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          294                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22193500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22193500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22193500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22193500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22193500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22193500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.150000                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.150000                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.150000                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.150000                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.150000                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.150000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75488.095238                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75488.095238                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75488.095238                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75488.095238                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75488.095238                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75488.095238                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23482000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     23482000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23482000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     23482000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23482000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     23482000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.149847                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.149847                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.149847                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.149847                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.149847                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.149847                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79870.748299                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79870.748299                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79870.748299                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 79870.748299                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79870.748299                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 79870.748299                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          215.001500                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          214.408451                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 39                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              397                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.098237                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   140.723037                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    74.278463                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004295                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.002267                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006561                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   140.281348                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    74.127103                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004281                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.002262                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006543                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          397                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          200                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          195                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          202                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012115                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3933                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3933                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackClean_hits::writebacks            1                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total            1                       # number of WritebackClean hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           18                       # number of ReadCleanReq hits
@@ -1068,18 +1078,18 @@ system.cpu.l2cache.demand_misses::total           403                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          276                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          127                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          403                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3375000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3375000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     21544500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     21544500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      6694500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      6694500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     21544500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10069500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     31614000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     21544500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10069500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     31614000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3603000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3603000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     22833000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     22833000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      6961000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      6961000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     22833000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10564000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     33397000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     22833000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10564000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     33397000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackClean_accesses::writebacks            1                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total            1                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           42                       # number of ReadExReq accesses(hits+misses)
@@ -1106,18 +1116,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.913832                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.938776                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.863946                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.913832                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80357.142857                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80357.142857                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78059.782609                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78059.782609                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78758.823529                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78758.823529                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78059.782609                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79287.401575                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78446.650124                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78059.782609                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79287.401575                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78446.650124                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82728.260870                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82728.260870                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81894.117647                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81894.117647                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82728.260870                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83181.102362                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82870.967742                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82728.260870                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83181.102362                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82870.967742                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1142,18 +1152,18 @@ system.cpu.l2cache.demand_mshr_misses::total          397
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          276                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          121                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          397                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2955000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2955000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     18784500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     18784500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5499000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      5499000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18784500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8454000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     27238500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18784500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8454000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     27238500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3183000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3183000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     20073000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     20073000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5729500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      5729500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     20073000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8912500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     28985500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     20073000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8912500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     28985500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.938776                       # mshr miss rate for ReadCleanReq accesses
@@ -1166,25 +1176,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.900227
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.938776                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.823129                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.900227                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70357.142857                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70357.142857                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68059.782609                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68059.782609                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69607.594937                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69607.594937                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68059.782609                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69867.768595                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68610.831234                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68059.782609                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69867.768595                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68610.831234                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72728.260870                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72728.260870                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72525.316456                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72525.316456                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72728.260870                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73657.024793                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73011.335013                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72728.260870                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73657.024793                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73011.335013                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests          443                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests           45                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           399                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           42                       # Transaction distribution
@@ -1211,18 +1221,18 @@ system.cpu.toL2Bus.snoop_fanout::min_value            0                       #
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::total            441                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         223500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
+system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        441000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization          2.4                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        223494                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
 system.membus.snoop_filter.tot_requests           397                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     17458500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     18422500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                355                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                42                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               42                       # Transaction distribution
@@ -1243,9 +1253,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 397                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              488000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2102000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             12.0                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              486500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.6                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2098750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             11.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index 9180fbc8c..4a82d75c8 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -172,7 +172,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -534,7 +534,7 @@ pipelined=true
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=prefetcher tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
@@ -813,6 +813,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -824,7 +825,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -832,29 +833,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -874,6 +882,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -905,9 +914,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
index 9e032676c..81299f400 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:10:34
-gem5 executing on e108600-lin, pid 12211
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:52:56
+gem5 executing on e108600-lin, pid 17478
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 18821000 because target called exit()
+Exiting @ tick 20299000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index bfd96912f..867d50715 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,39 +1,39 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000019                       # Number of seconds simulated
-sim_ticks                                    19046000                       # Number of ticks simulated
-final_tick                                   19046000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000020                       # Number of seconds simulated
+sim_ticks                                    20299000                       # Number of ticks simulated
+final_tick                                   20299000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  51970                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60857                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              215490046                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 266056                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  44590                       # Simulator instruction rate (inst/s)
+host_op_rate                                    52212                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              197038809                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265156                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             18560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.l2cache.prefetcher         1728                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                28480                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                28416                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        18560                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           18560                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu.inst                290                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                128                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                127                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.l2cache.prefetcher           27                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   445                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            974482831                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            430116560                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     90727712                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1495327103                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       974482831                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          974482831                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           974482831                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           430116560                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     90727712                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1495327103                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total                   444                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            914330755                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            400413813                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     85127346                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1399871915                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       914330755                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          914330755                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           914330755                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           400413813                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     85127346                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1399871915                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           445                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         445                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -80,7 +80,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        19004500                       # Total gap between requests
+system.physmem.totGap                        20257500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -95,12 +95,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       246                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       132                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       241                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       137                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        36                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        16                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         2                       # What read queue length does an incoming req see
@@ -191,86 +191,96 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           63                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      429.714286                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     289.613657                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     357.341954                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127              8     12.70%     12.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           17     26.98%     39.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           11     17.46%     57.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            6      9.52%     66.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            3      4.76%     71.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      3.17%     74.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      3.17%     77.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      3.17%     80.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           12     19.05%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             63                       # Bytes accessed per row activation
-system.physmem.totQLat                        4296708                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  12640458                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           62                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      435.612903                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     295.342416                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     353.563376                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127              8     12.90%     12.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           16     25.81%     38.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           10     16.13%     54.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            7     11.29%     66.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      3.23%     69.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      4.84%     74.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      3.23%     77.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            4      6.45%     83.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     16.13%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             62                       # Bytes accessed per row activation
+system.physmem.totQLat                        6110750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  14454500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2225000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9655.52                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       13732.02                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28405.52                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1495.33                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32482.02                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1403.02                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1495.33                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1403.02                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.68                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.68                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.96                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.96                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.86                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.84                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        373                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.82                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        42706.74                       # Average gap between requests
+system.physmem.avgGap                        45522.47                       # Average gap between requests
 system.physmem.pageHitRate                      83.82                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     287280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     156750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2152800                       # Energy for read commands per rank (pJ)
+system.physmem_0.actEnergy                     349860                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     170775                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2334780                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10689210                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                 123000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 14426160                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              911.173851                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         148750                       # Time in different power states
+system.physmem_0.refreshEnergy           1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                3572760                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  28800                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy           5648700                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy               960                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                 13335915                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              656.941626                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime               12232500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE          19000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        15177500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     128520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                      70125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                    811200                       # Energy for read commands per rank (pJ)
+system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN         2500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT         7376750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     12380750                       # Time in different power states
+system.physmem_1.actEnergy                     164220                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                      64515                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                    842520                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10733670                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                  84000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 12844635                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              811.282804                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        1145250                       # Time in different power states
+system.physmem_1.refreshEnergy           1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                1468320                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                  69120                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy           7424250                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy            237600                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                 11499825                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              566.493842                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime               16895250                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE         110000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        15228250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    2439                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1443                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               524                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                  915                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     448                       # Number of BTB hits
+system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN       618500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         2773750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN     16276750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                    2441                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1444                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               522                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                  916                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     449                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             48.961749                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             49.017467                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     286                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 57                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups             163                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits                 13                       # Number of indirect target hits.
 system.cpu.branchPred.indirectMisses              150                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted           60                       # Number of mispredicted indirect branches.
+system.cpu.branchPredindirectMispredicted           59                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -300,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -330,7 +340,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -360,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -391,85 +401,85 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        19046000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            38093                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        20299000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            40599                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               6117                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles               6170                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                          11468                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2439                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                747                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          8723                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1091                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  171                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           274                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          416                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.Branches                        2441                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                748                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          8322                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1087                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  161                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           286                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          434                       # Number of stall cycles due to full MSHR
 system.cpu.fetch.CacheLines                      3907                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   178                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              16246                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.839530                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.200509                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheSquashes                   179                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              15916                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.856748                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.206522                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9855     60.66%     60.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     2507     15.43%     76.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      520      3.20%     79.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                     3364     20.71%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9525     59.85%     59.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     2508     15.76%     75.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      521      3.27%     78.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                     3362     21.12%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                16246                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.064028                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.301053                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     5842                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  4705                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      5178                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   135                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    386                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  375                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total                15916                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.060125                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.282470                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     5812                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  4409                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      5179                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   132                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    384                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  374                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   162                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  10177                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  1679                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    386                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     6957                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    1136                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           2347                       # count of cycles rename stalled for serializing inst
+system.cpu.decode.DecodedInsts                  10178                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  1683                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    384                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     6925                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    1165                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           2515                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                      4188                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1232                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                   9097                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                   461                       # Number of squashed instructions processed by rename
+system.cpu.rename.UnblockCycles                   739                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                   9100                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                   467                       # Number of squashed instructions processed by rename
 system.cpu.rename.ROBFullEvents                    24                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                      1                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LQFullEvents                     28                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                   1125                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands                9457                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 41127                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups             9997                       # Number of integer rename lookups
+system.cpu.rename.SQFullEvents                    631                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands                9458                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 41150                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            10006                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                17                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5494                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     3963                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     3964                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 29                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             27                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       333                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 1824                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1284                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                       330                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 1823                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1289                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       8515                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                       8513                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  38                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      7229                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               177                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            3175                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqInstsIssued                      7228                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               182                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            3173                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined         8254                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              1                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         16246                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.444971                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.838160                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         15916                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.454134                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.844472                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               11980     73.74%     73.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1997     12.29%     86.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1618      9.96%     95.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 608      3.74%     99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                  43      0.26%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               11653     73.22%     73.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1992     12.52%     85.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1620     10.18%     95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 608      3.82%     99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                  43      0.27%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -477,147 +487,147 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            4                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           16246                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           15916                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     416     28.89%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    475     32.99%     61.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                   549     38.12%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     416     28.85%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    475     32.94%     61.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                   551     38.21%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  4534     62.72%     62.72% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    5      0.07%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4533     62.71%     62.71% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    5      0.07%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.78% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     62.83% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.83% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.83% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1606     22.22%     85.05% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1081     14.95%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1605     22.21%     85.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1082     14.97%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   7229                       # Type of FU issued
-system.cpu.iq.rate                           0.189772                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                        1440                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.199198                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              32277                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             11719                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         6614                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   7228                       # Type of FU issued
+system.cpu.iq.rate                           0.178034                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                        1442                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.199502                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              31952                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             11715                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         6617                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  44                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8641                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8642                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      28                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               12                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads          797                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads          796                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          346                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          351                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            7                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            18                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    386                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     339                       # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles                    384                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     345                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    11                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts                8566                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts                8564                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  1824                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1284                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts                  1823                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1289                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 26                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     6                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             59                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          319                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect             60                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          318                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                  378                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  6820                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1423                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               409                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts                  6821                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1422                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               407                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                            13                       # number of nop insts executed
-system.cpu.iew.exec_refs                         2448                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1296                       # Number of branches executed
+system.cpu.iew.exec_refs                         2447                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1298                       # Number of branches executed
 system.cpu.iew.exec_stores                       1025                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.179036                       # Inst execution rate
-system.cpu.iew.wb_sent                           6675                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          6630                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      2985                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      5422                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.174048                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.550535                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts            2710                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_rate                     0.168009                       # Inst execution rate
+system.cpu.iew.wb_sent                           6677                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          6633                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      2981                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      5419                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.163378                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.550101                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts            2706                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               365                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        15677                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.343050                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     0.979995                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               363                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        15349                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.350381                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     0.988718                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        13011     82.99%     82.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1405      8.96%     91.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          598      3.81%     95.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          299      1.91%     97.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          169      1.08%     98.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           80      0.51%     99.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           44      0.28%     99.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           28      0.18%     99.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           43      0.27%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        12681     82.62%     82.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1407      9.17%     91.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          599      3.90%     95.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          298      1.94%     97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          170      1.11%     98.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           79      0.51%     99.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           44      0.29%     99.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           28      0.18%     99.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           43      0.28%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        15677                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        15349                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4592                       # Number of instructions committed
 system.cpu.commit.committedOps                   5378                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -664,40 +674,40 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5378                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                    43                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        23565                       # The number of ROB reads
-system.cpu.rob.rob_writes                       16751                       # The number of ROB writes
-system.cpu.timesIdled                             216                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           21847                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        23233                       # The number of ROB reads
+system.cpu.rob.rob_writes                       16740                       # The number of ROB writes
+system.cpu.timesIdled                             212                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           24683                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4592                       # Number of Instructions Simulated
 system.cpu.committedOps                          5378                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               8.295514                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         8.295514                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.120547                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.120547                       # IPC: Total IPC of All Threads
+system.cpu.cpi                               8.841246                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         8.841246                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.113106                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.113106                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                     6772                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    3788                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                     24217                       # number of cc regfile reads
+system.cpu.cc_regfile_reads                     24220                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                     2924                       # number of cc regfile writes
 system.cpu.misc_regfile_reads                    2559                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 1                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            84.349867                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            84.063183                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1930                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               143                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             13.496503                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    84.349867                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.164746                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.164746                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    84.063183                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.164186                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.164186                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          142                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.277344                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4725                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4725                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.tag_accesses              4723                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4723                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data         1188                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1188                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          722                       # number of WriteReq hits
@@ -710,76 +720,76 @@ system.cpu.dcache.demand_hits::cpu.data          1910                       # nu
 system.cpu.dcache.demand_hits::total             1910                       # number of demand (read+write) hits
 system.cpu.dcache.overall_hits::cpu.data         1910                       # number of overall hits
 system.cpu.dcache.overall_hits::total            1910                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          168                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           168                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data          167                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           167                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          191                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          191                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data          359                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            359                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          359                       # number of overall misses
-system.cpu.dcache.overall_misses::total           359                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     10937500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     10937500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      9601000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      9601000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       127000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       127000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     20538500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     20538500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     20538500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     20538500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1356                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1356                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          358                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            358                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          358                       # number of overall misses
+system.cpu.dcache.overall_misses::total           358                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     12032500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     12032500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      8019500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      8019500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       139000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       139000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     20052000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     20052000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     20052000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     20052000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1355                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1355                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2269                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2269                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2269                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2269                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.123894                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.123894                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2268                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2268                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2268                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2268                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.123247                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.123247                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.209200                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.209200                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.181818                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.181818                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.158219                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.158219                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.158219                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.158219                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65104.166667                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 65104.166667                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50267.015707                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 50267.015707                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        63500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        63500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 57210.306407                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 57210.306407                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 57210.306407                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 57210.306407                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.157848                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.157848                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.157848                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.157848                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72050.898204                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 72050.898204                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41986.910995                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41986.910995                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        69500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        69500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56011.173184                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56011.173184                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 56011.173184                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 56011.173184                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         1304                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          853                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              18                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    72.444444                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    47.388889                       # average number of cycles each access was blocked
 system.cpu.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu.dcache.writebacks::total                 1                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           65                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           65                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           64                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           64                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          150                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          150                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          215                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          215                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          215                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          215                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          214                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          214                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          214                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          214                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          103                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          103                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           41                       # number of WriteReq MSHR misses
@@ -788,140 +798,140 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          144
 system.cpu.dcache.demand_mshr_misses::total          144                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          144                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          144                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7149000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7149000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2700500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2700500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9849500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9849500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9849500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9849500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075959                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075959                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7984500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7984500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2595500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2595500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10580000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10580000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10580000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10580000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076015                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076015                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044907                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.044907                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063464                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.063464                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063464                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.063464                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69407.766990                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69407.766990                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65865.853659                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65865.853659                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68399.305556                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68399.305556                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68399.305556                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68399.305556                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063492                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.063492                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063492                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.063492                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77519.417476                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77519.417476                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63304.878049                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63304.878049                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73472.222222                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73472.222222                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73472.222222                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73472.222222                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                44                       # number of replacements
-system.cpu.icache.tags.tagsinuse           137.872552                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                3542                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           137.515573                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                3540                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               299                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             11.846154                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs             11.839465                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   137.872552                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.269282                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.269282                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   137.515573                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.268585                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.268585                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          255                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          110                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.498047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              8107                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             8107                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         3542                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            3542                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          3542                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             3542                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         3542                       # number of overall hits
-system.cpu.icache.overall_hits::total            3542                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          362                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           362                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          362                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            362                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          362                       # number of overall misses
-system.cpu.icache.overall_misses::total           362                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     22563992                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     22563992                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     22563992                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     22563992                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     22563992                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     22563992                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         3904                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         3904                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         3904                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         3904                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         3904                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         3904                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092725                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.092725                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.092725                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.092725                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.092725                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.092725                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62331.469613                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62331.469613                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62331.469613                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62331.469613                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62331.469613                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62331.469613                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         8558                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           35                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                95                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses              8109                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             8109                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst         3540                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            3540                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          3540                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             3540                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         3540                       # number of overall hits
+system.cpu.icache.overall_hits::total            3540                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          365                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           365                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          365                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            365                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          365                       # number of overall misses
+system.cpu.icache.overall_misses::total           365                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25051490                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25051490                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25051490                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25051490                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25051490                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25051490                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         3905                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         3905                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         3905                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         3905                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         3905                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         3905                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.093470                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.093470                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.093470                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.093470                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.093470                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.093470                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68634.219178                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68634.219178                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68634.219178                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68634.219178                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68634.219178                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68634.219178                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         9850                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           47                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                96                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    90.084211                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets           35                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs   102.604167                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           47                       # average number of cycles each access was blocked
 system.cpu.icache.writebacks::writebacks           44                       # number of writebacks
 system.cpu.icache.writebacks::total                44                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           63                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           63                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           63                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           63                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           63                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           63                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           66                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           66                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           66                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           66                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           66                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           66                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          299                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          299                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          299                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          299                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          299                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          299                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19836992                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     19836992                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19836992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     19836992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19836992                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     19836992                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.076588                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.076588                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.076588                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.076588                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.076588                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.076588                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66344.454849                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66344.454849                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66344.454849                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66344.454849                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66344.454849                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66344.454849                       # average overall mshr miss latency
-system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22011990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     22011990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22011990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     22011990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22011990                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     22011990                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.076569                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.076569                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.076569                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.076569                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.076569                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.076569                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73618.695652                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73618.695652                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73618.695652                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 73618.695652                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73618.695652                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 73618.695652                       # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.prefetcher.num_hwpf_issued          112                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified          112                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse           17.395386                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse           17.353048                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs               41                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.073171                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     9.233331                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher     8.162055                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000564                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.000498                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.001062                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks     9.225603                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher     8.127445                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000563                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.000496                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.001059                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1022           13                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
@@ -932,43 +942,43 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022     0.000793
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.001709                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             7676                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            7676                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackClean_hits::writebacks           33                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total           33                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data           10                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           10                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           11                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           11                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            8                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            8                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            8                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           10                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total              18                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           11                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total              19                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            8                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           10                       # number of overall hits
-system.cpu.l2cache.overall_hits::total             18                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data           31                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           31                       # number of ReadExReq misses
+system.cpu.l2cache.overall_hits::cpu.data           11                       # number of overall hits
+system.cpu.l2cache.overall_hits::total             19                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data           30                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           30                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          291                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total          291                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data          103                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total          103                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          291                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          134                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           425                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          133                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           424                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          291                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          134                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          425                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2572500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2572500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     19478500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     19478500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      6989500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      6989500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     19478500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9562000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     29040500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     19478500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9562000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     29040500                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::cpu.data          133                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          424                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2461000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2461000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     21652500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     21652500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7825000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      7825000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     21652500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10286000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     31938500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     21652500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10286000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     31938500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackClean_accesses::writebacks           33                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total           33                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           41                       # number of ReadExReq accesses(hits+misses)
@@ -983,48 +993,46 @@ system.cpu.l2cache.demand_accesses::total          443                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst          299                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          144                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          443                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.756098                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.756098                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.731707                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.731707                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.973244                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.973244                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.973244                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.930556                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.959368                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.923611                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.957111                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.973244                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.930556                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.959368                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82983.870968                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82983.870968                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 66936.426117                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 66936.426117                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 67859.223301                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 67859.223301                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66936.426117                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71358.208955                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68330.588235                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66936.426117                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71358.208955                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68330.588235                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.923611                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.957111                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82033.333333                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82033.333333                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74407.216495                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74407.216495                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75970.873786                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75970.873786                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74407.216495                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77338.345865                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75326.650943                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74407.216495                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77338.345865                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75326.650943                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            1                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total            1                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            5                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            6                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            7                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            5                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            6                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            7                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data            5                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
 system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher           53                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.HardPFReq_mshr_misses::total           53                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           30                       # number of ReadExReq MSHR misses
@@ -1040,21 +1048,21 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst          290
 system.cpu.l2cache.overall_mshr_misses::cpu.data          128                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher           53                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          471                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher      3053926                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total      3053926                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2154000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2154000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     17682000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     17682000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6104000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6104000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17682000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8258000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     25940000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17682000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8258000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher      3053926                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     28993926                       # number of overall MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher      1766926                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total      1766926                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2281000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2281000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19850000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19850000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6909500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6909500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19850000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9190500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     29040500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19850000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9190500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher      1766926                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     30807426                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.731707                       # mshr miss rate for ReadExReq accesses
@@ -1070,28 +1078,28 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.969900
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.888889                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     1.063205                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 57621.245283                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        71800                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        71800                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60972.413793                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60972.413793                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62285.714286                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62285.714286                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60972.413793                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64515.625000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62057.416268                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60972.413793                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64515.625000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61558.229299                       # average overall mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76033.333333                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76033.333333                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68448.275862                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68448.275862                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70505.102041                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70505.102041                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68448.275862                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71800.781250                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69474.880383                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68448.275862                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71800.781250                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65408.547771                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests          488                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests           74                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests           12                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops           26                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops           24                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            2                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           401                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean           45                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFReq           69                       # Transaction distribution
@@ -1119,9 +1127,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value            0                       #
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::total            512                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         289000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.5                       # Layer utilization (%)
+system.cpu.toL2Bus.reqLayer0.utilization          1.4                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        448999                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.4                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        216995                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
 system.membus.snoop_filter.tot_requests           445                       # Total number of requests made to the snoop filter.
@@ -1130,7 +1138,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     19046000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     20299000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                414                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                30                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               30                       # Transaction distribution
@@ -1151,9 +1159,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 445                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              562944                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               3.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2340257                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             12.3                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              564444                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2334750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             11.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index fb58e2bf8..1e3a930b1 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -593,7 +593,7 @@ size=64
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -710,6 +710,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -721,7 +722,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -729,29 +730,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -771,6 +779,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -780,7 +789,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -802,9 +811,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
index 8c26880d3..fa28c822f 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timin
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:23:13
-gem5 started Jul 21 2016 14:23:47
-gem5 executing on e108600-lin, pid 13281
+gem5 compiled Oct 13 2016 20:36:34
+gem5 started Oct 13 2016 20:36:59
+gem5 executing on e108600-lin, pid 36840
 command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/mips/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 22532000 because target called exit()
+Exiting @ tick 24405000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index fce732112..fb05a48a7 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000023                       # Number of seconds simulated
-sim_ticks                                    22838000                       # Number of ticks simulated
-final_tick                                   22838000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000024                       # Number of seconds simulated
+sim_ticks                                    24405000                       # Number of ticks simulated
+final_tick                                   24405000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  76246                       # Simulator instruction rate (inst/s)
-host_op_rate                                    76230                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              348191953                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252304                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                 101939                       # Simulator instruction rate (inst/s)
+host_op_rate                                   101907                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              497362491                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250452                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        4999                       # Number of instructions simulated
 sim_ops                                          4999                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     22838000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             21056                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8960                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                30016                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           21056                       # Nu
 system.physmem.num_reads::cpu.inst                329                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                140                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   469                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            921972152                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            392328575                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1314300727                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       921972152                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          921972152                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           921972152                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           392328575                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1314300727                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            862774022                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            367137882                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1229911903                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       862774022                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          862774022                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           862774022                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           367137882                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1229911903                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           469                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         469                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        22751500                       # Total gap between requests
+system.physmem.totGap                        24305500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,11 +91,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       276                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       130                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        41                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       270                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       135                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        40                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        17                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -187,83 +187,94 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          105                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      259.047619                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     178.738362                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     250.145511                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             30     28.57%     28.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           33     31.43%     60.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           19     18.10%     78.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            9      8.57%     86.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            4      3.81%     90.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      1.90%     92.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      1.90%     94.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            6      5.71%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            105                       # Bytes accessed per row activation
-system.physmem.totQLat                        4619250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13413000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          114                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      261.614035                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     175.762153                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     255.654479                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             36     31.58%     31.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           34     29.82%     61.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           19     16.67%     78.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            8      7.02%     85.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      3.51%     88.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      1.75%     90.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            4      3.51%     93.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      2.63%     96.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            4      3.51%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            114                       # Bytes accessed per row activation
+system.physmem.totQLat                        7578250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  16372000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2345000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9849.15                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       16158.32                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28599.15                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1314.30                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  34908.32                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1229.91                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1314.30                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1229.91                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.27                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.27                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           9.61                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       9.61                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.73                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.76                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        353                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        352                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.27                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   75.05                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        48510.66                       # Average gap between requests
-system.physmem.pageHitRate                      75.27                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     128520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                      70125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                    514800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        51824.09                       # Average gap between requests
+system.physmem.pageHitRate                      75.05                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     192780                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                      98670                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                    756840                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy                9522135                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                1146750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 12399450                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              783.164377                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE        1868000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        13458250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     521640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     284625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   2168400                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           1843920.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                1602840                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  46080                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy           8339100                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy            953280                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                 13833510                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              566.830977                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime               20709000                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE          23500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN      2481750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT         2828750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     18291000                       # Time in different power states
+system.physmem_1.actEnergy                     642600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     333960                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   2591820                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10729395                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                  87750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 14808930                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              935.350071                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         200750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        15221750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     22838000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    2189                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1457                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               425                       # Number of conditional branches incorrect
+system.physmem_1.refreshEnergy           1843920.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                4214580                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                  89760                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy           6593190                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy            180480                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                 16490310                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              675.693915                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime               14889250                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE         122500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN       470250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         8563750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN     14468500                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                    2188                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1456                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               424                       # Number of conditional branches incorrect
 system.cpu.branchPred.BTBLookups                 1784                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                     587                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct             32.903587                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     251                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.usedRAS                     252                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 70                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups             270                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits                  2                       # Number of indirect target hits.
 system.cpu.branchPred.indirectMisses              268                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted           96                       # Number of mispredicted indirect branches.
+system.cpu.branchPredindirectMispredicted           95                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
@@ -284,235 +295,235 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    7                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        22838000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            45677                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        24405000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            48811                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               9081                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          13012                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2189                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                840                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4774                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     870                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles               9089                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          13001                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2188                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                841                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          5447                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     868                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.PendingTrapStallCycles           205                       # Number of stall cycles due to pending traps
 system.cpu.fetch.CacheLines                      2050                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   263                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14495                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.897689                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.187204                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              15175                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.856738                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.144886                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11134     76.81%     76.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     1506     10.39%     87.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      111      0.77%     87.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      162      1.12%     89.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      279      1.92%     91.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      100      0.69%     91.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      142      0.98%     92.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      158      1.09%     93.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      903      6.23%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    11815     77.86%     77.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     1507      9.93%     87.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      111      0.73%     88.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      162      1.07%     89.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      279      1.84%     91.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      100      0.66%     92.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      140      0.92%     93.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      158      1.04%     94.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      903      5.95%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14495                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.047923                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.284870                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8449                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  2734                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2777                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   140                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    395                       # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total                15175                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.044826                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.266354                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8420                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  3451                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2768                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   142                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    394                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  183                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                    40                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  12026                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts                  12000                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   160                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    395                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8600                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     597                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            983                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2748                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1172                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11590                       # Number of instructions processed by rename
+system.cpu.rename.SquashCycles                    394                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8571                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     621                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1023                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2740                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1826                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11562                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     5                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                      4                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                    177                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                    968                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands                6955                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 13597                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            13364                       # Number of integer rename lookups
+system.cpu.rename.LQFullEvents                    193                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                   1606                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands                6927                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 13556                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            13323                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 3                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  3292                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     3663                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     3635                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 13                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts              9                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       307                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2472                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1158                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                       323                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2470                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1160                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 6                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                2                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       9034                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  10                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8125                       # Number of instructions issued
+system.cpu.iq.iqInstsAdded                       9019                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  11                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                      8119                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                19                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4044                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         2026                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved              1                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14495                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.560538                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.289389                       # Number of insts issued each cycle
+system.cpu.iq.iqSquashedInstsExamined            4030                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         2019                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         15175                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.535025                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.265920                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               11167     77.04%     77.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1340      9.24%     86.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 721      4.97%     91.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 460      3.17%     94.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 343      2.37%     96.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 283      1.95%     98.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 110      0.76%     99.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  52      0.36%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               11852     78.10%     78.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1334      8.79%     86.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 728      4.80%     91.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 454      2.99%     94.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 341      2.25%     96.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 284      1.87%     98.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 110      0.72%     99.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  53      0.35%     99.87% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  19      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14495                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           15175                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       7      3.87%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    117     64.64%     68.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    57     31.49%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       6      3.33%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    117     65.00%     68.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    57     31.67%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  4784     58.88%     58.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    4      0.05%     58.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     1      0.01%     58.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2273     27.98%     86.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1061     13.06%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4775     58.81%     58.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    4      0.05%     58.86% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     1      0.01%     58.87% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     58.90% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2274     28.01%     86.91% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1063     13.09%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8125                       # Type of FU issued
-system.cpu.iq.rate                           0.177879                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         181                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.022277                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              30941                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             13095                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         7347                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   8119                       # Type of FU issued
+system.cpu.iq.rate                           0.166335                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         180                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.022170                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              31608                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             13067                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7338                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  2                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8304                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8297                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       2                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               78                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1337                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1335                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            5                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           10                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          257                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          259                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            25                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    395                       # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles                    394                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                     491                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    59                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10646                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               156                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2472                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1158                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 10                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewUnblockCycles                    74                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10629                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               154                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2470                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1160                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 11                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    59                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    75                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             10                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect            101                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          339                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  440                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  7799                       # Number of executed instructions
+system.cpu.iew.predictedNotTakenIncorrect          338                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  439                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  7792                       # Number of executed instructions
 system.cpu.iew.iewExecLoadInsts                  2130                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               326                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts               327                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1602                       # number of nop insts executed
+system.cpu.iew.exec_nop                          1599                       # number of nop insts executed
 system.cpu.iew.exec_refs                         3179                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1368                       # Number of branches executed
+system.cpu.iew.exec_branches                     1364                       # Number of branches executed
 system.cpu.iew.exec_stores                       1049                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.170742                       # Inst execution rate
-system.cpu.iew.wb_sent                           7444                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          7349                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      2873                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      4285                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.160891                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.670478                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts            4999                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_rate                     0.159636                       # Inst execution rate
+system.cpu.iew.wb_sent                           7433                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7340                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      2867                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      4275                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.150376                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.670643                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts            4990                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls               9                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               385                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13612                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.414340                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.226502                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               384                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        14293                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.394599                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.198950                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11422     83.91%     83.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          884      6.49%     90.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          520      3.82%     94.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          254      1.87%     96.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          161      1.18%     97.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          165      1.21%     98.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           61      0.45%     98.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           41      0.30%     99.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          104      0.76%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        12101     84.66%     84.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          885      6.19%     90.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          521      3.65%     94.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          254      1.78%     96.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          160      1.12%     97.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          166      1.16%     98.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           63      0.44%     99.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           41      0.29%     99.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          102      0.71%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13612                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        14293                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5640                       # Number of instructions committed
 system.cpu.commit.committedOps                   5640                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -558,63 +569,63 @@ system.cpu.commit.op_class_0::MemWrite            901     15.98%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5640                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   104                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        24134                       # The number of ROB reads
-system.cpu.rob.rob_writes                       22169                       # The number of ROB writes
+system.cpu.commit.bw_lim_events                   102                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        24808                       # The number of ROB reads
+system.cpu.rob.rob_writes                       22150                       # The number of ROB writes
 system.cpu.timesIdled                             264                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           31182                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           33636                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4999                       # Number of Instructions Simulated
 system.cpu.committedOps                          4999                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               9.137227                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         9.137227                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.109442                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.109442                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    10569                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    5149                       # number of integer regfile writes
+system.cpu.cpi                               9.764153                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         9.764153                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.102415                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.102415                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    10563                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    5141                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                     160                       # number of misc regfile reads
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     22838000                       # Cumulative time (in ticks) in various power states
+system.cpu.misc_regfile_reads                     161                       # number of misc regfile reads
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            90.737808                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2395                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            91.114118                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2396                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               140                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             17.107143                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             17.114286                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    90.737808                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.022153                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.022153                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    91.114118                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.022245                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.022245                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          140                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           34                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          106                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          109                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.034180                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              5954                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             5954                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     22838000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data         1839                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1839                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          556                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            556                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2395                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2395                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2395                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2395                       # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data          557                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            557                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2396                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2396                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2396                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2396                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          167                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           167                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          345                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          345                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          512                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            512                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          512                       # number of overall misses
-system.cpu.dcache.overall_misses::total           512                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     12256500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     12256500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     24340499                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     24340499                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     36596999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     36596999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     36596999                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     36596999                       # number of overall miss cycles
+system.cpu.dcache.WriteReq_misses::cpu.data          344                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          344                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          511                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            511                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          511                       # number of overall misses
+system.cpu.dcache.overall_misses::total           511                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     12711500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     12711500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     34219499                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     34219499                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     46930999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     46930999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     46930999                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     46930999                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         2006                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         2006                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
@@ -625,34 +636,34 @@ system.cpu.dcache.overall_accesses::cpu.data         2907
 system.cpu.dcache.overall_accesses::total         2907                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.083250                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.083250                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.382908                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.382908                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.176127                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.176127                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.176127                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.176127                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73392.215569                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 73392.215569                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70552.171014                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70552.171014                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 71478.513672                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 71478.513672                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 71478.513672                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 71478.513672                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          600                       # number of cycles access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.381798                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.381798                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.175783                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.175783                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.175783                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.175783                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76116.766467                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 76116.766467                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 99475.287791                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 91841.485323                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 91841.485323                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 91841.485323                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 91841.485323                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          636                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                10                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           60                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    63.600000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           77                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          295                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          295                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          372                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          372                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          372                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          372                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          294                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          294                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          371                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          371                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          371                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          371                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           90                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           90                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
@@ -661,14 +672,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          140
 system.cpu.dcache.demand_mshr_misses::total          140                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          140                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          140                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7898000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7898000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4132999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4132999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12030999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12030999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12030999                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12030999                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8095000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      8095000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4915999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4915999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13010999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     13010999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13010999                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     13010999                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.044865                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.044865                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
@@ -677,67 +688,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.048160
 system.cpu.dcache.demand_mshr_miss_rate::total     0.048160                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.048160                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.048160                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87755.555556                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87755.555556                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82659.980000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82659.980000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85935.707143                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 85935.707143                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85935.707143                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 85935.707143                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     22838000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89944.444444                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89944.444444                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98319.980000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92935.707143                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 92935.707143                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92935.707143                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 92935.707143                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                17                       # number of replacements
-system.cpu.icache.tags.tagsinuse           158.952170                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1612                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           160.115290                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1613                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               332                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              4.855422                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              4.858434                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   158.952170                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.077613                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.077613                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   160.115290                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.078181                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.078181                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          315                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          141                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          174                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          183                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.153809                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses              4432                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses             4432                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     22838000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         1612                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1612                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1612                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1612                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1612                       # number of overall hits
-system.cpu.icache.overall_hits::total            1612                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          438                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           438                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          438                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            438                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          438                       # number of overall misses
-system.cpu.icache.overall_misses::total           438                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     33275000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     33275000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     33275000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     33275000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     33275000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     33275000                       # number of overall miss cycles
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst         1613                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1613                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1613                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1613                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1613                       # number of overall hits
+system.cpu.icache.overall_hits::total            1613                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          437                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           437                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          437                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            437                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          437                       # number of overall misses
+system.cpu.icache.overall_misses::total           437                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     35529000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     35529000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     35529000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     35529000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     35529000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     35529000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         2050                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         2050                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         2050                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::total         2050                       # number of demand (read+write) accesses
 system.cpu.icache.overall_accesses::cpu.inst         2050                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         2050                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.213659                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.213659                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.213659                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.213659                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.213659                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.213659                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75970.319635                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75970.319635                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75970.319635                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75970.319635                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75970.319635                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75970.319635                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.213171                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.213171                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.213171                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.213171                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.213171                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.213171                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81302.059497                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 81302.059497                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 81302.059497                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 81302.059497                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 81302.059497                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 81302.059497                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -746,55 +757,55 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.writebacks::writebacks           17                       # number of writebacks
 system.cpu.icache.writebacks::total                17                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          106                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          106                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          106                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          106                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          106                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          106                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          105                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          105                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          105                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          105                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          105                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          105                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          332                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          332                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          332                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          332                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          332                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          332                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26133000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     26133000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26133000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     26133000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26133000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     26133000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     28113000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     28113000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     28113000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     28113000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     28113000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     28113000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.161951                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.161951                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.161951                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.161951                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.161951                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.161951                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78713.855422                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78713.855422                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78713.855422                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 78713.855422                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78713.855422                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 78713.855422                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     22838000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84677.710843                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84677.710843                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84677.710843                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 84677.710843                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84677.710843                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 84677.710843                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          251.694203                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          253.317608                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 20                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              469                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.042644                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.892029                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    90.802174                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004910                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.002771                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.007681                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   162.143256                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    91.174352                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004948                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.002782                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.007731                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          469                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          171                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          298                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.014313                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4381                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4381                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     22838000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackClean_hits::writebacks           17                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total           17                       # number of WritebackClean hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            3                       # number of ReadCleanReq hits
@@ -815,18 +826,18 @@ system.cpu.l2cache.demand_misses::total           469                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          329                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          140                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          469                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4057000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4057000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25602000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     25602000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7760000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      7760000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     25602000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     11817000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     37419000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     25602000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     11817000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     37419000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4840000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4840000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     27582000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     27582000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7957000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      7957000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     27582000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     12797000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     40379000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     27582000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     12797000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     40379000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackClean_accesses::writebacks           17                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total           17                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           50                       # number of ReadExReq accesses(hits+misses)
@@ -853,18 +864,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.993644                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.990964                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.993644                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        81140                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        81140                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77817.629179                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77817.629179                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86222.222222                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86222.222222                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77817.629179                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84407.142857                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79784.648188                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77817.629179                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84407.142857                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79784.648188                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        96800                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        96800                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83835.866261                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83835.866261                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88411.111111                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88411.111111                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83835.866261                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91407.142857                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 86095.948827                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83835.866261                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91407.142857                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 86095.948827                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -883,18 +894,18 @@ system.cpu.l2cache.demand_mshr_misses::total          469
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          329                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          140                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          469                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3557000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3557000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22312000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22312000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6860000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6860000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22312000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10417000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     32729000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22312000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10417000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     32729000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4340000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4340000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     24292000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     24292000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7057000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      7057000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24292000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11397000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     35689000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24292000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11397000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     35689000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.990964                       # mshr miss rate for ReadCleanReq accesses
@@ -907,25 +918,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.993644
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.990964                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.993644                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        71140                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        71140                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67817.629179                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67817.629179                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76222.222222                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76222.222222                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67817.629179                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74407.142857                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69784.648188                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67817.629179                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74407.142857                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69784.648188                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        86800                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        86800                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73835.866261                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73835.866261                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78411.111111                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78411.111111                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73835.866261                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81407.142857                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76095.948827                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73835.866261                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81407.142857                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76095.948827                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests          489                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests           17                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     22838000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           422                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           50                       # Transaction distribution
@@ -954,7 +965,7 @@ system.cpu.toL2Bus.snoop_fanout::total            472                       # Re
 system.cpu.toL2Bus.reqLayer0.occupancy         261500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        498000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        210000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
 system.membus.snoop_filter.tot_requests           469                       # Total number of requests made to the snoop filter.
@@ -963,7 +974,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     22838000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                419                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
@@ -985,8 +996,8 @@ system.membus.snoop_fanout::min_value               0                       # Re
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 469                       # Request fanout histogram
 system.membus.reqLayer0.occupancy              581500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2494250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             10.9                       # Layer utilization (%)
+system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2488500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             10.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index ff42947ce..ff37cda83 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -124,7 +134,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -147,27 +157,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -179,6 +189,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -186,12 +197,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -213,9 +229,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -229,12 +245,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -251,6 +272,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
@@ -258,6 +280,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
 eventq_index=0
 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestToDir=system.ruby.dir_cntrl0.requestToDir
 responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -331,11 +357,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 forwardToCache=system.ruby.l1_cntrl0.forwardToCache
 issue_latency=2
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestFromCache=system.ruby.l1_cntrl0.requestFromCache
 responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -417,17 +448,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.cacheMemory
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.cacheMemory
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
@@ -440,18 +476,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
 netifs=
 number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
 ruby_system=system.ruby
 topology=Crossbar
@@ -618,32 +659,206 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14
+power_model=Null
 router_id=0
 virt_nets=5
 
@@ -756,8 +971,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14
+power_model=Null
 router_id=1
 virt_nets=5
 
@@ -870,8 +1091,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19
+power_model=Null
 router_id=2
 virt_nets=5
 
@@ -1018,9 +1245,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
index 735671e5f..2e6bde8a3 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 14 2016 22:04:10
-gem5 started Mar 14 2016 22:06:34
-gem5 executing on phenom, pid 29860
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
+gem5 compiled Oct 13 2016 20:36:34
+gem5 started Oct 13 2016 20:36:59
+gem5 executing on e108600-lin, pid 36842
+command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/mips/linux/simple-timing-ruby
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 100232 because target called exit()
+Exiting @ tick 106125 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 5b0097850..d2ad37c0f 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000100                       # Number of seconds simulated
-sim_ticks                                      100232                       # Number of ticks simulated
-final_tick                                     100232                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000106                       # Number of seconds simulated
+sim_ticks                                      106125                       # Number of ticks simulated
+final_tick                                     106125                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  93908                       # Simulator instruction rate (inst/s)
-host_op_rate                                    93894                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1668107                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 455812                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  64036                       # Simulator instruction rate (inst/s)
+host_op_rate                                    64023                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1204237                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 413260                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED       100232                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED       106125                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        94208                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              94208                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0        93952                       # Number of bytes written to this memory
@@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1472                       #
 system.mem_ctrls.num_reads::total                1472                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0         1468                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total               1468                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    939899433                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             939899433                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    937345359                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            937345359                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   1877244792                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1877244792                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    887707892                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             887707892                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    885295642                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            885295642                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   1773003534                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1773003534                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1472                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                       1468                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1472                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                     1468                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  58752                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   35456                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   60352                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  58880                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   35328                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   59776                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   94208                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                93952                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    554                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   502                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    552                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   510                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0                33                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0                31                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::4                 7                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                 3                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                13                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7                81                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7                83                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::8                66                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9               245                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               98                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11               45                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12              114                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13               45                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14              154                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15               14                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0                34                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9               250                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10              100                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11               44                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12              107                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13               46                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14              157                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15               13                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0                32                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::4                 7                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::5                 3                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                13                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7                74                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7                75                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::8                60                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9               247                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9               250                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::10              100                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11               46                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12              118                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               49                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14              178                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11               45                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12              110                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               48                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14              177                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15               14                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        100183                       # Total gap between requests
+system.mem_ctrls.totGap                        106076                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                 1468                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     918                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                     920                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -136,25 +136,25 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      8                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     50                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                     60                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      8                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                     11                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     51                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                     61                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::19                     60                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     67                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                     61                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::21                     61                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     59                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     58                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     58                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     59                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                     57                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
@@ -185,90 +185,101 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          336                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    348.571429                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   224.382213                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   328.447975                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           77     22.92%     22.92% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255          103     30.65%     53.57% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           48     14.29%     67.86% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           26      7.74%     75.60% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           11      3.27%     78.87% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            8      2.38%     81.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895           13      3.87%     85.12% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            7      2.08%     87.20% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           43     12.80%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          336                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples           58                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      15.706897                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     15.549891                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      2.720995                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13             5      8.62%      8.62% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15            26     44.83%     53.45% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            25     43.10%     96.55% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             1      1.72%     98.28% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35             1      1.72%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total            58                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples           58                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.258621                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.240724                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.806995                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               52     89.66%     89.66% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                4      6.90%     96.55% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                1      1.72%     98.28% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20                1      1.72%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total            58                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                        12638                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   30080                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       4590                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        13.77                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples          352                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    334.181818                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   220.342342                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   312.466834                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           73     20.74%     20.74% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255          116     32.95%     53.69% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           49     13.92%     67.61% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           31      8.81%     76.42% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           18      5.11%     81.53% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767           13      3.69%     85.23% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            9      2.56%     87.78% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            3      0.85%     88.64% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           40     11.36%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          352                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples           57                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean             16                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     15.842454                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      2.738613                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13             2      3.51%      3.51% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15            25     43.86%     47.37% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17            25     43.86%     91.23% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19             4      7.02%     98.25% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35             1      1.75%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total            57                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples           57                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.385965                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.360622                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.959062                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               48     84.21%     84.21% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                1      1.75%     85.96% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                4      7.02%     92.98% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19                3      5.26%     98.25% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20                1      1.75%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total            57                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                        18473                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   35953                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       4600                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        20.08                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   32.77                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       586.16                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       602.12                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    939.90                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    937.35                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   39.08                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       554.82                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       563.26                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    887.71                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    885.30                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         9.28                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.58                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    4.70                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         8.73                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     4.33                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    4.40                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      25.54                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      642                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     873                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 69.93                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                90.37                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         34.08                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    80.41                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   491400                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   273000                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 1547520                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                1099008                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              6102720                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             55680336                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy              7372800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               72566784                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            774.524869                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        11950                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF          3120                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         78690                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                  1882440                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                  1045800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 9247680                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                7993728                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              6102720                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             63740592                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy               302400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               90315360                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            963.960210                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE          182                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          3120                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         90404                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED       100232                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.avgWrQLen                      25.41                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      632                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     865                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 68.70                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                90.29                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         36.08                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    79.71                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   542640                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   289800                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 1565088                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                1085760                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         8604960.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             15123696                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy               297600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        24352224                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy         7106304                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy     647736.000000                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               59655384                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            562.123760                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                71087                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE          340                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          3646                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF          185                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN        18506                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         30044                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        53404                       # Time in different power states
+system.mem_ctrls_1.actEnergy                  2006340                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                  1070328                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 8944992                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                6715008                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         7990320.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             16837800                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               207360                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        31179912                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy          108672                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               75060732                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            707.286049                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                68578                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          148                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          3380                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN          283                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         33937                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        68377                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED       106125                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
@@ -289,8 +300,8 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    7                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON          100232                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                           100232                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON          106125                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                           106125                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5641                       # Number of instructions committed
@@ -309,7 +320,7 @@ system.cpu.num_mem_refs                          2037                       # nu
 system.cpu.num_load_insts                        1135                       # Number of load instructions
 system.cpu.num_store_insts                        902                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     100232                       # Number of busy cycles
+system.cpu.num_busy_cycles                     106125                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               886                       # Number of branches fetched
@@ -349,7 +360,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5642                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED       100232                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED       106125                       # Cumulative time (in ticks) in various power states
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   2940                       # delay histogram for all message
@@ -365,10 +376,10 @@ system.ruby.outstanding_req_hist_seqr::total         7679
 system.ruby.latency_hist_seqr::bucket_size           64                      
 system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples           7678                      
-system.ruby.latency_hist_seqr::mean         12.054441                      
-system.ruby.latency_hist_seqr::gmean         2.136034                      
-system.ruby.latency_hist_seqr::stdev        27.599754                      
-system.ruby.latency_hist_seqr            |        7372     96.01%     96.01% |         253      3.30%     99.31% |          37      0.48%     99.79% |           4      0.05%     99.84% |           6      0.08%     99.92% |           5      0.07%     99.99% |           0      0.00%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean         12.821959                      
+system.ruby.latency_hist_seqr::gmean         2.158431                      
+system.ruby.latency_hist_seqr::stdev        29.332675                      
+system.ruby.latency_hist_seqr            |        6783     88.34%     88.34% |         834     10.86%     99.21% |          40      0.52%     99.73% |           8      0.10%     99.83% |           8      0.10%     99.93% |           5      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist_seqr::total             7678                      
 system.ruby.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.hit_latency_hist_seqr::max_bucket            9                      
@@ -380,21 +391,21 @@ system.ruby.hit_latency_hist_seqr::total         6206
 system.ruby.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.miss_latency_hist_seqr::samples         1472                      
-system.ruby.miss_latency_hist_seqr::mean    58.660326                      
-system.ruby.miss_latency_hist_seqr::gmean    52.389786                      
-system.ruby.miss_latency_hist_seqr::stdev    35.865583                      
-system.ruby.miss_latency_hist_seqr       |        1166     79.21%     79.21% |         253     17.19%     96.40% |          37      2.51%     98.91% |           4      0.27%     99.18% |           6      0.41%     99.59% |           5      0.34%     99.93% |           0      0.00%     99.93% |           1      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    62.663723                      
+system.ruby.miss_latency_hist_seqr::gmean    55.319189                      
+system.ruby.miss_latency_hist_seqr::stdev    37.614530                      
+system.ruby.miss_latency_hist_seqr       |         577     39.20%     39.20% |         834     56.66%     95.86% |          40      2.72%     98.57% |           8      0.54%     99.12% |           8      0.54%     99.66% |           5      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist_seqr::total         1472                      
 system.ruby.Directory.incomplete_times_seqr         1471                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED       100232                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED       106125                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         6206                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses         1472                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         7678                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED       100232                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED       100232                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED       106125                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED       106125                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED       100232                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     7.332987                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED       106125                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     6.925795                      
 system.ruby.network.routers0.msg_count.Control::2         1472                      
 system.ruby.network.routers0.msg_count.Data::2         1468                      
 system.ruby.network.routers0.msg_count.Response_Data::4         1472                      
@@ -403,8 +414,8 @@ system.ruby.network.routers0.msg_bytes.Control::2        11776
 system.ruby.network.routers0.msg_bytes.Data::2       105696                      
 system.ruby.network.routers0.msg_bytes.Response_Data::4       105984                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3        11744                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED       100232                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     7.332987                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED       106125                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     6.925795                      
 system.ruby.network.routers1.msg_count.Control::2         1472                      
 system.ruby.network.routers1.msg_count.Data::2         1468                      
 system.ruby.network.routers1.msg_count.Response_Data::4         1472                      
@@ -413,8 +424,8 @@ system.ruby.network.routers1.msg_bytes.Control::2        11776
 system.ruby.network.routers1.msg_bytes.Data::2       105696                      
 system.ruby.network.routers1.msg_bytes.Response_Data::4       105984                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3        11744                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED       100232                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     7.332987                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED       106125                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     6.925795                      
 system.ruby.network.routers2.msg_count.Control::2         1472                      
 system.ruby.network.routers2.msg_count.Data::2         1468                      
 system.ruby.network.routers2.msg_count.Response_Data::4         1472                      
@@ -423,7 +434,7 @@ system.ruby.network.routers2.msg_bytes.Control::2        11776
 system.ruby.network.routers2.msg_bytes.Data::2       105696                      
 system.ruby.network.routers2.msg_bytes.Response_Data::4       105984                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3        11744                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED       100232                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED       106125                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Control            4416                      
 system.ruby.network.msg_count.Data               4404                      
 system.ruby.network.msg_count.Response_Data         4416                      
@@ -432,33 +443,33 @@ system.ruby.network.msg_byte.Control            35328
 system.ruby.network.msg_byte.Data              317088                      
 system.ruby.network.msg_byte.Response_Data       317952                      
 system.ruby.network.msg_byte.Writeback_Control        35232                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED       100232                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     7.340969                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED       106125                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     6.933333                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1472                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1468                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4       105984                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        11744                      
-system.ruby.network.routers0.throttle1.link_utilization     7.325006                      
+system.ruby.network.routers0.throttle1.link_utilization     6.918257                      
 system.ruby.network.routers0.throttle1.msg_count.Control::2         1472                      
 system.ruby.network.routers0.throttle1.msg_count.Data::2         1468                      
 system.ruby.network.routers0.throttle1.msg_bytes.Control::2        11776                      
 system.ruby.network.routers0.throttle1.msg_bytes.Data::2       105696                      
-system.ruby.network.routers1.throttle0.link_utilization     7.325006                      
+system.ruby.network.routers1.throttle0.link_utilization     6.918257                      
 system.ruby.network.routers1.throttle0.msg_count.Control::2         1472                      
 system.ruby.network.routers1.throttle0.msg_count.Data::2         1468                      
 system.ruby.network.routers1.throttle0.msg_bytes.Control::2        11776                      
 system.ruby.network.routers1.throttle0.msg_bytes.Data::2       105696                      
-system.ruby.network.routers1.throttle1.link_utilization     7.340969                      
+system.ruby.network.routers1.throttle1.link_utilization     6.933333                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1472                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1468                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4       105984                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        11744                      
-system.ruby.network.routers2.throttle0.link_utilization     7.340969                      
+system.ruby.network.routers2.throttle0.link_utilization     6.933333                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1472                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1468                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4       105984                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        11744                      
-system.ruby.network.routers2.throttle1.link_utilization     7.325006                      
+system.ruby.network.routers2.throttle1.link_utilization     6.918257                      
 system.ruby.network.routers2.throttle1.msg_count.Control::2         1472                      
 system.ruby.network.routers2.throttle1.msg_count.Data::2         1468                      
 system.ruby.network.routers2.throttle1.msg_bytes.Control::2        11776                      
@@ -476,10 +487,10 @@ system.ruby.delayVCHist.vnet_2::total            1468                       # de
 system.ruby.LD.latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.latency_hist_seqr::samples         1135                      
-system.ruby.LD.latency_hist_seqr::mean      33.525991                      
-system.ruby.LD.latency_hist_seqr::gmean     10.018050                      
-system.ruby.LD.latency_hist_seqr::stdev     38.312060                      
-system.ruby.LD.latency_hist_seqr         |         999     88.02%     88.02% |         116     10.22%     98.24% |          13      1.15%     99.38% |           0      0.00%     99.38% |           6      0.53%     99.91% |           1      0.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      35.394714                      
+system.ruby.LD.latency_hist_seqr::gmean     10.319359                      
+system.ruby.LD.latency_hist_seqr::stdev     39.399406                      
+system.ruby.LD.latency_hist_seqr         |         768     67.67%     67.67% |         344     30.31%     97.97% |          15      1.32%     99.30% |           4      0.35%     99.65% |           2      0.18%     99.82% |           2      0.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_seqr::total          1135                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
@@ -491,18 +502,18 @@ system.ruby.LD.hit_latency_hist_seqr::total          466
 system.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.miss_latency_hist_seqr::samples          669                      
-system.ruby.LD.miss_latency_hist_seqr::mean    56.182362                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    49.875907                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    35.208867                      
-system.ruby.LD.miss_latency_hist_seqr    |         533     79.67%     79.67% |         116     17.34%     97.01% |          13      1.94%     98.95% |           0      0.00%     98.95% |           6      0.90%     99.85% |           1      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    59.352765                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    52.447495                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    35.144031                      
+system.ruby.LD.miss_latency_hist_seqr    |         302     45.14%     45.14% |         344     51.42%     96.56% |          15      2.24%     98.80% |           4      0.60%     99.40% |           2      0.30%     99.70% |           2      0.30%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          669                      
-system.ruby.ST.latency_hist_seqr::bucket_size           64                      
-system.ruby.ST.latency_hist_seqr::max_bucket          639                      
+system.ruby.ST.latency_hist_seqr::bucket_size           32                      
+system.ruby.ST.latency_hist_seqr::max_bucket          319                      
 system.ruby.ST.latency_hist_seqr::samples          901                      
-system.ruby.ST.latency_hist_seqr::mean      13.069922                      
-system.ruby.ST.latency_hist_seqr::gmean      2.509564                      
-system.ruby.ST.latency_hist_seqr::stdev     28.093942                      
-system.ruby.ST.latency_hist_seqr         |         870     96.56%     96.56% |          27      3.00%     99.56% |           3      0.33%     99.89% |           0      0.00%     99.89% |           0      0.00%     99.89% |           0      0.00%     99.89% |           0      0.00%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::mean      13.442841                      
+system.ruby.ST.latency_hist_seqr::gmean      2.518866                      
+system.ruby.ST.latency_hist_seqr::stdev     27.757167                      
+system.ruby.ST.latency_hist_seqr         |         684     75.92%     75.92% |         130     14.43%     90.34% |          81      8.99%     99.33% |           0      0.00%     99.33% |           1      0.11%     99.45% |           3      0.33%     99.78% |           0      0.00%     99.78% |           0      0.00%     99.78% |           1      0.11%     99.89% |           1      0.11%    100.00%
 system.ruby.ST.latency_hist_seqr::total           901                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
@@ -511,21 +522,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean            1
 system.ruby.ST.hit_latency_hist_seqr::gmean            1                      
 system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |         684    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.hit_latency_hist_seqr::total          684                      
-system.ruby.ST.miss_latency_hist_seqr::bucket_size           64                      
-system.ruby.ST.miss_latency_hist_seqr::max_bucket          639                      
+system.ruby.ST.miss_latency_hist_seqr::bucket_size           32                      
+system.ruby.ST.miss_latency_hist_seqr::max_bucket          319                      
 system.ruby.ST.miss_latency_hist_seqr::samples          217                      
-system.ruby.ST.miss_latency_hist_seqr::mean    51.115207                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    45.620625                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    37.056021                      
-system.ruby.ST.miss_latency_hist_seqr    |         186     85.71%     85.71% |          27     12.44%     98.16% |           3      1.38%     99.54% |           0      0.00%     99.54% |           0      0.00%     99.54% |           0      0.00%     99.54% |           0      0.00%     99.54% |           1      0.46%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean    52.663594                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    46.326875                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    34.272225                      
+system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |         130     59.91%     59.91% |          81     37.33%     97.24% |           0      0.00%     97.24% |           1      0.46%     97.70% |           3      1.38%     99.08% |           0      0.00%     99.08% |           0      0.00%     99.08% |           1      0.46%     99.54% |           1      0.46%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total          217                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples         5642                      
-system.ruby.IFETCH.latency_hist_seqr::mean     7.572847                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.525495                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    22.420339                      
-system.ruby.IFETCH.latency_hist_seqr     |        5503     97.54%     97.54% |         110      1.95%     99.49% |          21      0.37%     99.86% |           4      0.07%     99.93% |           0      0.00%     99.93% |           4      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     8.181850                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.537199                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    24.735651                      
+system.ruby.IFETCH.latency_hist_seqr     |        5201     92.18%     92.18% |         409      7.25%     99.43% |          21      0.37%     99.81% |           4      0.07%     99.88% |           4      0.07%     99.95% |           3      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         5642                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
@@ -537,18 +548,18 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total         5056
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          586                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    64.283276                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    58.328027                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    35.386051                      
-system.ruby.IFETCH.miss_latency_hist_seqr |         447     76.28%     76.28% |         110     18.77%     95.05% |          21      3.58%     98.63% |           4      0.68%     99.32% |           0      0.00%     99.32% |           4      0.68%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    70.146758                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    62.782043                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    40.099052                      
+system.ruby.IFETCH.miss_latency_hist_seqr |         145     24.74%     24.74% |         409     69.80%     94.54% |          21      3.58%     98.12% |           4      0.68%     98.81% |           4      0.68%     99.49% |           3      0.51%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          586                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::samples         1472                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean    58.660326                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    52.389786                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    35.865583                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |        1166     79.21%     79.21% |         253     17.19%     96.40% |          37      2.51%     98.91% |           4      0.27%     99.18% |           6      0.41%     99.59% |           5      0.34%     99.93% |           0      0.00%     99.93% |           1      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean    62.663723                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    55.319189                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    37.614530                      
+system.ruby.Directory.miss_mach_latency_hist_seqr |         577     39.20%     39.20% |         834     56.66%     95.86% |          40      2.72%     98.57% |           8      0.54%     99.12% |           8      0.54%     99.66% |           5      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist_seqr::total         1472                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket            9                      
@@ -579,26 +590,26 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples          669                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    56.182362                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    49.875907                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    35.208867                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |         533     79.67%     79.67% |         116     17.34%     97.01% |          13      1.94%     98.95% |           0      0.00%     98.95% |           6      0.90%     99.85% |           1      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    59.352765                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    52.447495                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    35.144031                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |         302     45.14%     45.14% |         344     51.42%     96.56% |          15      2.24%     98.80% |           4      0.60%     99.40% |           2      0.30%     99.70% |           2      0.30%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total          669                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          217                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    51.115207                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    45.620625                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    37.056021                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |         186     85.71%     85.71% |          27     12.44%     98.16% |           3      1.38%     99.54% |           0      0.00%     99.54% |           0      0.00%     99.54% |           0      0.00%     99.54% |           0      0.00%     99.54% |           1      0.46%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    52.663594                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    46.326875                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    34.272225                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         130     59.91%     59.91% |          81     37.33%     97.24% |           0      0.00%     97.24% |           1      0.46%     97.70% |           3      1.38%     99.08% |           0      0.00%     99.08% |           0      0.00%     99.08% |           1      0.46%     99.54% |           1      0.46%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          217                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples          586                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    64.283276                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    58.328027                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    35.386051                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         447     76.28%     76.28% |         110     18.77%     95.05% |          21      3.58%     98.63% |           4      0.68%     99.32% |           0      0.00%     99.32% |           4      0.68%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    70.146758                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    62.782043                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    40.099052                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         145     24.74%     24.74% |         409     69.80%     94.54% |          21      3.58%     98.12% |           4      0.68%     98.81% |           4      0.68%     99.49% |           3      0.51%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total          586                      
 system.ruby.Directory_Controller.GETX            1472      0.00%      0.00%
 system.ruby.Directory_Controller.PUTX            1468      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index 11c8c38c9..08a1c6669 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -174,7 +174,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -532,7 +532,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -591,7 +591,7 @@ size=64
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -708,6 +708,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -727,29 +728,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -769,6 +777,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -800,9 +809,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
index bd0101e05..7df757697 100755
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:27:08
-gem5 started Jul 21 2016 14:27:33
-gem5 executing on e108600-lin, pid 27995
+gem5 compiled Oct 13 2016 20:40:28
+gem5 started Oct 13 2016 20:40:51
+gem5 executing on e108600-lin, pid 9917
 command line: /work/curdun01/gem5-external.hg/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 19908000 because target called exit()
+Exiting @ tick 21268000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index ee06020dc..cfc1cce24 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    20159000                       # Number of ticks simulated
-final_tick                                   20159000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000021                       # Number of seconds simulated
+sim_ticks                                    21268000                       # Number of ticks simulated
+final_tick                                   21268000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  70194                       # Simulator instruction rate (inst/s)
-host_op_rate                                    70182                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              244226628                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249960                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                 112778                       # Simulator instruction rate (inst/s)
+host_op_rate                                   112739                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              413846380                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 248372                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        5792                       # Number of instructions simulated
 sim_ops                                          5792                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     20159000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             21952                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              6400                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                28352                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           21952                       # Nu
 system.physmem.num_reads::cpu.inst                343                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                100                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   443                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1088942904                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            317476065                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1406418969                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1088942904                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1088942904                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1088942904                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           317476065                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1406418969                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1032160993                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            300921572                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1333082565                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1032160993                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1032160993                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1032160993                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           300921572                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1333082565                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           445                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         445                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        20108500                       # Total gap between requests
+system.physmem.totGap                        21217500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,11 +91,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       245                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       139                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       235                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       147                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        44                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -187,78 +187,89 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           76                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      341.894737                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     206.930275                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     338.261263                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             24     31.58%     31.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           19     25.00%     56.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            9     11.84%     68.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            3      3.95%     72.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            4      5.26%     77.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            4      5.26%     82.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            5      6.58%     89.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            8     10.53%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             76                       # Bytes accessed per row activation
-system.physmem.totQLat                        3790750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  12134500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           75                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      351.573333                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     215.062906                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     340.509998                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             23     30.67%     30.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           18     24.00%     54.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           11     14.67%     69.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            2      2.67%     72.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      4.00%     76.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            4      5.33%     81.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      2.67%     84.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      4.00%     88.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            9     12.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             75                       # Bytes accessed per row activation
+system.physmem.totQLat                        5980000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  14323750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2225000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8518.54                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       13438.20                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27268.54                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1412.77                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32188.20                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1339.10                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1412.77                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1339.10                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.04                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.04                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.46                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.78                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.85                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        360                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   80.90                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        45187.64                       # Average gap between requests
+system.physmem.avgGap                        47679.78                       # Average gap between requests
 system.physmem.pageHitRate                      80.90                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     438480                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     239250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2496000                       # Energy for read commands per rank (pJ)
+system.physmem_0.actEnergy                     528360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     254265                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2877420                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10814895                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  32250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 15037995                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              947.872361                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE          11500                       # Time in different power states
+system.physmem_0.refreshEnergy           1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                3922170                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  28320                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy           5666370                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy             64320                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                 14570505                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              685.066353                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime               12593250                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE          17500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        15347250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                      68040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                      37125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                    288600                       # Energy for read commands per rank (pJ)
+system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN       167250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT         8137250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     12426000                       # Time in different power states
+system.physmem_1.actEnergy                      78540                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                      30360                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                    299880                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy                7519725                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                2903250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 11833860                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              747.441023                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        6690750                       # Time in different power states
+system.physmem_1.refreshEnergy           1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                 747840                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                1408800                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy           6431880                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy            712320                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                 10938900                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              514.317955                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime               13775500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE        3585000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        10557750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     20159000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    2407                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1979                       # Number of conditional branches predicted
+system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN      1854750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         1201500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN     14106750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                    2411                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1982                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               409                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2054                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     691                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups                 2056                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     693                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             33.641675                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     226                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             33.706226                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     227                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 35                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups             130                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits                 19                       # Number of indirect target hits.
@@ -284,236 +295,236 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    9                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        20159000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            40319                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        21268000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            42537                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               7699                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          13357                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2407                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                936                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4134                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     847                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles               7672                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          13369                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2411                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                939                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4149                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     849                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                    5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           146                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           22                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      1855                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   288                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              12429                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.074664                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.474276                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1861                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   290                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              12418                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.076582                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.475981                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10095     81.22%     81.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      166      1.34%     82.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      217      1.75%     84.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      147      1.18%     85.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      245      1.97%     87.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      146      1.17%     88.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      275      2.21%     90.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      148      1.19%     92.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      990      7.97%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10084     81.20%     81.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      166      1.34%     82.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      214      1.72%     84.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      147      1.18%     85.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      241      1.94%     87.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      150      1.21%     88.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      280      2.25%     90.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      148      1.19%     92.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      988      7.96%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                12429                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.059699                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.331283                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     7289                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  2789                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      1948                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   128                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    275                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  323                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total                12418                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.056680                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.314291                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7245                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2821                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      1946                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   130                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    276                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  324                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   149                       # Number of times decode detected a branch misprediction
 system.cpu.decode.DecodedInsts                  11479                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   451                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    275                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7458                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     805                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            449                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      1896                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1546                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11044                       # Number of instructions processed by rename
+system.cpu.rename.SquashCycles                    276                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     7413                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     800                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            463                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      1897                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1569                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11042                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                     12                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LQFullEvents                      2                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                   1504                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.SQFullEvents                   1522                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands                9711                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 17893                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            17867                       # Number of integer rename lookups
+system.cpu.rename.RenameLookups                 17897                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            17871                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                26                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4998                       # Number of HB maps that are committed
 system.cpu.rename.UndoneMaps                     4713                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 27                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             27                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       365                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 1936                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1592                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                       381                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 1937                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1590                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                55                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores               30                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      10175                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      10171                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  63                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8810                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                      8808                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                53                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4446                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3475                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            4442                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3474                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             47                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         12429                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.708826                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.510537                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         12418                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.709293                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.511827                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                9301     74.83%     74.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                 985      7.93%     82.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 659      5.30%     88.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 457      3.68%     91.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 433      3.48%     95.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 286      2.30%     97.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 214      1.72%     99.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  62      0.50%     99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  32      0.26%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9303     74.92%     74.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 969      7.80%     82.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 656      5.28%     88.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 462      3.72%     91.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 429      3.45%     95.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 293      2.36%     97.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 212      1.71%     99.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  64      0.52%     99.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  30      0.24%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           12429                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           12418                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      12      6.35%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     87     46.03%     52.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    90     47.62%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      12      6.32%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     88     46.32%     52.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    90     47.37%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5533     62.80%     62.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     62.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1811     20.56%     83.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1464     16.62%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5530     62.78%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.81% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1813     20.58%     83.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1463     16.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8810                       # Type of FU issued
-system.cpu.iq.rate                           0.218507                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         189                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.021453                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              30229                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             14654                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8112                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   8808                       # Type of FU issued
+system.cpu.iq.rate                           0.207067                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         190                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.021571                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              30215                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             14647                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         8115                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  62                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 36                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           27                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8965                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8964                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      34                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               83                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               79                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads          975                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads          976                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation            6                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          546                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          544                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             7                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    275                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     721                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    77                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10238                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                    276                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     722                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    71                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10234                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                32                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  1936                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1592                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts                  1937                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1590                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 53                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                     12                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    66                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents              6                       # Number of memory order violations
+system.cpu.iew.iewLSQFullEvents                    60                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect             68                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          256                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                  324                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8460                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1699                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               350                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts                  8463                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1703                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               345                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3077                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1359                       # Number of branches executed
-system.cpu.iew.exec_stores                       1378                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.209827                       # Inst execution rate
-system.cpu.iew.wb_sent                           8239                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8139                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      4432                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7119                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.201865                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.622559                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts            4448                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                         3080                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1358                       # Number of branches executed
+system.cpu.iew.exec_stores                       1377                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.198956                       # Inst execution rate
+system.cpu.iew.wb_sent                           8242                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          8142                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      4448                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      7158                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.191410                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.621403                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts            4444                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               270                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        11727                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.493903                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.354058                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        11716                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.494367                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.358573                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         9550     81.44%     81.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          859      7.32%     88.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          529      4.51%     93.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          217      1.85%     95.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          185      1.58%     96.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          107      0.91%     97.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          121      1.03%     98.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         9551     81.52%     81.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          850      7.26%     88.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          527      4.50%     93.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          215      1.84%     95.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          176      1.50%     96.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          112      0.96%     97.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          126      1.08%     98.64% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::7           49      0.42%     99.06% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::8          110      0.94%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        11727                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        11716                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5792                       # Number of instructions committed
 system.cpu.commit.committedOps                   5792                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -560,99 +571,99 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5792                       # Class of committed instruction
 system.cpu.commit.bw_lim_events                   110                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        21857                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21183                       # The number of ROB writes
-system.cpu.timesIdled                             230                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           27890                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        21842                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21175                       # The number of ROB writes
+system.cpu.timesIdled                             228                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           30119                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5792                       # Number of Instructions Simulated
 system.cpu.committedOps                          5792                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               6.961153                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.961153                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.143654                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.143654                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    13369                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7149                       # number of integer regfile writes
+system.cpu.cpi                               7.344095                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.344095                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.136164                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.136164                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    13368                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7153                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        25                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     20159000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            64.445386                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2199                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            64.389343                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2206                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               102                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             21.558824                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             21.627451                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    64.445386                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.015734                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.015734                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    64.389343                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.015720                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.015720                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          102                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           75                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.024902                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5374                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5374                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     20159000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data         1477                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1477                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          722                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            722                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2199                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2199                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2199                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2199                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses              5390                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5390                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data         1485                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1485                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          721                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            721                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2206                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2206                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2206                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2206                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          113                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           113                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          324                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          324                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          437                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            437                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          437                       # number of overall misses
-system.cpu.dcache.overall_misses::total           437                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7904000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7904000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     32053496                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     32053496                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     39957496                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     39957496                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     39957496                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     39957496                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1590                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1590                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data          325                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          325                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          438                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            438                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          438                       # number of overall misses
+system.cpu.dcache.overall_misses::total           438                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      8211000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      8211000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     32489496                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     32489496                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     40700496                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     40700496                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     40700496                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     40700496                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1598                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1598                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1046                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1046                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2636                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2636                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2636                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2636                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.071069                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.071069                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.309751                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.309751                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.165781                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.165781                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.165781                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.165781                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69946.902655                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 69946.902655                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 98930.543210                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 98930.543210                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 91435.917620                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 91435.917620                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 91435.917620                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 91435.917620                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          604                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         2644                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2644                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2644                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2644                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070713                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.070713                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.310707                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.310707                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.165658                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.165658                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.165658                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.165658                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72663.716814                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 72663.716814                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99967.680000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 99967.680000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 92923.506849                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 92923.506849                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 92923.506849                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 92923.506849                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          612                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   100.666667                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          102                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           56                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          277                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          277                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          333                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          333                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          333                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          333                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          278                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          278                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          334                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          334                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          334                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          334                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           57                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           57                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           47                       # number of WriteReq MSHR misses
@@ -661,88 +672,88 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          104
 system.cpu.dcache.demand_mshr_misses::total          104                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          104                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          104                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4485500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4485500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4548998                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4548998                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9034498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9034498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9034498                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9034498                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035849                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035849                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4669500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4669500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4693998                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4693998                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9363498                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9363498                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9363498                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9363498                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035670                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035670                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044933                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.044933                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.039454                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.039454                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.039454                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.039454                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78692.982456                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78692.982456                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96787.191489                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96787.191489                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86870.173077                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 86870.173077                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86870.173077                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 86870.173077                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     20159000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.039334                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.039334                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.039334                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.039334                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81921.052632                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81921.052632                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99872.297872                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99872.297872                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90033.634615                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 90033.634615                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90033.634615                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 90033.634615                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           169.030938                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1419                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           168.912200                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1425                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               349                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              4.065903                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              4.083095                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   169.030938                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.082535                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.082535                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   168.912200                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.082477                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.082477                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          349                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          183                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          166                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          179                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.170410                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4059                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4059                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     20159000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         1419                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1419                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1419                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1419                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1419                       # number of overall hits
-system.cpu.icache.overall_hits::total            1419                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              4071                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4071                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst         1425                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1425                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1425                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1425                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1425                       # number of overall hits
+system.cpu.icache.overall_hits::total            1425                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          436                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           436                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          436                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            436                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          436                       # number of overall misses
 system.cpu.icache.overall_misses::total           436                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31654500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31654500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31654500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31654500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31654500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31654500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1855                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1855                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1855                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1855                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1855                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1855                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.235040                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.235040                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.235040                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.235040                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.235040                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.235040                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72602.064220                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72602.064220                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72602.064220                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72602.064220                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72602.064220                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72602.064220                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          507                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     33901500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     33901500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     33901500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     33901500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     33901500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     33901500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1861                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1861                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1861                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1861                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1861                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1861                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.234283                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.234283                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.234283                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.234283                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.234283                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.234283                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77755.733945                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 77755.733945                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 77755.733945                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 77755.733945                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 77755.733945                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 77755.733945                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          567                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs   101.400000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs   113.400000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           86                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_hits::total           86                       # number of ReadReq MSHR hits
@@ -756,43 +767,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          350
 system.cpu.icache.demand_mshr_misses::total          350                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          350                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          350                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26454000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     26454000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26454000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     26454000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26454000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     26454000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.188679                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.188679                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.188679                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.188679                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.188679                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.188679                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75582.857143                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75582.857143                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75582.857143                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75582.857143                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75582.857143                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75582.857143                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     20159000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     28298000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     28298000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     28298000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     28298000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     28298000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     28298000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.188071                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.188071                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.188071                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.188071                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.188071                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.188071                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80851.428571                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80851.428571                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80851.428571                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 80851.428571                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80851.428571                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 80851.428571                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          231.417144                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          231.224808                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  8                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              443                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.018059                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   167.835616                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    63.581529                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005122                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001940                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.007062                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   167.706281                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    63.518527                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005118                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001938                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.007056                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          443                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          202                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.013519                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4075                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4075                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     20159000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            6                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            6                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data            2                       # number of ReadSharedReq hits
@@ -815,18 +826,18 @@ system.cpu.l2cache.demand_misses::total           446                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          344                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          102                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4475000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4475000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25861000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     25861000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4379000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      4379000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     25861000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      8854000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     34715000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     25861000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      8854000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     34715000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4620000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4620000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     27705000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     27705000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4563000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      4563000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     27705000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9183000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     36888000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     27705000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9183000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     36888000                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           47                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           47                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          350                       # number of ReadCleanReq accesses(hits+misses)
@@ -851,18 +862,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.982379                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.982857                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.980769                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.982379                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95212.765957                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95212.765957                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75177.325581                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75177.325581                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79618.181818                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79618.181818                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75177.325581                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86803.921569                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77836.322870                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75177.325581                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86803.921569                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77836.322870                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98297.872340                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98297.872340                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80537.790698                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80537.790698                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82963.636364                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82963.636364                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80537.790698                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90029.411765                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82708.520179                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80537.790698                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90029.411765                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82708.520179                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -881,18 +892,18 @@ system.cpu.l2cache.demand_mshr_misses::total          446
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          344                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          102                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4005000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4005000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22431000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22431000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      3849000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      3849000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22431000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7854000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     30285000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22431000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7854000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     30285000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4150000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4150000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     24275000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     24275000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4033000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4033000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24275000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8183000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     32458000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24275000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8183000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     32458000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for ReadCleanReq accesses
@@ -905,25 +916,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.982379
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980769                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.982379                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85212.765957                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85212.765957                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65206.395349                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65206.395349                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69981.818182                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69981.818182                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65206.395349                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        77000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67903.587444                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65206.395349                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        77000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67903.587444                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88297.872340                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88297.872340                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70566.860465                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70566.860465                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73327.272727                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73327.272727                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70566.860465                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80225.490196                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72775.784753                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70566.860465                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80225.490196                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72775.784753                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests          454                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            8                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     20159000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           404                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           47                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           47                       # Transaction distribution
@@ -951,16 +962,16 @@ system.cpu.toL2Bus.snoop_fanout::total            454                       # Re
 system.cpu.toL2Bus.reqLayer0.occupancy         227000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        523500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization          2.5                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        153000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
 system.membus.snoop_filter.tot_requests           445                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     20159000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                396                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                47                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               47                       # Transaction distribution
@@ -981,9 +992,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 445                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              553500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2340000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             11.6                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              553000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.6                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2325250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             10.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index 0ce55f79c..7609bf228 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -121,7 +131,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -144,27 +154,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -176,6 +186,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -183,12 +194,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -210,9 +226,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -226,12 +242,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -248,6 +269,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
@@ -255,6 +277,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
 eventq_index=0
 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestToDir=system.ruby.dir_cntrl0.requestToDir
 responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -328,11 +354,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 forwardToCache=system.ruby.l1_cntrl0.forwardToCache
 issue_latency=2
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestFromCache=system.ruby.l1_cntrl0.requestFromCache
 responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -414,17 +445,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.cacheMemory
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.cacheMemory
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 slave=system.cpu.icache_port system.cpu.dcache_port
@@ -437,18 +473,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
 netifs=
 number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
 ruby_system=system.ruby
 topology=Crossbar
@@ -615,32 +656,206 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14
+power_model=Null
 router_id=0
 virt_nets=5
 
@@ -753,8 +968,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14
+power_model=Null
 router_id=1
 virt_nets=5
 
@@ -867,8 +1088,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19
+power_model=Null
 router_id=2
 virt_nets=5
 
@@ -1015,9 +1242,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index ed1dc8177..36ed80c84 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:30:54
-gem5 started Jan 21 2016 14:31:28
-gem5 executing on zizzer, pid 8746
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
+gem5 compiled Oct 13 2016 20:43:27
+gem5 started Oct 13 2016 20:46:33
+gem5 executing on e108600-lin, pid 17405
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing-ruby
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Hello World!Exiting @ tick 81703 because target called exit()
+Hello World!Exiting @ tick 86746 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 3b20a8d52..a1c151f90 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000082                       # Number of seconds simulated
-sim_ticks                                       81703                       # Number of ticks simulated
-final_tick                                      81703                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000087                       # Number of seconds simulated
+sim_ticks                                       86746                       # Number of ticks simulated
+final_tick                                      86746                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                 107011                       # Simulator instruction rate (inst/s)
-host_op_rate                                   106993                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1640735                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 456212                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  61570                       # Simulator instruction rate (inst/s)
+host_op_rate                                    61552                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1002076                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 413704                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        81703                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        86746                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        82496                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              82496                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0        82240                       # Number of bytes written to this memory
@@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1289                       #
 system.mem_ctrls.num_reads::total                1289                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0         1285                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total               1285                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0   1009705886                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            1009705886                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0   1006572586                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total           1006572586                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   2016278472                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           2016278472                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    951006386                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             951006386                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    948055242                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            948055242                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   1899061628                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1899061628                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1289                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                       1285                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1289                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                     1285                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  43904                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   38592                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   43776                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  44800                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   37696                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   45504                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   82496                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                82240                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    603                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   579                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    589                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   555                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
 system.mem_ctrls.perBankRdBursts::0                28                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1                18                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1                17                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                 1                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                 8                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5               119                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6               115                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7               134                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8                61                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9                34                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               12                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11               59                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6               121                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7               141                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8                55                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9                31                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10               13                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11               62                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::12               21                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13               59                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14                9                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13               61                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14               14                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                8                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0                29                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0                28                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::1                18                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2                 2                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2                 1                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::3                 8                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::4                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5               117                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6               112                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7               138                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8                63                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5               118                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6               114                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7               141                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8                61                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::9                35                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10               13                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11               59                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12               21                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               51                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14               10                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10               14                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11               62                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12               23                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               64                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14               16                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::15                8                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         81643                       # Total gap between requests
+system.mem_ctrls.totGap                         86680                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                 1285                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     686                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                     700                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -136,25 +136,25 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     34                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      3                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      3                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     35                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::18                     45                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::19                     45                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     48                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                     46                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                     49                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                     49                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     46                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     44                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                     44                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                     44                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                     44                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                     44                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                     44                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     44                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                     44                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     44                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                     44                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
@@ -185,95 +185,103 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          227                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    379.207048                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   252.014148                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   323.708826                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           44     19.38%     19.38% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           63     27.75%     47.14% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           29     12.78%     59.91% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           17      7.49%     67.40% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           17      7.49%     74.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767           17      7.49%     82.38% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            9      3.96%     86.34% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            6      2.64%     88.99% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           25     11.01%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          227                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples           42                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      16.190476                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     15.978361                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      3.255300                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13             3      7.14%      7.14% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15            10     23.81%     30.95% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            26     61.90%     92.86% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             1      2.38%     95.24% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21             1      2.38%     97.62% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35             1      2.38%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total            42                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples           42                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.285714                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.270299                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.741972                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               36     85.71%     85.71% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                1      2.38%     88.10% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                4      9.52%     97.62% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                1      2.38%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total            42                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         8350                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   21384                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       3430                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        12.17                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples          247                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    359.384615                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   236.451062                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   319.751749                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           54     21.86%     21.86% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           65     26.32%     48.18% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           38     15.38%     63.56% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           27     10.93%     74.49% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639            8      3.24%     77.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767           10      4.05%     81.78% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895           11      4.45%     86.23% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            9      3.64%     89.88% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           25     10.12%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          247                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples           44                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      15.840909                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     15.640724                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      3.183849                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13             2      4.55%      4.55% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15            21     47.73%     52.27% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17            18     40.91%     93.18% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19             2      4.55%     97.73% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35             1      2.27%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total            44                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples           44                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.159091                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.147705                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.644951                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               41     93.18%     93.18% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                1      2.27%     95.45% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19                2      4.55%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total            44                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                        12987                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   26287                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       3500                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        18.55                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   31.17                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       537.36                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       535.79                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   1009.71                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                   1006.57                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   37.55                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       516.45                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       524.57                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    951.01                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    948.06                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         8.38                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     4.20                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    4.19                       # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil                         8.13                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     4.03                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    4.10                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      25.98                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      503                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     635                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 73.32                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                89.94                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         31.72                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    81.75                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   960120                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   533400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 4992000                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                3981312                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              5085600                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             48305448                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy              4498800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               68356680                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            875.021505                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE         7218                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF          2600                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         68316                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                   703080                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   390600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 3107520                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                2602368                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              5085600                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             45961380                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              6555000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               64405548                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            824.443779                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE        10688                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          2600                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         64875                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        81703                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.avgWrQLen                      25.18                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      508                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     652                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 72.57                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                89.32                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         33.68                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    81.12                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                  1099560                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   587328                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 4969440                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                3574656                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         6761040.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             10338432                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy               148224                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        27605784                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy         1209216                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               56293680                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            648.948424                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                63519                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE           64                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          2860                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN         3149                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         20134                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        60539                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   692580                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   367080                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 3027360                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                2363616                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         6761040.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy              9621600                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               296448                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        26302992                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy         2761728                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               52194444                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            601.692804                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                64843                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          422                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          2860                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         7192                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         18590                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        57682                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED        86746                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON           81703                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            81703                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON           86746                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            86746                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5327                       # Number of instructions committed
@@ -292,7 +300,7 @@ system.cpu.num_mem_refs                          1401                       # nu
 system.cpu.num_load_insts                         723                       # Number of load instructions
 system.cpu.num_store_insts                        678                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.999988                       # Number of idle cycles
-system.cpu.num_busy_cycles               81702.000012                       # Number of busy cycles
+system.cpu.num_busy_cycles               86745.000012                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.999988                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000012                       # Percentage of idle cycles
 system.cpu.Branches                              1121                       # Number of branches fetched
@@ -332,7 +340,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5370                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        81703                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        86746                       # Cumulative time (in ticks) in various power states
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   2574                       # delay histogram for all message
@@ -348,10 +356,10 @@ system.ruby.outstanding_req_hist_seqr::total         6759
 system.ruby.latency_hist_seqr::bucket_size           64                      
 system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples           6758                      
-system.ruby.latency_hist_seqr::mean         11.089819                      
-system.ruby.latency_hist_seqr::gmean         2.095228                      
-system.ruby.latency_hist_seqr::stdev        25.111209                      
-system.ruby.latency_hist_seqr            |        6551     96.94%     96.94% |         169      2.50%     99.44% |          28      0.41%     99.85% |           2      0.03%     99.88% |           5      0.07%     99.96% |           2      0.03%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean         11.836046                      
+system.ruby.latency_hist_seqr::gmean         2.117342                      
+system.ruby.latency_hist_seqr::stdev        27.149732                      
+system.ruby.latency_hist_seqr            |        6079     89.95%     89.95% |         633      9.37%     99.32% |          36      0.53%     99.85% |           1      0.01%     99.87% |           6      0.09%     99.96% |           2      0.03%     99.99% |           0      0.00%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist_seqr::total             6758                      
 system.ruby.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.hit_latency_hist_seqr::max_bucket            9                      
@@ -363,21 +371,21 @@ system.ruby.hit_latency_hist_seqr::total         5469
 system.ruby.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.miss_latency_hist_seqr::samples         1289                      
-system.ruby.miss_latency_hist_seqr::mean    53.899147                      
-system.ruby.miss_latency_hist_seqr::gmean    48.323546                      
-system.ruby.miss_latency_hist_seqr::stdev    32.275754                      
-system.ruby.miss_latency_hist_seqr       |        1082     83.94%     83.94% |         169     13.11%     97.05% |          28      2.17%     99.22% |           2      0.16%     99.38% |           5      0.39%     99.77% |           2      0.16%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    57.811482                      
+system.ruby.miss_latency_hist_seqr::gmean    51.058094                      
+system.ruby.miss_latency_hist_seqr::stdev    35.397665                      
+system.ruby.miss_latency_hist_seqr       |         610     47.32%     47.32% |         633     49.11%     96.43% |          36      2.79%     99.22% |           1      0.08%     99.30% |           6      0.47%     99.77% |           2      0.16%     99.92% |           0      0.00%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist_seqr::total         1289                      
 system.ruby.Directory.incomplete_times_seqr         1288                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        81703                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        86746                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         5469                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses         1289                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         6758                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        81703                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        81703                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        86746                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        86746                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        81703                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     7.876088                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        86746                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     7.418209                      
 system.ruby.network.routers0.msg_count.Control::2         1289                      
 system.ruby.network.routers0.msg_count.Data::2         1285                      
 system.ruby.network.routers0.msg_count.Response_Data::4         1289                      
@@ -386,8 +394,8 @@ system.ruby.network.routers0.msg_bytes.Control::2        10312
 system.ruby.network.routers0.msg_bytes.Data::2        92520                      
 system.ruby.network.routers0.msg_bytes.Response_Data::4        92808                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3        10280                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        81703                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     7.876088                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        86746                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     7.418209                      
 system.ruby.network.routers1.msg_count.Control::2         1289                      
 system.ruby.network.routers1.msg_count.Data::2         1285                      
 system.ruby.network.routers1.msg_count.Response_Data::4         1289                      
@@ -396,8 +404,8 @@ system.ruby.network.routers1.msg_bytes.Control::2        10312
 system.ruby.network.routers1.msg_bytes.Data::2        92520                      
 system.ruby.network.routers1.msg_bytes.Response_Data::4        92808                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3        10280                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        81703                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     7.876088                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        86746                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     7.418209                      
 system.ruby.network.routers2.msg_count.Control::2         1289                      
 system.ruby.network.routers2.msg_count.Data::2         1285                      
 system.ruby.network.routers2.msg_count.Response_Data::4         1289                      
@@ -406,7 +414,7 @@ system.ruby.network.routers2.msg_bytes.Control::2        10312
 system.ruby.network.routers2.msg_bytes.Data::2        92520                      
 system.ruby.network.routers2.msg_bytes.Response_Data::4        92808                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3        10280                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        81703                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        86746                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Control            3867                      
 system.ruby.network.msg_count.Data               3855                      
 system.ruby.network.msg_count.Response_Data         3867                      
@@ -415,33 +423,33 @@ system.ruby.network.msg_byte.Control            30936
 system.ruby.network.msg_byte.Data              277560                      
 system.ruby.network.msg_byte.Response_Data       278424                      
 system.ruby.network.msg_byte.Writeback_Control        30840                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        81703                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     7.885879                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        86746                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     7.427432                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1289                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1285                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        92808                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        10280                      
-system.ruby.network.routers0.throttle1.link_utilization     7.866296                      
+system.ruby.network.routers0.throttle1.link_utilization     7.408987                      
 system.ruby.network.routers0.throttle1.msg_count.Control::2         1289                      
 system.ruby.network.routers0.throttle1.msg_count.Data::2         1285                      
 system.ruby.network.routers0.throttle1.msg_bytes.Control::2        10312                      
 system.ruby.network.routers0.throttle1.msg_bytes.Data::2        92520                      
-system.ruby.network.routers1.throttle0.link_utilization     7.866296                      
+system.ruby.network.routers1.throttle0.link_utilization     7.408987                      
 system.ruby.network.routers1.throttle0.msg_count.Control::2         1289                      
 system.ruby.network.routers1.throttle0.msg_count.Data::2         1285                      
 system.ruby.network.routers1.throttle0.msg_bytes.Control::2        10312                      
 system.ruby.network.routers1.throttle0.msg_bytes.Data::2        92520                      
-system.ruby.network.routers1.throttle1.link_utilization     7.885879                      
+system.ruby.network.routers1.throttle1.link_utilization     7.427432                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1289                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1285                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        92808                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        10280                      
-system.ruby.network.routers2.throttle0.link_utilization     7.885879                      
+system.ruby.network.routers2.throttle0.link_utilization     7.427432                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1289                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1285                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        92808                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        10280                      
-system.ruby.network.routers2.throttle1.link_utilization     7.866296                      
+system.ruby.network.routers2.throttle1.link_utilization     7.408987                      
 system.ruby.network.routers2.throttle1.msg_count.Control::2         1289                      
 system.ruby.network.routers2.throttle1.msg_count.Data::2         1285                      
 system.ruby.network.routers2.throttle1.msg_bytes.Control::2        10312                      
@@ -459,10 +467,10 @@ system.ruby.delayVCHist.vnet_2::total            1285                       # de
 system.ruby.LD.latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.latency_hist_seqr::samples          715                      
-system.ruby.LD.latency_hist_seqr::mean      28.394406                      
-system.ruby.LD.latency_hist_seqr::gmean      8.251059                      
-system.ruby.LD.latency_hist_seqr::stdev     33.266069                      
-system.ruby.LD.latency_hist_seqr         |         656     91.75%     91.75% |          50      6.99%     98.74% |           8      1.12%     99.86% |           0      0.00%     99.86% |           0      0.00%     99.86% |           0      0.00%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      30.464336                      
+system.ruby.LD.latency_hist_seqr::gmean      8.484057                      
+system.ruby.LD.latency_hist_seqr::stdev     36.464169                      
+system.ruby.LD.latency_hist_seqr         |         540     75.52%     75.52% |         163     22.80%     98.32% |          10      1.40%     99.72% |           0      0.00%     99.72% |           1      0.14%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_seqr::total           715                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
@@ -474,18 +482,18 @@ system.ruby.LD.hit_latency_hist_seqr::total          320
 system.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.miss_latency_hist_seqr::samples          395                      
-system.ruby.LD.miss_latency_hist_seqr::mean    50.587342                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    45.603541                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    30.035585                      
-system.ruby.LD.miss_latency_hist_seqr    |         336     85.06%     85.06% |          50     12.66%     97.72% |           8      2.03%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           1      0.25%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    54.334177                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    47.961199                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    33.663530                      
+system.ruby.LD.miss_latency_hist_seqr    |         220     55.70%     55.70% |         163     41.27%     96.96% |          10      2.53%     99.49% |           0      0.00%     99.49% |           1      0.25%     99.75% |           1      0.25%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          395                      
-system.ruby.ST.latency_hist_seqr::bucket_size           32                      
-system.ruby.ST.latency_hist_seqr::max_bucket          319                      
+system.ruby.ST.latency_hist_seqr::bucket_size           64                      
+system.ruby.ST.latency_hist_seqr::max_bucket          639                      
 system.ruby.ST.latency_hist_seqr::samples          673                      
-system.ruby.ST.latency_hist_seqr::mean      16.656761                      
-system.ruby.ST.latency_hist_seqr::gmean      2.888882                      
-system.ruby.ST.latency_hist_seqr::stdev     31.530024                      
-system.ruby.ST.latency_hist_seqr         |         494     73.40%     73.40% |         146     21.69%     95.10% |          26      3.86%     98.96% |           0      0.00%     98.96% |           4      0.59%     99.55% |           0      0.00%     99.55% |           1      0.15%     99.70% |           0      0.00%     99.70% |           1      0.15%     99.85% |           1      0.15%    100.00%
+system.ruby.ST.latency_hist_seqr::mean      17.630015                      
+system.ruby.ST.latency_hist_seqr::gmean      2.926423                      
+system.ruby.ST.latency_hist_seqr::stdev     33.570929                      
+system.ruby.ST.latency_hist_seqr         |         555     82.47%     82.47% |         110     16.34%     98.81% |           6      0.89%     99.70% |           0      0.00%     99.70% |           1      0.15%     99.85% |           1      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist_seqr::total           673                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
@@ -494,21 +502,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean            1
 system.ruby.ST.hit_latency_hist_seqr::gmean            1                      
 system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |         494    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.hit_latency_hist_seqr::total          494                      
-system.ruby.ST.miss_latency_hist_seqr::bucket_size           32                      
-system.ruby.ST.miss_latency_hist_seqr::max_bucket          319                      
+system.ruby.ST.miss_latency_hist_seqr::bucket_size           64                      
+system.ruby.ST.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.ST.miss_latency_hist_seqr::samples          179                      
-system.ruby.ST.miss_latency_hist_seqr::mean    59.865922                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    53.981018                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    34.573548                      
-system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |         146     81.56%     81.56% |          26     14.53%     96.09% |           0      0.00%     96.09% |           4      2.23%     98.32% |           0      0.00%     98.32% |           1      0.56%     98.88% |           0      0.00%     98.88% |           1      0.56%     99.44% |           1      0.56%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean    63.525140                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    56.666113                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    37.000656                      
+system.ruby.ST.miss_latency_hist_seqr    |          61     34.08%     34.08% |         110     61.45%     95.53% |           6      3.35%     98.88% |           0      0.00%     98.88% |           1      0.56%     99.44% |           1      0.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total          179                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples         5370                      
-system.ruby.IFETCH.latency_hist_seqr::mean     8.088082                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.676829                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    21.661449                      
-system.ruby.IFETCH.latency_hist_seqr     |        5255     97.86%     97.86% |          93      1.73%     99.59% |          16      0.30%     99.89% |           1      0.02%     99.91% |           3      0.06%     99.96% |           2      0.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     8.629609                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.690107                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    23.432463                      
+system.ruby.IFETCH.latency_hist_seqr     |        4984     92.81%     92.81% |         360      6.70%     99.52% |          20      0.37%     99.89% |           1      0.02%     99.91% |           4      0.07%     99.98% |           0      0.00%     99.98% |           0      0.00%     99.98% |           1      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         5370                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
@@ -520,18 +528,18 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total         4655
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          715                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    54.234965                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    48.531211                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    32.684395                      
-system.ruby.IFETCH.miss_latency_hist_seqr |         600     83.92%     83.92% |          93     13.01%     96.92% |          16      2.24%     99.16% |           1      0.14%     99.30% |           3      0.42%     99.72% |           2      0.28%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    58.302098                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    51.492810                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    35.756740                      
+system.ruby.IFETCH.miss_latency_hist_seqr |         329     46.01%     46.01% |         360     50.35%     96.36% |          20      2.80%     99.16% |           1      0.14%     99.30% |           4      0.56%     99.86% |           0      0.00%     99.86% |           0      0.00%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          715                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::samples         1289                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean    53.899147                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    48.323546                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    32.275754                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |        1082     83.94%     83.94% |         169     13.11%     97.05% |          28      2.17%     99.22% |           2      0.16%     99.38% |           5      0.39%     99.77% |           2      0.16%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean    57.811482                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    51.058094                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    35.397665                      
+system.ruby.Directory.miss_mach_latency_hist_seqr |         610     47.32%     47.32% |         633     49.11%     96.43% |          36      2.79%     99.22% |           1      0.08%     99.30% |           6      0.47%     99.77% |           2      0.16%     99.92% |           0      0.00%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist_seqr::total         1289                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket            9                      
@@ -562,26 +570,26 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples          395                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    50.587342                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    45.603541                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    30.035585                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |         336     85.06%     85.06% |          50     12.66%     97.72% |           8      2.03%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           1      0.25%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    54.334177                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    47.961199                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    33.663530                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |         220     55.70%     55.70% |         163     41.27%     96.96% |          10      2.53%     99.49% |           0      0.00%     99.49% |           1      0.25%     99.75% |           1      0.25%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total          395                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          179                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    59.865922                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    53.981018                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    34.573548                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         146     81.56%     81.56% |          26     14.53%     96.09% |           0      0.00%     96.09% |           4      2.23%     98.32% |           0      0.00%     98.32% |           1      0.56%     98.88% |           0      0.00%     98.88% |           1      0.56%     99.44% |           1      0.56%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    63.525140                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    56.666113                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    37.000656                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |          61     34.08%     34.08% |         110     61.45%     95.53% |           6      3.35%     98.88% |           0      0.00%     98.88% |           1      0.56%     99.44% |           1      0.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          179                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples          715                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    54.234965                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    48.531211                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    32.684395                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         600     83.92%     83.92% |          93     13.01%     96.92% |          16      2.24%     99.16% |           1      0.14%     99.30% |           3      0.42%     99.72% |           2      0.28%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    58.302098                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    51.492810                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    35.756740                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         329     46.01%     46.01% |         360     50.35%     96.36% |          20      2.80%     99.16% |           1      0.14%     99.30% |           4      0.56%     99.86% |           0      0.00%     99.86% |           0      0.00%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total          715                      
 system.ruby.Directory_Controller.GETX            1289      0.00%      0.00%
 system.ruby.Directory_Controller.PUTX            1285      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 8fda1a50c..774234af5 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -179,7 +179,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -552,7 +552,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -756,6 +756,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -767,7 +768,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -775,29 +776,36 @@ width=16
 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -817,6 +825,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -848,9 +857,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
index 8cf3e8140..ce4c9483b 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:18
-gem5 executing on e108600-lin, pid 18560
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:09:20
+gem5 executing on e108600-lin, pid 17644
 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 21273500 because target called exit()
+Exiting @ tick 22466500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 401e565b1..d0952668c 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000021                       # Number of seconds simulated
-sim_ticks                                    21382500                       # Number of ticks simulated
-final_tick                                   21382500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000022                       # Number of seconds simulated
+sim_ticks                                    22466500                       # Number of ticks simulated
+final_tick                                   22466500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  21602                       # Simulator instruction rate (inst/s)
-host_op_rate                                    39134                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               85845466                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 271116                       # Number of bytes of host memory used
-host_seconds                                     0.25                       # Real time elapsed on the host
+host_inst_rate                                  32079                       # Simulator instruction rate (inst/s)
+host_op_rate                                    58113                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              133941475                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269032                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8896                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                26688                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        17792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           17792                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                139                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   417                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            832082310                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            416041155                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1248123465                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       832082310                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          832082310                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           832082310                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           416041155                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1248123465                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           417                       # Number of read requests accepted
+system.physmem.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst             17728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              9024                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26752                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        17728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           17728                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                277                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   418                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            789085972                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            401664701                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1190750673                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       789085972                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          789085972                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           789085972                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           401664701                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1190750673                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           418                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         417                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         418                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    26688                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    26752                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     26688                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     26752                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  31                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                  32                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                   1                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                   5                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                   8                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  51                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                  50                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                  44                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  21                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  37                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                  23                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                  24                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                  71                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 64                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                 16                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                  2                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                 19                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                  7                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                 20                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                  6                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                 17                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        21259500                       # Total gap between requests
+system.physmem.totGap                        22337000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     417                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     418                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -91,11 +91,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       246                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        40                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       242                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       129                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -187,318 +187,328 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           97                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      248.742268                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     161.877699                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     262.561948                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             36     37.11%     37.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           27     27.84%     64.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           16     16.49%     81.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            4      4.12%     85.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      2.06%     87.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            4      4.12%     91.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      2.06%     93.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      1.03%     94.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            5      5.15%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             97                       # Bytes accessed per row activation
-system.physmem.totQLat                        5040250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  12859000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2085000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12086.93                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples           95                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      246.568421                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     159.892164                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     259.040400                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             37     38.95%     38.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           23     24.21%     63.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           16     16.84%     80.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            6      6.32%     86.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      2.11%     88.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      3.16%     91.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      2.11%     93.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      2.11%     95.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            4      4.21%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             95                       # Bytes accessed per row activation
+system.physmem.totQLat                        6803250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  14640750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2090000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       16275.72                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30836.93                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1248.12                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  35025.72                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1190.75                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1248.12                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1190.75                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           9.75                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       9.75                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           9.30                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       9.30                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.67                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.69                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        309                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        310                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.10                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   74.16                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        50982.01                       # Average gap between requests
-system.physmem.pageHitRate                      74.10                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     173880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                      94875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                    912600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        53437.80                       # Average gap between requests
+system.physmem.pageHitRate                      74.16                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     285600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     125235                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   1413720                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10792665                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  32250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 13023390                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              822.573188                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE          13750                       # Time in different power states
+system.physmem_0.refreshEnergy           1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                2399130                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  30240                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy           7645980                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy            138240                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                 13267425                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              590.516301                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime               17035500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE          23500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        15314750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     415800                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     226875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1497600                       # Energy for read commands per rank (pJ)
+system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN       359250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT         4794250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     16769500                       # Time in different power states
+system.physmem_1.actEnergy                     485520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     235290                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1570800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10696050                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 117000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 13970445                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              882.390336                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         103000                       # Time in different power states
+system.physmem_1.refreshEnergy           1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                2963430                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                  82560                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy           7182000                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy              1440                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                 13750320                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              612.009347                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime               14672000                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE         109000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        15223250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    3511                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              3511                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               567                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2933                       # Number of BTB lookups
+system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN         3500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         6091750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN     15742250                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                    3488                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              3488                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               571                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 2960                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     414                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.usedRAS                     360                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 94                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups            2933                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits                496                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses             2437                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted          406                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.indirectLookups            2960                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits                483                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             2477                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          410                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        21382500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            42766                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        22466500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            44934                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              11494                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          15919                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        3511                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                910                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          9718                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1335                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                   93                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles              12177                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          15717                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        3488                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                843                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                         10477                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1321                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   78                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles          1414                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles           15                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles           30                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      2042                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   273                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              23431                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.223593                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.745730                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles           15                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                      2026                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   276                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              24836                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.141770                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.668775                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    19161     81.78%     81.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      166      0.71%     82.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      156      0.67%     83.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      235      1.00%     84.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      218      0.93%     85.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      215      0.92%     86.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      266      1.14%     87.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      168      0.72%     87.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2846     12.15%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    20599     82.94%     82.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      175      0.70%     83.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      165      0.66%     84.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      225      0.91%     85.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      209      0.84%     86.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      222      0.89%     86.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      269      1.08%     88.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      159      0.64%     88.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2813     11.33%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                23431                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.082098                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.372235                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    11586                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  7313                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3407                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   458                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    667                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  26631                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                    667                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    11849                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    2059                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1032                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      3561                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  4263                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  25112                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    14                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     80                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.SQFullEvents                   4127                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               28145                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 61260                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            35084                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                24836                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.077625                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.349780                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    12221                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  8128                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      3370                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   457                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    660                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  26405                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                    660                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    12481                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    1971                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1213                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      3524                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  4987                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  24875                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     8                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                     82                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.SQFullEvents                   4849                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               27762                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 60616                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            34638                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 4                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                 11063                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    17082                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 24                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             24                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      1417                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2745                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1552                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                11                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                7                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      21890                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  22                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     18162                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               138                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           12165                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        16733                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             10                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         23431                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.775127                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.748484                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                    16699                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 25                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             25                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      1436                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2622                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1598                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                10                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores               11                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      21775                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  23                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     18112                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               144                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           12051                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        16553                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             11                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         24836                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.729264                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.710819                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               18255     77.91%     77.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1208      5.16%     83.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 874      3.73%     86.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 566      2.42%     89.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 836      3.57%     92.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 600      2.56%     95.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 613      2.62%     97.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 346      1.48%     99.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                 133      0.57%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               19691     79.28%     79.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1200      4.83%     84.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 866      3.49%     87.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 575      2.32%     89.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 815      3.28%     93.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 575      2.32%     95.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 614      2.47%     97.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 364      1.47%     99.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                 136      0.55%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           23431                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           24836                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     213     76.07%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     76.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     51     18.21%     94.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    16      5.71%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     223     79.93%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     79.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     41     14.70%     94.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    15      5.38%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 14483     79.74%     79.75% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    6      0.03%     79.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     7      0.04%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2327     12.81%     92.64% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1337      7.36%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 14478     79.94%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    6      0.03%     79.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     7      0.04%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2258     12.47%     92.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1361      7.51%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  18162                       # Type of FU issued
-system.cpu.iq.rate                           0.424683                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         280                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.015417                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              60165                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             34082                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        16453                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  18112                       # Type of FU issued
+system.cpu.iq.rate                           0.403080                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         279                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.015404                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              61475                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             33854                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        16418                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  8                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  18436                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  18385                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads              200                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads              215                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1692                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            9                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1569                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses           13                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           13                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          617                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          663                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             9                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked             2                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    667                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1486                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                   141                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               21912                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                 9                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2745                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1552                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 22                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles                    660                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1482                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   153                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               21798                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                34                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2622                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1598                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 23                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   140                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   152                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             13                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            120                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          685                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  805                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 17078                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2088                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1084                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect            118                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          680                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  798                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 17038                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2047                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1074                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3333                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1727                       # Number of branches executed
-system.cpu.iew.exec_stores                       1245                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.399336                       # Inst execution rate
-system.cpu.iew.wb_sent                          16776                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         16457                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                     11050                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     17247                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.384815                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.640691                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts           12164                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                         3306                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1731                       # Number of branches executed
+system.cpu.iew.exec_stores                       1259                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.379178                       # Inst execution rate
+system.cpu.iew.wb_sent                          16737                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         16422                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                     11019                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     17148                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.365469                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.642582                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts           12050                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              12                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               655                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        21365                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.456213                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.347578                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               648                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        22793                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.427631                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.307645                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        18118     84.80%     84.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          989      4.63%     89.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          572      2.68%     92.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          729      3.41%     95.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          380      1.78%     97.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          132      0.62%     97.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          120      0.56%     98.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           73      0.34%     98.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          252      1.18%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        19538     85.72%     85.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1001      4.39%     90.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          566      2.48%     92.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          727      3.19%     95.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          384      1.68%     97.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          133      0.58%     98.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          124      0.54%     98.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           72      0.32%     98.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          248      1.09%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        21365                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        22793                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5380                       # Number of instructions committed
 system.cpu.commit.committedOps                   9747                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -544,94 +554,94 @@ system.cpu.commit.op_class_0::MemWrite            935      9.59%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              9747                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   252                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        43024                       # The number of ROB reads
-system.cpu.rob.rob_writes                       45919                       # The number of ROB writes
-system.cpu.timesIdled                             159                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           19335                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   248                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        44342                       # The number of ROB reads
+system.cpu.rob.rob_writes                       45672                       # The number of ROB writes
+system.cpu.timesIdled                             156                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           20098                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5380                       # Number of Instructions Simulated
 system.cpu.committedOps                          9747                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.949071                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.949071                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.125801                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.125801                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    21733                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   13291                       # number of integer regfile writes
+system.cpu.cpi                               8.352045                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         8.352045                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.119731                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.119731                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    21663                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   13219                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                      8307                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                     5092                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                    7667                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                      8286                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                     5066                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                    7640                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            81.328051                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2579                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               139                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             18.553957                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            81.537714                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2520                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             17.872340                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    81.328051                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.019855                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.019855                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          139                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data    81.537714                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.019907                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.019907                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.033936                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5679                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5679                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data         1719                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1719                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          860                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            860                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2579                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2579                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2579                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2579                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          116                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           116                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           75                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           75                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          191                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            191                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          191                       # number of overall misses
-system.cpu.dcache.overall_misses::total           191                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      9465500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      9465500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      6317000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      6317000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     15782500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     15782500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     15782500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     15782500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1835                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1835                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           94                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5567                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5567                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data         1661                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1661                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          859                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            859                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2520                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2520                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2520                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2520                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          117                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           117                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           76                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           76                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          193                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            193                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          193                       # number of overall misses
+system.cpu.dcache.overall_misses::total           193                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     10226000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     10226000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      7070500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      7070500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     17296500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     17296500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     17296500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     17296500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1778                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1778                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          935                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          935                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2770                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2770                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2770                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2770                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.063215                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.063215                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080214                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080214                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.068953                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.068953                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.068953                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.068953                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81599.137931                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 81599.137931                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84226.666667                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 84226.666667                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 82630.890052                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 82630.890052                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 82630.890052                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 82630.890052                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          124                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         2713                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2713                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2713                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2713                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.065804                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.065804                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081283                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.081283                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.071139                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.071139                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.071139                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.071139                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87401.709402                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 87401.709402                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93032.894737                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 93032.894737                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 89619.170984                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 89619.170984                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 89619.170984                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 89619.170984                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          132                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    41.333333                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs           44                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           52                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           52                       # number of ReadReq MSHR hits
@@ -639,96 +649,96 @@ system.cpu.dcache.demand_mshr_hits::cpu.data           52
 system.cpu.dcache.demand_mshr_hits::total           52                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.overall_mshr_hits::cpu.data           52                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total           52                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           64                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           64                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           75                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           75                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          139                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          139                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          139                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          139                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5739000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5739000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6242000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6242000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11981000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     11981000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11981000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     11981000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.034877                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.034877                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.080214                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.080214                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.050181                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.050181                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.050181                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.050181                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89671.875000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89671.875000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83226.666667                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83226.666667                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86194.244604                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 86194.244604                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86194.244604                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 86194.244604                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           65                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           65                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           76                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           76                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6448000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6448000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6994500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6994500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13442500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     13442500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13442500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     13442500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036558                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036558                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081283                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081283                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051972                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.051972                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051972                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.051972                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        99200                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        99200                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92032.894737                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92032.894737                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95336.879433                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 95336.879433                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95336.879433                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 95336.879433                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           130.610950                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1656                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               279                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.935484                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           130.260906                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1641                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               278                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.902878                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   130.610950                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.063775                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.063775                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          279                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          148                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.136230                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4363                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4363                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         1656                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1656                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1656                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1656                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1656                       # number of overall hits
-system.cpu.icache.overall_hits::total            1656                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          386                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           386                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          386                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            386                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          386                       # number of overall misses
-system.cpu.icache.overall_misses::total           386                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     29282500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     29282500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     29282500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     29282500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     29282500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     29282500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2042                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2042                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2042                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2042                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2042                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2042                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.189030                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.189030                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.189030                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.189030                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.189030                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.189030                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75861.398964                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75861.398964                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75861.398964                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75861.398964                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75861.398964                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75861.398964                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          121                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   130.260906                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.063604                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.063604                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          278                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          140                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.135742                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4330                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4330                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst         1641                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1641                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1641                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1641                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1641                       # number of overall hits
+system.cpu.icache.overall_hits::total            1641                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          385                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           385                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          385                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            385                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          385                       # number of overall misses
+system.cpu.icache.overall_misses::total           385                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     30146000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     30146000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     30146000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     30146000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     30146000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     30146000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2026                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2026                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2026                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2026                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2026                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2026                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.190030                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.190030                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.190030                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.190030                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.190030                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.190030                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78301.298701                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 78301.298701                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 78301.298701                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 78301.298701                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 78301.298701                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 78301.298701                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          171                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    40.333333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           57                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          107                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_hits::total          107                       # number of ReadReq MSHR hits
@@ -736,238 +746,238 @@ system.cpu.icache.demand_mshr_hits::cpu.inst          107
 system.cpu.icache.demand_mshr_hits::total          107                       # number of demand (read+write) MSHR hits
 system.cpu.icache.overall_mshr_hits::cpu.inst          107                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_hits::total          107                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          279                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          279                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          279                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          279                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          279                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          279                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22839500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22839500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22839500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22839500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22839500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22839500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.136631                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.136631                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.136631                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.136631                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.136631                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.136631                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81862.007168                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81862.007168                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81862.007168                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 81862.007168                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81862.007168                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 81862.007168                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          278                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          278                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          278                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          278                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23206500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     23206500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23206500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     23206500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23206500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     23206500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.137216                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.137216                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.137216                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.137216                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.137216                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.137216                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83476.618705                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83476.618705                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83476.618705                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 83476.618705                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83476.618705                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 83476.618705                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          212.046379                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          211.897546                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              417                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.002398                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              418                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.002392                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   130.650071                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    81.396308                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003987                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.002484                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006471                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          417                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          223                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012726                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             3761                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            3761                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   130.293933                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    81.603612                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003976                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.002490                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006467                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          418                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          186                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          232                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012756                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3770                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3770                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data           75                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           75                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          278                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          278                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data           64                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total           64                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          278                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          139                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           417                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          278                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          139                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          417                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6129000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      6129000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     22409000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     22409000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5642000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      5642000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     22409000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     11771000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     34180000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     22409000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     11771000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     34180000                       # number of overall miss cycles
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           75                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           75                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          279                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          279                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           64                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total           64                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          279                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          139                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          418                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          279                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          139                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          418                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           76                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           76                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          277                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          277                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           65                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           65                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          277                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          141                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           418                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          277                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          141                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          418                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6880500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6880500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     22777500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     22777500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      6350000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      6350000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     22777500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     13230500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     36008000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     22777500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     13230500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     36008000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           76                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           76                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          278                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          278                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           65                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           65                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          278                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          141                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          419                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          278                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          141                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          419                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996416                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996416                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996403                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996403                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996416                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996403                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.997608                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996416                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997613                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996403                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997608                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        81720                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        81720                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80607.913669                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80607.913669                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88156.250000                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88156.250000                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80607.913669                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84683.453237                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81966.426859                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80607.913669                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84683.453237                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81966.426859                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.997613                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90532.894737                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90532.894737                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82229.241877                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82229.241877                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97692.307692                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97692.307692                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82229.241877                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93833.333333                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 86143.540670                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82229.241877                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93833.333333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 86143.540670                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           75                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           75                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          278                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          278                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           64                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total           64                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          139                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          417                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          139                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          417                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5379000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5379000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19629000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19629000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5002000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      5002000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19629000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10381000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     30010000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19629000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10381000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     30010000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           76                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           76                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          277                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          277                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           65                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           65                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          277                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          418                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          277                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          418                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      6120500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      6120500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     20007500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     20007500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5700000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      5700000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     20007500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11820500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     31828000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     20007500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11820500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     31828000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996416                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996403                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996403                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996403                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997608                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997613                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996403                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997608                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        71720                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        71720                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70607.913669                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70607.913669                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78156.250000                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78156.250000                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70607.913669                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74683.453237                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71966.426859                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70607.913669                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74683.453237                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71966.426859                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests          418                       # Total number of requests made to the snoop filter.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997613                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80532.894737                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80532.894737                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72229.241877                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72229.241877                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87692.307692                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87692.307692                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72229.241877                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83833.333333                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76143.540670                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72229.241877                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83833.333333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76143.540670                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests          419                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           343                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           75                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           75                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          279                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq           64                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          558                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          278                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               836                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8896                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              26752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq           76                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           76                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          278                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           65                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          556                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          282                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               838                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17792                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              26816                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
 system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples          418                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.002392                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.048912                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          419                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.002387                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.048853                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                417     99.76%     99.76% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                418     99.76%     99.76% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  1      0.24%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            418                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         209000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        418500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        208500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests           417                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_fanout::total            419                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         209500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        417000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        211500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
+system.membus.snoop_filter.tot_requests           418                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     21382500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     22466500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                342                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                75                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               75                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                76                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               76                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq           342                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          834                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total          834                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    834                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total        26688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   26688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          836                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total          836                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    836                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total        26752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   26752                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples               417                       # Request fanout histogram
+system.membus.snoop_fanout::samples               418                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     417    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     418    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 417                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              503500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2228500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             10.4                       # Layer utilization (%)
+system.membus.snoop_fanout::total                 418                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              506000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2231250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              9.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index f585dbbc0..49adea038 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -105,18 +115,28 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 system=system
 port=system.ruby.l1_cntrl0.sequencer.slave[3]
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 int_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 pio_addr=2305843009213693952
 pio_latency=100
+power_model=Null
 system=system
 int_master=system.ruby.l1_cntrl0.sequencer.slave[4]
 int_slave=system.ruby.l1_cntrl0.sequencer.master[1]
@@ -136,8 +156,13 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 system=system
 port=system.ruby.l1_cntrl0.sequencer.slave[2]
 
@@ -155,7 +180,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 kvmInSE=false
@@ -178,27 +203,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -210,6 +235,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -217,12 +243,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -244,9 +275,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -260,12 +291,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -282,6 +318,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
@@ -289,6 +326,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
 eventq_index=0
 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestToDir=system.ruby.dir_cntrl0.requestToDir
 responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -362,11 +403,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.cpu.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 forwardToCache=system.ruby.l1_cntrl0.forwardToCache
 issue_latency=2
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestFromCache=system.ruby.l1_cntrl0.requestFromCache
 responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -448,17 +494,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.cacheMemory
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.cacheMemory
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave
@@ -472,18 +523,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
 netifs=
 number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
 ruby_system=system.ruby
 topology=Crossbar
@@ -650,32 +706,206 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14
+power_model=Null
 router_id=0
 virt_nets=5
 
@@ -788,8 +1018,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14
+power_model=Null
 router_id=1
 virt_nets=5
 
@@ -902,8 +1138,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19
+power_model=Null
 router_id=2
 virt_nets=5
 
@@ -1050,9 +1292,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 944308c19..60c5b94b3 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:41:03
-gem5 started Jan 21 2016 14:41:52
-gem5 executing on zizzer, pid 17892
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:09:01
+gem5 executing on e108600-lin, pid 17636
+command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing-ruby
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 87948 because target called exit()
+Exiting @ tick 91859 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 5369fe205..61c4aeeab 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000088                       # Number of seconds simulated
-sim_ticks                                       87948                       # Number of ticks simulated
-final_tick                                      87948                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000092                       # Number of seconds simulated
+sim_ticks                                       91859                       # Number of ticks simulated
+final_tick                                      91859                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  83700                       # Simulator instruction rate (inst/s)
-host_op_rate                                   151608                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1367648                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 473696                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  42401                       # Simulator instruction rate (inst/s)
+host_op_rate                                    76797                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 723555                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 431840                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        88128                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              88128                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_written::ruby.dir_cntrl0        87872                       # Number of bytes written to this memory
@@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0         1377                       #
 system.mem_ctrls.num_reads::total                1377                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_writes::ruby.dir_cntrl0         1373                       # Number of write requests responded to by this memory
 system.mem_ctrls.num_writes::total               1373                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0   1002046664                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            1002046664                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    999135853                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            999135853                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   2001182517                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           2001182517                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    959383403                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             959383403                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    956596523                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            956596523                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   1915979926                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1915979926                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1377                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                       1373                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1377                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrls.writeBursts                     1373                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  40320                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   47808                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   39936                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM                  41408                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   46720                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   41728                       # Total number of bytes written to DRAM
 system.mem_ctrls.bytesReadSys                   88128                       # Total read bytes from the system interface side
 system.mem_ctrls.bytesWrittenSys                87872                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    747                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   722                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ                    730                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   702                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0                59                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1                 1                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0                60                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1                 2                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::2                 6                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3                 9                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4                52                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5                55                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6                37                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7                64                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8                25                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9               119                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10              121                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11               21                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3                10                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4                51                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5                53                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6                39                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7                57                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8                28                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9               129                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10              115                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11               24                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::12                2                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13               21                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13               28                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14                8                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15               30                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0                51                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1                 1                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15               35                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0                55                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1                 2                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2                 6                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3                 7                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3                 8                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::4                52                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5                50                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6                36                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7                66                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8                25                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9               120                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10              125                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11               23                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5                48                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6                38                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7                60                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8                28                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9               130                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10              123                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11               24                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::12                2                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13               21                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13               31                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::14                8                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15               31                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15               37                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         87868                       # Total gap between requests
+system.mem_ctrls.totGap                         91773                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3                    0                       # Wr
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::6                 1373                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     630                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0                     647                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
@@ -137,23 +137,23 @@ system.mem_ctrls.wrQLenPdf::12                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::15                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      8                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     41                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                     40                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     40                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     38                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     33                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                     43                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                     44                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                     40                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
@@ -185,98 +185,108 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          271                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    293.313653                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   193.377642                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   283.497497                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           72     26.57%     26.57% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           83     30.63%     57.20% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           37     13.65%     70.85% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           23      8.49%     79.34% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           21      7.75%     87.08% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            5      1.85%     88.93% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            7      2.58%     91.51% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            3      1.11%     92.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           20      7.38%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          271                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples           38                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      16.289474                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     16.048466                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      3.463383                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13             1      2.63%      2.63% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15            15     39.47%     42.11% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            16     42.11%     84.21% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             4     10.53%     94.74% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21             1      2.63%     97.37% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35             1      2.63%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total            38                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples           38                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.421053                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.397539                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.919212                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               31     81.58%     81.58% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                5     13.16%     94.74% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                2      5.26%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total            38                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         9303                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   21273                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       3150                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        14.77                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples          263                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    304.669202                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   201.653389                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   284.735596                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           72     27.38%     27.38% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           68     25.86%     53.23% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           44     16.73%     69.96% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           29     11.03%     80.99% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           12      4.56%     85.55% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            9      3.42%     88.97% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            6      2.28%     91.25% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            3      1.14%     92.40% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           20      7.60%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          263                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples           40                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      16.100000                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     15.846587                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      3.484765                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13             3      7.50%      7.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15            12     30.00%     37.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17            19     47.50%     85.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19             4     10.00%     95.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21             1      2.50%     97.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35             1      2.50%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total            40                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples           40                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.300000                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.281263                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.822753                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               35     87.50%     87.50% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                3      7.50%     95.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19                2      5.00%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total            40                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                        12721                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   25014                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       3235                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        19.66                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   33.77                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       458.45                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       454.09                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   1002.05                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    999.14                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   38.66                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       450.78                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       454.26                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    959.38                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    956.60                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         7.13                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     3.58                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtil                         7.07                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     3.52                       # Data bus utilization in percentage for reads
 system.mem_ctrls.busUtilWrite                    3.55                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      25.04                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      420                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     556                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 66.67                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                85.41                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         31.95                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    76.19                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   657720                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   365400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 3407040                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                2623104                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              5594160                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             51093432                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy              6724800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               70465656                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            820.264661                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE        10886                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF          2860                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         72174                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                  1368360                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   760200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 4268160                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                3680640                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              5594160                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             54919728                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              3368400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               73959648                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            860.936931                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE         5575                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          2860                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         77782                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.avgWrQLen                      25.84                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      435                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     591                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 67.23                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                88.08                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         33.37                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    77.85                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   664020                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   340032                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 3175872                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                2246688                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         7375680.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             10273224                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy               269568                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        25208136                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy         4818816                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy     743760.000000                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               55115796                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            600.004311                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                68393                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE          346                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          3126                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF          798                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN        12549                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         19759                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        55281                       # Time in different power states
+system.mem_ctrls_1.actEnergy                  1285200                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   676200                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 4215456                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                3198816                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         6761040.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy              9576912                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               183552                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy        28147512                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy         3322368                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               57367056                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            624.512089                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                70328                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE          150                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          2866                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         8652                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         18464                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN        61727                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
 system.cpu.apic_clk_domain.clock                   16                       # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON           87948                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            87948                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON           91859                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            91859                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5381                       # Number of instructions committed
@@ -297,7 +307,7 @@ system.cpu.num_mem_refs                          1988                       # nu
 system.cpu.num_load_insts                        1053                       # Number of load instructions
 system.cpu.num_store_insts                        935                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.999989                       # Number of idle cycles
-system.cpu.num_busy_cycles               87947.000011                       # Number of busy cycles
+system.cpu.num_busy_cycles               91858.000011                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.999989                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000011                       # Percentage of idle cycles
 system.cpu.Branches                              1208                       # Number of branches fetched
@@ -337,7 +347,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       9748                       # Class of executed instruction
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   2750                       # delay histogram for all message
@@ -353,10 +363,10 @@ system.ruby.outstanding_req_hist_seqr::total         8852
 system.ruby.latency_hist_seqr::bucket_size           64                      
 system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples           8852                      
-system.ruby.latency_hist_seqr::mean          8.935382                      
-system.ruby.latency_hist_seqr::gmean         1.815175                      
-system.ruby.latency_hist_seqr::stdev        22.675647                      
-system.ruby.latency_hist_seqr            |        8624     97.42%     97.42% |         191      2.16%     99.58% |          24      0.27%     99.85% |           5      0.06%     99.91% |           2      0.02%     99.93% |           6      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean          9.377203                      
+system.ruby.latency_hist_seqr::gmean         1.827971                      
+system.ruby.latency_hist_seqr::stdev        23.652747                      
+system.ruby.latency_hist_seqr            |        8226     92.93%     92.93% |         589      6.65%     99.58% |          26      0.29%     99.88% |           4      0.05%     99.92% |           3      0.03%     99.95% |           4      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist_seqr::total             8852                      
 system.ruby.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.hit_latency_hist_seqr::max_bucket            9                      
@@ -368,21 +378,21 @@ system.ruby.hit_latency_hist_seqr::total         7475
 system.ruby.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.miss_latency_hist_seqr::samples         1377                      
-system.ruby.miss_latency_hist_seqr::mean    52.012346                      
-system.ruby.miss_latency_hist_seqr::gmean    46.179478                      
-system.ruby.miss_latency_hist_seqr::stdev    33.292581                      
-system.ruby.miss_latency_hist_seqr       |        1149     83.44%     83.44% |         191     13.87%     97.31% |          24      1.74%     99.06% |           5      0.36%     99.42% |           2      0.15%     99.56% |           6      0.44%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean    54.852578                      
+system.ruby.miss_latency_hist_seqr::gmean    48.312712                      
+system.ruby.miss_latency_hist_seqr::stdev    33.880423                      
+system.ruby.miss_latency_hist_seqr       |         751     54.54%     54.54% |         589     42.77%     97.31% |          26      1.89%     99.20% |           4      0.29%     99.49% |           3      0.22%     99.71% |           4      0.29%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist_seqr::total         1377                      
 system.ruby.Directory.incomplete_times_seqr         1376                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         7475                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses         1377                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         8852                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     7.817119                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     7.484297                      
 system.ruby.network.routers0.msg_count.Control::2         1377                      
 system.ruby.network.routers0.msg_count.Data::2         1373                      
 system.ruby.network.routers0.msg_count.Response_Data::4         1377                      
@@ -391,8 +401,8 @@ system.ruby.network.routers0.msg_bytes.Control::2        11016
 system.ruby.network.routers0.msg_bytes.Data::2        98856                      
 system.ruby.network.routers0.msg_bytes.Response_Data::4        99144                      
 system.ruby.network.routers0.msg_bytes.Writeback_Control::3        10984                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     7.817119                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     7.484297                      
 system.ruby.network.routers1.msg_count.Control::2         1377                      
 system.ruby.network.routers1.msg_count.Data::2         1373                      
 system.ruby.network.routers1.msg_count.Response_Data::4         1377                      
@@ -401,8 +411,8 @@ system.ruby.network.routers1.msg_bytes.Control::2        11016
 system.ruby.network.routers1.msg_bytes.Data::2        98856                      
 system.ruby.network.routers1.msg_bytes.Response_Data::4        99144                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::3        10984                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     7.817119                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     7.484297                      
 system.ruby.network.routers2.msg_count.Control::2         1377                      
 system.ruby.network.routers2.msg_count.Data::2         1373                      
 system.ruby.network.routers2.msg_count.Response_Data::4         1377                      
@@ -411,7 +421,7 @@ system.ruby.network.routers2.msg_bytes.Control::2        11016
 system.ruby.network.routers2.msg_bytes.Data::2        98856                      
 system.ruby.network.routers2.msg_bytes.Response_Data::4        99144                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3        10984                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Control            4131                      
 system.ruby.network.msg_count.Data               4119                      
 system.ruby.network.msg_count.Response_Data         4131                      
@@ -420,33 +430,33 @@ system.ruby.network.msg_byte.Control            33048
 system.ruby.network.msg_byte.Data              296568                      
 system.ruby.network.msg_byte.Response_Data       297432                      
 system.ruby.network.msg_byte.Writeback_Control        32952                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        87948                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     7.826215                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        91859                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     7.493006                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1377                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1373                      
 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        99144                      
 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        10984                      
-system.ruby.network.routers0.throttle1.link_utilization     7.808023                      
+system.ruby.network.routers0.throttle1.link_utilization     7.475588                      
 system.ruby.network.routers0.throttle1.msg_count.Control::2         1377                      
 system.ruby.network.routers0.throttle1.msg_count.Data::2         1373                      
 system.ruby.network.routers0.throttle1.msg_bytes.Control::2        11016                      
 system.ruby.network.routers0.throttle1.msg_bytes.Data::2        98856                      
-system.ruby.network.routers1.throttle0.link_utilization     7.808023                      
+system.ruby.network.routers1.throttle0.link_utilization     7.475588                      
 system.ruby.network.routers1.throttle0.msg_count.Control::2         1377                      
 system.ruby.network.routers1.throttle0.msg_count.Data::2         1373                      
 system.ruby.network.routers1.throttle0.msg_bytes.Control::2        11016                      
 system.ruby.network.routers1.throttle0.msg_bytes.Data::2        98856                      
-system.ruby.network.routers1.throttle1.link_utilization     7.826215                      
+system.ruby.network.routers1.throttle1.link_utilization     7.493006                      
 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1377                      
 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1373                      
 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        99144                      
 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        10984                      
-system.ruby.network.routers2.throttle0.link_utilization     7.826215                      
+system.ruby.network.routers2.throttle0.link_utilization     7.493006                      
 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1377                      
 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1373                      
 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        99144                      
 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        10984                      
-system.ruby.network.routers2.throttle1.link_utilization     7.808023                      
+system.ruby.network.routers2.throttle1.link_utilization     7.475588                      
 system.ruby.network.routers2.throttle1.msg_count.Control::2         1377                      
 system.ruby.network.routers2.throttle1.msg_count.Data::2         1373                      
 system.ruby.network.routers2.throttle1.msg_bytes.Control::2        11016                      
@@ -464,10 +474,10 @@ system.ruby.delayVCHist.vnet_2::total            1373                       # de
 system.ruby.LD.latency_hist_seqr::bucket_size           32                      
 system.ruby.LD.latency_hist_seqr::max_bucket          319                      
 system.ruby.LD.latency_hist_seqr::samples         1045                      
-system.ruby.LD.latency_hist_seqr::mean      22.607656                      
-system.ruby.LD.latency_hist_seqr::gmean      5.952637                      
-system.ruby.LD.latency_hist_seqr::stdev     28.358291                      
-system.ruby.LD.latency_hist_seqr         |         546     52.25%     52.25% |         420     40.19%     92.44% |          70      6.70%     99.14% |           2      0.19%     99.33% |           2      0.19%     99.52% |           4      0.38%     99.90% |           0      0.00%     99.90% |           1      0.10%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::mean      23.607656                      
+system.ruby.LD.latency_hist_seqr::gmean      6.057935                      
+system.ruby.LD.latency_hist_seqr::stdev     29.475705                      
+system.ruby.LD.latency_hist_seqr         |         546     52.25%     52.25% |         330     31.58%     83.83% |         162     15.50%     99.33% |           1      0.10%     99.43% |           4      0.38%     99.81% |           1      0.10%     99.90% |           0      0.00%     99.90% |           1      0.10%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_seqr::total          1045                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
@@ -479,18 +489,18 @@ system.ruby.LD.hit_latency_hist_seqr::total          546
 system.ruby.LD.miss_latency_hist_seqr::bucket_size           32                      
 system.ruby.LD.miss_latency_hist_seqr::max_bucket          319                      
 system.ruby.LD.miss_latency_hist_seqr::samples          499                      
-system.ruby.LD.miss_latency_hist_seqr::mean    46.250501                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    41.916728                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    24.776985                      
-system.ruby.LD.miss_latency_hist_seqr    |           0      0.00%      0.00% |         420     84.17%     84.17% |          70     14.03%     98.20% |           2      0.40%     98.60% |           2      0.40%     99.00% |           4      0.80%     99.80% |           0      0.00%     99.80% |           1      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean    48.344689                      
+system.ruby.LD.miss_latency_hist_seqr::gmean    43.484561                      
+system.ruby.LD.miss_latency_hist_seqr::stdev    25.453032                      
+system.ruby.LD.miss_latency_hist_seqr    |           0      0.00%      0.00% |         330     66.13%     66.13% |         162     32.46%     98.60% |           1      0.20%     98.80% |           4      0.80%     99.60% |           1      0.20%     99.80% |           0      0.00%     99.80% |           1      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist_seqr::total          499                      
 system.ruby.ST.latency_hist_seqr::bucket_size           64                      
 system.ruby.ST.latency_hist_seqr::max_bucket          639                      
 system.ruby.ST.latency_hist_seqr::samples          935                      
-system.ruby.ST.latency_hist_seqr::mean      15.124064                      
-system.ruby.ST.latency_hist_seqr::gmean      2.829099                      
-system.ruby.ST.latency_hist_seqr::stdev     31.003309                      
-system.ruby.ST.latency_hist_seqr         |         897     95.94%     95.94% |          28      2.99%     98.93% |           5      0.53%     99.47% |           3      0.32%     99.79% |           0      0.00%     99.79% |           2      0.21%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::mean      16.455615                      
+system.ruby.ST.latency_hist_seqr::gmean      2.877223                      
+system.ruby.ST.latency_hist_seqr::stdev     34.720603                      
+system.ruby.ST.latency_hist_seqr         |         821     87.81%     87.81% |         102     10.91%     98.72% |           6      0.64%     99.36% |           2      0.21%     99.57% |           2      0.21%     99.79% |           2      0.21%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist_seqr::total           935                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
@@ -502,18 +512,18 @@ system.ruby.ST.hit_latency_hist_seqr::total          681
 system.ruby.ST.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.ST.miss_latency_hist_seqr::samples          254                      
-system.ruby.ST.miss_latency_hist_seqr::mean    52.992126                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    45.979346                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    39.646660                      
-system.ruby.ST.miss_latency_hist_seqr    |         216     85.04%     85.04% |          28     11.02%     96.06% |           5      1.97%     98.03% |           3      1.18%     99.21% |           0      0.00%     99.21% |           2      0.79%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean    57.893701                      
+system.ruby.ST.miss_latency_hist_seqr::gmean    48.924758                      
+system.ruby.ST.miss_latency_hist_seqr::stdev    45.645746                      
+system.ruby.ST.miss_latency_hist_seqr    |         140     55.12%     55.12% |         102     40.16%     95.28% |           6      2.36%     97.64% |           2      0.79%     98.43% |           2      0.79%     99.21% |           2      0.79%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total          254                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples         6864                      
-system.ruby.IFETCH.latency_hist_seqr::mean     6.015589                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.426336                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    19.173758                      
-system.ruby.IFETCH.latency_hist_seqr     |        6753     98.38%     98.38% |          91      1.33%     99.71% |          13      0.19%     99.90% |           1      0.01%     99.91% |           2      0.03%     99.94% |           4      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     6.251748                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     1.432185                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    19.434647                      
+system.ruby.IFETCH.latency_hist_seqr     |        6521     95.00%     95.00% |         324      4.72%     99.72% |          15      0.22%     99.94% |           1      0.01%     99.96% |           1      0.01%     99.97% |           2      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total         6864                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
@@ -525,10 +535,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total         6241
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist_seqr::samples          623                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    56.260032                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    50.022291                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    35.712767                      
-system.ruby.IFETCH.miss_latency_hist_seqr |         512     82.18%     82.18% |          91     14.61%     96.79% |          13      2.09%     98.88% |           1      0.16%     99.04% |           2      0.32%     99.36% |           4      0.64%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    58.861958                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    52.329270                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    33.443818                      
+system.ruby.IFETCH.miss_latency_hist_seqr |         280     44.94%     44.94% |         324     52.01%     96.95% |          15      2.41%     99.36% |           1      0.16%     99.52% |           1      0.16%     99.68% |           2      0.32%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist_seqr::total          623                      
 system.ruby.RMW_Read.latency_hist_seqr::bucket_size            4                      
 system.ruby.RMW_Read.latency_hist_seqr::max_bucket           39                      
@@ -556,10 +566,10 @@ system.ruby.RMW_Read.miss_latency_hist_seqr::total            1
 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::samples         1377                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean    52.012346                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    46.179478                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    33.292581                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |        1149     83.44%     83.44% |         191     13.87%     97.31% |          24      1.74%     99.06% |           5      0.36%     99.42% |           2      0.15%     99.56% |           6      0.44%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean    54.852578                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    48.312712                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    33.880423                      
+system.ruby.Directory.miss_mach_latency_hist_seqr |         751     54.54%     54.54% |         589     42.77%     97.31% |          26      1.89%     99.20% |           4      0.29%     99.49% |           3      0.22%     99.71% |           4      0.29%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist_seqr::total         1377                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket            9                      
@@ -590,26 +600,26 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples          499                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    46.250501                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    41.916728                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    24.776985                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         420     84.17%     84.17% |          70     14.03%     98.20% |           2      0.40%     98.60% |           2      0.40%     99.00% |           4      0.80%     99.80% |           0      0.00%     99.80% |           1      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    48.344689                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    43.484561                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    25.453032                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         330     66.13%     66.13% |         162     32.46%     98.60% |           1      0.20%     98.80% |           4      0.80%     99.60% |           1      0.20%     99.80% |           0      0.00%     99.80% |           1      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total          499                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          254                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    52.992126                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    45.979346                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    39.646660                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |         216     85.04%     85.04% |          28     11.02%     96.06% |           5      1.97%     98.03% |           3      1.18%     99.21% |           0      0.00%     99.21% |           2      0.79%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    57.893701                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    48.924758                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    45.645746                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |         140     55.12%     55.12% |         102     40.16%     95.28% |           6      2.36%     97.64% |           2      0.79%     98.43% |           2      0.79%     99.21% |           2      0.79%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          254                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples          623                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    56.260032                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    50.022291                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    35.712767                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         512     82.18%     82.18% |          91     14.61%     96.79% |          13      2.09%     98.88% |           1      0.16%     99.04% |           2      0.32%     99.36% |           4      0.64%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    58.861958                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    52.329270                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    33.443818                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         280     44.94%     44.94% |         324     52.01%     96.95% |          15      2.41%     99.36% |           1      0.16%     99.52% |           1      0.16%     99.68% |           2      0.32%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total          623                      
 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::bucket_size            4                      
 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::max_bucket           39                      
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
index 83c5a15fe..965e2a045 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -600,7 +600,7 @@ size=48
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -740,6 +740,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -751,7 +752,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -759,29 +760,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -801,6 +809,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -810,7 +819,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -832,9 +841,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
index b07f24804..237d01682 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:26
-gem5 executing on e108600-lin, pid 39592
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:48
+gem5 executing on e108600-lin, pid 28095
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt
 
 Global frequency set at 1000000000000 ticks per second
@@ -14,4 +14,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 Hello world!
 Hello world!
-Exiting @ tick 25580500 because target called exit()
+Exiting @ tick 26661500 because target called exit()
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
index ad56ff040..0fd976f9c 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
@@ -1,43 +1,43 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000026                       # Number of seconds simulated
-sim_ticks                                    25607000                       # Number of ticks simulated
-final_tick                                   25607000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000027                       # Number of seconds simulated
+sim_ticks                                    26661500                       # Number of ticks simulated
+final_tick                                   26661500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 110915                       # Simulator instruction rate (inst/s)
-host_op_rate                                   110902                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              222369986                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 254744                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
+host_inst_rate                                  67147                       # Simulator instruction rate (inst/s)
+host_op_rate                                    67138                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              140157650                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253164                       # Number of bytes of host memory used
+host_seconds                                     0.19                       # Real time elapsed on the host
 sim_insts                                       12770                       # Number of instructions simulated
 sim_ops                                         12770                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     25607000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst             39936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             21824                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                61760                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        39936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           39936                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                624                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                341                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   965                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1559573554                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            852266958                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2411840512                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1559573554                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1559573554                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1559573554                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           852266958                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2411840512                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           966                       # Number of read requests accepted
+system.physmem.pwrStateResidencyTicks::UNDEFINED     26661500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst             40000                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             21888                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                61888                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        40000                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           40000                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                625                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                342                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   967                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1500290681                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            820959061                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2321249742                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1500290681                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1500290681                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1500290681                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           820959061                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2321249742                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           968                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         966                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         968                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    61824                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    61952                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     61824                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     61952                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -47,11 +47,11 @@ system.physmem.perBankRdBursts::1                 150                       # Pe
 system.physmem.perBankRdBursts::2                  77                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                  58                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  90                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  46                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                  32                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                  45                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                  33                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  50                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                  41                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                  37                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                  42                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                  38                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 28                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                 34                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 15                       # Per bank write bursts
@@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        25577000                       # Total gap between requests
+system.physmem.totGap                        26630500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     966                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     968                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -91,14 +91,14 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       351                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       323                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       171                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        89                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        23                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       332                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       313                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       185                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        94                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        37                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
@@ -187,105 +187,115 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          211                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      278.748815                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     172.887192                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     291.495109                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             76     36.02%     36.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           57     27.01%     63.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           23     10.90%     73.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           12      5.69%     79.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            8      3.79%     83.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           11      5.21%     88.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            6      2.84%     91.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            6      2.84%     94.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           12      5.69%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            211                       # Bytes accessed per row activation
-system.physmem.totQLat                       14120500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  32233000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      4830000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       14617.49                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          202                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      289.584158                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     180.299588                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     295.891915                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             69     34.16%     34.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           55     27.23%     61.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           20      9.90%     71.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           16      7.92%     79.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            9      4.46%     83.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            7      3.47%     87.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            9      4.46%     91.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      1.49%     93.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           14      6.93%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            202                       # Bytes accessed per row activation
+system.physmem.totQLat                       15942250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  34092250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      4840000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       16469.27                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  33367.49                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        2414.34                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  35219.27                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        2323.65                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     2414.34                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     2323.65                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          18.86                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      18.86                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          18.15                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      18.15                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         2.46                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        745                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        755                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.12                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   78.00                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        26477.23                       # Average gap between requests
-system.physmem.pageHitRate                      77.12                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     861840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     470250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   4477200                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        27510.85                       # Average gap between requests
+system.physmem.pageHitRate                      78.00                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     849660                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     436425                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   4191180                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               16092810                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  54750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 23482530                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              994.232548                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         763000                       # Time in different power states
+system.physmem_0.refreshEnergy           1843920.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                6127500                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  47520                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy           5972460                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy              1440                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                 19470105                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              730.243038                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime               12953500                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE          40500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        22830000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     703080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     383625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   2628600                       # Energy for read commands per rank (pJ)
+system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN         3750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        12735000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     13102250                       # Time in different power states
+system.physmem_1.actEnergy                     671160                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     330165                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   2720340                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               15488325                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 585000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 21314310                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              902.431754                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         878500                       # Time in different power states
+system.physmem_1.refreshEnergy           1843920.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                4612440                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 162240                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy           6908970                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy            373920                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                 17623155                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              660.971589                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime               16131250                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE         312000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        21974000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     25607000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    4896                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              2917                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               793                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 3827                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                    1151                       # Number of BTB hits
+system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN       973000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         9438250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN     15158250                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     26661500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                    4864                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              2895                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               795                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 3714                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                    1183                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             30.075777                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     688                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 51                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups             820                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits                149                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses              671                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted          136                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             31.852450                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     710                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 56                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups             762                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits                147                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses              615                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          133                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         4131                       # DTB read hits
-system.cpu.dtb.read_misses                         80                       # DTB read misses
+system.cpu.dtb.read_hits                         4130                       # DTB read hits
+system.cpu.dtb.read_misses                         76                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     4211                       # DTB read accesses
-system.cpu.dtb.write_hits                        2002                       # DTB write hits
-system.cpu.dtb.write_misses                        47                       # DTB write misses
+system.cpu.dtb.read_accesses                     4206                       # DTB read accesses
+system.cpu.dtb.write_hits                        2011                       # DTB write hits
+system.cpu.dtb.write_misses                        48                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    2049                       # DTB write accesses
-system.cpu.dtb.data_hits                         6133                       # DTB hits
-system.cpu.dtb.data_misses                        127                       # DTB misses
+system.cpu.dtb.write_accesses                    2059                       # DTB write accesses
+system.cpu.dtb.data_hits                         6141                       # DTB hits
+system.cpu.dtb.data_misses                        124                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     6260                       # DTB accesses
-system.cpu.itb.fetch_hits                        3841                       # ITB hits
+system.cpu.dtb.data_accesses                     6265                       # DTB accesses
+system.cpu.itb.fetch_hits                        3836                       # ITB hits
 system.cpu.itb.fetch_misses                        50                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    3891                       # ITB accesses
+system.cpu.itb.fetch_accesses                    3886                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -300,313 +310,313 @@ system.cpu.itb.data_acv                             0                       # DT
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload0.num_syscalls                  17                       # Number of system calls
 system.cpu.workload1.num_syscalls                  17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        25607000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            51215                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        26661500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            53324                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles                758                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          28344                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        4896                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1988                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                         10026                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     873                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  478                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      3841                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   575                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              26635                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.064164                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.464308                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles                748                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          27869                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        4864                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               2040                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          9408                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     875                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  344                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                      3836                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   566                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              26300                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.059658                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.449516                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    21569     80.98%     80.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      505      1.90%     82.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      398      1.49%     84.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      435      1.63%     86.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      472      1.77%     87.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      332      1.25%     89.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      468      1.76%     90.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      266      1.00%     91.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2190      8.22%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    21275     80.89%     80.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      504      1.92%     82.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      391      1.49%     84.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      446      1.70%     85.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      478      1.82%     87.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      367      1.40%     89.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      469      1.78%     90.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      276      1.05%     92.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2094      7.96%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                26635                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.095597                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.553432                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    36561                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                 11106                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3971                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   513                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    726                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  381                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   147                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  24763                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   394                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    726                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    36906                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    4191                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1623                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      4148                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  5283                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  23783                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    30                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                    282                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                    398                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                   4456                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               17841                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 29807                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            29789                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                26300                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.091216                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.522635                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    36528                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                 10375                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      3958                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   495                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    725                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  405                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   151                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  24583                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   377                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    725                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    36872                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    3499                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1435                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      4116                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  5434                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  23584                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    36                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                    223                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                    328                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                   4703                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               17574                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 29532                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            29514                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  9154                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     8687                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     8420                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 57                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             45                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      1771                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2529                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1253                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                14                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                4                       # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads                 1973                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores                1111                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads                 6                       # Number of conflicting loads.
-system.cpu.memDep1.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      21942                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  50                       # Number of non-speculative instructions added to the IQ
+system.cpu.rename.skidInsts                      1621                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 1925                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1093                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 7                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
+system.cpu.memDep1.insertedLoads                 2578                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores                1286                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads                15                       # Number of conflicting loads.
+system.cpu.memDep1.conflictingStores                4                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      21800                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  51                       # Number of non-speculative instructions added to the IQ
 system.cpu.iq.iqInstsIssued                     19296                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                47                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            9221                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         4863                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         26635                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.724460                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.451046                       # Number of insts issued each cycle
+system.cpu.iq.iqSquashedInstsIssued                51                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            9080                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         4753                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             17                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         26300                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.733688                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.450617                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               19310     72.50%     72.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                2394      8.99%     81.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1620      6.08%     87.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1274      4.78%     92.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                1030      3.87%     96.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 532      2.00%     98.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 319      1.20%     99.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 102      0.38%     99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  54      0.20%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               18970     72.13%     72.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                2362      8.98%     81.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1626      6.18%     87.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1294      4.92%     92.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                1061      4.03%     96.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 563      2.14%     98.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 282      1.07%     99.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  87      0.33%     99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  55      0.21%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           26635                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           26300                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      28      9.18%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    201     65.90%     75.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    76     24.92%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      29      9.70%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    191     63.88%     73.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    79     26.42%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  6749     65.93%     65.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     65.96% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.96% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2387     23.32%     89.30% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1095     10.70%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5884     66.04%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     66.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2015     22.62%     88.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1006     11.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10236                       # Type of FU issued
+system.cpu.iq.FU_type_0::total                   8910                       # Type of FU issued
 system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu                  6020     66.45%     66.47% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult                    1      0.01%     66.48% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     66.48% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     66.50% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead                 2019     22.28%     88.79% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite                1016     11.21%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu                  6849     65.94%     65.96% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult                    1      0.01%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead                 2411     23.21%     89.21% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite                1121     10.79%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total                   9060                       # Type of FU issued
+system.cpu.iq.FU_type_1::total                  10386                       # Type of FU issued
 system.cpu.iq.FU_type::total                    19296      0.00%      0.00% # Type of FU issued
-system.cpu.iq.rate                           0.376765                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0                      157                       # FU busy when requested
+system.cpu.iq.rate                           0.361863                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0                      151                       # FU busy when requested
 system.cpu.iq.fu_busy_cnt::1                      148                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total                  305                       # FU busy when requested
-system.cpu.iq.fu_busy_rate::0                0.008136                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_cnt::total                  299                       # FU busy when requested
+system.cpu.iq.fu_busy_rate::0                0.007825                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.fu_busy_rate::1                0.007670                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total            0.015806                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              65537                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             31224                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        17544                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate::total            0.015495                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              65200                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             30942                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        17504                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  19575                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  19569                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               93                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               39                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1344                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           20                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          388                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads          740                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           13                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          228                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           261                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads               45                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked           290                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads               97                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread1.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads          788                       # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation           12                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores          246                       # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads         1393                       # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses           14                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation           19                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores          421                       # Number of stores squashed
 system.cpu.iew.lsq.thread1.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread1.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread1.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked           288                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked           234                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    726                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    2949                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                   377                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               22125                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               143                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  4502                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2364                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 50                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     25                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   340                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                    725                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1992                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   420                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               21985                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               174                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  4503                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2379                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 51                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     21                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   390                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             32                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            130                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          639                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  769                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 18625                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0               2260                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1               1960                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total           4220                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               671                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect            134                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          638                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  772                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 18585                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0               1945                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1               2264                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total           4209                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               711                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp::0                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::1                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::total                      0                       # number of swp insts executed
-system.cpu.iew.exec_nop::0                         66                       # number of nop insts executed
-system.cpu.iew.exec_nop::1                         67                       # number of nop insts executed
-system.cpu.iew.exec_nop::total                    133                       # number of nop insts executed
-system.cpu.iew.exec_refs::0                      3318                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::1                      2963                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::total                  6281                       # number of memory reference insts executed
-system.cpu.iew.exec_branches::0                  1546                       # Number of branches executed
-system.cpu.iew.exec_branches::1                  1419                       # Number of branches executed
-system.cpu.iew.exec_branches::total              2965                       # Number of branches executed
-system.cpu.iew.exec_stores::0                    1058                       # Number of stores executed
-system.cpu.iew.exec_stores::1                    1003                       # Number of stores executed
-system.cpu.iew.exec_stores::total                2061                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.363663                       # Inst execution rate
-system.cpu.iew.wb_sent::0                        9379                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1                        8440                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total                   17819                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0                       9213                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::1                       8351                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::total                  17564                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0                   4854                       # num instructions producing a value
-system.cpu.iew.wb_producers::1                   4443                       # num instructions producing a value
-system.cpu.iew.wb_producers::total               9297                       # num instructions producing a value
-system.cpu.iew.wb_consumers::0                   6502                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::1                   5954                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::total              12456                       # num instructions consuming a value
-system.cpu.iew.wb_rate::0                    0.179889                       # insts written-back per cycle
-system.cpu.iew.wb_rate::1                    0.163058                       # insts written-back per cycle
-system.cpu.iew.wb_rate::total                0.342946                       # insts written-back per cycle
-system.cpu.iew.wb_fanout::0                  0.746540                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::1                  0.746221                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::total              0.746387                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts            9288                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop::0                         63                       # number of nop insts executed
+system.cpu.iew.exec_nop::1                         71                       # number of nop insts executed
+system.cpu.iew.exec_nop::total                    134                       # number of nop insts executed
+system.cpu.iew.exec_refs::0                      2942                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::1                      3338                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::total                  6280                       # number of memory reference insts executed
+system.cpu.iew.exec_branches::0                  1393                       # Number of branches executed
+system.cpu.iew.exec_branches::1                  1580                       # Number of branches executed
+system.cpu.iew.exec_branches::total              2973                       # Number of branches executed
+system.cpu.iew.exec_stores::0                     997                       # Number of stores executed
+system.cpu.iew.exec_stores::1                    1074                       # Number of stores executed
+system.cpu.iew.exec_stores::total                2071                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.348530                       # Inst execution rate
+system.cpu.iew.wb_sent::0                        8281                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1                        9496                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total                   17777                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0                       8197                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::1                       9327                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::total                  17524                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0                   4340                       # num instructions producing a value
+system.cpu.iew.wb_producers::1                   4919                       # num instructions producing a value
+system.cpu.iew.wb_producers::total               9259                       # num instructions producing a value
+system.cpu.iew.wb_consumers::0                   5879                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::1                   6619                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::total              12498                       # num instructions consuming a value
+system.cpu.iew.wb_rate::0                    0.153721                       # insts written-back per cycle
+system.cpu.iew.wb_rate::1                    0.174912                       # insts written-back per cycle
+system.cpu.iew.wb_rate::total                0.328633                       # insts written-back per cycle
+system.cpu.iew.wb_fanout::0                  0.738221                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::1                  0.743164                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::total              0.740839                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts            9130                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               647                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        26599                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.481371                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.387327                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               646                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        26282                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.487178                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.404713                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        21475     80.74%     80.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         2692     10.12%     90.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          910      3.42%     94.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          379      1.42%     95.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          247      0.93%     96.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          153      0.58%     97.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          207      0.78%     97.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7          128      0.48%     98.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          408      1.53%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        21298     81.04%     81.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         2499      9.51%     90.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          926      3.52%     94.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          403      1.53%     95.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          249      0.95%     96.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          154      0.59%     97.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          215      0.82%     97.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7          116      0.44%     98.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          422      1.61%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        26599                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        26282                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts::0              6402                       # Number of instructions committed
 system.cpu.commit.committedInsts::1              6402                       # Number of instructions committed
 system.cpu.commit.committedInsts::total         12804                       # Number of instructions committed
@@ -708,256 +718,256 @@ system.cpu.commit.op_class_1::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_1::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_1::total              6402                       # Class of committed instruction
 system.cpu.commit.op_class::total               12804      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.bw_lim_events                   408                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                       113983                       # The number of ROB reads
-system.cpu.rob.rob_writes                       45899                       # The number of ROB writes
-system.cpu.timesIdled                             392                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           24580                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   422                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                       113054                       # The number of ROB reads
+system.cpu.rob.rob_writes                       45570                       # The number of ROB writes
+system.cpu.timesIdled                             413                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           27024                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts::0                     6385                       # Number of Instructions Simulated
 system.cpu.committedInsts::1                     6385                       # Number of Instructions Simulated
 system.cpu.committedInsts::total                12770                       # Number of Instructions Simulated
 system.cpu.committedOps::0                       6385                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedOps::1                       6385                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedOps::total                  12770                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi::0                            8.021143                       # CPI: Cycles Per Instruction
-system.cpu.cpi::1                            8.021143                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         4.010572                       # CPI: Total CPI of All Threads
-system.cpu.ipc::0                            0.124671                       # IPC: Instructions Per Cycle
-system.cpu.ipc::1                            0.124671                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.249341                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    23552                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   13174                       # number of integer regfile writes
+system.cpu.cpi::0                            8.351449                       # CPI: Cycles Per Instruction
+system.cpu.cpi::1                            8.351449                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.175724                       # CPI: Total CPI of All Threads
+system.cpu.ipc::0                            0.119740                       # IPC: Instructions Per Cycle
+system.cpu.ipc::1                            0.119740                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.239479                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    23475                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   13132                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      2                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     25607000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     26661500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements::0              0                       # number of replacements
 system.cpu.dcache.tags.replacements::1              0                       # number of replacements
 system.cpu.dcache.tags.replacements::total            0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           214.351374                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                4238                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               341                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.428152                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           216.020971                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                4236                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               342                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.385965                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   214.351374                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.052332                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.052332                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          341                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          264                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.083252                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses             10843                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses            10843                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     25607000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data         3221                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            3221                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1017                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1017                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          4238                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             4238                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         4238                       # number of overall hits
-system.cpu.dcache.overall_hits::total            4238                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          300                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           300                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          713                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          713                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         1013                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1013                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         1013                       # number of overall misses
-system.cpu.dcache.overall_misses::total          1013                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     25278500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     25278500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     49654940                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     49654940                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     74933440                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     74933440                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     74933440                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     74933440                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3521                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3521                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data   216.020971                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.052739                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.052739                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          342                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          270                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.083496                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses             10868                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses            10868                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     26661500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data         3224                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3224                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1012                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1012                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          4236                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4236                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4236                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4236                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          309                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           309                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          718                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          718                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         1027                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1027                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1027                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1027                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     24016000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     24016000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     51330451                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     51330451                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     75346451                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     75346451                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     75346451                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     75346451                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         3533                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         3533                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         5251                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         5251                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         5251                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         5251                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085203                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.085203                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.412139                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.412139                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.192916                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.192916                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.192916                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.192916                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 84261.666667                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 84261.666667                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69642.272090                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69642.272090                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73971.806515                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73971.806515                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73971.806515                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73971.806515                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         6514                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         5263                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         5263                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         5263                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         5263                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.087461                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.087461                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.415029                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.415029                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.195136                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.195136                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.195136                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.195136                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77721.682848                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 77721.682848                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71490.878830                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 71490.878830                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 73365.580331                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73365.580331                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73365.580331                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73365.580331                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         5997                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               137                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               108                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    47.547445                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    55.527778                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          103                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          103                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          568                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          568                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          671                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          671                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          671                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          671                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          197                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          197                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data          145                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total          145                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          342                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          342                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          342                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          342                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     18892500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     18892500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     12000985                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     12000985                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     30893485                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     30893485                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     30893485                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     30893485                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.055950                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.055950                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083815                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083815                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.065130                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.065130                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.065130                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.065130                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 95901.015228                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 95901.015228                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82765.413793                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82765.413793                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90331.827485                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 90331.827485                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90331.827485                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 90331.827485                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     25607000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          110                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          110                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          574                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          574                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          684                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          684                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          684                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          684                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          199                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          199                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data          144                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total          144                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          343                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          343                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          343                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          343                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17847000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     17847000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     12459487                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     12459487                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     30306487                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     30306487                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     30306487                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     30306487                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.056326                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.056326                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.065172                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.065172                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.065172                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.065172                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89683.417085                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89683.417085                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86524.215278                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86524.215278                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88357.104956                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 88357.104956                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88357.104956                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 88357.104956                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     26661500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements::0              7                       # number of replacements
 system.cpu.icache.tags.replacements::1              0                       # number of replacements
 system.cpu.icache.tags.replacements::total            7                       # number of replacements
-system.cpu.icache.tags.tagsinuse           314.192674                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                2931                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               627                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              4.674641                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           318.055053                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                2937                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               628                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              4.676752                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   314.192674                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.153414                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.153414                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          620                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          246                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          374                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.302734                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              8297                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             8297                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     25607000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         2931                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            2931                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          2931                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             2931                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         2931                       # number of overall hits
-system.cpu.icache.overall_hits::total            2931                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          904                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           904                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          904                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            904                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          904                       # number of overall misses
-system.cpu.icache.overall_misses::total           904                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     70022492                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     70022492                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     70022492                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     70022492                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     70022492                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     70022492                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         3835                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         3835                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         3835                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         3835                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         3835                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         3835                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.235724                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.235724                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.235724                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.235724                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.235724                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.235724                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77458.508850                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 77458.508850                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 77458.508850                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 77458.508850                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 77458.508850                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 77458.508850                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         3069                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   318.055053                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.155300                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.155300                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          621                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          238                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          383                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.303223                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              8292                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             8292                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     26661500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst         2937                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            2937                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          2937                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             2937                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         2937                       # number of overall hits
+system.cpu.icache.overall_hits::total            2937                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          895                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           895                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          895                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            895                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          895                       # number of overall misses
+system.cpu.icache.overall_misses::total           895                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     72806995                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     72806995                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     72806995                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     72806995                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     72806995                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     72806995                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         3832                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         3832                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         3832                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         3832                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         3832                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         3832                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.233559                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.233559                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.233559                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.233559                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.233559                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.233559                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81348.597765                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 81348.597765                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 81348.597765                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 81348.597765                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 81348.597765                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 81348.597765                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         3504                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                61                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                58                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    50.311475                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    60.413793                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.writebacks::writebacks            7                       # number of writebacks
 system.cpu.icache.writebacks::total                 7                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          277                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          277                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          277                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          277                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          277                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          277                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          627                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          627                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          627                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          627                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          627                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          627                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     52227494                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     52227494                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     52227494                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     52227494                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     52227494                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     52227494                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.163494                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.163494                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.163494                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.163494                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.163494                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.163494                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83297.438596                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83297.438596                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83297.438596                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 83297.438596                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83297.438596                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 83297.438596                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     25607000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          267                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          267                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          267                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          267                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          267                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          267                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          628                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          628                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          628                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          628                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          628                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          628                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     54757996                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     54757996                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     54757996                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     54757996                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     54757996                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     54757996                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.163883                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.163883                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.163883                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.163883                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.163883                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.163883                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87194.261146                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87194.261146                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87194.261146                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 87194.261146                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87194.261146                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 87194.261146                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     26661500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements::0             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::1             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::total            0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          529.119750                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          534.674828                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 10                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              965                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.010363                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              967                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.010341                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   314.628551                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   214.491199                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009602                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.006546                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.016147                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          965                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          319                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          646                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.029449                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             8773                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            8773                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     25607000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   318.519168                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   216.155660                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009720                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.006597                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.016317                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          967                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          306                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          661                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.029510                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             8791                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            8791                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     26661500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackClean_hits::writebacks            7                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total            7                       # number of WritebackClean hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            3                       # number of ReadCleanReq hits
@@ -968,66 +978,66 @@ system.cpu.l2cache.overall_hits::cpu.inst            3                       # n
 system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data          145                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total          145                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          624                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          624                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          197                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          197                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          624                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          342                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           966                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          624                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          342                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          966                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     11774500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     11774500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     51248500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     51248500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     18588500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     18588500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     51248500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     30363000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     81611500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     51248500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     30363000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     81611500                       # number of overall miss cycles
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          625                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          625                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          198                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          198                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          625                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          343                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           968                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          625                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          343                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          968                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     12308500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     12308500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     53778000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     53778000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     17466000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     17466000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     53778000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     29774500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     83552500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     53778000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     29774500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     83552500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackClean_accesses::writebacks            7                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total            7                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data          145                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total          145                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          627                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          627                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          197                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          197                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          627                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          342                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          969                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          627                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          342                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          969                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          628                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          628                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          198                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          198                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          628                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          343                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          971                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          628                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          343                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          971                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.995215                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.995215                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.995223                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.995223                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.995215                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.995223                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.996904                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.995215                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.996910                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.995223                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.996904                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81203.448276                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81203.448276                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82129.006410                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82129.006410                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94357.868020                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94357.868020                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82129.006410                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88780.701754                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 84483.954451                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82129.006410                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88780.701754                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 84483.954451                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.996910                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84886.206897                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84886.206897                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86044.800000                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86044.800000                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88212.121212                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88212.121212                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86044.800000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86806.122449                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 86314.566116                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86044.800000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86806.122449                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 86314.566116                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1036,120 +1046,120 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          145                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total          145                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          624                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          624                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          197                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          197                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          624                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          342                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          966                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          624                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          342                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          966                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     10324500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     10324500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     45008500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     45008500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     16628500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     16628500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     45008500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     26953000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     71961500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     45008500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     26953000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     71961500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          625                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          625                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          198                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          198                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          625                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          343                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          968                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          625                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          343                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          968                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     10858500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     10858500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     47528000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     47528000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     15496000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     15496000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     47528000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     26354500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     73882500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     47528000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     26354500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     73882500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.995215                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.995215                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.995223                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.995223                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.995215                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.995223                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.996904                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.995215                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.996910                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.995223                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.996904                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71203.448276                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71203.448276                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72129.006410                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72129.006410                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84408.629442                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84408.629442                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72129.006410                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78809.941520                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74494.306418                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72129.006410                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78809.941520                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74494.306418                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests          976                       # Total number of requests made to the snoop filter.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.996910                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74886.206897                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74886.206897                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76044.800000                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76044.800000                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78262.626263                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78262.626263                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76044.800000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76835.276968                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76324.896694                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76044.800000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76835.276968                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76324.896694                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests          978                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            9                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     25607000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp           823                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     26661500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp           825                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            7                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq          145                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp          145                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          627                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          197                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1261                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          683                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1944                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        21824                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              62400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          628                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          198                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1263                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          685                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total              1948                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        21888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              62528                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
 system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples          969                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.002064                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.045408                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          971                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.002060                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.045361                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                967     99.79%     99.79% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                969     99.79%     99.79% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  2      0.21%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            969                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         495000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            971                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         496000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        940500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          3.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        511500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          2.0                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests           966                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.respLayer0.occupancy        942000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          3.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        513000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.9                       # Layer utilization (%)
+system.membus.snoop_filter.tot_requests           968                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     25607000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp                820                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED     26661500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp                822                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               145                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              145                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           821                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1931                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1931                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        61760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   61760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq           823                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1935                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1935                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        61888                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   61888                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples               966                       # Request fanout histogram
+system.membus.snoop_fanout::samples               968                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     966    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     968    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 966                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             1177000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               4.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            5133750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             20.0                       # Layer utilization (%)
+system.membus.snoop_fanout::total                 968                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             1179500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               4.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            5127250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             19.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 50d6b0572..c4ebeae2c 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -590,7 +590,7 @@ size=64
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -707,6 +707,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -718,7 +719,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -726,29 +727,36 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -768,6 +776,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -777,7 +786,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -799,9 +808,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
index a008eb955..e1ebd0d0b 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:30:06
-gem5 started Jul 21 2016 14:30:36
-gem5 executing on e108600-lin, pid 38673
+gem5 compiled Oct 13 2016 20:43:27
+gem5 started Oct 13 2016 20:45:42
+gem5 executing on e108600-lin, pid 17390
 command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/02.insttest/sparc/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
@@ -21,4 +21,4 @@ LDTX:		Passed
 LDTW:		Passed
 STTW:		Passed
 Done
-Exiting @ tick 28845500 because target called exit()
+Exiting @ tick 29908500 because target called exit()
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 698dda741..24ae64048 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,50 +1,50 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000029                       # Number of seconds simulated
-sim_ticks                                    29089500                       # Number of ticks simulated
-final_tick                                   29089500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000030                       # Number of seconds simulated
+sim_ticks                                    29908500                       # Number of ticks simulated
+final_tick                                   29908500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39190                       # Simulator instruction rate (inst/s)
-host_op_rate                                    39188                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               78964807                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252916                       # Number of bytes of host memory used
-host_seconds                                     0.37                       # Real time elapsed on the host
+host_inst_rate                                  58398                       # Simulator instruction rate (inst/s)
+host_op_rate                                    58392                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              120966219                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251080                       # Number of bytes of host memory used
+host_seconds                                     0.25                       # Real time elapsed on the host
 sim_insts                                       14436                       # Number of instructions simulated
 sim_ops                                         14436                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     29089500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst             23232                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED     29908500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst             23360                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              9408                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                32640                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        23232                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           23232                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                363                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                32768                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        23360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           23360                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                365                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                147                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   510                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            798638684                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            323415665                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1122054350                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       798638684                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          798638684                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           798638684                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           323415665                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1122054350                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           511                       # Number of read requests accepted
+system.physmem.num_reads::total                   512                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            781048866                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            314559406                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1095608272                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       781048866                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          781048866                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           781048866                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           314559406                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1095608272                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           513                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         511                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         513                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    32704                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    32832                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     32704                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     32832                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 105                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                  28                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  53                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                  55                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                  27                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  23                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                   0                       # Per bank write bursts
@@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        29058000                       # Total gap between requests
+system.physmem.totGap                        29877000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     511                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     513                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -91,10 +91,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       298                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       149                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        51                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         9                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       282                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       156                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        58                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -187,310 +187,321 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           75                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      411.306667                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     274.853259                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     343.874505                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             13     17.33%     17.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           19     25.33%     42.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           12     16.00%     58.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            6      8.00%     66.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            5      6.67%     73.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            8     10.67%     84.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      1.33%     85.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           11     14.67%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             75                       # Bytes accessed per row activation
-system.physmem.totQLat                        3266500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  12847750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2555000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6392.37                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples           78                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      394.666667                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     253.933476                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     348.475070                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             17     21.79%     21.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           19     24.36%     46.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           12     15.38%     61.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            5      6.41%     67.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            5      6.41%     74.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      1.28%     75.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            6      7.69%     83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      1.28%     84.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           12     15.38%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             78                       # Bytes accessed per row activation
+system.physmem.totQLat                        6721500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  16340250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2565000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13102.34                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25142.37                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1124.25                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31852.34                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1097.75                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1124.25                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1097.75                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           8.78                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       8.78                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           8.58                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       8.58                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.54                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.64                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        427                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        424                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.56                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   82.65                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        56864.97                       # Average gap between requests
-system.physmem.pageHitRate                      83.56                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     309960                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     169125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2113800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        58239.77                       # Average gap between requests
+system.physmem.pageHitRate                      82.65                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     357000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     174570                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2199120                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               16083405                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  63000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 20264970                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              858.003493                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE          22500                       # Time in different power states
+system.physmem_0.refreshEnergy           1843920.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                3642300                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  63360                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy           9900900                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy             16800                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                 18197970                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              608.449701                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime               21617000                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE          40500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        22830000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     241920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     132000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1396200                       # Energy for read commands per rank (pJ)
+system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN        44000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT         7338500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     21705500                       # Time in different power states
+system.physmem_1.actEnergy                     278460                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     121440                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1463700                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               15332715                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 721500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 19350015                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              819.264991                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        4570750                       # Time in different power states
+system.physmem_1.refreshEnergy           1843920.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                2522250                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                  86880                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy          10426440                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy            493920                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                 17237010                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              576.319973                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime               24154250                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE         143000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        21719750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     29089500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                   12614                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              7656                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect              1475                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 9453                       # Number of BTB lookups
+system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN      1286000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         4831250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN     22868250                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     29908500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                   12304                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              7429                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect              1435                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 9156                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     736                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.usedRAS                     730                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                166                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups            9453                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits               1844                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses             7609                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted          897                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.indirectLookups            9156                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits               1824                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             7332                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          865                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        29089500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            58180                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        29908500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            59818                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              15554                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          59055                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                       12614                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               2580                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                         17529                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    3145                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                    6                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1090                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           25                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      7530                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   720                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              35776                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.650688                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.904189                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles              15502                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          57440                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                       12304                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               2554                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                         17524                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    3065                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                    5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1117                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           12                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                      7446                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   730                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              35692                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.609324                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.874327                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    23025     64.36%     64.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     4506     12.60%     76.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      507      1.42%     78.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      451      1.26%     79.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      761      2.13%     81.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      707      1.98%     83.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      297      0.83%     84.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      355      0.99%     85.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     5167     14.44%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    23194     64.98%     64.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     4479     12.55%     77.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      496      1.39%     78.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      441      1.24%     80.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      761      2.13%     82.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      680      1.91%     84.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      284      0.80%     84.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      358      1.00%     85.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     4999     14.01%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                35776                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.216810                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.015040                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    12463                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                 13012                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      7932                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   797                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1572                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  42051                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1572                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    13239                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    1819                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           9760                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      7921                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1465                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  37034                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                     10                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.SQFullEvents                   1048                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               31990                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 66442                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            54845                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                35692                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.205691                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.960246                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    12333                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                 13299                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      7732                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   796                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1532                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  41071                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1532                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    13082                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    2036                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           9748                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      7750                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1544                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  36233                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                     13                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.SQFullEvents                   1128                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               31392                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 65112                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            53717                       # Number of integer rename lookups
 system.cpu.rename.CommittedMaps                 13819                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    18171                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                796                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            801                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      4352                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 4576                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                2920                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                15                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               11                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      28828                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 757                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     25362                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               118                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           15149                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        11337                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            282                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         35776                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.708911                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.503990                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                    17573                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                793                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            793                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      4281                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 4496                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                2885                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                12                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                8                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      28450                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 744                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     25032                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               132                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           14758                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        10993                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            269                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         35692                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.701334                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.501806                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               26518     74.12%     74.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3268      9.13%     83.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1619      4.53%     87.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1541      4.31%     92.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                1236      3.45%     95.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 752      2.10%     97.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 465      1.30%     98.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 277      0.77%     99.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                 100      0.28%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               26613     74.56%     74.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3169      8.88%     83.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1586      4.44%     87.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1525      4.27%     92.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                1197      3.35%     95.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 748      2.10%     97.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 484      1.36%     98.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 276      0.77%     99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  94      0.26%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           35776                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           35692                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     154     52.56%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     52.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     51     17.41%     69.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    88     30.03%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     164     53.07%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     53.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     53     17.15%     70.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    92     29.77%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 18584     73.27%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     73.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 4272     16.84%     90.12% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                2506      9.88%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 18346     73.29%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     73.29% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 4185     16.72%     90.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                2501      9.99%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  25362                       # Type of FU issued
-system.cpu.iq.rate                           0.435923                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         293                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.011553                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              86911                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             44761                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        22611                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  25032                       # Type of FU issued
+system.cpu.iq.rate                           0.418469                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         309                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012344                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              86197                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             43979                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        22374                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  25655                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  25341                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               33                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               32                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         2351                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         2271                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           28                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores         1472                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores         1437                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            26                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            22                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1572                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1852                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    15                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               31164                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               242                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  4576                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2920                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                757                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles                   1532                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    2073                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    16                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               30726                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               235                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  4496                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2885                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                744                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      7                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     4                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             28                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            211                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect         1624                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1835                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 23718                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  3945                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1644                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect            207                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect         1575                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1782                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 23436                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  3882                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1596                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1579                       # number of nop insts executed
-system.cpu.iew.exec_refs                         6245                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     5021                       # Number of branches executed
-system.cpu.iew.exec_stores                       2300                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.407666                       # Inst execution rate
-system.cpu.iew.wb_sent                          23107                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         22611                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                     10526                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     13786                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.388639                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.763528                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts           15913                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                          1532                       # number of nop insts executed
+system.cpu.iew.exec_refs                         6191                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     4986                       # Number of branches executed
+system.cpu.iew.exec_stores                       2309                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.391788                       # Inst execution rate
+system.cpu.iew.wb_sent                          22845                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         22374                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                     10411                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     13650                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.374035                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.762711                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts           15475                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1475                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        32637                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.464565                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.243420                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts              1435                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        32615                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.464878                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.257144                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        25892     79.33%     79.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         3639     11.15%     90.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1211      3.71%     94.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          601      1.84%     96.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          338      1.04%     97.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          300      0.92%     97.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          374      1.15%     99.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           54      0.17%     99.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          228      0.70%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        25974     79.64%     79.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         3555     10.90%     90.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1191      3.65%     94.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          577      1.77%     95.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          319      0.98%     96.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          311      0.95%     97.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          392      1.20%     99.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           57      0.17%     99.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          239      0.73%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        32637                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        32615                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                15162                       # Number of instructions committed
 system.cpu.commit.committedOps                  15162                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -536,104 +547,104 @@ system.cpu.commit.op_class_0::MemWrite           1448      9.55%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total             15162                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   228                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        62661                       # The number of ROB reads
-system.cpu.rob.rob_writes                       65377                       # The number of ROB writes
-system.cpu.timesIdled                             196                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           22404                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   239                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        62190                       # The number of ROB reads
+system.cpu.rob.rob_writes                       64431                       # The number of ROB writes
+system.cpu.timesIdled                             194                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           24126                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                       14436                       # Number of Instructions Simulated
 system.cpu.committedOps                         14436                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               4.030202                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         4.030202                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.248127                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.248127                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    36851                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   20552                       # number of integer regfile writes
-system.cpu.misc_regfile_reads                    8143                       # number of misc regfile reads
+system.cpu.cpi                               4.143669                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.143669                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.241332                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.241332                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    36480                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   20296                       # number of integer regfile writes
+system.cpu.misc_regfile_reads                    8094                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     29089500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     29908500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            99.825953                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                4648                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            99.158435                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                4579                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             31.835616                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             31.363014                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    99.825953                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.024372                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.024372                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    99.158435                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.024209                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.024209                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses             10540                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses            10540                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     29089500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data         3609                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            3609                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses             10412                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses            10412                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     29908500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data         3540                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3540                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1033                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total           1033                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          4642                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             4642                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         4642                       # number of overall hits
-system.cpu.dcache.overall_hits::total            4642                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          140                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           140                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          4573                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4573                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4573                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4573                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          145                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           145                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          409                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          409                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          549                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            549                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          549                       # number of overall misses
-system.cpu.dcache.overall_misses::total           549                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      9476500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      9476500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     27259981                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     27259981                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     36736481                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     36736481                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     36736481                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     36736481                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3749                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3749                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          554                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            554                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          554                       # number of overall misses
+system.cpu.dcache.overall_misses::total           554                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11443500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11443500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     29003985                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     29003985                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     40447485                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     40447485                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     40447485                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     40447485                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         3685                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         3685                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         5191                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         5191                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         5191                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         5191                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037343                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.037343                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         5127                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         5127                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         5127                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         5127                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.039349                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.039349                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.283634                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.283634                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.105760                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.105760                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.105760                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.105760                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67689.285714                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67689.285714                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66650.320293                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66650.320293                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 66915.265938                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66915.265938                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 66915.265938                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66915.265938                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1333                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.108055                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.108055                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.108055                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.108055                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78920.689655                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 78920.689655                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70914.388753                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70914.388753                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 73009.900722                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73009.900722                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73009.900722                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73009.900722                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         1437                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                23                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                19                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    57.956522                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    75.631579                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           75                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           75                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           80                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          326                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          326                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          401                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          401                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          401                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          401                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          406                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          406                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          406                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          406                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           65                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           65                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           83                       # number of WriteReq MSHR misses
@@ -642,138 +653,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          148
 system.cpu.dcache.demand_mshr_misses::total          148                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          148                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          148                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5190500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5190500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6454500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6454500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11645000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     11645000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11645000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     11645000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017338                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017338                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6078000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6078000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6888000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6888000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12966000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     12966000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12966000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     12966000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017639                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017639                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.057559                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028511                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.028511                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028511                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.028511                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79853.846154                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79853.846154                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77765.060241                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77765.060241                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78682.432432                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78682.432432                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78682.432432                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78682.432432                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     29089500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028867                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.028867                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028867                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028867                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93507.692308                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93507.692308                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82987.951807                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82987.951807                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87608.108108                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 87608.108108                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87608.108108                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 87608.108108                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     29908500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           206.188252                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                6949                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               365                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             19.038356                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           204.747820                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                6856                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               367                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.681199                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   206.188252                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.100678                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.100678                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   204.747820                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.099975                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.099975                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          367                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          275                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.178223                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             15425                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            15425                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     29089500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         6949                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            6949                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          6949                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             6949                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         6949                       # number of overall hits
-system.cpu.icache.overall_hits::total            6949                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          581                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           581                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          581                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            581                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          581                       # number of overall misses
-system.cpu.icache.overall_misses::total           581                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     40938500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     40938500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     40938500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     40938500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     40938500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     40938500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         7530                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         7530                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         7530                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         7530                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         7530                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         7530                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.077158                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.077158                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.077158                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.077158                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.077158                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.077158                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70462.134251                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70462.134251                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70462.134251                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70462.134251                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70462.134251                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70462.134251                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          194                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_task_id_percent::1024     0.179199                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             15259                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            15259                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     29908500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst         6856                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            6856                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          6856                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             6856                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         6856                       # number of overall hits
+system.cpu.icache.overall_hits::total            6856                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          590                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           590                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          590                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            590                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          590                       # number of overall misses
+system.cpu.icache.overall_misses::total           590                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     45891500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     45891500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     45891500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     45891500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     45891500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     45891500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         7446                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         7446                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         7446                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         7446                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         7446                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         7446                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.079237                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.079237                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.079237                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.079237                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.079237                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.079237                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77782.203390                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 77782.203390                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 77782.203390                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 77782.203390                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 77782.203390                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 77782.203390                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          123                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           97                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          123                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          216                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          216                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          216                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          216                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          216                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          216                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          365                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          365                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          365                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          365                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          365                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          365                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     27977500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     27977500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     27977500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     27977500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27977500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     27977500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.048473                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.048473                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.048473                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.048473                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.048473                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.048473                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76650.684932                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76650.684932                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76650.684932                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 76650.684932                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76650.684932                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 76650.684932                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     29089500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          223                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          223                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          223                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          223                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          223                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          223                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          367                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          367                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          367                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          367                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          367                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          367                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     30257500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     30257500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     30257500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     30257500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     30257500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     30257500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.049288                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.049288                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.049288                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.049288                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.049288                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.049288                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82445.504087                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82445.504087                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82445.504087                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 82445.504087                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82445.504087                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 82445.504087                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     29908500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          305.425349                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          303.316506                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              509                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.003929                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              511                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.003914                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   205.546698                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    99.878652                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.006273                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.003048                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.009321                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   204.106814                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    99.209691                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.006229                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.003028                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.009256                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          399                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.015533                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4613                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4613                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     29089500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.015594                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4631                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4631                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     29908500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            2                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            2                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -782,64 +793,64 @@ system.cpu.l2cache.overall_hits::cpu.inst            2                       # n
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data           83                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           83                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          363                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          363                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          365                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          365                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data           65                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total           65                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          363                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          365                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          148                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           511                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          363                       # number of overall misses
+system.cpu.l2cache.demand_misses::total           513                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          365                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          148                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          511                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6329000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      6329000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     27407000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     27407000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5095500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      5095500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     27407000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     11424500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     38831500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     27407000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     11424500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     38831500                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total          513                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6762500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6762500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     29684000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     29684000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5983000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      5983000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     29684000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     12745500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     42429500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     29684000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     12745500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     42429500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           83                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           83                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          365                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          365                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          367                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          367                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           65                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total           65                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          365                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          367                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          148                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          513                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          365                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          515                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          367                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          148                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          513                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          515                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.994521                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.994521                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.994550                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.994550                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.994521                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.994550                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.996101                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994521                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.996117                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994550                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.996101                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76253.012048                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76253.012048                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75501.377410                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75501.377410                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78392.307692                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78392.307692                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75501.377410                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77192.567568                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75991.193738                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75501.377410                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77192.567568                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75991.193738                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.996117                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81475.903614                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81475.903614                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81326.027397                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81326.027397                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92046.153846                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92046.153846                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81326.027397                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86118.243243                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82708.576998                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81326.027397                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86118.243243                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82708.576998                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -848,119 +859,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           83                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           83                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          363                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          363                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          365                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          365                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           65                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total           65                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          363                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          365                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          148                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          511                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          363                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          513                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          365                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          148                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          511                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5499000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5499000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     23777000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     23777000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4465500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4465500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23777000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9964500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     33741500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23777000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9964500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     33741500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total          513                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5932500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5932500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     26034000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     26034000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5353000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      5353000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     26034000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11285500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     37319500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     26034000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11285500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     37319500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.994521                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.994521                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.994550                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.994550                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994521                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994550                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.996101                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994521                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.996117                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994550                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.996101                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66253.012048                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66253.012048                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65501.377410                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65501.377410                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        68700                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        68700                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65501.377410                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67327.702703                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66030.332681                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65501.377410                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67327.702703                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66030.332681                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests          513                       # Total number of requests made to the snoop filter.
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.996117                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71475.903614                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71475.903614                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71326.027397                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71326.027397                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82353.846154                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82353.846154                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71326.027397                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76253.378378                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72747.563353                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71326.027397                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76253.378378                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72747.563353                       # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests          515                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            2                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     29089500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp           428                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     29908500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp           430                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           83                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           83                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          365                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          367                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq           65                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          730                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          734                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          294                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1024                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total              1028                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23488                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              32704                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              32832                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
 system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples          513                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.003899                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.062378                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          515                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.003883                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.062257                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                511     99.61%     99.61% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                513     99.61%     99.61% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  2      0.39%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            513                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         256500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            515                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         257500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        547500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        550500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.8                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        219000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests           511                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
+system.membus.snoop_filter.tot_requests           513                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     29089500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp                426                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED     29908500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp                428                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                83                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               83                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           428                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1020                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1020                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        32576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   32576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq           430                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1024                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1024                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        32704                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   32704                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples               511                       # Request fanout histogram
+system.membus.snoop_fanout::samples               513                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     511    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     513    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 511                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              623000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 513                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              627500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2693500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              9.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2707250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              9.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
index 407eb5e1e..1efeb5f99 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
@@ -23,7 +23,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:536870911
+mem_ranges=0:536870911:0:0:0:0
 memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
@@ -153,27 +153,27 @@ transition_latency=100000000
 
 [system.mem_ctrl]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -193,6 +193,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -202,7 +203,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:536870911
+range=0:536870911:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -224,9 +225,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -235,6 +236,7 @@ port=system.membus.master[0]
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -246,7 +248,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -254,3 +256,10 @@ width=16
 master=system.mem_ctrl.port
 slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout
index 7b44dd5a2..4e8f563cb 100755
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linu
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:26
-gem5 executing on e108600-lin, pid 39594
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:47
+gem5 executing on e108600-lin, pid 28091
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple
 
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ Beginning simulation!
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 405365000 because target called exit()
+Exiting @ tick 461109000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
index f8c482cd0..090f011e7 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000415                       # Number of seconds simulated
-sim_ticks                                   414695000                       # Number of ticks simulated
-final_tick                                  414695000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000461                       # Number of seconds simulated
+sim_ticks                                   461109000                       # Number of ticks simulated
+final_tick                                  461109000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 187951                       # Simulator instruction rate (inst/s)
-host_op_rate                                   187881                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            12069868237                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 635076                       # Number of bytes of host memory used
+host_inst_rate                                 212686                       # Simulator instruction rate (inst/s)
+host_op_rate                                   212584                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            15184120914                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 634004                       # Number of bytes of host memory used
 host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        6453                       # Number of instructions simulated
 sim_ops                                          6453                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED    414695000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED    461109000                       # Cumulative time (in ticks) in various power states
 system.mem_ctrl.bytes_read::cpu.inst            25852                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::cpu.data             8844                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::total               34696                       # Number of bytes read from this memory
@@ -26,63 +26,63 @@ system.mem_ctrl.num_reads::cpu.data              1190                       # Nu
 system.mem_ctrl.num_reads::total                 7653                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_writes::cpu.data              865                       # Number of write requests responded to by this memory
 system.mem_ctrl.num_writes::total                 865                       # Number of write requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst            62339792                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data            21326517                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total               83666309                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst       62339792                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total          62339792                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::cpu.data           16146807                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::total              16146807                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst           62339792                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data           37473324                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total              99813116                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.inst            56064835                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data            19179847                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total               75244682                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst       56064835                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total          56064835                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::cpu.data           14521512                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::total              14521512                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst           56064835                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data           33701359                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total              89766194                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrl.readReqs                         7654                       # Number of read requests accepted
 system.mem_ctrl.writeReqs                         865                       # Number of write requests accepted
 system.mem_ctrl.readBursts                       7654                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrl.writeBursts                       865                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrl.bytesReadDRAM                  478016                       # Total number of bytes read from DRAM
-system.mem_ctrl.bytesReadWrQ                    11840                       # Total number of bytes read from write queue
+system.mem_ctrl.bytesReadDRAM                  477504                       # Total number of bytes read from DRAM
+system.mem_ctrl.bytesReadWrQ                    12352                       # Total number of bytes read from write queue
 system.mem_ctrl.bytesWritten                     6144                       # Total number of bytes written to DRAM
 system.mem_ctrl.bytesReadSys                    34700                       # Total read bytes from the system interface side
 system.mem_ctrl.bytesWrittenSys                  6696                       # Total written bytes from the system interface side
-system.mem_ctrl.servicedByWrQ                     185                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrl.mergedWrBursts                    746                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrl.servicedByWrQ                     193                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrl.mergedWrBursts                    752                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrl.neitherReadNorWriteReqs             0                       # Number of requests that are neither read nor write
 system.mem_ctrl.perBankRdBursts::0               1736                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::1                393                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::2                768                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::3                800                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::4                766                       # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::4                764                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::5                293                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::6                  6                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::7                 26                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::8                  0                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::9                  1                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::10               257                       # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::10               249                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::11               578                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::12               167                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::13              1431                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::14                89                       # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::14                91                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::15               158                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::0                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::1                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::2                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::3                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::4                 26                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::5                  3                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::4                 18                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::5                  7                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::6                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::7                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::8                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::9                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::10                 5                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::10                 7                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::11                 0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::12                 0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::13                18                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::13                20                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::14                44                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
 system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
 system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
-system.mem_ctrl.totGap                      414618000                       # Total gap between requests
+system.mem_ctrl.totGap                      461032000                       # Total gap between requests
 system.mem_ctrl.readPktSize::0                      0                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::1                      0                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::2                   6633                       # Read request sizes (log2)
@@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3                   809                       # Wr
 system.mem_ctrl.writePktSize::4                     0                       # Write request sizes (log2)
 system.mem_ctrl.writePktSize::5                     0                       # Write request sizes (log2)
 system.mem_ctrl.writePktSize::6                     0                       # Write request sizes (log2)
-system.mem_ctrl.rdQLenPdf::0                     7469                       # What read queue length does an incoming req see
+system.mem_ctrl.rdQLenPdf::0                     7461                       # What read queue length does an incoming req see
 system.mem_ctrl.rdQLenPdf::1                        0                       # What read queue length does an incoming req see
 system.mem_ctrl.rdQLenPdf::2                        0                       # What read queue length does an incoming req see
 system.mem_ctrl.rdQLenPdf::3                        0                       # What read queue length does an incoming req see
@@ -146,12 +146,12 @@ system.mem_ctrl.wrQLenPdf::13                       1                       # Wh
 system.mem_ctrl.wrQLenPdf::14                       1                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::15                       1                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::16                       1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::17                       7                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::18                       7                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::19                       7                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::20                       7                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::21                       7                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::22                       7                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::17                       6                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::18                       6                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::19                       6                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::20                       6                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::21                       6                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::22                       6                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::23                       6                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::24                       6                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::25                       6                       # What write queue length does an incoming req see
@@ -193,87 +193,95 @@ system.mem_ctrl.wrQLenPdf::60                       0                       # Wh
 system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples          765                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean     630.044444                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean    420.142008                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev    402.263677                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127           142     18.56%     18.56% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255           72      9.41%     27.97% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383           39      5.10%     33.07% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511           50      6.54%     39.61% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639           49      6.41%     46.01% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767           26      3.40%     49.41% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895           27      3.53%     52.94% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-1023           39      5.10%     58.04% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151          321     41.96%    100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total           765                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::samples          766                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean     629.556136                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean    420.481555                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev    399.288519                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127           144     18.80%     18.80% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255           67      8.75%     27.55% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383           42      5.48%     33.03% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511           49      6.40%     39.43% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639           40      5.22%     44.65% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767           39      5.09%     49.74% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895           38      4.96%     54.70% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::896-1023           34      4.44%     59.14% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151          313     40.86%    100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total           766                       # Bytes accessed per row activation
 system.mem_ctrl.rdPerTurnAround::samples            6                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::mean     1155.166667                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::gmean    1053.155116                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::stdev     490.786070                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::512-575            1     16.67%     16.67% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::576-639            1     16.67%     33.33% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1152-1215            1     16.67%     50.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1280-1343            1     16.67%     66.67% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1408-1471            1     16.67%     83.33% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1728-1791            1     16.67%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::mean            1237                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::gmean    1086.549947                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::stdev     686.122730                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::512-639            2     33.33%     33.33% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::1152-1279            2     33.33%     66.67% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::1408-1535            1     16.67%     83.33% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::2304-2431            1     16.67%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrl.rdPerTurnAround::total              6                       # Reads before turning the bus around for writes
 system.mem_ctrl.wrPerTurnAround::samples            6                       # Writes before turning the bus around for reads
 system.mem_ctrl.wrPerTurnAround::mean              16                       # Writes before turning the bus around for reads
 system.mem_ctrl.wrPerTurnAround::gmean      16.000000                       # Writes before turning the bus around for reads
 system.mem_ctrl.wrPerTurnAround::16                 6    100.00%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrl.wrPerTurnAround::total              6                       # Writes before turning the bus around for reads
-system.mem_ctrl.totQLat                      26666250                       # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat                166710000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrl.totBusLat                    37345000                       # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat                       3570.26                       # Average queueing delay per DRAM burst
+system.mem_ctrl.totQLat                      73323250                       # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat                213217000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totBusLat                    37305000                       # Total ticks spent in databus transfers
+system.mem_ctrl.avgQLat                       9827.54                       # Average queueing delay per DRAM burst
 system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat                 22320.26                       # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW                       1152.69                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW                         14.82                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys                      83.68                       # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys                      16.15                       # Average system write bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat                 28577.54                       # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW                       1035.56                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBW                         13.32                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys                      75.25                       # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBWSys                      14.52                       # Average system write bandwidth in MiByte/s
 system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil                          9.12                       # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead                      9.01                       # Data bus utilization in percentage for reads
-system.mem_ctrl.busUtilWrite                     0.12                       # Data bus utilization in percentage for writes
+system.mem_ctrl.busUtil                          8.19                       # Data bus utilization in percentage
+system.mem_ctrl.busUtilRead                      8.09                       # Data bus utilization in percentage for reads
+system.mem_ctrl.busUtilWrite                     0.10                       # Data bus utilization in percentage for writes
 system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
-system.mem_ctrl.avgWrQLen                       22.92                       # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits                      6707                       # Number of row buffer hits during reads
-system.mem_ctrl.writeRowHits                       88                       # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate                  89.80                       # Row buffer hit rate for reads
-system.mem_ctrl.writeRowHitRate                 73.95                       # Row buffer hit rate for writes
-system.mem_ctrl.avgGap                       48669.80                       # Average gap between requests
-system.mem_ctrl.pageHitRate                     89.55                       # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy                   3409560                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy                   1860375                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy                 37159200                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_0.writeEnergy                  187920                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy              26953680                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy             262129320                       # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy              17820750                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy               349520805                       # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower             846.438251                       # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE      26708250                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::REF       13780000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT      372456750                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrl_1.actEnergy                   2373840                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy                   1295250                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy                 20833800                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_1.writeEnergy                  434160                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy              26953680                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy             231001335                       # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy              45144000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy               328036065                       # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower             794.350717                       # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE      73389500                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::REF       13780000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT      325838500                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED    414695000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.avgWrQLen                       23.97                       # Average write queue length when enqueuing
+system.mem_ctrl.readRowHits                      6701                       # Number of row buffer hits during reads
+system.mem_ctrl.writeRowHits                       86                       # Number of row buffer hits during writes
+system.mem_ctrl.readRowHitRate                  89.81                       # Row buffer hit rate for reads
+system.mem_ctrl.writeRowHitRate                 76.11                       # Row buffer hit rate for writes
+system.mem_ctrl.avgGap                       54118.09                       # Average gap between requests
+system.mem_ctrl.pageHitRate                     89.61                       # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy                   3184440                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy                   1681185                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy                 34164900                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.writeEnergy                  130500                       # Energy for write commands per rank (pJ)
+system.mem_ctrl_0.refreshEnergy          36263760.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_0.actBackEnergy              65335680                       # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy               1899360                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.actPowerDownEnergy        128211240                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_0.prePowerDownEnergy         12180000                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_0.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_0.totalEnergy               283051065                       # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower             613.847162                       # Core power per rank (mW)
+system.mem_ctrl_0.totalIdleTime             312833500                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_0.memoryStateTime::IDLE        882000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::REF       15340000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::PRE_PDN     31715250                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT      132053500                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT_PDN    281118250                       # Time in different power states
+system.mem_ctrl_1.actEnergy                   2313360                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy                   1225785                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.readEnergy                 19099500                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_1.writeEnergy                  370620                       # Energy for write commands per rank (pJ)
+system.mem_ctrl_1.refreshEnergy          35649120.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_1.actBackEnergy              44402430                       # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy               1287360                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.actPowerDownEnergy        129142620                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_1.prePowerDownEnergy         18055680                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_1.selfRefreshEnergy           8894220                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_1.totalEnergy               260440695                       # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower             564.812507                       # Core power per rank (mW)
+system.mem_ctrl_1.totalIdleTime             359701750                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_1.memoryStateTime::IDLE       1420000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::REF       15098000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::SREF      30156500                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::PRE_PDN     47020500                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT       84176750                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT_PDN    283237250                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED    461109000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -307,8 +315,8 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON       414695000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                           414695                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON       461109000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                           461109                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6453                       # Number of instructions committed
@@ -327,7 +335,7 @@ system.cpu.num_mem_refs                          2065                       # nu
 system.cpu.num_load_insts                        1197                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     414695                       # Number of busy cycles
+system.cpu.num_busy_cycles                     461109                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1060                       # Number of branches fetched
@@ -372,7 +380,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED    414695000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED    461109000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                7654                       # Transaction distribution
 system.membus.trans_dist::ReadResp               7653                       # Transaction distribution
 system.membus.trans_dist::WriteReq                865                       # Transaction distribution
@@ -396,10 +404,10 @@ system.membus.snoop_fanout::min_value               0                       # Re
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                8519                       # Request fanout histogram
 system.membus.reqLayer0.occupancy             9384000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
-system.membus.respLayer0.occupancy           14691750                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3578000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
+system.membus.reqLayer0.utilization               2.0                       # Layer utilization (%)
+system.membus.respLayer0.occupancy           14690000                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization              3.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3572750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
index f8108d4cd..5a1f94c78 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
@@ -23,7 +23,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:536870911
+mem_ranges=0:536870911:0:0:0:0
 memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
@@ -100,7 +100,7 @@ icache_port=system.cpu.icache.cpu_side
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -151,7 +151,7 @@ size=64
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -275,7 +275,7 @@ system=system
 [system.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -320,27 +320,27 @@ size=262144
 
 [system.mem_ctrl]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -360,6 +360,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -369,7 +370,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:536870911
+range=0:536870911:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -391,9 +392,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -402,6 +403,7 @@ port=system.membus.master[0]
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -413,7 +415,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -421,3 +423,10 @@ width=16
 master=system.mem_ctrl.port
 slave=system.l2cache.mem_side system.system_port
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout
index 7505aca67..2e75b8af5 100755
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linu
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:26
-gem5 executing on e108600-lin, pid 39597
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:46
+gem5 executing on e108600-lin, pid 28074
 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level
 
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ Beginning simulation!
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 61470000 because target called exit()
+Exiting @ tick 64758000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
index 1f58ca472..47755a477 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000062                       # Number of seconds simulated
-sim_ticks                                    62213000                       # Number of ticks simulated
-final_tick                                   62213000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000065                       # Number of seconds simulated
+sim_ticks                                    64758000                       # Number of ticks simulated
+final_tick                                   64758000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 276862                       # Simulator instruction rate (inst/s)
-host_op_rate                                   276760                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2667377590                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 639424                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 560678                       # Simulator instruction rate (inst/s)
+host_op_rate                                   559951                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5612828222                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 638096                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6453                       # Number of instructions simulated
 sim_ops                                          6453                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     62213000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
 system.mem_ctrl.bytes_read::cpu.inst            17792                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::cpu.data            10752                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::total               28544                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total          17792                       # Nu
 system.mem_ctrl.num_reads::cpu.inst               278                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_reads::cpu.data               168                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_reads::total                  446                       # Number of read requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst           285985244                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data           172825615                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total              458810859                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst      285985244                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total         285985244                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst          285985244                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data          172825615                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total             458810859                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.inst           274745977                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data           166033540                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total              440779518                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst      274745977                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total         274745977                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst          274745977                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data          166033540                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total             440779518                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrl.readReqs                          446                       # Number of read requests accepted
 system.mem_ctrl.writeReqs                           0                       # Number of write requests accepted
 system.mem_ctrl.readBursts                        446                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14                 0                       # Pe
 system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
 system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
 system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
-system.mem_ctrl.totGap                       61962000                       # Total gap between requests
+system.mem_ctrl.totGap                       64501000                       # Total gap between requests
 system.mem_ctrl.readPktSize::0                      0                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::1                      0                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::2                      0                       # Read request sizes (log2)
@@ -187,70 +187,80 @@ system.mem_ctrl.wrQLenPdf::60                       0                       # Wh
 system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples           95                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean     270.147368                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean    185.768755                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev    255.860208                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127            22     23.16%     23.16% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255           36     37.89%     61.05% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383           14     14.74%     75.79% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511            5      5.26%     81.05% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639            6      6.32%     87.37% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767            6      6.32%     93.68% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895            1      1.05%     94.74% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151            5      5.26%    100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total            95                       # Bytes accessed per row activation
-system.mem_ctrl.totQLat                       3590750                       # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat                 11953250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.bytesPerActivate::samples          105                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean     264.533333                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean    181.831163                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev    249.307389                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127            27     25.71%     25.71% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255           40     38.10%     63.81% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383           10      9.52%     73.33% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511            9      8.57%     81.90% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639            7      6.67%     88.57% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767            6      5.71%     94.29% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895            1      0.95%     95.24% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151            5      4.76%    100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total           105                       # Bytes accessed per row activation
+system.mem_ctrl.totQLat                       6134000                       # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat                 14496500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.mem_ctrl.totBusLat                     2230000                       # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat                       8051.01                       # Average queueing delay per DRAM burst
+system.mem_ctrl.avgQLat                      13753.36                       # Average queueing delay per DRAM burst
 system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat                 26801.01                       # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW                        458.81                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat                 32503.36                       # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW                        440.78                       # Average DRAM read bandwidth in MiByte/s
 system.mem_ctrl.avgWrBW                          0.00                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys                     458.81                       # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys                     440.78                       # Average system read bandwidth in MiByte/s
 system.mem_ctrl.avgWrBWSys                       0.00                       # Average system write bandwidth in MiByte/s
 system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil                          3.58                       # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead                      3.58                       # Data bus utilization in percentage for reads
+system.mem_ctrl.busUtil                          3.44                       # Data bus utilization in percentage
+system.mem_ctrl.busUtilRead                      3.44                       # Data bus utilization in percentage for reads
 system.mem_ctrl.busUtilWrite                     0.00                       # Data bus utilization in percentage for writes
 system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
 system.mem_ctrl.avgWrQLen                        0.00                       # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits                       340                       # Number of row buffer hits during reads
+system.mem_ctrl.readRowHits                       337                       # Number of row buffer hits during reads
 system.mem_ctrl.writeRowHits                        0                       # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate                  76.23                       # Row buffer hit rate for reads
+system.mem_ctrl.readRowHitRate                  75.56                       # Row buffer hit rate for reads
 system.mem_ctrl.writeRowHitRate                   nan                       # Row buffer hit rate for writes
-system.mem_ctrl.avgGap                      138928.25                       # Average gap between requests
-system.mem_ctrl.pageHitRate                     76.23                       # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy                    309960                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy                    169125                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy                  1583400                       # Energy for read commands per rank (pJ)
+system.mem_ctrl.avgGap                      144621.08                       # Average gap between requests
+system.mem_ctrl.pageHitRate                     75.56                       # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy                    314160                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy                    163185                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy                  1542240                       # Energy for read commands per rank (pJ)
 system.mem_ctrl_0.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy               3559920                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy              37021500                       # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy                383250                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy                43027155                       # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower             785.686791                       # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE        966000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::REF        1820000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT       52514000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrl_1.actEnergy                    370440                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy                    202125                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy                  1466400                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.refreshEnergy          4917120.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_0.actBackEnergy               3812160                       # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy                131040                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.actPowerDownEnergy         22575420                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_0.prePowerDownEnergy          2515200                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_0.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_0.totalEnergy                35970525                       # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower             555.454282                       # Core power per rank (mW)
+system.mem_ctrl_0.totalIdleTime              55623250                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_0.memoryStateTime::IDLE         77000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::REF        2080000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::PRE_PDN      6549500                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT        6531250                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT_PDN     49520250                       # Time in different power states
+system.mem_ctrl_1.actEnergy                    464100                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy                    235290                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.readEnergy                  1642200                       # Energy for read commands per rank (pJ)
 system.mem_ctrl_1.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy               3559920                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy              35989515                       # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy               1288500                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy                42876900                       # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower             782.943096                       # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE       1815750                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::REF        1820000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT       51141750                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     62213000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl_1.refreshEnergy          4917120.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_1.actBackEnergy               4174680                       # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy                251520                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.actPowerDownEnergy         24338430                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_1.prePowerDownEnergy           604800                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_1.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_1.totalEnergy                36628140                       # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower             565.609126                       # Core power per rank (mW)
+system.mem_ctrl_1.totalIdleTime              54728750                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_1.memoryStateTime::IDLE        283000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::REF        2080000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::PRE_PDN      1573250                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT        7457000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT_PDN     53364750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -284,8 +294,8 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        62213000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            62213                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        64758000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            64758                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6453                       # Number of instructions committed
@@ -304,7 +314,7 @@ system.cpu.num_mem_refs                          2065                       # nu
 system.cpu.num_load_insts                        1197                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      62213                       # Number of busy cycles
+system.cpu.num_busy_cycles                      64758                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1060                       # Number of branches fetched
@@ -343,23 +353,23 @@ system.cpu.op_class::MemWrite                     868     13.43%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       6463                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     62213000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           104.646393                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse           104.399751                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1887                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               168                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             11.232143                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   104.646393                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.102194                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.102194                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   104.399751                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.101953                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.101953                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           12                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.164062                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              4278                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             4278                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     62213000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data         1095                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1095                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          792                       # number of WriteReq hits
@@ -376,14 +386,14 @@ system.cpu.dcache.demand_misses::cpu.data          168                       # n
 system.cpu.dcache.demand_misses::total            168                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          168                       # number of overall misses
 system.cpu.dcache.overall_misses::total           168                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      9887000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      9887000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      7630000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      7630000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     17517000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     17517000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     17517000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     17517000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     10261000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     10261000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      7802000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      7802000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     18063000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     18063000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     18063000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     18063000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1190                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1190                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
@@ -400,14 +410,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.081752
 system.cpu.dcache.demand_miss_rate::total     0.081752                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.081752                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.081752                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 104073.684211                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 104073.684211                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104520.547945                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 104520.547945                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 104267.857143                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 104267.857143                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 104267.857143                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 104267.857143                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108010.526316                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 108010.526316                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106876.712329                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 106876.712329                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 107517.857143                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 107517.857143                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 107517.857143                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 107517.857143                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -422,14 +432,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          168
 system.cpu.dcache.demand_mshr_misses::total          168                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          168                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      9697000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      9697000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      7484000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      7484000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     17181000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     17181000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     17181000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     17181000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     10071000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     10071000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      7656000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      7656000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     17727000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     17727000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     17727000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     17727000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.079832                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.079832                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
@@ -438,31 +448,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.081752
 system.cpu.dcache.demand_mshr_miss_rate::total     0.081752                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.081752                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.081752                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 102073.684211                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 102073.684211                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102520.547945                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102520.547945                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 102267.857143                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 102267.857143                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 102267.857143                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 102267.857143                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     62213000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106010.526316                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106010.526316                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104876.712329                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104876.712329                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105517.857143                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 105517.857143                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105517.857143                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 105517.857143                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                62                       # number of replacements
-system.cpu.icache.tags.tagsinuse           113.718871                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           113.445692                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                6183                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               281                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             22.003559                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   113.718871                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.444214                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.444214                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   113.445692                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.443147                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.443147                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          219                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.855469                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses             13209                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses            13209                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     62213000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst         6183                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            6183                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          6183                       # number of demand (read+write) hits
@@ -475,12 +485,12 @@ system.cpu.icache.demand_misses::cpu.inst          281                       # n
 system.cpu.icache.demand_misses::total            281                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          281                       # number of overall misses
 system.cpu.icache.overall_misses::total           281                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     28558000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     28558000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     28558000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     28558000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     28558000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     28558000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     30557000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     30557000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     30557000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     30557000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     30557000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     30557000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         6464                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         6464                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         6464                       # number of demand (read+write) accesses
@@ -493,12 +503,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.043472
 system.cpu.icache.demand_miss_rate::total     0.043472                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.043472                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.043472                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101629.893238                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 101629.893238                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 101629.893238                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 101629.893238                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 101629.893238                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 101629.893238                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108743.772242                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 108743.772242                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 108743.772242                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 108743.772242                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 108743.772242                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 108743.772242                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -511,31 +521,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          281
 system.cpu.icache.demand_mshr_misses::total          281                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          281                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          281                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     27996000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     27996000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     27996000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     27996000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27996000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     27996000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     29995000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     29995000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     29995000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     29995000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     29995000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     29995000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.043472                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.043472                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.043472                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.043472                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.043472                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.043472                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99629.893238                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99629.893238                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99629.893238                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 99629.893238                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99629.893238                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 99629.893238                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106743.772242                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106743.772242                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106743.772242                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 106743.772242                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106743.772242                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 106743.772242                       # average overall mshr miss latency
 system.l2bus.snoop_filter.tot_requests            511                       # Total number of requests made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_requests           63                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.l2bus.snoop_filter.tot_snoops                0                       # Total number of snoops made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l2bus.pwrStateResidencyTicks::UNDEFINED     62213000                       # Cumulative time (in ticks) in various power states
+system.l2bus.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
 system.l2bus.trans_dist::ReadResp                 376                       # Transaction distribution
 system.l2bus.trans_dist::CleanEvict                62                       # Transaction distribution
 system.l2bus.trans_dist::ReadExReq                 73                       # Transaction distribution
@@ -563,28 +573,28 @@ system.l2bus.snoop_fanout::total                  449                       # Re
 system.l2bus.reqLayer0.occupancy               511000                       # Layer occupancy (ticks)
 system.l2bus.reqLayer0.utilization                0.8                       # Layer utilization (%)
 system.l2bus.respLayer0.occupancy              843000                       # Layer occupancy (ticks)
-system.l2bus.respLayer0.utilization               1.4                       # Layer utilization (%)
+system.l2bus.respLayer0.utilization               1.3                       # Layer utilization (%)
 system.l2bus.respLayer1.occupancy              504000                       # Layer occupancy (ticks)
 system.l2bus.respLayer1.utilization               0.8                       # Layer utilization (%)
-system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     62213000                       # Cumulative time (in ticks) in various power states
+system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
 system.l2cache.tags.replacements                    0                       # number of replacements
-system.l2cache.tags.tagsinuse              233.175851                       # Cycle average of tags in use
+system.l2cache.tags.tagsinuse              232.606847                       # Cycle average of tags in use
 system.l2cache.tags.total_refs                     65                       # Total number of references to valid blocks.
 system.l2cache.tags.sampled_refs                  446                       # Sample count of references to valid blocks.
 system.l2cache.tags.avg_refs                 0.145740                       # Average number of references to valid blocks.
 system.l2cache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.l2cache.tags.occ_blocks::cpu.inst   128.472749                       # Average occupied blocks per requestor
-system.l2cache.tags.occ_blocks::cpu.data   104.703102                       # Average occupied blocks per requestor
-system.l2cache.tags.occ_percent::cpu.inst     0.031365                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::cpu.data     0.025562                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::total       0.056928                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_blocks::cpu.inst   128.152617                       # Average occupied blocks per requestor
+system.l2cache.tags.occ_blocks::cpu.data   104.454231                       # Average occupied blocks per requestor
+system.l2cache.tags.occ_percent::cpu.inst     0.031287                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::cpu.data     0.025502                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::total       0.056789                       # Average percentage of cache occupancy
 system.l2cache.tags.occ_task_id_blocks::1024          446                       # Occupied blocks per task id
 system.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
 system.l2cache.tags.age_task_id_blocks_1024::1          384                       # Occupied blocks per task id
 system.l2cache.tags.occ_task_id_percent::1024     0.108887                       # Percentage of cache occupancy per task id
 system.l2cache.tags.tag_accesses                 4534                       # Number of tag accesses
 system.l2cache.tags.data_accesses                4534                       # Number of data accesses
-system.l2cache.pwrStateResidencyTicks::UNDEFINED     62213000                       # Cumulative time (in ticks) in various power states
+system.l2cache.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
 system.l2cache.ReadSharedReq_hits::cpu.inst            3                       # number of ReadSharedReq hits
 system.l2cache.ReadSharedReq_hits::total            3                       # number of ReadSharedReq hits
 system.l2cache.demand_hits::cpu.inst                3                       # number of demand (read+write) hits
@@ -602,17 +612,17 @@ system.l2cache.demand_misses::total               446                       # nu
 system.l2cache.overall_misses::cpu.inst           278                       # number of overall misses
 system.l2cache.overall_misses::cpu.data           168                       # number of overall misses
 system.l2cache.overall_misses::total              446                       # number of overall misses
-system.l2cache.ReadExReq_miss_latency::cpu.data      7265000                       # number of ReadExReq miss cycles
-system.l2cache.ReadExReq_miss_latency::total      7265000                       # number of ReadExReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.inst     27088000                       # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.data      9412000                       # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::total     36500000                       # number of ReadSharedReq miss cycles
-system.l2cache.demand_miss_latency::cpu.inst     27088000                       # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::cpu.data     16677000                       # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::total     43765000                       # number of demand (read+write) miss cycles
-system.l2cache.overall_miss_latency::cpu.inst     27088000                       # number of overall miss cycles
-system.l2cache.overall_miss_latency::cpu.data     16677000                       # number of overall miss cycles
-system.l2cache.overall_miss_latency::total     43765000                       # number of overall miss cycles
+system.l2cache.ReadExReq_miss_latency::cpu.data      7437000                       # number of ReadExReq miss cycles
+system.l2cache.ReadExReq_miss_latency::total      7437000                       # number of ReadExReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.inst     29087000                       # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.data      9786000                       # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::total     38873000                       # number of ReadSharedReq miss cycles
+system.l2cache.demand_miss_latency::cpu.inst     29087000                       # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::cpu.data     17223000                       # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::total     46310000                       # number of demand (read+write) miss cycles
+system.l2cache.overall_miss_latency::cpu.inst     29087000                       # number of overall miss cycles
+system.l2cache.overall_miss_latency::cpu.data     17223000                       # number of overall miss cycles
+system.l2cache.overall_miss_latency::total     46310000                       # number of overall miss cycles
 system.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
 system.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
 system.l2cache.ReadSharedReq_accesses::cpu.inst          281                       # number of ReadSharedReq accesses(hits+misses)
@@ -635,17 +645,17 @@ system.l2cache.demand_miss_rate::total       0.993318                       # mi
 system.l2cache.overall_miss_rate::cpu.inst     0.989324                       # miss rate for overall accesses
 system.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.l2cache.overall_miss_rate::total      0.993318                       # miss rate for overall accesses
-system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99520.547945                       # average ReadExReq miss latency
-system.l2cache.ReadExReq_avg_miss_latency::total 99520.547945                       # average ReadExReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97438.848921                       # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99073.684211                       # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::total 97855.227882                       # average ReadSharedReq miss latency
-system.l2cache.demand_avg_miss_latency::cpu.inst 97438.848921                       # average overall miss latency
-system.l2cache.demand_avg_miss_latency::cpu.data 99267.857143                       # average overall miss latency
-system.l2cache.demand_avg_miss_latency::total 98127.802691                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.inst 97438.848921                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.data 99267.857143                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::total 98127.802691                       # average overall miss latency
+system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101876.712329                       # average ReadExReq miss latency
+system.l2cache.ReadExReq_avg_miss_latency::total 101876.712329                       # average ReadExReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104629.496403                       # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103010.526316                       # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::total 104217.158177                       # average ReadSharedReq miss latency
+system.l2cache.demand_avg_miss_latency::cpu.inst 104629.496403                       # average overall miss latency
+system.l2cache.demand_avg_miss_latency::cpu.data 102517.857143                       # average overall miss latency
+system.l2cache.demand_avg_miss_latency::total 103834.080717                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.inst 104629.496403                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.data 102517.857143                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::total 103834.080717                       # average overall miss latency
 system.l2cache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.l2cache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -663,17 +673,17 @@ system.l2cache.demand_mshr_misses::total          446                       # nu
 system.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
 system.l2cache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
 system.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
-system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5805000                       # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadExReq_mshr_miss_latency::total      5805000                       # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     21528000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7512000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::total     29040000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.inst     21528000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.data     13317000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::total     34845000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.inst     21528000                       # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.data     13317000                       # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::total     34845000                       # number of overall MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5977000                       # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::total      5977000                       # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     23527000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7886000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::total     31413000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.inst     23527000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.data     13863000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::total     37390000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.inst     23527000                       # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.data     13863000                       # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::total     37390000                       # number of overall MSHR miss cycles
 system.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst     0.989324                       # mshr miss rate for ReadSharedReq accesses
@@ -685,24 +695,24 @@ system.l2cache.demand_mshr_miss_rate::total     0.993318                       #
 system.l2cache.overall_mshr_miss_rate::cpu.inst     0.989324                       # mshr miss rate for overall accesses
 system.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.l2cache.overall_mshr_miss_rate::total     0.993318                       # mshr miss rate for overall accesses
-system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79520.547945                       # average ReadExReq mshr miss latency
-system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79520.547945                       # average ReadExReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77438.848921                       # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79073.684211                       # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77855.227882                       # average ReadSharedReq mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77438.848921                       # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79267.857143                       # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::total 78127.802691                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77438.848921                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79267.857143                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::total 78127.802691                       # average overall mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81876.712329                       # average ReadExReq mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81876.712329                       # average ReadExReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84629.496403                       # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83010.526316                       # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84217.158177                       # average ReadSharedReq mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84629.496403                       # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82517.857143                       # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::total 83834.080717                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84629.496403                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82517.857143                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::total 83834.080717                       # average overall mshr miss latency
 system.membus.snoop_filter.tot_requests           446                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     62213000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                373                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
@@ -725,7 +735,7 @@ system.membus.snoop_fanout::max_value               0                       # Re
 system.membus.snoop_fanout::total                 446                       # Request fanout histogram
 system.membus.reqLayer0.occupancy              446000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            2375750                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.8                       # Layer utilization (%)
+system.membus.respLayer0.occupancy            2377500                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization              3.7                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini
index 6eea99b33..2d26791e9 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini
@@ -23,7 +23,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:536870911
+mem_ranges=0:536870911:0:0:0:0
 memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
@@ -166,7 +166,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -271,27 +271,27 @@ transition_latency=100000000
 
 [system.mem_ctrl]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -311,6 +311,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -320,7 +321,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:536870911
+range=0:536870911:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -342,9 +343,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -353,6 +354,7 @@ port=system.membus.master[0]
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -364,7 +366,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -372,3 +374,10 @@ width=16
 master=system.mem_ctrl.port
 slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout
index eb0348157..40266a5d8 100755
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 15:05:26
-gem5 executing on e108600-lin, pid 24207
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:05:23
+gem5 executing on e108600-lin, pid 17594
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 325849000 because target called exit()
+Exiting @ tick 372284000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
index 670cfd0c1..afb55617d 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000333                       # Number of seconds simulated
-sim_ticks                                   332645000                       # Number of ticks simulated
-final_tick                                  332645000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000372                       # Number of seconds simulated
+sim_ticks                                   372284000                       # Number of ticks simulated
+final_tick                                  372284000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 141116                       # Simulator instruction rate (inst/s)
-host_op_rate                                   163173                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9403646091                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 651444                       # Number of bytes of host memory used
+host_inst_rate                                 131983                       # Simulator instruction rate (inst/s)
+host_op_rate                                   152589                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9840410910                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 650048                       # Number of bytes of host memory used
 host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        4988                       # Number of instructions simulated
 sim_ops                                          5770                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED    332645000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED    372284000                       # Cumulative time (in ticks) in various power states
 system.mem_ctrl.bytes_read::cpu.inst            20108                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::cpu.data             4672                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::total               24780                       # Number of bytes read from this memory
@@ -26,16 +26,16 @@ system.mem_ctrl.num_reads::cpu.data              1061                       # Nu
 system.mem_ctrl.num_reads::total                 6088                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_writes::cpu.data              936                       # Number of write requests responded to by this memory
 system.mem_ctrl.num_writes::total                 936                       # Number of write requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst            60448827                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data            14045003                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total               74493830                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst       60448827                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total          60448827                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::cpu.data           11110944                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::total              11110944                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst           60448827                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data           25155947                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total              85604774                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.inst            54012528                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data            12549559                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total               66562087                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst       54012528                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total          54012528                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::cpu.data            9927905                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::total               9927905                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst           54012528                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data           22477463                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total              76489992                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrl.readReqs                         6089                       # Number of read requests accepted
 system.mem_ctrl.writeReqs                         936                       # Number of write requests accepted
 system.mem_ctrl.readBursts                       6089                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -82,7 +82,7 @@ system.mem_ctrl.perBankWrBursts::14                 0                       # Pe
 system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
 system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
 system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
-system.mem_ctrl.totGap                      332568000                       # Total gap between requests
+system.mem_ctrl.totGap                      372207000                       # Total gap between requests
 system.mem_ctrl.readPktSize::0                     70                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::1                      1                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::2                   5858                       # Read request sizes (log2)
@@ -193,20 +193,20 @@ system.mem_ctrl.wrQLenPdf::60                       0                       # Wh
 system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples          498                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean     770.698795                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean    632.685353                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev    340.090332                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127            21      4.22%      4.22% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255           40      8.03%     12.25% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383           36      7.23%     19.48% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511           28      5.62%     25.10% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639           23      4.62%     29.72% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767           25      5.02%     34.74% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895           24      4.82%     39.56% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-1023           28      5.62%     45.18% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151          273     54.82%    100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total           498                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::samples          514                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean     749.322957                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean    608.037375                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev    344.826867                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127            25      4.86%      4.86% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255           42      8.17%     13.04% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383           44      8.56%     21.60% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511           26      5.06%     26.65% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639           25      4.86%     31.52% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767           34      6.61%     38.13% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895           27      5.25%     43.39% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::896-1023           27      5.25%     48.64% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151          264     51.36%    100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total           514                       # Bytes accessed per row activation
 system.mem_ctrl.rdPerTurnAround::samples            4                       # Reads before turning the bus around for writes
 system.mem_ctrl.rdPerTurnAround::mean     1490.500000                       # Reads before turning the bus around for writes
 system.mem_ctrl.rdPerTurnAround::gmean    1373.591360                       # Reads before turning the bus around for writes
@@ -221,58 +221,68 @@ system.mem_ctrl.wrPerTurnAround::mean              16                       # Wr
 system.mem_ctrl.wrPerTurnAround::gmean      16.000000                       # Writes before turning the bus around for reads
 system.mem_ctrl.wrPerTurnAround::16                 4    100.00%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrl.wrPerTurnAround::total              4                       # Writes before turning the bus around for reads
-system.mem_ctrl.totQLat                      17899250                       # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat                130193000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totQLat                      57609500                       # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat                169903250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.mem_ctrl.totBusLat                    29945000                       # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat                       2988.69                       # Average queueing delay per DRAM burst
+system.mem_ctrl.avgQLat                       9619.22                       # Average queueing delay per DRAM burst
 system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat                 21738.69                       # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW                       1152.27                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW                         12.31                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys                      74.51                       # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys                      11.11                       # Average system write bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat                 28369.22                       # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW                       1029.58                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBW                         11.00                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys                      66.57                       # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBWSys                       9.93                       # Average system write bandwidth in MiByte/s
 system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil                          9.10                       # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead                      9.00                       # Data bus utilization in percentage for reads
-system.mem_ctrl.busUtilWrite                     0.10                       # Data bus utilization in percentage for writes
+system.mem_ctrl.busUtil                          8.13                       # Data bus utilization in percentage
+system.mem_ctrl.busUtilRead                      8.04                       # Data bus utilization in percentage for reads
+system.mem_ctrl.busUtilWrite                     0.09                       # Data bus utilization in percentage for writes
 system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
 system.mem_ctrl.avgWrQLen                       24.94                       # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits                      5487                       # Number of row buffer hits during reads
+system.mem_ctrl.readRowHits                      5473                       # Number of row buffer hits during reads
 system.mem_ctrl.writeRowHits                       62                       # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate                  91.62                       # Row buffer hit rate for reads
+system.mem_ctrl.readRowHitRate                  91.38                       # Row buffer hit rate for reads
 system.mem_ctrl.writeRowHitRate                 76.54                       # Row buffer hit rate for writes
-system.mem_ctrl.avgGap                       47340.64                       # Average gap between requests
-system.mem_ctrl.pageHitRate                     91.42                       # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy                   2812320                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy                   1534500                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy                 38048400                       # Energy for read commands per rank (pJ)
+system.mem_ctrl.avgGap                       52983.20                       # Average gap between requests
+system.mem_ctrl.pageHitRate                     91.19                       # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy                   2727480                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy                   1438305                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy                 35364420                       # Energy for read commands per rank (pJ)
 system.mem_ctrl_0.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy              21359520                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy             216770715                       # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy               6219750                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy               286745205                       # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower             876.139742                       # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE       7265500                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::REF       10920000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT      309110750                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrl_1.actEnergy                    922320                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy                    503250                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy                  7893600                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_1.writeEnergy                  311040                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy              21359520                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy             188416350                       # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy              31092000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy               250498080                       # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower             765.387945                       # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE      51038750                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::REF       10920000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT      265729250                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED    332645000                       # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED    332645000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl_0.refreshEnergy          28888080.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_0.actBackEnergy              64999380                       # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy               1619520                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.actPowerDownEnergy         98643060                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_0.prePowerDownEnergy          3533760                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_0.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_0.totalEnergy               237214005                       # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower             637.183891                       # Core power per rank (mW)
+system.mem_ctrl_0.totalIdleTime             225396250                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_0.memoryStateTime::IDLE        954000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::REF       12220000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::PRE_PDN      9196500                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT      133713750                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT_PDN    216199750                       # Time in different power states
+system.mem_ctrl_1.actEnergy                    971040                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy                    512325                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.readEnergy                  7389900                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_1.writeEnergy                  334080                       # Energy for write commands per rank (pJ)
+system.mem_ctrl_1.refreshEnergy          27658800.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_1.actBackEnergy              18607080                       # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy                791520                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.actPowerDownEnergy        128152530                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_1.prePowerDownEnergy          7837920                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_1.selfRefreshEnergy           7265340                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_1.totalEnergy               199520535                       # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower             535.934929                       # Core power per rank (mW)
+system.mem_ctrl_1.totalIdleTime             328663750                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_1.memoryStateTime::IDLE        770000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::REF       11706000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::SREF      27971000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::PRE_PDN     20415250                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT       30385000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT_PDN    281036750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED    372284000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED    372284000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -302,7 +312,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED    332645000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED    372284000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -332,7 +342,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED    332645000                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED    372284000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -362,7 +372,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED    332645000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED    372284000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -393,8 +403,8 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON       332645000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                           332645                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON       372284000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                           372284                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4988                       # Number of instructions committed
@@ -415,7 +425,7 @@ system.cpu.num_mem_refs                          2035                       # nu
 system.cpu.num_load_insts                        1085                       # Number of load instructions
 system.cpu.num_store_insts                        950                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.001000                       # Number of idle cycles
-system.cpu.num_busy_cycles               332644.999000                       # Number of busy cycles
+system.cpu.num_busy_cycles               372283.999000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1107                       # Number of branches fetched
@@ -460,7 +470,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED    332645000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED    372284000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                6078                       # Transaction distribution
 system.membus.trans_dist::ReadResp               6088                       # Transaction distribution
 system.membus.trans_dist::WriteReq                925                       # Transaction distribution
@@ -487,10 +497,10 @@ system.membus.snoop_fanout::min_value               0                       # Re
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7025                       # Request fanout histogram
 system.membus.reqLayer0.occupancy             7961000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
-system.membus.respLayer0.occupancy           11412500                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3325250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
+system.membus.reqLayer0.utilization               2.1                       # Layer utilization (%)
+system.membus.respLayer0.occupancy           11413250                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization              3.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3327250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini
index ad9e5a13b..733323a88 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini
@@ -23,7 +23,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:536870911
+mem_ranges=0:536870911:0:0:0:0
 memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
@@ -102,7 +102,7 @@ icache_port=system.cpu.icache.cpu_side
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -198,7 +198,7 @@ sys=system
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -258,7 +258,7 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
 id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
@@ -393,7 +393,7 @@ system=system
 [system.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -438,27 +438,27 @@ size=262144
 
 [system.mem_ctrl]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -478,6 +478,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -487,7 +488,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:536870911
+range=0:536870911:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -509,9 +510,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -520,6 +521,7 @@ port=system.membus.master[0]
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -531,7 +533,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -539,3 +541,10 @@ width=16
 master=system.mem_ctrl.port
 slave=system.l2cache.mem_side system.system_port
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout
index a3411dc5e..7a7d67b77 100755
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 15:03:01
-gem5 executing on e108600-lin, pid 24156
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:05:17
+gem5 executing on e108600-lin, pid 17589
 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 49855000 because target called exit()
+Exiting @ tick 52453000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
index 005f27b4b..3eb7c70d8 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000050                       # Number of seconds simulated
-sim_ticks                                    50074000                       # Number of ticks simulated
-final_tick                                   50074000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000052                       # Number of seconds simulated
+sim_ticks                                    52453000                       # Number of ticks simulated
+final_tick                                   52453000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 207988                       # Simulator instruction rate (inst/s)
-host_op_rate                                   240459                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2085706484                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 655032                       # Number of bytes of host memory used
+host_inst_rate                                 234245                       # Simulator instruction rate (inst/s)
+host_op_rate                                   270642                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2457731659                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 654144                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        4988                       # Number of instructions simulated
 sim_ops                                          5770                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.mem_ctrl.bytes_read::cpu.inst            14400                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::cpu.data             8064                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::total               22464                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total          14400                       # Nu
 system.mem_ctrl.num_reads::cpu.inst               225                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_reads::cpu.data               126                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_reads::total                  351                       # Number of read requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst           287574390                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data           161041658                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total              448616048                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst      287574390                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total         287574390                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst          287574390                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data          161041658                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total             448616048                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.inst           274531485                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data           153737632                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total              428269117                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst      274531485                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total         274531485                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst          274531485                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data          153737632                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total             428269117                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrl.readReqs                          351                       # Number of read requests accepted
 system.mem_ctrl.writeReqs                           0                       # Number of write requests accepted
 system.mem_ctrl.readBursts                        351                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14                 0                       # Pe
 system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
 system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
 system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
-system.mem_ctrl.totGap                       49975000                       # Total gap between requests
+system.mem_ctrl.totGap                       52348000                       # Total gap between requests
 system.mem_ctrl.readPktSize::0                      0                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::1                      0                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::2                      0                       # Read request sizes (log2)
@@ -187,71 +187,81 @@ system.mem_ctrl.wrQLenPdf::60                       0                       # Wh
 system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples           73                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean     300.712329                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean    213.377798                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev    265.316032                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127            14     19.18%     19.18% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255           25     34.25%     53.42% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383           14     19.18%     72.60% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511            5      6.85%     79.45% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639            7      9.59%     89.04% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767            1      1.37%     90.41% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895            2      2.74%     93.15% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151            5      6.85%    100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total            73                       # Bytes accessed per row activation
-system.mem_ctrl.totQLat                       2342250                       # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat                  8923500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.bytesPerActivate::samples           75                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean     285.866667                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean    188.503913                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev    282.583704                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127            22     29.33%     29.33% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255           20     26.67%     56.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383           15     20.00%     76.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511            4      5.33%     81.33% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639            4      5.33%     86.67% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767            2      2.67%     89.33% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895            2      2.67%     92.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151            6      8.00%    100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total            75                       # Bytes accessed per row activation
+system.mem_ctrl.totQLat                       4720500                       # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat                 11301750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.mem_ctrl.totBusLat                     1755000                       # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat                       6673.08                       # Average queueing delay per DRAM burst
+system.mem_ctrl.avgQLat                      13448.72                       # Average queueing delay per DRAM burst
 system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat                 25423.08                       # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW                        448.62                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat                 32198.72                       # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW                        428.27                       # Average DRAM read bandwidth in MiByte/s
 system.mem_ctrl.avgWrBW                          0.00                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys                     448.62                       # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys                     428.27                       # Average system read bandwidth in MiByte/s
 system.mem_ctrl.avgWrBWSys                       0.00                       # Average system write bandwidth in MiByte/s
 system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil                          3.50                       # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead                      3.50                       # Data bus utilization in percentage for reads
+system.mem_ctrl.busUtil                          3.35                       # Data bus utilization in percentage
+system.mem_ctrl.busUtilRead                      3.35                       # Data bus utilization in percentage for reads
 system.mem_ctrl.busUtilWrite                     0.00                       # Data bus utilization in percentage for writes
 system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
 system.mem_ctrl.avgWrQLen                        0.00                       # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits                       274                       # Number of row buffer hits during reads
+system.mem_ctrl.readRowHits                       270                       # Number of row buffer hits during reads
 system.mem_ctrl.writeRowHits                        0                       # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate                  78.06                       # Row buffer hit rate for reads
+system.mem_ctrl.readRowHitRate                  76.92                       # Row buffer hit rate for reads
 system.mem_ctrl.writeRowHitRate                   nan                       # Row buffer hit rate for writes
-system.mem_ctrl.avgGap                      142378.92                       # Average gap between requests
-system.mem_ctrl.pageHitRate                     78.06                       # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy                    347760                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl.avgGap                      149139.60                       # Average gap between requests
+system.mem_ctrl.pageHitRate                     76.92                       # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy                    378420                       # Energy for activate commands per rank (pJ)
 system.mem_ctrl_0.preEnergy                    189750                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy                  1817400                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.readEnergy                  1813560                       # Energy for read commands per rank (pJ)
 system.mem_ctrl_0.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy               3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy              31477680                       # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy                574500                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy                37458450                       # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower             797.370018                       # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE        805250                       # Time in different power states
+system.mem_ctrl_0.refreshEnergy          3687840.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_0.actBackEnergy               4500720                       # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy                 84480                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.actPowerDownEnergy         19212990                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_0.prePowerDownEnergy            88320                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_0.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_0.totalEnergy                29956080                       # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower             571.095108                       # Core power per rank (mW)
+system.mem_ctrl_0.totalIdleTime              42304000                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_0.memoryStateTime::IDLE         53000                       # Time in different power states
 system.mem_ctrl_0.memoryStateTime::REF        1560000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT       44626000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrl_1.actEnergy                    189000                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy                    103125                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy                   741000                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::PRE_PDN       229750                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT        8478750                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT_PDN     42131500                       # Time in different power states
+system.mem_ctrl_1.actEnergy                    199920                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy                     94875                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.readEnergy                   692580                       # Energy for read commands per rank (pJ)
 system.mem_ctrl_1.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy               3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy              30101985                       # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy               1781250                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy                35967720                       # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower             765.637167                       # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE       3011750                       # Time in different power states
+system.mem_ctrl_1.refreshEnergy          3687840.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_1.actBackEnergy               2032620                       # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy                139680                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.actPowerDownEnergy         19936320                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_1.prePowerDownEnergy          1502400                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_1.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_1.totalEnergy                28286235                       # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower             539.260491                       # Core power per rank (mW)
+system.mem_ctrl_1.totalIdleTime              44784500                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_1.memoryStateTime::IDLE        200000                       # Time in different power states
 system.mem_ctrl_1.memoryStateTime::REF        1560000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT       42630250                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl_1.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::PRE_PDN      3909750                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT        3056250                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT_PDN     43727000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -281,7 +291,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -311,7 +321,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -341,7 +351,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -372,8 +382,8 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        50074000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            50074                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        52453000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            52453                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4988                       # Number of instructions committed
@@ -394,7 +404,7 @@ system.cpu.num_mem_refs                          2035                       # nu
 system.cpu.num_load_insts                        1085                       # Number of load instructions
 system.cpu.num_store_insts                        950                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.001000                       # Number of idle cycles
-system.cpu.num_busy_cycles               50073.999000                       # Number of busy cycles
+system.cpu.num_busy_cycles               52452.999000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1107                       # Number of branches fetched
@@ -433,23 +443,23 @@ system.cpu.op_class::MemWrite                     950     16.29%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5831                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            84.375326                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            84.380856                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1855                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               142                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             13.063380                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    84.375326                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.082398                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.082398                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    84.380856                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.082403                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.082403                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          142                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          123                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.138672                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              4136                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             4136                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data          951                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             951                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          882                       # number of WriteReq hits
@@ -470,14 +480,14 @@ system.cpu.dcache.demand_misses::cpu.data          142                       # n
 system.cpu.dcache.demand_misses::total            142                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          142                       # number of overall misses
 system.cpu.dcache.overall_misses::total           142                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      8615000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      8615000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      4388000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      4388000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     13003000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     13003000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     13003000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     13003000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      9073000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      9073000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      4652000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      4652000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     13725000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     13725000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     13725000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     13725000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1050                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1050                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
@@ -498,14 +508,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.071899
 system.cpu.dcache.demand_miss_rate::total     0.071899                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.071899                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.071899                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87020.202020                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 87020.202020                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102046.511628                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 102046.511628                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 91570.422535                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 91570.422535                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 91570.422535                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 91570.422535                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91646.464646                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 91646.464646                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108186.046512                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 108186.046512                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 96654.929577                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 96654.929577                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 96654.929577                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 96654.929577                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -520,14 +530,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          142
 system.cpu.dcache.demand_mshr_misses::total          142                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          142                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8417000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      8417000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4302000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4302000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12719000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12719000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12719000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12719000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8875000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      8875000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4566000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4566000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13441000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     13441000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13441000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     13441000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.094286                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.094286                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046486                       # mshr miss rate for WriteReq accesses
@@ -536,31 +546,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.071899
 system.cpu.dcache.demand_mshr_miss_rate::total     0.071899                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.071899                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.071899                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85020.202020                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85020.202020                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100046.511628                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100046.511628                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89570.422535                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 89570.422535                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89570.422535                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 89570.422535                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89646.464646                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89646.464646                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106186.046512                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106186.046512                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94654.929577                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 94654.929577                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94654.929577                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 94654.929577                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                70                       # number of replacements
-system.cpu.icache.tags.tagsinuse            96.598037                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse            96.586088                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                4779                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               249                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             19.192771                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    96.598037                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.377336                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.377336                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst    96.586088                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.377289                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.377289                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          179                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          128                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.699219                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses             10305                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses            10305                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst         4779                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            4779                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          4779                       # number of demand (read+write) hits
@@ -573,12 +583,12 @@ system.cpu.icache.demand_misses::cpu.inst          249                       # n
 system.cpu.icache.demand_misses::total            249                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          249                       # number of overall misses
 system.cpu.icache.overall_misses::total           249                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     23815000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     23815000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     23815000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     23815000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     23815000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     23815000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25472000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25472000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25472000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25472000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25472000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25472000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         5028                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         5028                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         5028                       # number of demand (read+write) accesses
@@ -591,12 +601,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.049523
 system.cpu.icache.demand_miss_rate::total     0.049523                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.049523                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.049523                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 95642.570281                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 95642.570281                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 95642.570281                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 95642.570281                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 95642.570281                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 95642.570281                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102297.188755                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 102297.188755                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 102297.188755                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 102297.188755                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 102297.188755                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 102297.188755                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -609,31 +619,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          249
 system.cpu.icache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          249                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          249                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23317000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     23317000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23317000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     23317000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23317000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     23317000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24974000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     24974000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24974000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     24974000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24974000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     24974000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.049523                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.049523                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.049523                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.049523                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.049523                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.049523                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 93642.570281                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 93642.570281                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 93642.570281                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 93642.570281                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 93642.570281                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 93642.570281                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100297.188755                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100297.188755                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100297.188755                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 100297.188755                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100297.188755                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 100297.188755                       # average overall mshr miss latency
 system.l2bus.snoop_filter.tot_requests            461                       # Total number of requests made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_requests           94                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_requests           10                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.l2bus.snoop_filter.tot_snoops                0                       # Total number of snoops made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l2bus.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.l2bus.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.l2bus.trans_dist::ReadResp                 348                       # Transaction distribution
 system.l2bus.trans_dist::CleanEvict                70                       # Transaction distribution
 system.l2bus.trans_dist::ReadExReq                 43                       # Transaction distribution
@@ -661,28 +671,28 @@ system.l2bus.snoop_fanout::total                  391                       # Re
 system.l2bus.reqLayer0.occupancy               461000                       # Layer occupancy (ticks)
 system.l2bus.reqLayer0.utilization                0.9                       # Layer utilization (%)
 system.l2bus.respLayer0.occupancy              747000                       # Layer occupancy (ticks)
-system.l2bus.respLayer0.utilization               1.5                       # Layer utilization (%)
+system.l2bus.respLayer0.utilization               1.4                       # Layer utilization (%)
 system.l2bus.respLayer1.occupancy              426000                       # Layer occupancy (ticks)
-system.l2bus.respLayer1.utilization               0.9                       # Layer utilization (%)
-system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.l2bus.respLayer1.utilization               0.8                       # Layer utilization (%)
+system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.l2cache.tags.replacements                    0                       # number of replacements
-system.l2cache.tags.tagsinuse              184.338383                       # Cycle average of tags in use
+system.l2cache.tags.tagsinuse              184.362995                       # Cycle average of tags in use
 system.l2cache.tags.total_refs                    100                       # Total number of references to valid blocks.
 system.l2cache.tags.sampled_refs                  351                       # Sample count of references to valid blocks.
 system.l2cache.tags.avg_refs                 0.284900                       # Average number of references to valid blocks.
 system.l2cache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.l2cache.tags.occ_blocks::cpu.inst   107.366220                       # Average occupied blocks per requestor
-system.l2cache.tags.occ_blocks::cpu.data    76.972162                       # Average occupied blocks per requestor
-system.l2cache.tags.occ_percent::cpu.inst     0.026212                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::cpu.data     0.018792                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::total       0.045004                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_blocks::cpu.inst   107.367017                       # Average occupied blocks per requestor
+system.l2cache.tags.occ_blocks::cpu.data    76.995978                       # Average occupied blocks per requestor
+system.l2cache.tags.occ_percent::cpu.inst     0.026213                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::cpu.data     0.018798                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::total       0.045010                       # Average percentage of cache occupancy
 system.l2cache.tags.occ_task_id_blocks::1024          351                       # Occupied blocks per task id
-system.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.l2cache.tags.age_task_id_blocks_1024::1          289                       # Occupied blocks per task id
+system.l2cache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
+system.l2cache.tags.age_task_id_blocks_1024::1          292                       # Occupied blocks per task id
 system.l2cache.tags.occ_task_id_percent::1024     0.085693                       # Percentage of cache occupancy per task id
 system.l2cache.tags.tag_accesses                 3959                       # Number of tag accesses
 system.l2cache.tags.data_accesses                3959                       # Number of data accesses
-system.l2cache.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.l2cache.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.l2cache.ReadSharedReq_hits::cpu.inst           24                       # number of ReadSharedReq hits
 system.l2cache.ReadSharedReq_hits::cpu.data           16                       # number of ReadSharedReq hits
 system.l2cache.ReadSharedReq_hits::total           40                       # number of ReadSharedReq hits
@@ -703,17 +713,17 @@ system.l2cache.demand_misses::total               351                       # nu
 system.l2cache.overall_misses::cpu.inst           225                       # number of overall misses
 system.l2cache.overall_misses::cpu.data           126                       # number of overall misses
 system.l2cache.overall_misses::total              351                       # number of overall misses
-system.l2cache.ReadExReq_miss_latency::cpu.data      4173000                       # number of ReadExReq miss cycles
-system.l2cache.ReadExReq_miss_latency::total      4173000                       # number of ReadExReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.inst     22026000                       # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.data      7756000                       # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::total     29782000                       # number of ReadSharedReq miss cycles
-system.l2cache.demand_miss_latency::cpu.inst     22026000                       # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::cpu.data     11929000                       # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::total     33955000                       # number of demand (read+write) miss cycles
-system.l2cache.overall_miss_latency::cpu.inst     22026000                       # number of overall miss cycles
-system.l2cache.overall_miss_latency::cpu.data     11929000                       # number of overall miss cycles
-system.l2cache.overall_miss_latency::total     33955000                       # number of overall miss cycles
+system.l2cache.ReadExReq_miss_latency::cpu.data      4437000                       # number of ReadExReq miss cycles
+system.l2cache.ReadExReq_miss_latency::total      4437000                       # number of ReadExReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.inst     23683000                       # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.data      8214000                       # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::total     31897000                       # number of ReadSharedReq miss cycles
+system.l2cache.demand_miss_latency::cpu.inst     23683000                       # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::cpu.data     12651000                       # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::total     36334000                       # number of demand (read+write) miss cycles
+system.l2cache.overall_miss_latency::cpu.inst     23683000                       # number of overall miss cycles
+system.l2cache.overall_miss_latency::cpu.data     12651000                       # number of overall miss cycles
+system.l2cache.overall_miss_latency::total     36334000                       # number of overall miss cycles
 system.l2cache.ReadExReq_accesses::cpu.data           43                       # number of ReadExReq accesses(hits+misses)
 system.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
 system.l2cache.ReadSharedReq_accesses::cpu.inst          249                       # number of ReadSharedReq accesses(hits+misses)
@@ -736,17 +746,17 @@ system.l2cache.demand_miss_rate::total       0.897698                       # mi
 system.l2cache.overall_miss_rate::cpu.inst     0.903614                       # miss rate for overall accesses
 system.l2cache.overall_miss_rate::cpu.data     0.887324                       # miss rate for overall accesses
 system.l2cache.overall_miss_rate::total      0.897698                       # miss rate for overall accesses
-system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97046.511628                       # average ReadExReq miss latency
-system.l2cache.ReadExReq_avg_miss_latency::total 97046.511628                       # average ReadExReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97893.333333                       # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93445.783133                       # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::total 96694.805195                       # average ReadSharedReq miss latency
-system.l2cache.demand_avg_miss_latency::cpu.inst 97893.333333                       # average overall miss latency
-system.l2cache.demand_avg_miss_latency::cpu.data 94674.603175                       # average overall miss latency
-system.l2cache.demand_avg_miss_latency::total 96737.891738                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.inst 97893.333333                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.data 94674.603175                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::total 96737.891738                       # average overall miss latency
+system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103186.046512                       # average ReadExReq miss latency
+system.l2cache.ReadExReq_avg_miss_latency::total 103186.046512                       # average ReadExReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 105257.777778                       # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98963.855422                       # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::total 103561.688312                       # average ReadSharedReq miss latency
+system.l2cache.demand_avg_miss_latency::cpu.inst 105257.777778                       # average overall miss latency
+system.l2cache.demand_avg_miss_latency::cpu.data 100404.761905                       # average overall miss latency
+system.l2cache.demand_avg_miss_latency::total 103515.669516                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.inst 105257.777778                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.data 100404.761905                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::total 103515.669516                       # average overall miss latency
 system.l2cache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.l2cache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -764,17 +774,17 @@ system.l2cache.demand_mshr_misses::total          351                       # nu
 system.l2cache.overall_mshr_misses::cpu.inst          225                       # number of overall MSHR misses
 system.l2cache.overall_mshr_misses::cpu.data          126                       # number of overall MSHR misses
 system.l2cache.overall_mshr_misses::total          351                       # number of overall MSHR misses
-system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3313000                       # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadExReq_mshr_miss_latency::total      3313000                       # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     17526000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6096000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::total     23622000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.inst     17526000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.data      9409000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::total     26935000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.inst     17526000                       # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.data      9409000                       # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::total     26935000                       # number of overall MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3577000                       # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::total      3577000                       # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     19183000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6554000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::total     25737000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.inst     19183000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.data     10131000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::total     29314000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.inst     19183000                       # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.data     10131000                       # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::total     29314000                       # number of overall MSHR miss cycles
 system.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst     0.903614                       # mshr miss rate for ReadSharedReq accesses
@@ -786,24 +796,24 @@ system.l2cache.demand_mshr_miss_rate::total     0.897698                       #
 system.l2cache.overall_mshr_miss_rate::cpu.inst     0.903614                       # mshr miss rate for overall accesses
 system.l2cache.overall_mshr_miss_rate::cpu.data     0.887324                       # mshr miss rate for overall accesses
 system.l2cache.overall_mshr_miss_rate::total     0.897698                       # mshr miss rate for overall accesses
-system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77046.511628                       # average ReadExReq mshr miss latency
-system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77046.511628                       # average ReadExReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77893.333333                       # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73445.783133                       # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76694.805195                       # average ReadSharedReq mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77893.333333                       # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.data 74674.603175                       # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::total 76737.891738                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77893.333333                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.data 74674.603175                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::total 76737.891738                       # average overall mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83186.046512                       # average ReadExReq mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83186.046512                       # average ReadExReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 85257.777778                       # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78963.855422                       # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83561.688312                       # average ReadSharedReq mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 85257.777778                       # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80404.761905                       # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::total 83515.669516                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 85257.777778                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80404.761905                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::total 83515.669516                       # average overall mshr miss latency
 system.membus.snoop_filter.tot_requests           351                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     50074000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     52453000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                308                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
@@ -826,7 +836,7 @@ system.membus.snoop_fanout::max_value               0                       # Re
 system.membus.snoop_fanout::total                 351                       # Request fanout histogram
 system.membus.reqLayer0.occupancy              351000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1865500                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.7                       # Layer utilization (%)
+system.membus.respLayer0.occupancy            1866250                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization              3.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
index de0268a39..3f1a37472 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
@@ -23,7 +23,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:536870911
+mem_ranges=0:536870911:0:0:0:0
 memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
@@ -155,27 +155,27 @@ transition_latency=100000000
 
 [system.mem_ctrl]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -195,6 +195,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -204,7 +205,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:536870911
+range=0:536870911:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -226,9 +227,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -237,6 +238,7 @@ port=system.membus.master[0]
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -248,7 +250,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -256,3 +258,10 @@ width=16
 master=system.mem_ctrl.port
 slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout
index 194a454d5..05f1fc1ff 100755
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:23:13
-gem5 started Jul 21 2016 14:23:48
-gem5 executing on e108600-lin, pid 13288
+gem5 compiled Oct 13 2016 20:36:34
+gem5 started Oct 13 2016 20:36:59
+gem5 executing on e108600-lin, pid 36838
 command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
 
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ Beginning simulation!
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 368887000 because target called exit()
+Exiting @ tick 423127000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
index 60c6ac279..b290494a3 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000377                       # Number of seconds simulated
-sim_ticks                                   376893000                       # Number of ticks simulated
-final_tick                                  376893000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000423                       # Number of seconds simulated
+sim_ticks                                   423127000                       # Number of ticks simulated
+final_tick                                  423127000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 173660                       # Simulator instruction rate (inst/s)
-host_op_rate                                   173583                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            11593149844                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 632708                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                 243919                       # Simulator instruction rate (inst/s)
+host_op_rate                                   243782                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            18277293383                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 631884                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED    376893000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED    423127000                       # Cumulative time (in ticks) in various power states
 system.mem_ctrl.bytes_read::cpu.inst            22568                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::cpu.data             4301                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::total               26869                       # Number of bytes read from this memory
@@ -26,27 +26,27 @@ system.mem_ctrl.num_reads::cpu.data              1135                       # Nu
 system.mem_ctrl.num_reads::total                 6777                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_writes::cpu.data              901                       # Number of write requests responded to by this memory
 system.mem_ctrl.num_writes::total                 901                       # Number of write requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst            59879064                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data            11411727                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total               71290791                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst       59879064                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total          59879064                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::cpu.data            9554436                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::total               9554436                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst           59879064                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data           20966163                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total              80845227                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.inst            53336232                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data            10164797                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total               63501029                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst       53336232                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total          53336232                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::cpu.data            8510447                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::total               8510447                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst           53336232                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data           18675244                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total              72011476                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrl.readReqs                         6778                       # Number of read requests accepted
 system.mem_ctrl.writeReqs                         901                       # Number of write requests accepted
 system.mem_ctrl.readBursts                       6778                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrl.writeBursts                       901                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrl.bytesReadDRAM                  428096                       # Total number of bytes read from DRAM
-system.mem_ctrl.bytesReadWrQ                     5696                       # Total number of bytes read from write queue
+system.mem_ctrl.bytesReadDRAM                  427712                       # Total number of bytes read from DRAM
+system.mem_ctrl.bytesReadWrQ                     6080                       # Total number of bytes read from write queue
 system.mem_ctrl.bytesWritten                     4096                       # Total number of bytes written to DRAM
 system.mem_ctrl.bytesReadSys                    26873                       # Total read bytes from the system interface side
 system.mem_ctrl.bytesWrittenSys                  3601                       # Total written bytes from the system interface side
-system.mem_ctrl.servicedByWrQ                      89                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrl.mergedWrBursts                    811                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrl.servicedByWrQ                      95                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrl.mergedWrBursts                    808                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrl.neitherReadNorWriteReqs             0                       # Number of requests that are neither read nor write
 system.mem_ctrl.perBankRdBursts::0                275                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::1                  0                       # Per bank write bursts
@@ -55,14 +55,14 @@ system.mem_ctrl.perBankRdBursts::3                  0                       # Pe
 system.mem_ctrl.perBankRdBursts::4                215                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::5                 18                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::6                105                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::7                519                       # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::7                516                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::8                543                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::9               1212                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::10               899                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::11               350                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::12               677                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::13               398                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::14              1429                       # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::14              1426                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::15                49                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::0                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::1                  0                       # Per bank write bursts
@@ -71,18 +71,18 @@ system.mem_ctrl.perBankWrBursts::3                  0                       # Pe
 system.mem_ctrl.perBankWrBursts::4                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::5                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::6                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::7                  8                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::7                  5                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::8                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::9                  7                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::10                 0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::11                 2                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::12                30                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::13                 0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::14                14                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::15                 3                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::14                19                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::15                 1                       # Per bank write bursts
 system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
 system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
-system.mem_ctrl.totGap                      376816000                       # Total gap between requests
+system.mem_ctrl.totGap                      423050000                       # Total gap between requests
 system.mem_ctrl.readPktSize::0                     79                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::1                      1                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::2                   6698                       # Read request sizes (log2)
@@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3                     0                       # Wr
 system.mem_ctrl.writePktSize::4                     0                       # Write request sizes (log2)
 system.mem_ctrl.writePktSize::5                     0                       # Write request sizes (log2)
 system.mem_ctrl.writePktSize::6                     0                       # Write request sizes (log2)
-system.mem_ctrl.rdQLenPdf::0                     6689                       # What read queue length does an incoming req see
+system.mem_ctrl.rdQLenPdf::0                     6683                       # What read queue length does an incoming req see
 system.mem_ctrl.rdQLenPdf::1                        0                       # What read queue length does an incoming req see
 system.mem_ctrl.rdQLenPdf::2                        0                       # What read queue length does an incoming req see
 system.mem_ctrl.rdQLenPdf::3                        0                       # What read queue length does an incoming req see
@@ -155,9 +155,9 @@ system.mem_ctrl.wrQLenPdf::22                       5                       # Wh
 system.mem_ctrl.wrQLenPdf::23                       5                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::24                       5                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::25                       5                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::26                       4                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::27                       4                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::28                       4                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::26                       5                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::27                       5                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::28                       5                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::29                       4                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::30                       4                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::31                       4                       # What write queue length does an incoming req see
@@ -193,26 +193,26 @@ system.mem_ctrl.wrQLenPdf::60                       0                       # Wh
 system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples          838                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean     513.374702                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean    298.080754                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev    413.335022                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127           263     31.38%     31.38% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255           85     10.14%     41.53% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383           42      5.01%     46.54% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511           43      5.13%     51.67% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639           44      5.25%     56.92% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767           53      6.32%     63.25% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895           15      1.79%     65.04% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-1023           22      2.63%     67.66% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151          271     32.34%    100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total           838                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::samples          846                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean     508.141844                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean    296.960814                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev    409.521445                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127           262     30.97%     30.97% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255           81      9.57%     40.54% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383           50      5.91%     46.45% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511           56      6.62%     53.07% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639           41      4.85%     57.92% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767           45      5.32%     63.24% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895           28      3.31%     66.55% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::896-1023           22      2.60%     69.15% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151          261     30.85%    100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total           846                       # Bytes accessed per row activation
 system.mem_ctrl.rdPerTurnAround::samples            4                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::mean     1522.250000                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::gmean    1505.224255                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::stdev     263.075876                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1216-1279            1     25.00%     25.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1280-1343            1     25.00%     50.00% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::mean     1385.500000                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::gmean    1320.719140                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::stdev     457.578044                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::768-831            1     25.00%     25.00% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::1216-1279            1     25.00%     50.00% # Reads before turning the bus around for writes
 system.mem_ctrl.rdPerTurnAround::1664-1727            1     25.00%     75.00% # Reads before turning the bus around for writes
 system.mem_ctrl.rdPerTurnAround::1792-1855            1     25.00%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrl.rdPerTurnAround::total              4                       # Reads before turning the bus around for writes
@@ -221,57 +221,67 @@ system.mem_ctrl.wrPerTurnAround::mean              16                       # Wr
 system.mem_ctrl.wrPerTurnAround::gmean      16.000000                       # Writes before turning the bus around for reads
 system.mem_ctrl.wrPerTurnAround::16                 4    100.00%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrl.wrPerTurnAround::total              4                       # Writes before turning the bus around for reads
-system.mem_ctrl.totQLat                      28198000                       # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat                153616750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrl.totBusLat                    33445000                       # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat                       4215.58                       # Average queueing delay per DRAM burst
+system.mem_ctrl.totQLat                      74613750                       # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat                199920000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totBusLat                    33415000                       # Total ticks spent in databus transfers
+system.mem_ctrl.avgQLat                      11164.71                       # Average queueing delay per DRAM burst
 system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat                 22965.58                       # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW                       1135.86                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW                         10.87                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys                      71.30                       # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys                       9.55                       # Average system write bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat                 29914.71                       # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW                       1010.84                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBW                          9.68                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys                      63.51                       # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBWSys                       8.51                       # Average system write bandwidth in MiByte/s
 system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil                          8.96                       # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead                      8.87                       # Data bus utilization in percentage for reads
+system.mem_ctrl.busUtil                          7.97                       # Data bus utilization in percentage
+system.mem_ctrl.busUtilRead                      7.90                       # Data bus utilization in percentage for reads
 system.mem_ctrl.busUtilWrite                     0.08                       # Data bus utilization in percentage for writes
 system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
-system.mem_ctrl.avgWrQLen                       23.23                       # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits                      5853                       # Number of row buffer hits during reads
+system.mem_ctrl.avgWrQLen                       22.62                       # Average write queue length when enqueuing
+system.mem_ctrl.readRowHits                      5839                       # Number of row buffer hits during reads
 system.mem_ctrl.writeRowHits                       57                       # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate                  87.50                       # Row buffer hit rate for reads
-system.mem_ctrl.writeRowHitRate                 63.33                       # Row buffer hit rate for writes
-system.mem_ctrl.avgGap                       49070.97                       # Average gap between requests
-system.mem_ctrl.pageHitRate                     87.18                       # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy                   1020600                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy                    556875                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy                  8806200                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_0.writeEnergy                   51840                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy              24410880                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy             141780375                       # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy             100031250                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy               276658020                       # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower             739.727326                       # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE     165010500                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::REF       12480000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT      196602500                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrl_1.actEnergy                   5299560                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy                   2891625                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy                 42939000                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_1.writeEnergy                  362880                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy              24410880                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy             252188235                       # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy               3192750                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy               331284930                       # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower             885.747138                       # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE       2538750                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::REF       12480000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT      359011750                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED    376893000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.readRowHitRate                  87.37                       # Row buffer hit rate for reads
+system.mem_ctrl.writeRowHitRate                 61.29                       # Row buffer hit rate for writes
+system.mem_ctrl.avgGap                       55091.81                       # Average gap between requests
+system.mem_ctrl.pageHitRate                     87.01                       # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy                    985320                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy                    519915                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy                  8061060                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.writeEnergy                   26100                       # Energy for write commands per rank (pJ)
+system.mem_ctrl_0.refreshEnergy          33190560.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_0.actBackEnergy              21232500                       # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy               1932000                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.actPowerDownEnergy         84890100                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_0.prePowerDownEnergy         43723680                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_0.selfRefreshEnergy          22684200                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_0.totalEnergy               217245435                       # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower             513.427832                       # Core power per rank (mW)
+system.mem_ctrl_0.totalIdleTime             369366500                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_0.memoryStateTime::IDLE       2976000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::REF       14106000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::SREF      71507250                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::PRE_PDN    113857500                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT       34569250                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT_PDN    186111000                       # Time in different power states
+system.mem_ctrl_1.actEnergy                   5090820                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy                   2690655                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.readEnergy                 39648420                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_1.writeEnergy                  307980                       # Energy for write commands per rank (pJ)
+system.mem_ctrl_1.refreshEnergy          33190560.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_1.actBackEnergy              77391750                       # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy               1169760                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.actPowerDownEnergy        113578770                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_1.prePowerDownEnergy           493920                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_1.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_1.totalEnergy               273562635                       # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower             646.525303                       # Core power per rank (mW)
+system.mem_ctrl_1.totalIdleTime             250424500                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_1.memoryStateTime::IDLE        900000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::REF       14040000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::PRE_PDN      1291250                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT      157762500                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT_PDN    249133250                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED    423127000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -291,8 +301,8 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    7                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON       376893000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                           376893                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON       423127000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                           423127                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5641                       # Number of instructions committed
@@ -311,7 +321,7 @@ system.cpu.num_mem_refs                          2037                       # nu
 system.cpu.num_load_insts                        1135                       # Number of load instructions
 system.cpu.num_store_insts                        902                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     376893                       # Number of busy cycles
+system.cpu.num_busy_cycles                     423127                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               886                       # Number of branches fetched
@@ -356,7 +366,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED    376893000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED    423127000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                6778                       # Transaction distribution
 system.membus.trans_dist::ReadResp               6777                       # Transaction distribution
 system.membus.trans_dist::WriteReq                901                       # Transaction distribution
@@ -380,10 +390,10 @@ system.membus.snoop_fanout::min_value               0                       # Re
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7679                       # Request fanout histogram
 system.membus.reqLayer0.occupancy             8580000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
-system.membus.respLayer0.occupancy           12853500                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3555500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
+system.membus.reqLayer0.utilization               2.0                       # Layer utilization (%)
+system.membus.respLayer0.occupancy           12855500                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization              3.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3550250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
index cf4a132b7..4bc508e65 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
@@ -23,7 +23,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:536870911
+mem_ranges=0:536870911:0:0:0:0
 memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
@@ -100,7 +100,7 @@ icache_port=system.cpu.icache.cpu_side
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -151,7 +151,7 @@ size=64
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -277,7 +277,7 @@ system=system
 [system.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -322,27 +322,27 @@ size=262144
 
 [system.mem_ctrl]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -362,6 +362,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -371,7 +372,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:536870911
+range=0:536870911:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -393,9 +394,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -404,6 +405,7 @@ port=system.membus.master[0]
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -415,7 +417,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -423,3 +425,10 @@ width=16
 master=system.mem_ctrl.port
 slave=system.l2cache.mem_side system.system_port
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout
index 760ae9b2e..26dbf1e79 100755
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:23:13
-gem5 started Jul 21 2016 14:23:48
-gem5 executing on e108600-lin, pid 13287
+gem5 compiled Oct 13 2016 20:36:34
+gem5 started Oct 13 2016 20:36:59
+gem5 executing on e108600-lin, pid 36839
 command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
 
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ Beginning simulation!
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 58892000 because target called exit()
+Exiting @ tick 62333000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
index 27ea6dc01..3bd6c6ff6 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000059                       # Number of seconds simulated
-sim_ticks                                    59115000                       # Number of ticks simulated
-final_tick                                   59115000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000062                       # Number of seconds simulated
+sim_ticks                                    62333000                       # Number of ticks simulated
+final_tick                                   62333000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 219311                       # Simulator instruction rate (inst/s)
-host_op_rate                                   219196                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2295881155                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 637060                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                 499257                       # Simulator instruction rate (inst/s)
+host_op_rate                                   498740                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5505866075                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 635976                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     59115000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
 system.mem_ctrl.bytes_read::cpu.inst            18752                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::cpu.data             8768                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::total               27520                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total          18752                       # Nu
 system.mem_ctrl.num_reads::cpu.inst               293                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_reads::cpu.data               137                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_reads::total                  430                       # Number of read requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst           317212213                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data           148321069                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total              465533283                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst      317212213                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total         317212213                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst          317212213                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data          148321069                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total             465533283                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.inst           300835833                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data           140663854                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total              441499687                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst      300835833                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total         300835833                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst          300835833                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data          140663854                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total             441499687                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrl.readReqs                          430                       # Number of read requests accepted
 system.mem_ctrl.writeReqs                           0                       # Number of write requests accepted
 system.mem_ctrl.readBursts                        430                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14                 0                       # Pe
 system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
 system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
 system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
-system.mem_ctrl.totGap                       58984000                       # Total gap between requests
+system.mem_ctrl.totGap                       62196000                       # Total gap between requests
 system.mem_ctrl.readPktSize::0                      0                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::1                      0                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::2                      0                       # Read request sizes (log2)
@@ -187,70 +187,81 @@ system.mem_ctrl.wrQLenPdf::60                       0                       # Wh
 system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples          110                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean     237.963636                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean    174.172417                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev    212.375811                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127            28     25.45%     25.45% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255           42     38.18%     63.64% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383           19     17.27%     80.91% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511            8      7.27%     88.18% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639            4      3.64%     91.82% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767            4      3.64%     95.45% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895            2      1.82%     97.27% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151            3      2.73%    100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total           110                       # Bytes accessed per row activation
-system.mem_ctrl.totQLat                       3632500                       # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat                 11695000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.bytesPerActivate::samples          113                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean     241.840708                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean    173.064480                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev    223.138673                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127            30     26.55%     26.55% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255           41     36.28%     62.83% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383           20     17.70%     80.53% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511            8      7.08%     87.61% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639            5      4.42%     92.04% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767            2      1.77%     93.81% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895            3      2.65%     96.46% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::896-1023            1      0.88%     97.35% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151            3      2.65%    100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total           113                       # Bytes accessed per row activation
+system.mem_ctrl.totQLat                       6850250                       # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat                 14912750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.mem_ctrl.totBusLat                     2150000                       # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat                       8447.67                       # Average queueing delay per DRAM burst
+system.mem_ctrl.avgQLat                      15930.81                       # Average queueing delay per DRAM burst
 system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat                 27197.67                       # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW                        465.53                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat                 34680.81                       # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW                        441.50                       # Average DRAM read bandwidth in MiByte/s
 system.mem_ctrl.avgWrBW                          0.00                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys                     465.53                       # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys                     441.50                       # Average system read bandwidth in MiByte/s
 system.mem_ctrl.avgWrBWSys                       0.00                       # Average system write bandwidth in MiByte/s
 system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil                          3.64                       # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead                      3.64                       # Data bus utilization in percentage for reads
+system.mem_ctrl.busUtil                          3.45                       # Data bus utilization in percentage
+system.mem_ctrl.busUtilRead                      3.45                       # Data bus utilization in percentage for reads
 system.mem_ctrl.busUtilWrite                     0.00                       # Data bus utilization in percentage for writes
 system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
 system.mem_ctrl.avgWrQLen                        0.00                       # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits                       315                       # Number of row buffer hits during reads
+system.mem_ctrl.readRowHits                       316                       # Number of row buffer hits during reads
 system.mem_ctrl.writeRowHits                        0                       # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate                  73.26                       # Row buffer hit rate for reads
+system.mem_ctrl.readRowHitRate                  73.49                       # Row buffer hit rate for reads
 system.mem_ctrl.writeRowHitRate                   nan                       # Row buffer hit rate for writes
-system.mem_ctrl.avgGap                      137172.09                       # Average gap between requests
-system.mem_ctrl.pageHitRate                     73.26                       # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy                    196560                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy                    107250                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy                   670800                       # Energy for read commands per rank (pJ)
+system.mem_ctrl.avgGap                      144641.86                       # Average gap between requests
+system.mem_ctrl.pageHitRate                     73.49                       # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy                    192780                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy                     98670                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy                   671160                       # Energy for read commands per rank (pJ)
 system.mem_ctrl_0.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy               3559920                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy              25637175                       # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy              10369500                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy                40541205                       # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower             740.292712                       # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE      17115500                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::REF        1820000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT       35842000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrl_1.actEnergy                    612360                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy                    334125                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy                  2425800                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.refreshEnergy          4917120.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_0.actBackEnergy               2176830                       # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy                210240                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.actPowerDownEnergy         19527630                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_0.prePowerDownEnergy          3815040                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_0.selfRefreshEnergy           1573140                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_0.totalEnergy                33182610                       # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower             532.337778                       # Core power per rank (mW)
+system.mem_ctrl_0.totalIdleTime              56494000                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_0.memoryStateTime::IDLE        323000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::REF        2086000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::SREF       4253250                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::PRE_PDN      9935000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT        2911750                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT_PDN     42824000                       # Time in different power states
+system.mem_ctrl_1.actEnergy                    621180                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy                    330165                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.readEnergy                  2399040                       # Energy for read commands per rank (pJ)
 system.mem_ctrl_1.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy               3559920                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy              37236105                       # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy                195000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy                44363310                       # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower             810.085321                       # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE        336500                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::REF        1820000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT       52811500                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     59115000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl_1.refreshEnergy          4917120.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_1.actBackEnergy               5632170                       # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy                168480                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.actPowerDownEnergy         22617030                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_1.prePowerDownEnergy            64320                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_1.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_1.totalEnergy                36749505                       # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower             587.463363                       # Core power per rank (mW)
+system.mem_ctrl_1.totalIdleTime              49768000                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_1.memoryStateTime::IDLE        176000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::REF        1843250                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::PRE_PDN       167500                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT       10545750                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT_PDN     49600500                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -270,8 +281,8 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    7                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        59115000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            59115                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        62333000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            62333                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5641                       # Number of instructions committed
@@ -290,7 +301,7 @@ system.cpu.num_mem_refs                          2037                       # nu
 system.cpu.num_load_insts                        1135                       # Number of load instructions
 system.cpu.num_store_insts                        902                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      59115                       # Number of busy cycles
+system.cpu.num_busy_cycles                      62333                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                               886                       # Number of branches fetched
@@ -329,23 +340,23 @@ system.cpu.op_class::MemWrite                     902     15.99%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5642                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     59115000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            86.123929                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            86.045434                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1899                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               137                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             13.861314                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    86.123929                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.084105                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.084105                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    86.045434                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.084029                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.084029                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          137                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.133789                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              4209                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             4209                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     59115000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data         1048                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1048                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          851                       # number of WriteReq hits
@@ -362,14 +373,14 @@ system.cpu.dcache.demand_misses::cpu.data          137                       # n
 system.cpu.dcache.demand_misses::total            137                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          137                       # number of overall misses
 system.cpu.dcache.overall_misses::total           137                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      9045000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      9045000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5476000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5476000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     14521000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     14521000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     14521000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     14521000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     10089000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     10089000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5605000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5605000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     15694000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     15694000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     15694000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     15694000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1135                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1135                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
@@ -386,14 +397,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.067289
 system.cpu.dcache.demand_miss_rate::total     0.067289                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.067289                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.067289                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103965.517241                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 103965.517241                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data       109520                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total       109520                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 105992.700730                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 105992.700730                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 105992.700730                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 105992.700730                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115965.517241                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 115965.517241                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data       112100                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total       112100                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 114554.744526                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 114554.744526                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 114554.744526                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 114554.744526                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -408,14 +419,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          137
 system.cpu.dcache.demand_mshr_misses::total          137                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          137                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8871000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      8871000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5376000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5376000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14247000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     14247000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14247000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     14247000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      9915000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      9915000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5505000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5505000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     15420000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     15420000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     15420000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     15420000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076652                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076652                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
@@ -424,31 +435,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067289
 system.cpu.dcache.demand_mshr_miss_rate::total     0.067289                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067289                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.067289                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 101965.517241                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 101965.517241                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data       107520                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total       107520                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103992.700730                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 103992.700730                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103992.700730                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 103992.700730                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     59115000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 113965.517241                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 113965.517241                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data       110100                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total       110100                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 112554.744526                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 112554.744526                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 112554.744526                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 112554.744526                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                94                       # number of replacements
-system.cpu.icache.tags.tagsinuse           109.937395                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           109.768952                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                5346                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               297                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs                    18                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   109.937395                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.429443                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.429443                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   109.768952                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.428785                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.428785                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          203                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          140                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          141                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.792969                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses             11583                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses            11583                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     59115000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst         5346                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            5346                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          5346                       # number of demand (read+write) hits
@@ -461,12 +472,12 @@ system.cpu.icache.demand_misses::cpu.inst          297                       # n
 system.cpu.icache.demand_misses::total            297                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          297                       # number of overall misses
 system.cpu.icache.overall_misses::total           297                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     30106000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     30106000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     30106000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     30106000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     30106000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     30106000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     32151000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     32151000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     32151000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     32151000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     32151000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     32151000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         5643                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         5643                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         5643                       # number of demand (read+write) accesses
@@ -479,12 +490,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.052632
 system.cpu.icache.demand_miss_rate::total     0.052632                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.052632                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.052632                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101367.003367                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 101367.003367                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 101367.003367                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 101367.003367                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 101367.003367                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 101367.003367                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108252.525253                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 108252.525253                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 108252.525253                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 108252.525253                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 108252.525253                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 108252.525253                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -497,31 +508,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          297
 system.cpu.icache.demand_mshr_misses::total          297                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          297                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          297                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     29512000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     29512000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     29512000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     29512000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     29512000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     29512000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     31557000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     31557000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     31557000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     31557000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     31557000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     31557000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.052632                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.052632                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.052632                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.052632                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.052632                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.052632                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99367.003367                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99367.003367                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99367.003367                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 99367.003367                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99367.003367                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 99367.003367                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106252.525253                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106252.525253                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106252.525253                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 106252.525253                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106252.525253                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 106252.525253                       # average overall mshr miss latency
 system.l2bus.snoop_filter.tot_requests            528                       # Total number of requests made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_requests           94                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.l2bus.snoop_filter.tot_snoops                0                       # Total number of snoops made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l2bus.pwrStateResidencyTicks::UNDEFINED     59115000                       # Cumulative time (in ticks) in various power states
+system.l2bus.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
 system.l2bus.trans_dist::ReadResp                 384                       # Transaction distribution
 system.l2bus.trans_dist::CleanEvict                94                       # Transaction distribution
 system.l2bus.trans_dist::ReadExReq                 50                       # Transaction distribution
@@ -547,30 +558,30 @@ system.l2bus.snoop_fanout::min_value                0                       # Re
 system.l2bus.snoop_fanout::max_value                0                       # Request fanout histogram
 system.l2bus.snoop_fanout::total                  434                       # Request fanout histogram
 system.l2bus.reqLayer0.occupancy               528000                       # Layer occupancy (ticks)
-system.l2bus.reqLayer0.utilization                0.9                       # Layer utilization (%)
+system.l2bus.reqLayer0.utilization                0.8                       # Layer utilization (%)
 system.l2bus.respLayer0.occupancy              891000                       # Layer occupancy (ticks)
-system.l2bus.respLayer0.utilization               1.5                       # Layer utilization (%)
+system.l2bus.respLayer0.utilization               1.4                       # Layer utilization (%)
 system.l2bus.respLayer1.occupancy              411000                       # Layer occupancy (ticks)
 system.l2bus.respLayer1.utilization               0.7                       # Layer utilization (%)
-system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     59115000                       # Cumulative time (in ticks) in various power states
+system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
 system.l2cache.tags.replacements                    0                       # number of replacements
-system.l2cache.tags.tagsinuse              216.263710                       # Cycle average of tags in use
+system.l2cache.tags.tagsinuse              215.766788                       # Cycle average of tags in use
 system.l2cache.tags.total_refs                     98                       # Total number of references to valid blocks.
 system.l2cache.tags.sampled_refs                  430                       # Sample count of references to valid blocks.
 system.l2cache.tags.avg_refs                 0.227907                       # Average number of references to valid blocks.
 system.l2cache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.l2cache.tags.occ_blocks::cpu.inst   130.091113                       # Average occupied blocks per requestor
-system.l2cache.tags.occ_blocks::cpu.data    86.172597                       # Average occupied blocks per requestor
-system.l2cache.tags.occ_percent::cpu.inst     0.031761                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::cpu.data     0.021038                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::total       0.052799                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_blocks::cpu.inst   129.675199                       # Average occupied blocks per requestor
+system.l2cache.tags.occ_blocks::cpu.data    86.091590                       # Average occupied blocks per requestor
+system.l2cache.tags.occ_percent::cpu.inst     0.031659                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::cpu.data     0.021018                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::total       0.052677                       # Average percentage of cache occupancy
 system.l2cache.tags.occ_task_id_blocks::1024          430                       # Occupied blocks per task id
-system.l2cache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.l2cache.tags.age_task_id_blocks_1024::1          354                       # Occupied blocks per task id
+system.l2cache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
+system.l2cache.tags.age_task_id_blocks_1024::1          356                       # Occupied blocks per task id
 system.l2cache.tags.occ_task_id_percent::1024     0.104980                       # Percentage of cache occupancy per task id
 system.l2cache.tags.tag_accesses                 4654                       # Number of tag accesses
 system.l2cache.tags.data_accesses                4654                       # Number of data accesses
-system.l2cache.pwrStateResidencyTicks::UNDEFINED     59115000                       # Cumulative time (in ticks) in various power states
+system.l2cache.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
 system.l2cache.ReadSharedReq_hits::cpu.inst            4                       # number of ReadSharedReq hits
 system.l2cache.ReadSharedReq_hits::total            4                       # number of ReadSharedReq hits
 system.l2cache.demand_hits::cpu.inst                4                       # number of demand (read+write) hits
@@ -588,17 +599,17 @@ system.l2cache.demand_misses::total               430                       # nu
 system.l2cache.overall_misses::cpu.inst           293                       # number of overall misses
 system.l2cache.overall_misses::cpu.data           137                       # number of overall misses
 system.l2cache.overall_misses::total              430                       # number of overall misses
-system.l2cache.ReadExReq_miss_latency::cpu.data      5226000                       # number of ReadExReq miss cycles
-system.l2cache.ReadExReq_miss_latency::total      5226000                       # number of ReadExReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.inst     28537000                       # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.data      8610000                       # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::total     37147000                       # number of ReadSharedReq miss cycles
-system.l2cache.demand_miss_latency::cpu.inst     28537000                       # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::cpu.data     13836000                       # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::total     42373000                       # number of demand (read+write) miss cycles
-system.l2cache.overall_miss_latency::cpu.inst     28537000                       # number of overall miss cycles
-system.l2cache.overall_miss_latency::cpu.data     13836000                       # number of overall miss cycles
-system.l2cache.overall_miss_latency::total     42373000                       # number of overall miss cycles
+system.l2cache.ReadExReq_miss_latency::cpu.data      5355000                       # number of ReadExReq miss cycles
+system.l2cache.ReadExReq_miss_latency::total      5355000                       # number of ReadExReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.inst     30582000                       # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.data      9654000                       # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::total     40236000                       # number of ReadSharedReq miss cycles
+system.l2cache.demand_miss_latency::cpu.inst     30582000                       # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::cpu.data     15009000                       # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::total     45591000                       # number of demand (read+write) miss cycles
+system.l2cache.overall_miss_latency::cpu.inst     30582000                       # number of overall miss cycles
+system.l2cache.overall_miss_latency::cpu.data     15009000                       # number of overall miss cycles
+system.l2cache.overall_miss_latency::total     45591000                       # number of overall miss cycles
 system.l2cache.ReadExReq_accesses::cpu.data           50                       # number of ReadExReq accesses(hits+misses)
 system.l2cache.ReadExReq_accesses::total           50                       # number of ReadExReq accesses(hits+misses)
 system.l2cache.ReadSharedReq_accesses::cpu.inst          297                       # number of ReadSharedReq accesses(hits+misses)
@@ -621,17 +632,17 @@ system.l2cache.demand_miss_rate::total       0.990783                       # mi
 system.l2cache.overall_miss_rate::cpu.inst     0.986532                       # miss rate for overall accesses
 system.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.l2cache.overall_miss_rate::total      0.990783                       # miss rate for overall accesses
-system.l2cache.ReadExReq_avg_miss_latency::cpu.data       104520                       # average ReadExReq miss latency
-system.l2cache.ReadExReq_avg_miss_latency::total       104520                       # average ReadExReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97395.904437                       # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98965.517241                       # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::total 97755.263158                       # average ReadSharedReq miss latency
-system.l2cache.demand_avg_miss_latency::cpu.inst 97395.904437                       # average overall miss latency
-system.l2cache.demand_avg_miss_latency::cpu.data 100992.700730                       # average overall miss latency
-system.l2cache.demand_avg_miss_latency::total 98541.860465                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.inst 97395.904437                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.data 100992.700730                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::total 98541.860465                       # average overall miss latency
+system.l2cache.ReadExReq_avg_miss_latency::cpu.data       107100                       # average ReadExReq miss latency
+system.l2cache.ReadExReq_avg_miss_latency::total       107100                       # average ReadExReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104375.426621                       # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110965.517241                       # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::total 105884.210526                       # average ReadSharedReq miss latency
+system.l2cache.demand_avg_miss_latency::cpu.inst 104375.426621                       # average overall miss latency
+system.l2cache.demand_avg_miss_latency::cpu.data 109554.744526                       # average overall miss latency
+system.l2cache.demand_avg_miss_latency::total 106025.581395                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.inst 104375.426621                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.data 109554.744526                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::total 106025.581395                       # average overall miss latency
 system.l2cache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.l2cache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -649,17 +660,17 @@ system.l2cache.demand_mshr_misses::total          430                       # nu
 system.l2cache.overall_mshr_misses::cpu.inst          293                       # number of overall MSHR misses
 system.l2cache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
 system.l2cache.overall_mshr_misses::total          430                       # number of overall MSHR misses
-system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4226000                       # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadExReq_mshr_miss_latency::total      4226000                       # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     22677000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6870000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::total     29547000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.inst     22677000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.data     11096000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::total     33773000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.inst     22677000                       # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.data     11096000                       # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::total     33773000                       # number of overall MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4355000                       # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::total      4355000                       # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     24722000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7914000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::total     32636000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.inst     24722000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.data     12269000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::total     36991000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.inst     24722000                       # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.data     12269000                       # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::total     36991000                       # number of overall MSHR miss cycles
 system.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst     0.986532                       # mshr miss rate for ReadSharedReq accesses
@@ -671,24 +682,24 @@ system.l2cache.demand_mshr_miss_rate::total     0.990783                       #
 system.l2cache.overall_mshr_miss_rate::cpu.inst     0.986532                       # mshr miss rate for overall accesses
 system.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.l2cache.overall_mshr_miss_rate::total     0.990783                       # mshr miss rate for overall accesses
-system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        84520                       # average ReadExReq mshr miss latency
-system.l2cache.ReadExReq_avg_mshr_miss_latency::total        84520                       # average ReadExReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77395.904437                       # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78965.517241                       # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77755.263158                       # average ReadSharedReq mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.904437                       # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80992.700730                       # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::total 78541.860465                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.904437                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80992.700730                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::total 78541.860465                       # average overall mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        87100                       # average ReadExReq mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::total        87100                       # average ReadExReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84375.426621                       # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90965.517241                       # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85884.210526                       # average ReadSharedReq mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84375.426621                       # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.data 89554.744526                       # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::total 86025.581395                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84375.426621                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.data 89554.744526                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::total 86025.581395                       # average overall mshr miss latency
 system.membus.snoop_filter.tot_requests           430                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     59115000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                380                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
@@ -711,7 +722,7 @@ system.membus.snoop_fanout::max_value               0                       # Re
 system.membus.snoop_fanout::total                 430                       # Request fanout histogram
 system.membus.reqLayer0.occupancy              430000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            2298000                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.9                       # Layer utilization (%)
+system.membus.respLayer0.occupancy            2298250                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization              3.7                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini
index a434b8376..d1ab85628 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini
@@ -23,7 +23,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:536870911
+mem_ranges=0:536870911:0:0:0:0
 memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
@@ -152,27 +152,27 @@ transition_latency=100000000
 
 [system.mem_ctrl]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -192,6 +192,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -201,7 +202,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:536870911
+range=0:536870911:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -223,9 +224,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -234,6 +235,7 @@ port=system.membus.master[0]
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -245,7 +247,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -253,3 +255,10 @@ width=16
 master=system.mem_ctrl.port
 slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout
index 9b1207098..4568a6760 100755
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linu
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:30:06
-gem5 started Jul 21 2016 14:30:37
-gem5 executing on e108600-lin, pid 38687
+gem5 compiled Oct 13 2016 20:43:27
+gem5 started Oct 13 2016 20:47:16
+gem5 executing on e108600-lin, pid 17418
 command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
 info: Entering event queue @ 0.  Starting simulation...
-Hello World!Exiting @ tick 333033000 because target called exit()
+Hello World!Exiting @ tick 380341000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt
index 9a120d100..ba7428ffa 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000340                       # Number of seconds simulated
-sim_ticks                                   340278000                       # Number of ticks simulated
-final_tick                                  340278000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000380                       # Number of seconds simulated
+sim_ticks                                   380341000                       # Number of ticks simulated
+final_tick                                  380341000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 140763                       # Simulator instruction rate (inst/s)
-host_op_rate                                   140716                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8627820590                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 633396                       # Number of bytes of host memory used
+host_inst_rate                                 148243                       # Simulator instruction rate (inst/s)
+host_op_rate                                   148143                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            10150108269                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 632328                       # Number of bytes of host memory used
 host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        5548                       # Number of instructions simulated
 sim_ops                                          5548                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED    340278000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED    380341000                       # Cumulative time (in ticks) in various power states
 system.mem_ctrl.bytes_read::cpu.inst            22364                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::cpu.data             4640                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::total               27004                       # Number of bytes read from this memory
@@ -26,26 +26,26 @@ system.mem_ctrl.num_reads::cpu.data               718                       # Nu
 system.mem_ctrl.num_reads::total                 6309                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_writes::cpu.data              673                       # Number of write requests responded to by this memory
 system.mem_ctrl.num_writes::total                 673                       # Number of write requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst            65722733                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data            13635909                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total               79358642                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst       65722733                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total          65722733                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::cpu.data           14884888                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::total              14884888                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst           65722733                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data           28520798                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total              94243530                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.inst            58799866                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data            12199579                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total               70999445                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst       58799866                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total          58799866                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::cpu.data           13316997                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::total              13316997                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst           58799866                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data           25516576                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total              84316442                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrl.readReqs                         6310                       # Number of read requests accepted
 system.mem_ctrl.writeReqs                         673                       # Number of write requests accepted
 system.mem_ctrl.readBursts                       6310                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrl.writeBursts                       673                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrl.bytesReadDRAM                  397824                       # Total number of bytes read from DRAM
-system.mem_ctrl.bytesReadWrQ                     6016                       # Total number of bytes read from write queue
+system.mem_ctrl.bytesReadDRAM                  397760                       # Total number of bytes read from DRAM
+system.mem_ctrl.bytesReadWrQ                     6080                       # Total number of bytes read from write queue
 system.mem_ctrl.bytesWritten                     6144                       # Total number of bytes written to DRAM
 system.mem_ctrl.bytesReadSys                    27008                       # Total read bytes from the system interface side
 system.mem_ctrl.bytesWrittenSys                  5065                       # Total written bytes from the system interface side
-system.mem_ctrl.servicedByWrQ                      94                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrl.servicedByWrQ                      95                       # Number of DRAM read bursts serviced by the write queue
 system.mem_ctrl.mergedWrBursts                    548                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrl.neitherReadNorWriteReqs             0                       # Number of requests that are neither read nor write
 system.mem_ctrl.perBankRdBursts::0                220                       # Per bank write bursts
@@ -53,7 +53,7 @@ system.mem_ctrl.perBankRdBursts::1                 84                       # Pe
 system.mem_ctrl.perBankRdBursts::2                  2                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::3                199                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::4                  0                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::5               1005                       # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::5               1004                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::6               1555                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::7                875                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::8                710                       # Per bank write bursts
@@ -69,7 +69,7 @@ system.mem_ctrl.perBankWrBursts::1                  0                       # Pe
 system.mem_ctrl.perBankWrBursts::2                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::3                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::4                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::5                 17                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::5                 16                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::6                 42                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::7                 19                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::8                  0                       # Per bank write bursts
@@ -77,12 +77,12 @@ system.mem_ctrl.perBankWrBursts::9                  5                       # Pe
 system.mem_ctrl.perBankWrBursts::10                 0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::11                 0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::12                 4                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::13                 9                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::13                10                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::14                 0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
 system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
 system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
-system.mem_ctrl.totGap                      340201000                       # Total gap between requests
+system.mem_ctrl.totGap                      380264000                       # Total gap between requests
 system.mem_ctrl.readPktSize::0                     88                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::1                      2                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::2                   5711                       # Read request sizes (log2)
@@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3                   604                       # Wr
 system.mem_ctrl.writePktSize::4                     0                       # Write request sizes (log2)
 system.mem_ctrl.writePktSize::5                     0                       # Write request sizes (log2)
 system.mem_ctrl.writePktSize::6                     0                       # Write request sizes (log2)
-system.mem_ctrl.rdQLenPdf::0                     6216                       # What read queue length does an incoming req see
+system.mem_ctrl.rdQLenPdf::0                     6215                       # What read queue length does an incoming req see
 system.mem_ctrl.rdQLenPdf::1                        0                       # What read queue length does an incoming req see
 system.mem_ctrl.rdQLenPdf::2                        0                       # What read queue length does an incoming req see
 system.mem_ctrl.rdQLenPdf::3                        0                       # What read queue length does an incoming req see
@@ -193,24 +193,24 @@ system.mem_ctrl.wrQLenPdf::60                       0                       # Wh
 system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples          569                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean     706.474517                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean    522.857650                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev    386.052257                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127            51      8.96%      8.96% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255           75     13.18%     22.14% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383           39      6.85%     29.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511           23      4.04%     33.04% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639           22      3.87%     36.91% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767           18      3.16%     40.07% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895           19      3.34%     43.41% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-1023           24      4.22%     47.63% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151          298     52.37%    100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total           569                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::samples          575                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean     700.438261                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean    528.229400                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev    375.888489                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127            45      7.83%      7.83% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255           73     12.70%     20.52% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383           37      6.43%     26.96% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511           35      6.09%     33.04% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639           26      4.52%     37.57% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767           27      4.70%     42.26% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895           26      4.52%     46.78% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::896-1023           27      4.70%     51.48% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151          279     48.52%    100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total           575                       # Bytes accessed per row activation
 system.mem_ctrl.rdPerTurnAround::samples            6                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::mean      772.333333                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::gmean     643.216539                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::stdev     524.537383                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::mean      772.166667                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::gmean     643.154197                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::stdev     524.176084                       # Reads before turning the bus around for writes
 system.mem_ctrl.rdPerTurnAround::256-319            2     33.33%     33.33% # Reads before turning the bus around for writes
 system.mem_ctrl.rdPerTurnAround::640-703            1     16.67%     50.00% # Reads before turning the bus around for writes
 system.mem_ctrl.rdPerTurnAround::704-767            1     16.67%     66.67% # Reads before turning the bus around for writes
@@ -222,60 +222,70 @@ system.mem_ctrl.wrPerTurnAround::mean              16                       # Wr
 system.mem_ctrl.wrPerTurnAround::gmean      16.000000                       # Writes before turning the bus around for reads
 system.mem_ctrl.wrPerTurnAround::16                 6    100.00%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrl.wrPerTurnAround::total              6                       # Writes before turning the bus around for reads
-system.mem_ctrl.totQLat                      19583750                       # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat                136133750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrl.totBusLat                    31080000                       # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat                       3150.54                       # Average queueing delay per DRAM burst
+system.mem_ctrl.totQLat                      59680000                       # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat                176211250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totBusLat                    31075000                       # Total ticks spent in databus transfers
+system.mem_ctrl.avgQLat                       9602.57                       # Average queueing delay per DRAM burst
 system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat                 21900.54                       # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW                       1169.11                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW                         18.06                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys                      79.37                       # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys                      14.88                       # Average system write bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat                 28352.57                       # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW                       1045.80                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBW                         16.15                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys                      71.01                       # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBWSys                      13.32                       # Average system write bandwidth in MiByte/s
 system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil                          9.27                       # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead                      9.13                       # Data bus utilization in percentage for reads
-system.mem_ctrl.busUtilWrite                     0.14                       # Data bus utilization in percentage for writes
+system.mem_ctrl.busUtil                          8.30                       # Data bus utilization in percentage
+system.mem_ctrl.busUtilRead                      8.17                       # Data bus utilization in percentage for reads
+system.mem_ctrl.busUtilWrite                     0.13                       # Data bus utilization in percentage for writes
 system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
-system.mem_ctrl.avgWrQLen                       23.19                       # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits                      5657                       # Number of row buffer hits during reads
-system.mem_ctrl.writeRowHits                       82                       # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate                  91.01                       # Row buffer hit rate for reads
-system.mem_ctrl.writeRowHitRate                 65.60                       # Row buffer hit rate for writes
-system.mem_ctrl.avgGap                       48718.46                       # Average gap between requests
-system.mem_ctrl.pageHitRate                     90.51                       # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy                   2653560                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy                   1447875                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy                 30108000                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_0.writeEnergy                  505440                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy              21868080                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy             217242675                       # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy              10477500                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy               284303130                       # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower             848.491929                       # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE      15805250                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::REF       11180000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT      311151750                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrl_1.actEnergy                   1617840                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy                    882750                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy                 17635800                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_1.writeEnergy                  116640                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy              21868080                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy             174520890                       # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy              47944500                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy               264586500                       # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower             789.680799                       # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE      79696000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::REF       11180000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT      245540000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED    340278000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.avgWrQLen                       23.12                       # Average write queue length when enqueuing
+system.mem_ctrl.readRowHits                      5650                       # Number of row buffer hits during reads
+system.mem_ctrl.writeRowHits                       83                       # Number of row buffer hits during writes
+system.mem_ctrl.readRowHitRate                  90.91                       # Row buffer hit rate for reads
+system.mem_ctrl.writeRowHitRate                 66.40                       # Row buffer hit rate for writes
+system.mem_ctrl.avgGap                       54455.68                       # Average gap between requests
+system.mem_ctrl.pageHitRate                     90.43                       # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy                   2598960                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy                   1377585                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy                 28124460                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.writeEnergy                  401940                       # Energy for write commands per rank (pJ)
+system.mem_ctrl_0.refreshEnergy          29502720.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_0.actBackEnergy              55884510                       # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy                903360                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.actPowerDownEnergy        108619200                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_0.prePowerDownEnergy          6618240                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_0.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_0.totalEnergy               234030975                       # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower             615.318415                       # Core power per rank (mW)
+system.mem_ctrl_0.totalIdleTime             255286000                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_0.memoryStateTime::IDLE        462000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::REF       12480000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::PRE_PDN     17232500                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT      111848750                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT_PDN    238317750                       # Time in different power states
+system.mem_ctrl_1.actEnergy                   1527960                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy                    804540                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.readEnergy                 16243500                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_1.writeEnergy                   99180                       # Energy for write commands per rank (pJ)
+system.mem_ctrl_1.refreshEnergy          28273440.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_1.actBackEnergy              35538930                       # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy               1997760                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.actPowerDownEnergy         96272430                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_1.prePowerDownEnergy         16892160                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_1.selfRefreshEnergy          11758020                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_1.totalEnergy               209407920                       # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower             550.579039                       # Core power per rank (mW)
+system.mem_ctrl_1.totalIdleTime             297220000                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_1.memoryStateTime::IDLE       3473000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::REF       11978000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::SREF      42087750                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::PRE_PDN     43986250                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT       67670000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT_PDN    211146000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED    380341000                       # Cumulative time (in ticks) in various power states
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON       340278000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                           340278                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON       380341000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                           380341                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5548                       # Number of instructions committed
@@ -294,7 +304,7 @@ system.cpu.num_mem_refs                          1404                       # nu
 system.cpu.num_load_insts                         726                       # Number of load instructions
 system.cpu.num_store_insts                        678                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.001000                       # Number of idle cycles
-system.cpu.num_busy_cycles               340277.999000                       # Number of busy cycles
+system.cpu.num_busy_cycles               380340.999000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1187                       # Number of branches fetched
@@ -339,7 +349,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED    340278000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED    380341000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                6310                       # Transaction distribution
 system.membus.trans_dist::ReadResp               6309                       # Transaction distribution
 system.membus.trans_dist::WriteReq                673                       # Transaction distribution
@@ -363,10 +373,10 @@ system.membus.snoop_fanout::min_value               0                       # Re
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                6983                       # Request fanout histogram
 system.membus.reqLayer0.occupancy             7656000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer0.occupancy           12692500                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2298500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.membus.reqLayer0.utilization               2.0                       # Layer utilization (%)
+system.membus.respLayer0.occupancy           12691750                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization              3.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2300750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini
index 24d190659..d90641228 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini
@@ -23,7 +23,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:536870911
+mem_ranges=0:536870911:0:0:0:0
 memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
@@ -100,7 +100,7 @@ icache_port=system.cpu.icache.cpu_side
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -151,7 +151,7 @@ size=64
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -274,7 +274,7 @@ system=system
 [system.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -319,27 +319,27 @@ size=262144
 
 [system.mem_ctrl]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -359,6 +359,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -368,7 +369,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:536870911
+range=0:536870911:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -390,9 +391,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -401,6 +402,7 @@ port=system.membus.master[0]
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -412,7 +414,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -420,3 +422,10 @@ width=16
 master=system.mem_ctrl.port
 slave=system.l2cache.mem_side system.system_port
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout
index 362a2e4dd..95530f5be 100755
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linu
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:30:06
-gem5 started Jul 21 2016 14:30:36
-gem5 executing on e108600-lin, pid 38678
+gem5 compiled Oct 13 2016 20:43:27
+gem5 started Oct 13 2016 20:45:43
+gem5 executing on e108600-lin, pid 17392
 command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
 info: Entering event queue @ 0.  Starting simulation...
-Hello World!Exiting @ tick 53334000 because target called exit()
+Hello World!Exiting @ tick 56511000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
index 563f4d9b3..898894976 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000054                       # Number of seconds simulated
-sim_ticks                                    53605000                       # Number of ticks simulated
-final_tick                                   53605000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000057                       # Number of seconds simulated
+sim_ticks                                    56511000                       # Number of ticks simulated
+final_tick                                   56511000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 205629                       # Simulator instruction rate (inst/s)
-host_op_rate                                   205519                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1984690430                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 637752                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                 292382                       # Simulator instruction rate (inst/s)
+host_op_rate                                   292023                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2971184542                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 636424                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5548                       # Number of instructions simulated
 sim_ops                                          5548                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     53605000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     56511000                       # Cumulative time (in ticks) in various power states
 system.mem_ctrl.bytes_read::cpu.inst            16448                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::cpu.data             8768                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::total               25216                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total          16448                       # Nu
 system.mem_ctrl.num_reads::cpu.inst               257                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_reads::cpu.data               137                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_reads::total                  394                       # Number of read requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst           306837049                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data           163566831                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total              470403880                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst      306837049                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total         306837049                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst          306837049                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data          163566831                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total             470403880                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.inst           291058378                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data           155155633                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total              446214011                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst      291058378                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total         291058378                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst          291058378                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data          155155633                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total             446214011                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrl.readReqs                          394                       # Number of read requests accepted
 system.mem_ctrl.writeReqs                           0                       # Number of write requests accepted
 system.mem_ctrl.readBursts                        394                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14                 0                       # Pe
 system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
 system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
 system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
-system.mem_ctrl.totGap                       53508000                       # Total gap between requests
+system.mem_ctrl.totGap                       56394000                       # Total gap between requests
 system.mem_ctrl.readPktSize::0                      0                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::1                      0                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::2                      0                       # Read request sizes (log2)
@@ -187,77 +187,83 @@ system.mem_ctrl.wrQLenPdf::60                       0                       # Wh
 system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples           92                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean     246.260870                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean    176.635417                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev    203.037423                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::64-127           28     30.43%     30.43% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-191           15     16.30%     46.74% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::192-255           11     11.96%     58.70% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-319            8      8.70%     67.39% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::320-383            6      6.52%     73.91% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-447            7      7.61%     81.52% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::448-511            3      3.26%     84.78% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-575            3      3.26%     88.04% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::576-639            6      6.52%     94.57% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-703            2      2.17%     96.74% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-831            1      1.09%     97.83% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-959            2      2.17%    100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total            92                       # Bytes accessed per row activation
-system.mem_ctrl.totQLat                       2887500                       # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat                 10275000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.bytesPerActivate::samples           98                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean     248.816327                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean    183.748429                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev    196.431638                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127            26     26.53%     26.53% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255           31     31.63%     58.16% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383           15     15.31%     73.47% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511           13     13.27%     86.73% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639            9      9.18%     95.92% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767            2      2.04%     97.96% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::896-1023            1      1.02%     98.98% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151            1      1.02%    100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total            98                       # Bytes accessed per row activation
+system.mem_ctrl.totQLat                       5793000                       # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat                 13180500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.mem_ctrl.totBusLat                     1970000                       # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat                       7328.68                       # Average queueing delay per DRAM burst
+system.mem_ctrl.avgQLat                      14703.05                       # Average queueing delay per DRAM burst
 system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat                 26078.68                       # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW                        470.40                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat                 33453.05                       # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW                        446.21                       # Average DRAM read bandwidth in MiByte/s
 system.mem_ctrl.avgWrBW                          0.00                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys                     470.40                       # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys                     446.21                       # Average system read bandwidth in MiByte/s
 system.mem_ctrl.avgWrBWSys                       0.00                       # Average system write bandwidth in MiByte/s
 system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil                          3.68                       # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead                      3.68                       # Data bus utilization in percentage for reads
+system.mem_ctrl.busUtil                          3.49                       # Data bus utilization in percentage
+system.mem_ctrl.busUtilRead                      3.49                       # Data bus utilization in percentage for reads
 system.mem_ctrl.busUtilWrite                     0.00                       # Data bus utilization in percentage for writes
 system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
 system.mem_ctrl.avgWrQLen                        0.00                       # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits                       296                       # Number of row buffer hits during reads
+system.mem_ctrl.readRowHits                       292                       # Number of row buffer hits during reads
 system.mem_ctrl.writeRowHits                        0                       # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate                  75.13                       # Row buffer hit rate for reads
+system.mem_ctrl.readRowHitRate                  74.11                       # Row buffer hit rate for reads
 system.mem_ctrl.writeRowHitRate                   nan                       # Row buffer hit rate for writes
-system.mem_ctrl.avgGap                      135807.11                       # Average gap between requests
-system.mem_ctrl.pageHitRate                     75.13                       # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy                    378000                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy                    206250                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy                  1614600                       # Energy for read commands per rank (pJ)
+system.mem_ctrl.avgGap                      143131.98                       # Average gap between requests
+system.mem_ctrl.pageHitRate                     74.11                       # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy                    421260                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy                    216315                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy                  1756440                       # Energy for read commands per rank (pJ)
 system.mem_ctrl_0.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy               3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy              30461940                       # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy               1478250                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy                37190400                       # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower             791.306152                       # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE       2310750                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::REF        1560000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT       43141000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrl_1.actEnergy                    272160                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy                    148500                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy                  1053000                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.refreshEnergy          4302480.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_0.actBackEnergy               4075500                       # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy                122880                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.actPowerDownEnergy         21123630                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_0.prePowerDownEnergy           357120                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_0.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_0.totalEnergy                32375625                       # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower             572.905837                       # Core power per rank (mW)
+system.mem_ctrl_0.totalIdleTime              47002000                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_0.memoryStateTime::IDLE         71000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::REF        1820000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::PRE_PDN       929250                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT        7357750                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT_PDN     46333000                       # Time in different power states
+system.mem_ctrl_1.actEnergy                    307020                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy                    155595                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.readEnergy                  1056720                       # Energy for read commands per rank (pJ)
 system.mem_ctrl_1.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy               3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy              29252115                       # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy               2526750                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy                36303885                       # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower             772.793039                       # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE       5312750                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::REF        1560000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT       41373250                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     53605000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl_1.refreshEnergy          4302480.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_1.actBackEnergy               2785590                       # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy                293760                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.actPowerDownEnergy         20523420                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_1.prePowerDownEnergy          1777920                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_1.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_1.totalEnergy                31202505                       # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower             552.146785                       # Core power per rank (mW)
+system.mem_ctrl_1.totalIdleTime              49582750                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_1.memoryStateTime::IDLE        557000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::REF        1820000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::PRE_PDN      4629500                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT        4495750                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT_PDN     45008750                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     56511000                       # Cumulative time (in ticks) in various power states
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        53605000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            53605                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        56511000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            56511                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5548                       # Number of instructions committed
@@ -276,7 +282,7 @@ system.cpu.num_mem_refs                          1404                       # nu
 system.cpu.num_load_insts                         726                       # Number of load instructions
 system.cpu.num_store_insts                        678                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.001000                       # Number of idle cycles
-system.cpu.num_busy_cycles               53604.999000                       # Number of busy cycles
+system.cpu.num_busy_cycles               56510.999000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1187                       # Number of branches fetched
@@ -315,23 +321,23 @@ system.cpu.op_class::MemWrite                     678     12.13%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5591                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     53605000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     56511000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            83.787726                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            83.847801                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1253                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              9.079710                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    83.787726                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.081824                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.081824                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    83.847801                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.081883                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.081883                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          128                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.134766                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              2920                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             2920                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     53605000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     56511000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data          662                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             662                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          591                       # number of WriteReq hits
@@ -348,14 +354,14 @@ system.cpu.dcache.demand_misses::cpu.data          138                       # n
 system.cpu.dcache.demand_misses::total            138                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.dcache.overall_misses::total           138                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      5756000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      5756000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      8522000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      8522000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     14278000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     14278000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     14278000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     14278000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      6576000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6576000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      8937000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      8937000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     15513000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     15513000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     15513000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     15513000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data          718                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total          718                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          673                       # number of WriteReq accesses(hits+misses)
@@ -372,14 +378,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.099209
 system.cpu.dcache.demand_miss_rate::total     0.099209                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.099209                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.099209                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102785.714286                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 102785.714286                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103926.829268                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 103926.829268                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 103463.768116                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 103463.768116                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 103463.768116                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 103463.768116                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 117428.571429                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 117428.571429                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108987.804878                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 108987.804878                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 112413.043478                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 112413.043478                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 112413.043478                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 112413.043478                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -394,14 +400,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          138
 system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5644000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5644000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      8358000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      8358000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14002000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     14002000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14002000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     14002000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6464000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6464000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      8773000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      8773000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     15237000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     15237000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     15237000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     15237000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.077994                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.077994                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.121842                       # mshr miss rate for WriteReq accesses
@@ -410,31 +416,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.099209
 system.cpu.dcache.demand_mshr_miss_rate::total     0.099209                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.099209                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.099209                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100785.714286                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100785.714286                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101926.829268                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101926.829268                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101463.768116                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 101463.768116                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101463.768116                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 101463.768116                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     53605000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115428.571429                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115428.571429                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106987.804878                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106987.804878                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 110413.043478                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 110413.043478                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 110413.043478                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 110413.043478                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     56511000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                71                       # number of replacements
-system.cpu.icache.tags.tagsinuse            98.163046                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse            98.324434                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                5333                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               259                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             20.590734                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    98.163046                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.383449                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.383449                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst    98.324434                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.384080                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.384080                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          188                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          129                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          134                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.734375                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses             11443                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses            11443                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     53605000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     56511000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst         5333                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            5333                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          5333                       # number of demand (read+write) hits
@@ -447,12 +453,12 @@ system.cpu.icache.demand_misses::cpu.inst          259                       # n
 system.cpu.icache.demand_misses::total            259                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          259                       # number of overall misses
 system.cpu.icache.overall_misses::total           259                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     26157000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     26157000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     26157000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     26157000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     26157000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     26157000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     27828000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     27828000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     27828000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     27828000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     27828000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     27828000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         5592                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         5592                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         5592                       # number of demand (read+write) accesses
@@ -465,12 +471,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.046316
 system.cpu.icache.demand_miss_rate::total     0.046316                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.046316                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.046316                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100992.277992                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 100992.277992                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 100992.277992                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 100992.277992                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 100992.277992                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 100992.277992                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 107444.015444                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 107444.015444                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 107444.015444                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 107444.015444                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 107444.015444                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 107444.015444                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -483,31 +489,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          259
 system.cpu.icache.demand_mshr_misses::total          259                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          259                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          259                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25639000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     25639000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     25639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25639000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     25639000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     27310000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     27310000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     27310000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     27310000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27310000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     27310000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.046316                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.046316                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.046316                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.046316                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.046316                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.046316                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98992.277992                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98992.277992                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98992.277992                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 98992.277992                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98992.277992                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 98992.277992                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 105444.015444                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 105444.015444                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 105444.015444                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 105444.015444                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 105444.015444                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 105444.015444                       # average overall mshr miss latency
 system.l2bus.snoop_filter.tot_requests            468                       # Total number of requests made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_requests           73                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.l2bus.snoop_filter.tot_snoops                0                       # Total number of snoops made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l2bus.pwrStateResidencyTicks::UNDEFINED     53605000                       # Cumulative time (in ticks) in various power states
+system.l2bus.pwrStateResidencyTicks::UNDEFINED     56511000                       # Cumulative time (in ticks) in various power states
 system.l2bus.trans_dist::ReadResp                 315                       # Transaction distribution
 system.l2bus.trans_dist::CleanEvict                71                       # Transaction distribution
 system.l2bus.trans_dist::ReadExReq                 82                       # Transaction distribution
@@ -533,30 +539,30 @@ system.l2bus.snoop_fanout::min_value                0                       # Re
 system.l2bus.snoop_fanout::max_value                1                       # Request fanout histogram
 system.l2bus.snoop_fanout::total                  397                       # Request fanout histogram
 system.l2bus.reqLayer0.occupancy               468000                       # Layer occupancy (ticks)
-system.l2bus.reqLayer0.utilization                0.9                       # Layer utilization (%)
+system.l2bus.reqLayer0.utilization                0.8                       # Layer utilization (%)
 system.l2bus.respLayer0.occupancy              777000                       # Layer occupancy (ticks)
 system.l2bus.respLayer0.utilization               1.4                       # Layer utilization (%)
 system.l2bus.respLayer1.occupancy              414000                       # Layer occupancy (ticks)
-system.l2bus.respLayer1.utilization               0.8                       # Layer utilization (%)
-system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     53605000                       # Cumulative time (in ticks) in various power states
+system.l2bus.respLayer1.utilization               0.7                       # Layer utilization (%)
+system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     56511000                       # Cumulative time (in ticks) in various power states
 system.l2cache.tags.replacements                    0                       # number of replacements
-system.l2cache.tags.tagsinuse              200.697345                       # Cycle average of tags in use
+system.l2cache.tags.tagsinuse              201.052259                       # Cycle average of tags in use
 system.l2cache.tags.total_refs                     73                       # Total number of references to valid blocks.
 system.l2cache.tags.sampled_refs                  394                       # Sample count of references to valid blocks.
 system.l2cache.tags.avg_refs                 0.185279                       # Average number of references to valid blocks.
 system.l2cache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.l2cache.tags.occ_blocks::cpu.inst   117.835895                       # Average occupied blocks per requestor
-system.l2cache.tags.occ_blocks::cpu.data    82.861451                       # Average occupied blocks per requestor
-system.l2cache.tags.occ_percent::cpu.inst     0.028769                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::cpu.data     0.020230                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::total       0.048998                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_blocks::cpu.inst   118.133782                       # Average occupied blocks per requestor
+system.l2cache.tags.occ_blocks::cpu.data    82.918477                       # Average occupied blocks per requestor
+system.l2cache.tags.occ_percent::cpu.inst     0.028841                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::cpu.data     0.020244                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::total       0.049085                       # Average percentage of cache occupancy
 system.l2cache.tags.occ_task_id_blocks::1024          394                       # Occupied blocks per task id
-system.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.l2cache.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
+system.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.l2cache.tags.age_task_id_blocks_1024::1          332                       # Occupied blocks per task id
 system.l2cache.tags.occ_task_id_percent::1024     0.096191                       # Percentage of cache occupancy per task id
 system.l2cache.tags.tag_accesses                 4130                       # Number of tag accesses
 system.l2cache.tags.data_accesses                4130                       # Number of data accesses
-system.l2cache.pwrStateResidencyTicks::UNDEFINED     53605000                       # Cumulative time (in ticks) in various power states
+system.l2cache.pwrStateResidencyTicks::UNDEFINED     56511000                       # Cumulative time (in ticks) in various power states
 system.l2cache.ReadSharedReq_hits::cpu.inst            2                       # number of ReadSharedReq hits
 system.l2cache.ReadSharedReq_hits::cpu.data            1                       # number of ReadSharedReq hits
 system.l2cache.ReadSharedReq_hits::total            3                       # number of ReadSharedReq hits
@@ -577,17 +583,17 @@ system.l2cache.demand_misses::total               394                       # nu
 system.l2cache.overall_misses::cpu.inst           257                       # number of overall misses
 system.l2cache.overall_misses::cpu.data           137                       # number of overall misses
 system.l2cache.overall_misses::total              394                       # number of overall misses
-system.l2cache.ReadExReq_miss_latency::cpu.data      8112000                       # number of ReadExReq miss cycles
-system.l2cache.ReadExReq_miss_latency::total      8112000                       # number of ReadExReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.inst     24816000                       # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.data      5453000                       # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::total     30269000                       # number of ReadSharedReq miss cycles
-system.l2cache.demand_miss_latency::cpu.inst     24816000                       # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::cpu.data     13565000                       # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::total     38381000                       # number of demand (read+write) miss cycles
-system.l2cache.overall_miss_latency::cpu.inst     24816000                       # number of overall miss cycles
-system.l2cache.overall_miss_latency::cpu.data     13565000                       # number of overall miss cycles
-system.l2cache.overall_miss_latency::total     38381000                       # number of overall miss cycles
+system.l2cache.ReadExReq_miss_latency::cpu.data      8527000                       # number of ReadExReq miss cycles
+system.l2cache.ReadExReq_miss_latency::total      8527000                       # number of ReadExReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.inst     26487000                       # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.data      6273000                       # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::total     32760000                       # number of ReadSharedReq miss cycles
+system.l2cache.demand_miss_latency::cpu.inst     26487000                       # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::cpu.data     14800000                       # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::total     41287000                       # number of demand (read+write) miss cycles
+system.l2cache.overall_miss_latency::cpu.inst     26487000                       # number of overall miss cycles
+system.l2cache.overall_miss_latency::cpu.data     14800000                       # number of overall miss cycles
+system.l2cache.overall_miss_latency::total     41287000                       # number of overall miss cycles
 system.l2cache.ReadExReq_accesses::cpu.data           82                       # number of ReadExReq accesses(hits+misses)
 system.l2cache.ReadExReq_accesses::total           82                       # number of ReadExReq accesses(hits+misses)
 system.l2cache.ReadSharedReq_accesses::cpu.inst          259                       # number of ReadSharedReq accesses(hits+misses)
@@ -610,17 +616,17 @@ system.l2cache.demand_miss_rate::total       0.992443                       # mi
 system.l2cache.overall_miss_rate::cpu.inst     0.992278                       # miss rate for overall accesses
 system.l2cache.overall_miss_rate::cpu.data     0.992754                       # miss rate for overall accesses
 system.l2cache.overall_miss_rate::total      0.992443                       # miss rate for overall accesses
-system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98926.829268                       # average ReadExReq miss latency
-system.l2cache.ReadExReq_avg_miss_latency::total 98926.829268                       # average ReadExReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96560.311284                       # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99145.454545                       # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::total 97016.025641                       # average ReadSharedReq miss latency
-system.l2cache.demand_avg_miss_latency::cpu.inst 96560.311284                       # average overall miss latency
-system.l2cache.demand_avg_miss_latency::cpu.data 99014.598540                       # average overall miss latency
-system.l2cache.demand_avg_miss_latency::total 97413.705584                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.inst 96560.311284                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.data 99014.598540                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::total 97413.705584                       # average overall miss latency
+system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103987.804878                       # average ReadExReq miss latency
+system.l2cache.ReadExReq_avg_miss_latency::total 103987.804878                       # average ReadExReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 103062.256809                       # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 114054.545455                       # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::total       105000                       # average ReadSharedReq miss latency
+system.l2cache.demand_avg_miss_latency::cpu.inst 103062.256809                       # average overall miss latency
+system.l2cache.demand_avg_miss_latency::cpu.data 108029.197080                       # average overall miss latency
+system.l2cache.demand_avg_miss_latency::total 104789.340102                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.inst 103062.256809                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.data 108029.197080                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::total 104789.340102                       # average overall miss latency
 system.l2cache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.l2cache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -638,17 +644,17 @@ system.l2cache.demand_mshr_misses::total          394                       # nu
 system.l2cache.overall_mshr_misses::cpu.inst          257                       # number of overall MSHR misses
 system.l2cache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
 system.l2cache.overall_mshr_misses::total          394                       # number of overall MSHR misses
-system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      6472000                       # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadExReq_mshr_miss_latency::total      6472000                       # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     19676000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4353000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::total     24029000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.inst     19676000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.data     10825000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::total     30501000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.inst     19676000                       # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.data     10825000                       # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::total     30501000                       # number of overall MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      6887000                       # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::total      6887000                       # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     21347000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5173000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::total     26520000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.inst     21347000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.data     12060000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::total     33407000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.inst     21347000                       # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.data     12060000                       # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::total     33407000                       # number of overall MSHR miss cycles
 system.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst     0.992278                       # mshr miss rate for ReadSharedReq accesses
@@ -660,24 +666,24 @@ system.l2cache.demand_mshr_miss_rate::total     0.992443                       #
 system.l2cache.overall_mshr_miss_rate::cpu.inst     0.992278                       # mshr miss rate for overall accesses
 system.l2cache.overall_mshr_miss_rate::cpu.data     0.992754                       # mshr miss rate for overall accesses
 system.l2cache.overall_mshr_miss_rate::total     0.992443                       # mshr miss rate for overall accesses
-system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.829268                       # average ReadExReq mshr miss latency
-system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.829268                       # average ReadExReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76560.311284                       # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79145.454545                       # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77016.025641                       # average ReadSharedReq mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76560.311284                       # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79014.598540                       # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::total 77413.705584                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76560.311284                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79014.598540                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::total 77413.705584                       # average overall mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83987.804878                       # average ReadExReq mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83987.804878                       # average ReadExReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 83062.256809                       # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 94054.545455                       # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        85000                       # average ReadSharedReq mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83062.256809                       # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.data 88029.197080                       # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::total 84789.340102                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83062.256809                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.data 88029.197080                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::total 84789.340102                       # average overall mshr miss latency
 system.membus.snoop_filter.tot_requests           394                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     53605000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     56511000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                312                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                82                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               82                       # Transaction distribution
@@ -700,7 +706,7 @@ system.membus.snoop_fanout::max_value               0                       # Re
 system.membus.snoop_fanout::total                 394                       # Request fanout histogram
 system.membus.reqLayer0.occupancy              394000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            2102000                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.9                       # Layer utilization (%)
+system.membus.respLayer0.occupancy            2102500                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization              3.7                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini
index f9a7ceaa3..612b72e20 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini
@@ -23,7 +23,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:536870911
+mem_ranges=0:536870911:0:0:0:0
 memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
@@ -199,27 +199,27 @@ transition_latency=100000000
 
 [system.mem_ctrl]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -239,6 +239,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -248,7 +249,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:536870911
+range=0:536870911:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -270,9 +271,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -281,6 +282,7 @@ port=system.membus.master[2]
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -292,7 +294,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -300,3 +302,10 @@ width=16
 master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port
 slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.interrupts.int_master system.system_port
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout
index c68473235..3227a9df4 100755
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:19
-gem5 executing on e108600-lin, pid 18562
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:11:23
+gem5 executing on e108600-lin, pid 17668
 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 445082000 because target called exit()
+Exiting @ tick 507841000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt
index 7312a839d..d3b77ec90 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000455                       # Number of seconds simulated
-sim_ticks                                   454507000                       # Number of ticks simulated
-final_tick                                  454507000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000508                       # Number of seconds simulated
+sim_ticks                                   507841000                       # Number of ticks simulated
+final_tick                                  507841000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  76712                       # Simulator instruction rate (inst/s)
-host_op_rate                                   138489                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6101741543                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 651776                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  96340                       # Simulator instruction rate (inst/s)
+host_op_rate                                   173892                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8558810197                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 650468                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        5712                       # Number of instructions simulated
 sim_ops                                         10314                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED    454507000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED    507841000                       # Cumulative time (in ticks) in various power states
 system.mem_ctrl.bytes_read::cpu.inst            58264                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::cpu.data             7167                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::total               65431                       # Number of bytes read from this memory
@@ -26,29 +26,29 @@ system.mem_ctrl.num_reads::cpu.data              1084                       # Nu
 system.mem_ctrl.num_reads::total                 8367                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_writes::cpu.data              941                       # Number of write requests responded to by this memory
 system.mem_ctrl.num_writes::total                 941                       # Number of write requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst           128191645                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data            15768734                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total              143960379                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst      128191645                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total         128191645                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::cpu.data           15753333                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::total              15753333                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst          128191645                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data           31522067                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total             159713712                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.inst           114728823                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data            14112685                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total              128841507                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst      114728823                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total         114728823                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::cpu.data           14098901                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::total              14098901                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst          114728823                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data           28211586                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total             142940409                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrl.readReqs                         8367                       # Number of read requests accepted
 system.mem_ctrl.writeReqs                         941                       # Number of write requests accepted
 system.mem_ctrl.readBursts                       8367                       # Number of DRAM read bursts, including those serviced by the write queue
 system.mem_ctrl.writeBursts                       941                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrl.bytesReadDRAM                  524736                       # Total number of bytes read from DRAM
-system.mem_ctrl.bytesReadWrQ                    10752                       # Total number of bytes read from write queue
-system.mem_ctrl.bytesWritten                     6144                       # Total number of bytes written to DRAM
+system.mem_ctrl.bytesReadDRAM                  525184                       # Total number of bytes read from DRAM
+system.mem_ctrl.bytesReadWrQ                    10304                       # Total number of bytes read from write queue
+system.mem_ctrl.bytesWritten                     7168                       # Total number of bytes written to DRAM
 system.mem_ctrl.bytesReadSys                    65431                       # Total read bytes from the system interface side
 system.mem_ctrl.bytesWrittenSys                  7160                       # Total written bytes from the system interface side
-system.mem_ctrl.servicedByWrQ                     168                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrl.mergedWrBursts                    819                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrl.servicedByWrQ                     161                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrl.mergedWrBursts                    810                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrl.neitherReadNorWriteReqs             0                       # Number of requests that are neither read nor write
-system.mem_ctrl.perBankRdBursts::0                273                       # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::0                277                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::1                  4                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::2                227                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::3                102                       # Per bank write bursts
@@ -58,13 +58,13 @@ system.mem_ctrl.perBankRdBursts::6               1103                       # Pe
 system.mem_ctrl.perBankRdBursts::7                906                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::8                703                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::9                490                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::10              1055                       # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::10              1059                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::11                59                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::12                11                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::13               489                       # Per bank write bursts
 system.mem_ctrl.perBankRdBursts::14                78                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::15               115                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::0                  6                       # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::15               114                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::0                 10                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::1                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::2                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::3                  0                       # Per bank write bursts
@@ -72,17 +72,17 @@ system.mem_ctrl.perBankWrBursts::4                  0                       # Pe
 system.mem_ctrl.perBankWrBursts::5                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::6                  0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::7                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::8                  2                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::9                 53                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::10                23                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::8                  3                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::9                 54                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::10                34                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::11                 7                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::12                 0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::13                 0                       # Per bank write bursts
 system.mem_ctrl.perBankWrBursts::14                 0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::15                 5                       # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::15                 4                       # Per bank write bursts
 system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
 system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
-system.mem_ctrl.totGap                      454381000                       # Total gap between requests
+system.mem_ctrl.totGap                      507709000                       # Total gap between requests
 system.mem_ctrl.readPktSize::0                    135                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::1                     14                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::2                    119                       # Read request sizes (log2)
@@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3                   861                       # Wr
 system.mem_ctrl.writePktSize::4                     0                       # Write request sizes (log2)
 system.mem_ctrl.writePktSize::5                     0                       # Write request sizes (log2)
 system.mem_ctrl.writePktSize::6                     0                       # Write request sizes (log2)
-system.mem_ctrl.rdQLenPdf::0                     8199                       # What read queue length does an incoming req see
+system.mem_ctrl.rdQLenPdf::0                     8206                       # What read queue length does an incoming req see
 system.mem_ctrl.rdQLenPdf::1                        0                       # What read queue length does an incoming req see
 system.mem_ctrl.rdQLenPdf::2                        0                       # What read queue length does an incoming req see
 system.mem_ctrl.rdQLenPdf::3                        0                       # What read queue length does an incoming req see
@@ -146,8 +146,8 @@ system.mem_ctrl.wrQLenPdf::13                       1                       # Wh
 system.mem_ctrl.wrQLenPdf::14                       1                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::15                       1                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::16                       1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::17                       7                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::18                       7                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::17                       8                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::18                       8                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::19                       7                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::20                       7                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::21                       7                       # What write queue length does an incoming req see
@@ -155,13 +155,13 @@ system.mem_ctrl.wrQLenPdf::22                       7                       # Wh
 system.mem_ctrl.wrQLenPdf::23                       7                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::24                       7                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::25                       7                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::26                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::27                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::28                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::29                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::30                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::31                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::32                       6                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::26                       7                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::27                       7                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::28                       7                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::29                       7                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::30                       7                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::31                       7                       # What write queue length does an incoming req see
+system.mem_ctrl.wrQLenPdf::32                       7                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::33                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::34                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::35                       0                       # What write queue length does an incoming req see
@@ -193,94 +193,105 @@ system.mem_ctrl.wrQLenPdf::60                       0                       # Wh
 system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples          849                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean     622.812721                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean    426.803074                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev    394.306776                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127           142     16.73%     16.73% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255           69      8.13%     24.85% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383           77      9.07%     33.92% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511           63      7.42%     41.34% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639           55      6.48%     47.82% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767           39      4.59%     52.41% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895           28      3.30%     55.71% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-1023           21      2.47%     58.19% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151          355     41.81%    100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total           849                       # Bytes accessed per row activation
-system.mem_ctrl.rdPerTurnAround::samples            6                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::mean     1282.333333                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::gmean    1020.532539                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::stdev     764.587906                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::256-383            1     16.67%     16.67% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::384-511            1     16.67%     33.33% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1280-1407            1     16.67%     50.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1408-1535            1     16.67%     66.67% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1920-2047            1     16.67%     83.33% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::2048-2175            1     16.67%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::total              6                       # Reads before turning the bus around for writes
-system.mem_ctrl.wrPerTurnAround::samples            6                       # Writes before turning the bus around for reads
+system.mem_ctrl.bytesPerActivate::samples          856                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean     618.018692                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean    421.107711                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev    393.969749                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127           148     17.29%     17.29% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255           75      8.76%     26.05% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383           73      8.53%     34.58% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511           52      6.07%     40.65% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639           57      6.66%     47.31% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767           49      5.72%     53.04% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895           36      4.21%     57.24% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::896-1023           15      1.75%     59.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151          351     41.00%    100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total           856                       # Bytes accessed per row activation
+system.mem_ctrl.rdPerTurnAround::samples            7                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::mean     1165.285714                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::gmean     941.793638                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::stdev     714.559471                       # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::256-383            1     14.29%     14.29% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::384-511            1     14.29%     28.57% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::640-767            1     14.29%     42.86% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::1280-1407            1     14.29%     57.14% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::1408-1535            1     14.29%     71.43% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::1920-2047            1     14.29%     85.71% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::2048-2175            1     14.29%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::total              7                       # Reads before turning the bus around for writes
+system.mem_ctrl.wrPerTurnAround::samples            7                       # Writes before turning the bus around for reads
 system.mem_ctrl.wrPerTurnAround::mean              16                       # Writes before turning the bus around for reads
 system.mem_ctrl.wrPerTurnAround::gmean      16.000000                       # Writes before turning the bus around for reads
-system.mem_ctrl.wrPerTurnAround::16                 6    100.00%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrl.wrPerTurnAround::total              6                       # Writes before turning the bus around for reads
-system.mem_ctrl.totQLat                      29381000                       # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat                183112250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrl.totBusLat                    40995000                       # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat                       3583.49                       # Average queueing delay per DRAM burst
+system.mem_ctrl.wrPerTurnAround::16                 7    100.00%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrl.wrPerTurnAround::total              7                       # Writes before turning the bus around for reads
+system.mem_ctrl.totQLat                      82515500                       # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat                236378000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totBusLat                    41030000                       # Total ticks spent in databus transfers
+system.mem_ctrl.avgQLat                      10055.51                       # Average queueing delay per DRAM burst
 system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat                 22333.49                       # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW                       1154.52                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW                         13.52                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys                     143.96                       # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys                      15.75                       # Average system write bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat                 28805.51                       # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW                       1034.15                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBW                         14.11                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys                     128.84                       # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBWSys                      14.10                       # Average system write bandwidth in MiByte/s
 system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil                          9.13                       # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead                      9.02                       # Data bus utilization in percentage for reads
+system.mem_ctrl.busUtil                          8.19                       # Data bus utilization in percentage
+system.mem_ctrl.busUtilRead                      8.08                       # Data bus utilization in percentage for reads
 system.mem_ctrl.busUtilWrite                     0.11                       # Data bus utilization in percentage for writes
 system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
-system.mem_ctrl.avgWrQLen                       23.84                       # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits                      7356                       # Number of row buffer hits during reads
-system.mem_ctrl.writeRowHits                       85                       # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate                  89.72                       # Row buffer hit rate for reads
-system.mem_ctrl.writeRowHitRate                 69.67                       # Row buffer hit rate for writes
-system.mem_ctrl.avgGap                       48816.18                       # Average gap between requests
+system.mem_ctrl.avgWrQLen                       23.79                       # Average write queue length when enqueuing
+system.mem_ctrl.readRowHits                      7357                       # Number of row buffer hits during reads
+system.mem_ctrl.writeRowHits                       98                       # Number of row buffer hits during writes
+system.mem_ctrl.readRowHitRate                  89.65                       # Row buffer hit rate for reads
+system.mem_ctrl.writeRowHitRate                 74.81                       # Row buffer hit rate for writes
+system.mem_ctrl.avgGap                       54545.44                       # Average gap between requests
 system.mem_ctrl.pageHitRate                     89.42                       # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy                   3281040                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy                   1790250                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy                 40294800                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_0.writeEnergy                   38880                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy              29496480                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy             248297130                       # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy              53313000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy               376511580                       # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower             833.243697                       # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE      86206500                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::REF       15080000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT      350589750                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrl_1.actEnergy                   3129840                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy                   1707750                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy                 23275200                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_1.writeEnergy                  583200                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy              29496480                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy             273625650                       # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy              31095000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy               362913120                       # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower             803.149454                       # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE      50725000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::REF       15080000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT      387261000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED    454507000                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED    454507000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl_0.actEnergy                   3127320                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy                   1647030                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy                 37149420                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.writeEnergy                   52200                       # Energy for write commands per rank (pJ)
+system.mem_ctrl_0.refreshEnergy          36263760.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_0.actBackEnergy              70559160                       # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy               1716480                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.actPowerDownEnergy        113314290                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_0.prePowerDownEnergy         13222080                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_0.selfRefreshEnergy          17426520                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_0.totalEnergy               294478260                       # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower             579.862821                       # Core power per rank (mW)
+system.mem_ctrl_0.totalIdleTime             347720500                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_0.memoryStateTime::IDLE       1584000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::REF       15358000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::SREF      65707000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::PRE_PDN     34427500                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT      142245250                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT_PDN    248519250                       # Time in different power states
+system.mem_ctrl_1.actEnergy                   3034500                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy                   1601490                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.readEnergy                 21441420                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_1.writeEnergy                  532440                       # Energy for write commands per rank (pJ)
+system.mem_ctrl_1.refreshEnergy          39336960.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_1.actBackEnergy              51598110                       # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy               1155360                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.actPowerDownEnergy        151289970                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_1.prePowerDownEnergy         18740160                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_1.selfRefreshEnergy           3216240                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_1.totalEnergy               291946650                       # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower             574.877779                       # Core power per rank (mW)
+system.mem_ctrl_1.totalIdleTime             391695500                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_1.memoryStateTime::IDLE        757000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::REF       16646000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::SREF      11100000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::PRE_PDN     48800500                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT       98712250                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT_PDN    331825250                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED    507841000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED    507841000                       # Cumulative time (in ticks) in various power states
 system.cpu.apic_clk_domain.clock                16000                       # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED    454507000                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED    454507000                       # Cumulative time (in ticks) in various power states
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED    507841000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED    507841000                       # Cumulative time (in ticks) in various power states
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON       454507000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                           454507                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON       507841000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                           507841                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5712                       # Number of instructions committed
@@ -301,7 +312,7 @@ system.cpu.num_mem_refs                          2025                       # nu
 system.cpu.num_load_insts                        1084                       # Number of load instructions
 system.cpu.num_store_insts                        941                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.001000                       # Number of idle cycles
-system.cpu.num_busy_cycles               454506.999000                       # Number of busy cycles
+system.cpu.num_busy_cycles               507840.999000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1306                       # Number of branches fetched
@@ -346,7 +357,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED    454507000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED    507841000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                8367                       # Transaction distribution
 system.membus.trans_dist::ReadResp               8367                       # Transaction distribution
 system.membus.trans_dist::WriteReq                941                       # Transaction distribution
@@ -374,10 +385,10 @@ system.membus.snoop_fanout::min_value               0                       # Re
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                9308                       # Request fanout histogram
 system.membus.reqLayer2.occupancy            10249000                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               2.3                       # Layer utilization (%)
-system.membus.respLayer0.occupancy           16547250                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3431500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.8                       # Layer utilization (%)
+system.membus.reqLayer2.utilization               2.0                       # Layer utilization (%)
+system.membus.respLayer0.occupancy           16544750                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization              3.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3432250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini
index 1ce461f16..c3a9301a3 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini
@@ -23,7 +23,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:536870911
+mem_ranges=0:536870911:0:0:0:0
 memories=system.mem_ctrl
 mmap_using_noreserve=false
 multi_thread=false
@@ -106,7 +106,7 @@ eventq_index=0
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -171,7 +171,7 @@ system=system
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -321,7 +321,7 @@ system=system
 [system.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
@@ -366,27 +366,27 @@ size=262144
 
 [system.mem_ctrl]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -406,6 +406,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -415,7 +416,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:536870911
+range=0:536870911:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -437,9 +438,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -448,6 +449,7 @@ port=system.membus.master[2]
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -459,7 +461,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -467,3 +469,10 @@ width=16
 master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port
 slave=system.l2cache.mem_side system.cpu.interrupts.int_master system.system_port
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout
index cdf63e901..736ff89ea 100755
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:17
-gem5 executing on e108600-lin, pid 18545
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 21:09:22
+gem5 executing on e108600-lin, pid 17647
 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level
 
 Global frequency set at 1000000000000 ticks per second
 Beginning simulation!
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 55844000 because target called exit()
+Exiting @ tick 58513000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
index a74924642..bf9b895e3 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000056                       # Number of seconds simulated
-sim_ticks                                    56435000                       # Number of ticks simulated
-final_tick                                   56435000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000059                       # Number of seconds simulated
+sim_ticks                                    58513000                       # Number of ticks simulated
+final_tick                                   58513000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 125605                       # Simulator instruction rate (inst/s)
-host_op_rate                                   226732                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1240265940                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 656384                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 325988                       # Simulator instruction rate (inst/s)
+host_op_rate                                   588251                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3335289412                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 654560                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5712                       # Number of instructions simulated
 sim_ops                                         10314                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
 system.mem_ctrl.bytes_read::cpu.inst            14656                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::cpu.data             8640                       # Number of bytes read from this memory
 system.mem_ctrl.bytes_read::total               23296                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total          14656                       # Nu
 system.mem_ctrl.num_reads::cpu.inst               229                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_reads::cpu.data               135                       # Number of read requests responded to by this memory
 system.mem_ctrl.num_reads::total                  364                       # Number of read requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst           259696997                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data           153096483                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total              412793479                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst      259696997                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total         259696997                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst          259696997                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data          153096483                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total             412793479                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.inst           250474254                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data           147659494                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total              398133748                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst      250474254                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total         250474254                       # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst          250474254                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data          147659494                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total             398133748                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrl.readReqs                          364                       # Number of read requests accepted
 system.mem_ctrl.writeReqs                           0                       # Number of write requests accepted
 system.mem_ctrl.readBursts                        364                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14                 0                       # Pe
 system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
 system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
 system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
-system.mem_ctrl.totGap                       56304000                       # Total gap between requests
+system.mem_ctrl.totGap                       58376000                       # Total gap between requests
 system.mem_ctrl.readPktSize::0                      0                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::1                      0                       # Read request sizes (log2)
 system.mem_ctrl.readPktSize::2                      0                       # Read request sizes (log2)
@@ -187,77 +187,88 @@ system.mem_ctrl.wrQLenPdf::60                       0                       # Wh
 system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
 system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples          117                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean     193.094017                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean    128.926887                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev    215.889898                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127            57     48.72%     48.72% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255           28     23.93%     72.65% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383           16     13.68%     86.32% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511            6      5.13%     91.45% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639            2      1.71%     93.16% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767            2      1.71%     94.87% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895            3      2.56%     97.44% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151            3      2.56%    100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total           117                       # Bytes accessed per row activation
-system.mem_ctrl.totQLat                       3777750                       # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat                 10602750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.bytesPerActivate::samples          108                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean     199.703704                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean    135.091179                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev    199.282229                       # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127            52     48.15%     48.15% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255           21     19.44%     67.59% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383           15     13.89%     81.48% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511            8      7.41%     88.89% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639            7      6.48%     95.37% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767            2      1.85%     97.22% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895            1      0.93%     98.15% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::896-1023            1      0.93%     99.07% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151            1      0.93%    100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total           108                       # Bytes accessed per row activation
+system.mem_ctrl.totQLat                       5858750                       # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat                 12683750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.mem_ctrl.totBusLat                     1820000                       # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat                      10378.43                       # Average queueing delay per DRAM burst
+system.mem_ctrl.avgQLat                      16095.47                       # Average queueing delay per DRAM burst
 system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat                 29128.43                       # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW                        412.79                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat                 34845.47                       # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW                        398.13                       # Average DRAM read bandwidth in MiByte/s
 system.mem_ctrl.avgWrBW                          0.00                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys                     412.79                       # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys                     398.13                       # Average system read bandwidth in MiByte/s
 system.mem_ctrl.avgWrBWSys                       0.00                       # Average system write bandwidth in MiByte/s
 system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil                          3.22                       # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead                      3.22                       # Data bus utilization in percentage for reads
+system.mem_ctrl.busUtil                          3.11                       # Data bus utilization in percentage
+system.mem_ctrl.busUtilRead                      3.11                       # Data bus utilization in percentage for reads
 system.mem_ctrl.busUtilWrite                     0.00                       # Data bus utilization in percentage for writes
 system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
 system.mem_ctrl.avgWrQLen                        0.00                       # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits                       241                       # Number of row buffer hits during reads
+system.mem_ctrl.readRowHits                       248                       # Number of row buffer hits during reads
 system.mem_ctrl.writeRowHits                        0                       # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate                  66.21                       # Row buffer hit rate for reads
+system.mem_ctrl.readRowHitRate                  68.13                       # Row buffer hit rate for reads
 system.mem_ctrl.writeRowHitRate                   nan                       # Row buffer hit rate for writes
-system.mem_ctrl.avgGap                      154681.32                       # Average gap between requests
-system.mem_ctrl.pageHitRate                     66.21                       # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy                    309960                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy                    169125                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy                  1201200                       # Energy for read commands per rank (pJ)
+system.mem_ctrl.avgGap                      160373.63                       # Average gap between requests
+system.mem_ctrl.pageHitRate                     68.13                       # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy                    292740                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy                    136620                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy                  1170960                       # Energy for read commands per rank (pJ)
 system.mem_ctrl_0.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy               3559920                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy              32277105                       # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy               4545000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy                42062310                       # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower             768.068476                       # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE       7392500                       # Time in different power states
+system.mem_ctrl_0.refreshEnergy          4302480.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_0.actBackEnergy               2975970                       # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy                 96960                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.actPowerDownEnergy         20164320                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_0.prePowerDownEnergy          2885760                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_0.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_0.totalEnergy                32025810                       # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower             547.321100                       # Core power per rank (mW)
+system.mem_ctrl_0.totalIdleTime              51467750                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_0.memoryStateTime::IDLE         59000                       # Time in different power states
 system.mem_ctrl_0.memoryStateTime::REF        1820000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT       45565000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrl_1.actEnergy                    574560                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy                    313500                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy                  1552200                       # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::PRE_PDN      7513000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT        4902000                       # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT_PDN     44219000                       # Time in different power states
+system.mem_ctrl_1.actEnergy                    535500                       # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy                    273240                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.readEnergy                  1428000                       # Energy for read commands per rank (pJ)
 system.mem_ctrl_1.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy               3559920                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy              36915480                       # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy                476250                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy                43391910                       # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower             792.347310                       # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE       2122500                       # Time in different power states
+system.mem_ctrl_1.refreshEnergy          4302480.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrl_1.actBackEnergy               3735210                       # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy                150720                       # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.actPowerDownEnergy         22328040                       # Energy for active power-down per rank (pJ)
+system.mem_ctrl_1.prePowerDownEnergy           370560                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrl_1.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrl_1.totalEnergy                33123750                       # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower             566.084895                       # Core power per rank (mW)
+system.mem_ctrl_1.totalIdleTime              49870500                       # Total Idle time Per DRAM Rank
+system.mem_ctrl_1.memoryStateTime::IDLE        184000                       # Time in different power states
 system.mem_ctrl_1.memoryStateTime::REF        1820000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT       52384500                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
+system.mem_ctrl_1.memoryStateTime::SREF             0                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::PRE_PDN       965000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT        6563000                       # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT_PDN     48981000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
 system.cpu.apic_clk_domain.clock                16000                       # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        56435000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            56435                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON        58513000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                            58513                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5712                       # Number of instructions committed
@@ -278,7 +289,7 @@ system.cpu.num_mem_refs                          2025                       # nu
 system.cpu.num_load_insts                        1084                       # Number of load instructions
 system.cpu.num_store_insts                        941                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.001000                       # Number of idle cycles
-system.cpu.num_busy_cycles               56434.999000                       # Number of busy cycles
+system.cpu.num_busy_cycles               58512.999000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                              1306                       # Number of branches fetched
@@ -317,23 +328,23 @@ system.cpu.op_class::MemWrite                     941      9.12%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                      10314                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            81.661133                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            81.299644                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1890                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               135                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs                    14                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    81.661133                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.079747                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.079747                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    81.299644                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.079394                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.079394                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           12                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          123                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.131836                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              4185                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             4185                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data         1028                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1028                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          862                       # number of WriteReq hits
@@ -350,14 +361,14 @@ system.cpu.dcache.demand_misses::cpu.data          135                       # n
 system.cpu.dcache.demand_misses::total            135                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          135                       # number of overall misses
 system.cpu.dcache.overall_misses::total           135                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      6076000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      6076000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      8376000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      8376000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     14452000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     14452000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     14452000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     14452000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      6406000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6406000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      8602000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      8602000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     15008000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     15008000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     15008000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     15008000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1084                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1084                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          941                       # number of WriteReq accesses(hits+misses)
@@ -374,14 +385,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.066667
 system.cpu.dcache.demand_miss_rate::total     0.066667                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.066667                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.066667                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data       108500                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total       108500                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106025.316456                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 106025.316456                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 107051.851852                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 107051.851852                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 107051.851852                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 107051.851852                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 111170.370370                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 111170.370370                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -396,14 +407,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          135
 system.cpu.dcache.demand_mshr_misses::total          135                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          135                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          135                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5964000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5964000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      8218000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      8218000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14182000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     14182000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14182000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     14182000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6294000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6294000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      8444000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      8444000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14738000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     14738000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14738000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     14738000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.051661                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.051661                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083953                       # mshr miss rate for WriteReq accesses
@@ -412,31 +423,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066667
 system.cpu.dcache.demand_mshr_miss_rate::total     0.066667                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066667                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.066667                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data       106500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total       106500                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104025.316456                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104025.316456                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105051.851852                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 105051.851852                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105051.851852                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 105051.851852                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                58                       # number of replacements
-system.cpu.icache.tags.tagsinuse            91.248553                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse            90.704136                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                7048                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               235                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             29.991489                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    91.248553                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.356440                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.356440                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst    90.704136                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.354313                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.354313                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          177                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          134                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.691406                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses             14801                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses            14801                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst         7048                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            7048                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          7048                       # number of demand (read+write) hits
@@ -449,12 +460,12 @@ system.cpu.icache.demand_misses::cpu.inst          235                       # n
 system.cpu.icache.demand_misses::total            235                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          235                       # number of overall misses
 system.cpu.icache.overall_misses::total           235                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     24107000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     24107000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     24107000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     24107000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     24107000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     24107000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25629000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25629000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25629000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25629000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25629000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25629000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         7283                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         7283                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         7283                       # number of demand (read+write) accesses
@@ -467,12 +478,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.032267
 system.cpu.icache.demand_miss_rate::total     0.032267                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.032267                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.032267                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102582.978723                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 102582.978723                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 102582.978723                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 102582.978723                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 102582.978723                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 102582.978723                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 109059.574468                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 109059.574468                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -485,31 +496,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          235
 system.cpu.icache.demand_mshr_misses::total          235                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          235                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          235                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23637000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     23637000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23637000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     23637000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23637000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     23637000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25159000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     25159000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25159000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     25159000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25159000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     25159000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.032267                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.032267                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.032267                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.032267                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.032267                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.032267                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100582.978723                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100582.978723                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100582.978723                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 100582.978723                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100582.978723                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 100582.978723                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468                       # average overall mshr miss latency
 system.l2bus.snoop_filter.tot_requests            428                       # Total number of requests made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_requests           59                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.l2bus.snoop_filter.tot_snoops                0                       # Total number of snoops made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l2bus.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
+system.l2bus.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
 system.l2bus.trans_dist::ReadResp                 291                       # Transaction distribution
 system.l2bus.trans_dist::CleanEvict                58                       # Transaction distribution
 system.l2bus.trans_dist::ReadExReq                 79                       # Transaction distribution
@@ -535,30 +546,30 @@ system.l2bus.snoop_fanout::min_value                0                       # Re
 system.l2bus.snoop_fanout::max_value                1                       # Request fanout histogram
 system.l2bus.snoop_fanout::total                  370                       # Request fanout histogram
 system.l2bus.reqLayer0.occupancy               428000                       # Layer occupancy (ticks)
-system.l2bus.reqLayer0.utilization                0.8                       # Layer utilization (%)
+system.l2bus.reqLayer0.utilization                0.7                       # Layer utilization (%)
 system.l2bus.respLayer0.occupancy              705000                       # Layer occupancy (ticks)
 system.l2bus.respLayer0.utilization               1.2                       # Layer utilization (%)
 system.l2bus.respLayer1.occupancy              405000                       # Layer occupancy (ticks)
 system.l2bus.respLayer1.utilization               0.7                       # Layer utilization (%)
-system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
+system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
 system.l2cache.tags.replacements                    0                       # number of replacements
-system.l2cache.tags.tagsinuse              188.623694                       # Cycle average of tags in use
+system.l2cache.tags.tagsinuse              187.541609                       # Cycle average of tags in use
 system.l2cache.tags.total_refs                     64                       # Total number of references to valid blocks.
 system.l2cache.tags.sampled_refs                  364                       # Sample count of references to valid blocks.
 system.l2cache.tags.avg_refs                 0.175824                       # Average number of references to valid blocks.
 system.l2cache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.l2cache.tags.occ_blocks::cpu.inst   106.912326                       # Average occupied blocks per requestor
-system.l2cache.tags.occ_blocks::cpu.data    81.711368                       # Average occupied blocks per requestor
-system.l2cache.tags.occ_percent::cpu.inst     0.026102                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::cpu.data     0.019949                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::total       0.046051                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_blocks::cpu.inst   106.193515                       # Average occupied blocks per requestor
+system.l2cache.tags.occ_blocks::cpu.data    81.348095                       # Average occupied blocks per requestor
+system.l2cache.tags.occ_percent::cpu.inst     0.025926                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::cpu.data     0.019860                       # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::total       0.045787                       # Average percentage of cache occupancy
 system.l2cache.tags.occ_task_id_blocks::1024          364                       # Occupied blocks per task id
 system.l2cache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.l2cache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
 system.l2cache.tags.occ_task_id_percent::1024     0.088867                       # Percentage of cache occupancy per task id
 system.l2cache.tags.tag_accesses                 3788                       # Number of tag accesses
 system.l2cache.tags.data_accesses                3788                       # Number of data accesses
-system.l2cache.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
+system.l2cache.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
 system.l2cache.ReadSharedReq_hits::cpu.inst            6                       # number of ReadSharedReq hits
 system.l2cache.ReadSharedReq_hits::total            6                       # number of ReadSharedReq hits
 system.l2cache.demand_hits::cpu.inst                6                       # number of demand (read+write) hits
@@ -576,17 +587,17 @@ system.l2cache.demand_misses::total               364                       # nu
 system.l2cache.overall_misses::cpu.inst           229                       # number of overall misses
 system.l2cache.overall_misses::cpu.data           135                       # number of overall misses
 system.l2cache.overall_misses::total              364                       # number of overall misses
-system.l2cache.ReadExReq_miss_latency::cpu.data      7981000                       # number of ReadExReq miss cycles
-system.l2cache.ReadExReq_miss_latency::total      7981000                       # number of ReadExReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.inst     22804000                       # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.data      5796000                       # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::total     28600000                       # number of ReadSharedReq miss cycles
-system.l2cache.demand_miss_latency::cpu.inst     22804000                       # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::cpu.data     13777000                       # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::total     36581000                       # number of demand (read+write) miss cycles
-system.l2cache.overall_miss_latency::cpu.inst     22804000                       # number of overall miss cycles
-system.l2cache.overall_miss_latency::cpu.data     13777000                       # number of overall miss cycles
-system.l2cache.overall_miss_latency::total     36581000                       # number of overall miss cycles
+system.l2cache.ReadExReq_miss_latency::cpu.data      8207000                       # number of ReadExReq miss cycles
+system.l2cache.ReadExReq_miss_latency::total      8207000                       # number of ReadExReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.inst     24326000                       # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.data      6126000                       # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::total     30452000                       # number of ReadSharedReq miss cycles
+system.l2cache.demand_miss_latency::cpu.inst     24326000                       # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::cpu.data     14333000                       # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::total     38659000                       # number of demand (read+write) miss cycles
+system.l2cache.overall_miss_latency::cpu.inst     24326000                       # number of overall miss cycles
+system.l2cache.overall_miss_latency::cpu.data     14333000                       # number of overall miss cycles
+system.l2cache.overall_miss_latency::total     38659000                       # number of overall miss cycles
 system.l2cache.ReadExReq_accesses::cpu.data           79                       # number of ReadExReq accesses(hits+misses)
 system.l2cache.ReadExReq_accesses::total           79                       # number of ReadExReq accesses(hits+misses)
 system.l2cache.ReadSharedReq_accesses::cpu.inst          235                       # number of ReadSharedReq accesses(hits+misses)
@@ -609,17 +620,17 @@ system.l2cache.demand_miss_rate::total       0.983784                       # mi
 system.l2cache.overall_miss_rate::cpu.inst     0.974468                       # miss rate for overall accesses
 system.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.l2cache.overall_miss_rate::total      0.983784                       # miss rate for overall accesses
-system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101025.316456                       # average ReadExReq miss latency
-system.l2cache.ReadExReq_avg_miss_latency::total 101025.316456                       # average ReadExReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 99580.786026                       # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data       103500                       # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::total 100350.877193                       # average ReadSharedReq miss latency
-system.l2cache.demand_avg_miss_latency::cpu.inst 99580.786026                       # average overall miss latency
-system.l2cache.demand_avg_miss_latency::cpu.data 102051.851852                       # average overall miss latency
-system.l2cache.demand_avg_miss_latency::total 100497.252747                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.inst 99580.786026                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.data 102051.851852                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::total 100497.252747                       # average overall miss latency
+system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103886.075949                       # average ReadExReq miss latency
+system.l2cache.ReadExReq_avg_miss_latency::total 103886.075949                       # average ReadExReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 106227.074236                       # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109392.857143                       # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::total 106849.122807                       # average ReadSharedReq miss latency
+system.l2cache.demand_avg_miss_latency::cpu.inst 106227.074236                       # average overall miss latency
+system.l2cache.demand_avg_miss_latency::cpu.data 106170.370370                       # average overall miss latency
+system.l2cache.demand_avg_miss_latency::total 106206.043956                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370                       # average overall miss latency
+system.l2cache.overall_avg_miss_latency::total 106206.043956                       # average overall miss latency
 system.l2cache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.l2cache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -637,17 +648,17 @@ system.l2cache.demand_mshr_misses::total          364                       # nu
 system.l2cache.overall_mshr_misses::cpu.inst          229                       # number of overall MSHR misses
 system.l2cache.overall_mshr_misses::cpu.data          135                       # number of overall MSHR misses
 system.l2cache.overall_mshr_misses::total          364                       # number of overall MSHR misses
-system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      6401000                       # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadExReq_mshr_miss_latency::total      6401000                       # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     18224000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4676000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::total     22900000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.inst     18224000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.data     11077000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::total     29301000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.inst     18224000                       # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.data     11077000                       # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::total     29301000                       # number of overall MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      6627000                       # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::total      6627000                       # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     19746000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5006000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::total     24752000                       # number of ReadSharedReq MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.inst     19746000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.data     11633000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::total     31379000                       # number of demand (read+write) MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.inst     19746000                       # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.data     11633000                       # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::total     31379000                       # number of overall MSHR miss cycles
 system.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst     0.974468                       # mshr miss rate for ReadSharedReq accesses
@@ -659,24 +670,24 @@ system.l2cache.demand_mshr_miss_rate::total     0.983784                       #
 system.l2cache.overall_mshr_miss_rate::cpu.inst     0.974468                       # mshr miss rate for overall accesses
 system.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.l2cache.overall_mshr_miss_rate::total     0.983784                       # mshr miss rate for overall accesses
-system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81025.316456                       # average ReadExReq mshr miss latency
-system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81025.316456                       # average ReadExReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 79580.786026                       # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        83500                       # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80350.877193                       # average ReadSharedReq mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79580.786026                       # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82051.851852                       # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::total 80497.252747                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79580.786026                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82051.851852                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::total 80497.252747                       # average overall mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949                       # average ReadExReq mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949                       # average ReadExReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236                       # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143                       # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807                       # average ReadSharedReq mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236                       # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370                       # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370                       # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956                       # average overall mshr miss latency
 system.membus.snoop_filter.tot_requests           364                       # Total number of requests made to the snoop filter.
 system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     56435000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                285                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                79                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               79                       # Transaction distribution
@@ -701,7 +712,7 @@ system.membus.snoop_fanout::max_value               0                       # Re
 system.membus.snoop_fanout::total                 364                       # Request fanout histogram
 system.membus.reqLayer2.occupancy              364000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.6                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1954250                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.5                       # Layer utilization (%)
+system.membus.respLayer0.occupancy            1951250                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization              3.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini
index 19a9a115f..bd0cc03e4 100644
--- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini
+++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cp_cntrl0 cpu0 cpu1 cpu2 dir_cntrl0 dispatcher_coalescer dis
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,13 +23,19 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:536870911
+mem_ranges=0:536870911:0:0:0:0
 memories=system.mem_ctrls system.ruby.phys_mem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -56,11 +63,16 @@ L2cache=system.cp_cntrl0.L2cache
 buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=15
 l2_hit_latency=18
 mandatoryQueue=system.cp_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 probeToCore=system.cp_cntrl0.probeToCore
 recycle_latency=10
 requestFromCore=system.cp_cntrl0.requestFromCore
@@ -218,17 +230,22 @@ coreid=0
 dcache=system.cp_cntrl0.L1D0cache
 dcache_hit_latency=2
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.cp_cntrl0.L1Icache
 icache_hit_latency=2
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=0
 master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave
@@ -242,17 +259,22 @@ coreid=1
 dcache=system.cp_cntrl0.L1D1cache
 dcache_hit_latency=2
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.cp_cntrl0.L1Icache
 icache_hit_latency=2
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=1
 
@@ -278,6 +300,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu0.clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -293,6 +316,10 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -328,18 +355,28 @@ walker=system.cpu0.dtb.walker
 [system.cpu0.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu0.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.cp_cntrl0.sequencer.slave[3]
 
 [system.cpu0.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu0.apic_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 int_latency=1000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=2305843009213693952
 pio_latency=100000
+power_model=Null
 system=system
 int_master=system.cp_cntrl0.sequencer.slave[4]
 int_slave=system.cp_cntrl0.sequencer.master[1]
@@ -359,8 +396,13 @@ walker=system.cpu0.itb.walker
 [system.cpu0.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu0.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 system=system
 port=system.cp_cntrl0.sequencer.slave[2]
 
@@ -378,7 +420,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/gpu-hello/bin/x86/linux/gpu-hello
 gid=100
 input=cin
 kvmInSE=false
@@ -397,10 +439,15 @@ children=CUs0 CUs1 clk_domain
 CUs=system.cpu1.CUs0 system.cpu1.CUs1
 clk_domain=system.cpu1.clk_domain
 cpu_pointer=system.cpu0
+default_p_state=UNDEFINED
 eventq_index=0
 globalmem=65536
 impl_kern_boundary_sync=false
 n_wf=8
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 separate_acquire_release=false
 timing=true
 translation=false
@@ -413,6 +460,7 @@ coalescer_to_vrf_bus_width=32
 countPages=false
 cu_id=0
 debugSegFault=false
+default_p_state=UNDEFINED
 dpbypass_pipe_length=4
 eventq_index=0
 execPolicy=OLDEST-FIRST
@@ -428,7 +476,11 @@ n_wf=8
 num_SIMDs=4
 num_global_mem_pipes=1
 num_shared_mem_pipes=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 perLaneTLB=false
+power_model=Null
 prefetch_depth=0
 prefetch_prev_type=PF_PHASE
 prefetch_stride=1
@@ -448,9 +500,14 @@ translation_port=system.l1_coalescer0.slave[0]
 [system.cpu1.CUs0.ldsBus]
 type=Bridge
 clk_domain=system.cpu1.clk_domain
+default_p_state=UNDEFINED
 delay=0
 eventq_index=0
-ranges=0:18446744073709551615
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+ranges=0:18446744073709551615:0:0:0:0
 req_size=16
 resp_size=16
 master=system.cpu1.CUs0.localDataStore.cuPort
@@ -461,8 +518,13 @@ type=LdsState
 bankConflictPenalty=1
 banks=32
 clk_domain=system.cpu1.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
-range=0:65535
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+range=0:65535:0:0:0:0
 size=65536
 cuPort=system.cpu1.CUs0.ldsBus.master
 
@@ -472,6 +534,7 @@ eventq_index=0
 min_alloc=4
 num_regs_per_simd=2048
 simd_id=0
+wfSize=64
 
 [system.cpu1.CUs0.vector_register_file1]
 type=VectorRegisterFile
@@ -479,6 +542,7 @@ eventq_index=0
 min_alloc=4
 num_regs_per_simd=2048
 simd_id=1
+wfSize=64
 
 [system.cpu1.CUs0.vector_register_file2]
 type=VectorRegisterFile
@@ -486,6 +550,7 @@ eventq_index=0
 min_alloc=4
 num_regs_per_simd=2048
 simd_id=2
+wfSize=64
 
 [system.cpu1.CUs0.vector_register_file3]
 type=VectorRegisterFile
@@ -493,197 +558,230 @@ eventq_index=0
 min_alloc=4
 num_regs_per_simd=2048
 simd_id=3
+wfSize=64
 
 [system.cpu1.CUs0.wavefronts00]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=0
 
 [system.cpu1.CUs0.wavefronts01]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=1
 
 [system.cpu1.CUs0.wavefronts02]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=2
 
 [system.cpu1.CUs0.wavefronts03]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=3
 
 [system.cpu1.CUs0.wavefronts04]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=4
 
 [system.cpu1.CUs0.wavefronts05]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=5
 
 [system.cpu1.CUs0.wavefronts06]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=6
 
 [system.cpu1.CUs0.wavefronts07]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=7
 
 [system.cpu1.CUs0.wavefronts08]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=0
 
 [system.cpu1.CUs0.wavefronts09]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=1
 
 [system.cpu1.CUs0.wavefronts10]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=2
 
 [system.cpu1.CUs0.wavefronts11]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=3
 
 [system.cpu1.CUs0.wavefronts12]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=4
 
 [system.cpu1.CUs0.wavefronts13]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=5
 
 [system.cpu1.CUs0.wavefronts14]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=6
 
 [system.cpu1.CUs0.wavefronts15]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=7
 
 [system.cpu1.CUs0.wavefronts16]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=0
 
 [system.cpu1.CUs0.wavefronts17]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=1
 
 [system.cpu1.CUs0.wavefronts18]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=2
 
 [system.cpu1.CUs0.wavefronts19]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=3
 
 [system.cpu1.CUs0.wavefronts20]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=4
 
 [system.cpu1.CUs0.wavefronts21]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=5
 
 [system.cpu1.CUs0.wavefronts22]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=6
 
 [system.cpu1.CUs0.wavefronts23]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=7
 
 [system.cpu1.CUs0.wavefronts24]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=0
 
 [system.cpu1.CUs0.wavefronts25]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=1
 
 [system.cpu1.CUs0.wavefronts26]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=2
 
 [system.cpu1.CUs0.wavefronts27]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=3
 
 [system.cpu1.CUs0.wavefronts28]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=4
 
 [system.cpu1.CUs0.wavefronts29]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=5
 
 [system.cpu1.CUs0.wavefronts30]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=6
 
 [system.cpu1.CUs0.wavefronts31]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=7
 
 [system.cpu1.CUs1]
@@ -694,6 +792,7 @@ coalescer_to_vrf_bus_width=32
 countPages=false
 cu_id=1
 debugSegFault=false
+default_p_state=UNDEFINED
 dpbypass_pipe_length=4
 eventq_index=0
 execPolicy=OLDEST-FIRST
@@ -709,7 +808,11 @@ n_wf=8
 num_SIMDs=4
 num_global_mem_pipes=1
 num_shared_mem_pipes=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 perLaneTLB=false
+power_model=Null
 prefetch_depth=0
 prefetch_prev_type=PF_PHASE
 prefetch_stride=1
@@ -729,9 +832,14 @@ translation_port=system.l1_coalescer1.slave[0]
 [system.cpu1.CUs1.ldsBus]
 type=Bridge
 clk_domain=system.cpu1.clk_domain
+default_p_state=UNDEFINED
 delay=0
 eventq_index=0
-ranges=0:18446744073709551615
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+ranges=0:18446744073709551615:0:0:0:0
 req_size=16
 resp_size=16
 master=system.cpu1.CUs1.localDataStore.cuPort
@@ -742,8 +850,13 @@ type=LdsState
 bankConflictPenalty=1
 banks=32
 clk_domain=system.cpu1.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
-range=0:65535
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+range=0:65535:0:0:0:0
 size=65536
 cuPort=system.cpu1.CUs1.ldsBus.master
 
@@ -753,6 +866,7 @@ eventq_index=0
 min_alloc=4
 num_regs_per_simd=2048
 simd_id=0
+wfSize=64
 
 [system.cpu1.CUs1.vector_register_file1]
 type=VectorRegisterFile
@@ -760,6 +874,7 @@ eventq_index=0
 min_alloc=4
 num_regs_per_simd=2048
 simd_id=1
+wfSize=64
 
 [system.cpu1.CUs1.vector_register_file2]
 type=VectorRegisterFile
@@ -767,6 +882,7 @@ eventq_index=0
 min_alloc=4
 num_regs_per_simd=2048
 simd_id=2
+wfSize=64
 
 [system.cpu1.CUs1.vector_register_file3]
 type=VectorRegisterFile
@@ -774,197 +890,230 @@ eventq_index=0
 min_alloc=4
 num_regs_per_simd=2048
 simd_id=3
+wfSize=64
 
 [system.cpu1.CUs1.wavefronts00]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=0
 
 [system.cpu1.CUs1.wavefronts01]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=1
 
 [system.cpu1.CUs1.wavefronts02]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=2
 
 [system.cpu1.CUs1.wavefronts03]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=3
 
 [system.cpu1.CUs1.wavefronts04]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=4
 
 [system.cpu1.CUs1.wavefronts05]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=5
 
 [system.cpu1.CUs1.wavefronts06]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=6
 
 [system.cpu1.CUs1.wavefronts07]
 type=Wavefront
 eventq_index=0
 simdId=0
+wfSize=64
 wf_slot_id=7
 
 [system.cpu1.CUs1.wavefronts08]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=0
 
 [system.cpu1.CUs1.wavefronts09]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=1
 
 [system.cpu1.CUs1.wavefronts10]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=2
 
 [system.cpu1.CUs1.wavefronts11]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=3
 
 [system.cpu1.CUs1.wavefronts12]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=4
 
 [system.cpu1.CUs1.wavefronts13]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=5
 
 [system.cpu1.CUs1.wavefronts14]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=6
 
 [system.cpu1.CUs1.wavefronts15]
 type=Wavefront
 eventq_index=0
 simdId=1
+wfSize=64
 wf_slot_id=7
 
 [system.cpu1.CUs1.wavefronts16]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=0
 
 [system.cpu1.CUs1.wavefronts17]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=1
 
 [system.cpu1.CUs1.wavefronts18]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=2
 
 [system.cpu1.CUs1.wavefronts19]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=3
 
 [system.cpu1.CUs1.wavefronts20]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=4
 
 [system.cpu1.CUs1.wavefronts21]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=5
 
 [system.cpu1.CUs1.wavefronts22]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=6
 
 [system.cpu1.CUs1.wavefronts23]
 type=Wavefront
 eventq_index=0
 simdId=2
+wfSize=64
 wf_slot_id=7
 
 [system.cpu1.CUs1.wavefronts24]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=0
 
 [system.cpu1.CUs1.wavefronts25]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=1
 
 [system.cpu1.CUs1.wavefronts26]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=2
 
 [system.cpu1.CUs1.wavefronts27]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=3
 
 [system.cpu1.CUs1.wavefronts28]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=4
 
 [system.cpu1.CUs1.wavefronts29]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=5
 
 [system.cpu1.CUs1.wavefronts30]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=6
 
 [system.cpu1.CUs1.wavefronts31]
 type=Wavefront
 eventq_index=0
 simdId=3
+wfSize=64
 wf_slot_id=7
 
 [system.cpu1.clk_domain]
@@ -987,9 +1136,14 @@ children=cl_driver
 cl_driver=system.cpu2.cl_driver
 clk_domain=system.clk_domain
 cpu=system.cpu0
+default_p_state=UNDEFINED
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=8589934592
 pio_latency=1000
+power_model=Null
 shader_pointer=system.cpu1
 system=system
 dma=system.piobus.slave[1]
@@ -998,7 +1152,7 @@ translation_port=system.dispatcher_coalescer.slave[0]
 
 [system.cpu2.cl_driver]
 type=ClDriver
-codefile=/home/stever/hg/m5sim.org/gem5/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
+codefile=/arm/projectscratch/randd/systems/dist/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
 eventq_index=0
 filename=hsa
 
@@ -1012,11 +1166,16 @@ TCC_select_num_bits=0
 buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.dir_cntrl0.directory
 eventq_index=0
 l3_hit_latency=15
 noTCCdir=false
 number_of_TBEs=5120
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 probeToCore=system.dir_cntrl0.probeToCore
 recycle_latency=10
 requestFromCores=system.dir_cntrl0.requestFromCores
@@ -1131,8 +1290,13 @@ type=TLBCoalescer
 children=clk_domain
 clk_domain=system.dispatcher_coalescer.clk_domain
 coalescingWindow=1
+default_p_state=UNDEFINED
 disableCoalescing=false
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 probesPerCycle=2
 master=system.dispatcher_tlb.slave[0]
 slave=system.cpu2.translation_port
@@ -1158,11 +1322,16 @@ accessDistance=false
 allocationPolicy=true
 assoc=32
 clk_domain=system.dispatcher_tlb.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hitLatency=1
 maxOutstandingReqs=64
 missLatency1=5
 missLatency2=750
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 size=32
 master=system.l2_coalescer.slave[1]
 slave=system.dispatcher_coalescer.master[0]
@@ -1194,8 +1363,13 @@ type=TLBCoalescer
 children=clk_domain
 clk_domain=system.l1_coalescer0.clk_domain
 coalescingWindow=1
+default_p_state=UNDEFINED
 disableCoalescing=false
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 probesPerCycle=2
 master=system.l1_tlb0.slave[0]
 slave=system.cpu1.CUs0.translation_port[0]
@@ -1219,8 +1393,13 @@ type=TLBCoalescer
 children=clk_domain
 clk_domain=system.l1_coalescer1.clk_domain
 coalescingWindow=1
+default_p_state=UNDEFINED
 disableCoalescing=false
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 probesPerCycle=2
 master=system.l1_tlb1.slave[0]
 slave=system.cpu1.CUs1.translation_port[0]
@@ -1246,11 +1425,16 @@ accessDistance=false
 allocationPolicy=true
 assoc=32
 clk_domain=system.l1_tlb0.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hitLatency=1
 maxOutstandingReqs=64
 missLatency1=5
 missLatency2=750
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 size=32
 master=system.l2_coalescer.slave[2]
 slave=system.l1_coalescer0.master[0]
@@ -1276,11 +1460,16 @@ accessDistance=false
 allocationPolicy=true
 assoc=32
 clk_domain=system.l1_tlb1.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hitLatency=1
 maxOutstandingReqs=64
 missLatency1=5
 missLatency2=750
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 size=32
 master=system.l2_coalescer.slave[3]
 slave=system.l1_coalescer1.master[0]
@@ -1304,8 +1493,13 @@ type=TLBCoalescer
 children=clk_domain
 clk_domain=system.l2_coalescer.clk_domain
 coalescingWindow=1
+default_p_state=UNDEFINED
 disableCoalescing=false
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 probesPerCycle=2
 master=system.l2_tlb.slave[0]
 slave=system.sqc_tlb.master[0] system.dispatcher_tlb.master[0] system.l1_tlb0.master[0] system.l1_tlb1.master[0]
@@ -1331,11 +1525,16 @@ accessDistance=false
 allocationPolicy=true
 assoc=32
 clk_domain=system.l2_tlb.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hitLatency=69
 maxOutstandingReqs=64
 missLatency1=5
 missLatency2=750
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 size=4096
 master=system.l3_coalescer.slave[0]
 slave=system.l2_coalescer.master[0]
@@ -1359,8 +1558,13 @@ type=TLBCoalescer
 children=clk_domain
 clk_domain=system.l3_coalescer.clk_domain
 coalescingWindow=1
+default_p_state=UNDEFINED
 disableCoalescing=false
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 probesPerCycle=2
 master=system.l3_tlb.slave[0]
 slave=system.l2_tlb.master[0]
@@ -1386,11 +1590,16 @@ accessDistance=false
 allocationPolicy=true
 assoc=32
 clk_domain=system.l3_tlb.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hitLatency=150
 maxOutstandingReqs=64
 missLatency1=5
 missLatency2=750
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 size=8192
 slave=system.l3_coalescer.master[0]
 
@@ -1410,27 +1619,27 @@ voltage=1.000000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -1442,6 +1651,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -1449,12 +1659,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=false
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
-range=0:536870911
+power_model=Null
+range=0:536870911:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1476,9 +1691,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -1488,9 +1703,14 @@ port=system.dir_cntrl0.memory
 [system.piobus]
 type=NoncoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=0
 frontend_latency=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 response_latency=0
 use_default_range=false
 width=32
@@ -1504,12 +1724,17 @@ access_backing_store=true
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=5
 number_of_virtual_networks=10
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 phys_mem=system.ruby.phys_mem
+power_model=Null
 randomization=false
 
 [system.ruby.clk_domain]
@@ -1522,18 +1747,23 @@ voltage_domain=system.voltage_domain
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_link_buffers72 int_link_buffers73 int_link_buffers74 int_link_buffers75 int_link_buffers76 int_link_buffers77 int_link_buffers78 int_link_buffers79 int_links0 int_links1 int_links2 int_links3
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 system.ruby.network.int_link_buffers72 system.ruby.network.int_link_buffers73 system.ruby.network.int_link_buffers74 system.ruby.network.int_link_buffers75 system.ruby.network.int_link_buffers76 system.ruby.network.int_link_buffers77 system.ruby.network.int_link_buffers78 system.ruby.network.int_link_buffers79
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
 netifs=
 number_of_virtual_networks=10
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 routers=system.ruby.network.ext_links0.int_node system.ruby.network.ext_links1.int_node system.ruby.network.ext_links2.int_node
 ruby_system=system.ruby
 topology=Crossbar
@@ -1555,8 +1785,14 @@ weight=1
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 port_buffers36 port_buffers37 port_buffers38 port_buffers39 port_buffers40 port_buffers41 port_buffers42 port_buffers43 port_buffers44 port_buffers45 port_buffers46 port_buffers47 port_buffers48 port_buffers49 port_buffers50 port_buffers51 port_buffers52 port_buffers53 port_buffers54 port_buffers55 port_buffers56 port_buffers57 port_buffers58 port_buffers59 port_buffers60 port_buffers61 port_buffers62 port_buffers63 port_buffers64 port_buffers65 port_buffers66 port_buffers67 port_buffers68 port_buffers69 port_buffers70 port_buffers71 port_buffers72 port_buffers73 port_buffers74 port_buffers75 port_buffers76 port_buffers77 port_buffers78 port_buffers79 port_buffers80 port_buffers81 port_buffers82 port_buffers83 port_buffers84 port_buffers85 port_buffers86 port_buffers87 port_buffers88 port_buffers89
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 port_buffers=system.ruby.network.ext_links0.int_node.port_buffers00 system.ruby.network.ext_links0.int_node.port_buffers01 system.ruby.network.ext_links0.int_node.port_buffers02 system.ruby.network.ext_links0.int_node.port_buffers03 system.ruby.network.ext_links0.int_node.port_buffers04 system.ruby.network.ext_links0.int_node.port_buffers05 system.ruby.network.ext_links0.int_node.port_buffers06 system.ruby.network.ext_links0.int_node.port_buffers07 system.ruby.network.ext_links0.int_node.port_buffers08 system.ruby.network.ext_links0.int_node.port_buffers09 system.ruby.network.ext_links0.int_node.port_buffers10 system.ruby.network.ext_links0.int_node.port_buffers11 system.ruby.network.ext_links0.int_node.port_buffers12 system.ruby.network.ext_links0.int_node.port_buffers13 system.ruby.network.ext_links0.int_node.port_buffers14 system.ruby.network.ext_links0.int_node.port_buffers15 system.ruby.network.ext_links0.int_node.port_buffers16 system.ruby.network.ext_links0.int_node.port_buffers17 system.ruby.network.ext_links0.int_node.port_buffers18 system.ruby.network.ext_links0.int_node.port_buffers19 system.ruby.network.ext_links0.int_node.port_buffers20 system.ruby.network.ext_links0.int_node.port_buffers21 system.ruby.network.ext_links0.int_node.port_buffers22 system.ruby.network.ext_links0.int_node.port_buffers23 system.ruby.network.ext_links0.int_node.port_buffers24 system.ruby.network.ext_links0.int_node.port_buffers25 system.ruby.network.ext_links0.int_node.port_buffers26 system.ruby.network.ext_links0.int_node.port_buffers27 system.ruby.network.ext_links0.int_node.port_buffers28 system.ruby.network.ext_links0.int_node.port_buffers29 system.ruby.network.ext_links0.int_node.port_buffers30 system.ruby.network.ext_links0.int_node.port_buffers31 system.ruby.network.ext_links0.int_node.port_buffers32 system.ruby.network.ext_links0.int_node.port_buffers33 system.ruby.network.ext_links0.int_node.port_buffers34 system.ruby.network.ext_links0.int_node.port_buffers35 system.ruby.network.ext_links0.int_node.port_buffers36 system.ruby.network.ext_links0.int_node.port_buffers37 system.ruby.network.ext_links0.int_node.port_buffers38 system.ruby.network.ext_links0.int_node.port_buffers39 system.ruby.network.ext_links0.int_node.port_buffers40 system.ruby.network.ext_links0.int_node.port_buffers41 system.ruby.network.ext_links0.int_node.port_buffers42 system.ruby.network.ext_links0.int_node.port_buffers43 system.ruby.network.ext_links0.int_node.port_buffers44 system.ruby.network.ext_links0.int_node.port_buffers45 system.ruby.network.ext_links0.int_node.port_buffers46 system.ruby.network.ext_links0.int_node.port_buffers47 system.ruby.network.ext_links0.int_node.port_buffers48 system.ruby.network.ext_links0.int_node.port_buffers49 system.ruby.network.ext_links0.int_node.port_buffers50 system.ruby.network.ext_links0.int_node.port_buffers51 system.ruby.network.ext_links0.int_node.port_buffers52 system.ruby.network.ext_links0.int_node.port_buffers53 system.ruby.network.ext_links0.int_node.port_buffers54 system.ruby.network.ext_links0.int_node.port_buffers55 system.ruby.network.ext_links0.int_node.port_buffers56 system.ruby.network.ext_links0.int_node.port_buffers57 system.ruby.network.ext_links0.int_node.port_buffers58 system.ruby.network.ext_links0.int_node.port_buffers59 system.ruby.network.ext_links0.int_node.port_buffers60 system.ruby.network.ext_links0.int_node.port_buffers61 system.ruby.network.ext_links0.int_node.port_buffers62 system.ruby.network.ext_links0.int_node.port_buffers63 system.ruby.network.ext_links0.int_node.port_buffers64 system.ruby.network.ext_links0.int_node.port_buffers65 system.ruby.network.ext_links0.int_node.port_buffers66 system.ruby.network.ext_links0.int_node.port_buffers67 system.ruby.network.ext_links0.int_node.port_buffers68 system.ruby.network.ext_links0.int_node.port_buffers69 system.ruby.network.ext_links0.int_node.port_buffers70 system.ruby.network.ext_links0.int_node.port_buffers71 system.ruby.network.ext_links0.int_node.port_buffers72 system.ruby.network.ext_links0.int_node.port_buffers73 system.ruby.network.ext_links0.int_node.port_buffers74 system.ruby.network.ext_links0.int_node.port_buffers75 system.ruby.network.ext_links0.int_node.port_buffers76 system.ruby.network.ext_links0.int_node.port_buffers77 system.ruby.network.ext_links0.int_node.port_buffers78 system.ruby.network.ext_links0.int_node.port_buffers79 system.ruby.network.ext_links0.int_node.port_buffers80 system.ruby.network.ext_links0.int_node.port_buffers81 system.ruby.network.ext_links0.int_node.port_buffers82 system.ruby.network.ext_links0.int_node.port_buffers83 system.ruby.network.ext_links0.int_node.port_buffers84 system.ruby.network.ext_links0.int_node.port_buffers85 system.ruby.network.ext_links0.int_node.port_buffers86 system.ruby.network.ext_links0.int_node.port_buffers87 system.ruby.network.ext_links0.int_node.port_buffers88 system.ruby.network.ext_links0.int_node.port_buffers89
+power_model=Null
 router_id=0
 virt_nets=10
 
@@ -2205,8 +2441,14 @@ weight=1
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 port_buffers36 port_buffers37 port_buffers38 port_buffers39 port_buffers40 port_buffers41 port_buffers42 port_buffers43 port_buffers44 port_buffers45 port_buffers46 port_buffers47 port_buffers48 port_buffers49 port_buffers50 port_buffers51 port_buffers52 port_buffers53 port_buffers54 port_buffers55 port_buffers56 port_buffers57 port_buffers58 port_buffers59 port_buffers60 port_buffers61 port_buffers62 port_buffers63 port_buffers64 port_buffers65 port_buffers66 port_buffers67 port_buffers68 port_buffers69 port_buffers70 port_buffers71 port_buffers72 port_buffers73 port_buffers74 port_buffers75 port_buffers76 port_buffers77 port_buffers78 port_buffers79
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 port_buffers=system.ruby.network.ext_links1.int_node.port_buffers00 system.ruby.network.ext_links1.int_node.port_buffers01 system.ruby.network.ext_links1.int_node.port_buffers02 system.ruby.network.ext_links1.int_node.port_buffers03 system.ruby.network.ext_links1.int_node.port_buffers04 system.ruby.network.ext_links1.int_node.port_buffers05 system.ruby.network.ext_links1.int_node.port_buffers06 system.ruby.network.ext_links1.int_node.port_buffers07 system.ruby.network.ext_links1.int_node.port_buffers08 system.ruby.network.ext_links1.int_node.port_buffers09 system.ruby.network.ext_links1.int_node.port_buffers10 system.ruby.network.ext_links1.int_node.port_buffers11 system.ruby.network.ext_links1.int_node.port_buffers12 system.ruby.network.ext_links1.int_node.port_buffers13 system.ruby.network.ext_links1.int_node.port_buffers14 system.ruby.network.ext_links1.int_node.port_buffers15 system.ruby.network.ext_links1.int_node.port_buffers16 system.ruby.network.ext_links1.int_node.port_buffers17 system.ruby.network.ext_links1.int_node.port_buffers18 system.ruby.network.ext_links1.int_node.port_buffers19 system.ruby.network.ext_links1.int_node.port_buffers20 system.ruby.network.ext_links1.int_node.port_buffers21 system.ruby.network.ext_links1.int_node.port_buffers22 system.ruby.network.ext_links1.int_node.port_buffers23 system.ruby.network.ext_links1.int_node.port_buffers24 system.ruby.network.ext_links1.int_node.port_buffers25 system.ruby.network.ext_links1.int_node.port_buffers26 system.ruby.network.ext_links1.int_node.port_buffers27 system.ruby.network.ext_links1.int_node.port_buffers28 system.ruby.network.ext_links1.int_node.port_buffers29 system.ruby.network.ext_links1.int_node.port_buffers30 system.ruby.network.ext_links1.int_node.port_buffers31 system.ruby.network.ext_links1.int_node.port_buffers32 system.ruby.network.ext_links1.int_node.port_buffers33 system.ruby.network.ext_links1.int_node.port_buffers34 system.ruby.network.ext_links1.int_node.port_buffers35 system.ruby.network.ext_links1.int_node.port_buffers36 system.ruby.network.ext_links1.int_node.port_buffers37 system.ruby.network.ext_links1.int_node.port_buffers38 system.ruby.network.ext_links1.int_node.port_buffers39 system.ruby.network.ext_links1.int_node.port_buffers40 system.ruby.network.ext_links1.int_node.port_buffers41 system.ruby.network.ext_links1.int_node.port_buffers42 system.ruby.network.ext_links1.int_node.port_buffers43 system.ruby.network.ext_links1.int_node.port_buffers44 system.ruby.network.ext_links1.int_node.port_buffers45 system.ruby.network.ext_links1.int_node.port_buffers46 system.ruby.network.ext_links1.int_node.port_buffers47 system.ruby.network.ext_links1.int_node.port_buffers48 system.ruby.network.ext_links1.int_node.port_buffers49 system.ruby.network.ext_links1.int_node.port_buffers50 system.ruby.network.ext_links1.int_node.port_buffers51 system.ruby.network.ext_links1.int_node.port_buffers52 system.ruby.network.ext_links1.int_node.port_buffers53 system.ruby.network.ext_links1.int_node.port_buffers54 system.ruby.network.ext_links1.int_node.port_buffers55 system.ruby.network.ext_links1.int_node.port_buffers56 system.ruby.network.ext_links1.int_node.port_buffers57 system.ruby.network.ext_links1.int_node.port_buffers58 system.ruby.network.ext_links1.int_node.port_buffers59 system.ruby.network.ext_links1.int_node.port_buffers60 system.ruby.network.ext_links1.int_node.port_buffers61 system.ruby.network.ext_links1.int_node.port_buffers62 system.ruby.network.ext_links1.int_node.port_buffers63 system.ruby.network.ext_links1.int_node.port_buffers64 system.ruby.network.ext_links1.int_node.port_buffers65 system.ruby.network.ext_links1.int_node.port_buffers66 system.ruby.network.ext_links1.int_node.port_buffers67 system.ruby.network.ext_links1.int_node.port_buffers68 system.ruby.network.ext_links1.int_node.port_buffers69 system.ruby.network.ext_links1.int_node.port_buffers70 system.ruby.network.ext_links1.int_node.port_buffers71 system.ruby.network.ext_links1.int_node.port_buffers72 system.ruby.network.ext_links1.int_node.port_buffers73 system.ruby.network.ext_links1.int_node.port_buffers74 system.ruby.network.ext_links1.int_node.port_buffers75 system.ruby.network.ext_links1.int_node.port_buffers76 system.ruby.network.ext_links1.int_node.port_buffers77 system.ruby.network.ext_links1.int_node.port_buffers78 system.ruby.network.ext_links1.int_node.port_buffers79
+power_model=Null
 router_id=1
 virt_nets=10
 
@@ -2785,8 +3027,14 @@ weight=1
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 port_buffers36 port_buffers37 port_buffers38 port_buffers39 port_buffers40 port_buffers41 port_buffers42 port_buffers43 port_buffers44 port_buffers45 port_buffers46 port_buffers47 port_buffers48 port_buffers49 port_buffers50 port_buffers51 port_buffers52 port_buffers53 port_buffers54 port_buffers55 port_buffers56 port_buffers57 port_buffers58 port_buffers59 port_buffers60 port_buffers61 port_buffers62 port_buffers63 port_buffers64 port_buffers65 port_buffers66 port_buffers67 port_buffers68 port_buffers69 port_buffers70 port_buffers71 port_buffers72 port_buffers73 port_buffers74 port_buffers75 port_buffers76 port_buffers77 port_buffers78 port_buffers79
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 port_buffers=system.ruby.network.ext_links2.int_node.port_buffers00 system.ruby.network.ext_links2.int_node.port_buffers01 system.ruby.network.ext_links2.int_node.port_buffers02 system.ruby.network.ext_links2.int_node.port_buffers03 system.ruby.network.ext_links2.int_node.port_buffers04 system.ruby.network.ext_links2.int_node.port_buffers05 system.ruby.network.ext_links2.int_node.port_buffers06 system.ruby.network.ext_links2.int_node.port_buffers07 system.ruby.network.ext_links2.int_node.port_buffers08 system.ruby.network.ext_links2.int_node.port_buffers09 system.ruby.network.ext_links2.int_node.port_buffers10 system.ruby.network.ext_links2.int_node.port_buffers11 system.ruby.network.ext_links2.int_node.port_buffers12 system.ruby.network.ext_links2.int_node.port_buffers13 system.ruby.network.ext_links2.int_node.port_buffers14 system.ruby.network.ext_links2.int_node.port_buffers15 system.ruby.network.ext_links2.int_node.port_buffers16 system.ruby.network.ext_links2.int_node.port_buffers17 system.ruby.network.ext_links2.int_node.port_buffers18 system.ruby.network.ext_links2.int_node.port_buffers19 system.ruby.network.ext_links2.int_node.port_buffers20 system.ruby.network.ext_links2.int_node.port_buffers21 system.ruby.network.ext_links2.int_node.port_buffers22 system.ruby.network.ext_links2.int_node.port_buffers23 system.ruby.network.ext_links2.int_node.port_buffers24 system.ruby.network.ext_links2.int_node.port_buffers25 system.ruby.network.ext_links2.int_node.port_buffers26 system.ruby.network.ext_links2.int_node.port_buffers27 system.ruby.network.ext_links2.int_node.port_buffers28 system.ruby.network.ext_links2.int_node.port_buffers29 system.ruby.network.ext_links2.int_node.port_buffers30 system.ruby.network.ext_links2.int_node.port_buffers31 system.ruby.network.ext_links2.int_node.port_buffers32 system.ruby.network.ext_links2.int_node.port_buffers33 system.ruby.network.ext_links2.int_node.port_buffers34 system.ruby.network.ext_links2.int_node.port_buffers35 system.ruby.network.ext_links2.int_node.port_buffers36 system.ruby.network.ext_links2.int_node.port_buffers37 system.ruby.network.ext_links2.int_node.port_buffers38 system.ruby.network.ext_links2.int_node.port_buffers39 system.ruby.network.ext_links2.int_node.port_buffers40 system.ruby.network.ext_links2.int_node.port_buffers41 system.ruby.network.ext_links2.int_node.port_buffers42 system.ruby.network.ext_links2.int_node.port_buffers43 system.ruby.network.ext_links2.int_node.port_buffers44 system.ruby.network.ext_links2.int_node.port_buffers45 system.ruby.network.ext_links2.int_node.port_buffers46 system.ruby.network.ext_links2.int_node.port_buffers47 system.ruby.network.ext_links2.int_node.port_buffers48 system.ruby.network.ext_links2.int_node.port_buffers49 system.ruby.network.ext_links2.int_node.port_buffers50 system.ruby.network.ext_links2.int_node.port_buffers51 system.ruby.network.ext_links2.int_node.port_buffers52 system.ruby.network.ext_links2.int_node.port_buffers53 system.ruby.network.ext_links2.int_node.port_buffers54 system.ruby.network.ext_links2.int_node.port_buffers55 system.ruby.network.ext_links2.int_node.port_buffers56 system.ruby.network.ext_links2.int_node.port_buffers57 system.ruby.network.ext_links2.int_node.port_buffers58 system.ruby.network.ext_links2.int_node.port_buffers59 system.ruby.network.ext_links2.int_node.port_buffers60 system.ruby.network.ext_links2.int_node.port_buffers61 system.ruby.network.ext_links2.int_node.port_buffers62 system.ruby.network.ext_links2.int_node.port_buffers63 system.ruby.network.ext_links2.int_node.port_buffers64 system.ruby.network.ext_links2.int_node.port_buffers65 system.ruby.network.ext_links2.int_node.port_buffers66 system.ruby.network.ext_links2.int_node.port_buffers67 system.ruby.network.ext_links2.int_node.port_buffers68 system.ruby.network.ext_links2.int_node.port_buffers69 system.ruby.network.ext_links2.int_node.port_buffers70 system.ruby.network.ext_links2.int_node.port_buffers71 system.ruby.network.ext_links2.int_node.port_buffers72 system.ruby.network.ext_links2.int_node.port_buffers73 system.ruby.network.ext_links2.int_node.port_buffers74 system.ruby.network.ext_links2.int_node.port_buffers75 system.ruby.network.ext_links2.int_node.port_buffers76 system.ruby.network.ext_links2.int_node.port_buffers77 system.ruby.network.ext_links2.int_node.port_buffers78 system.ruby.network.ext_links2.int_node.port_buffers79
+power_model=Null
 router_id=2
 virt_nets=10
 
@@ -3670,24 +3918,332 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers40]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers41]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers42]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers43]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers44]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers45]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers46]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers47]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers48]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers49]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers50]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers51]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers52]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers53]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers54]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers55]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers56]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers57]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers58]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers59]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers60]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers61]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers62]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers63]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers64]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers65]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers66]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers67]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers68]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers69]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers70]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers71]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers72]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers73]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers74]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers75]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers76]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers77]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers78]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers79]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=512
+dst_inport=
+dst_node=system.ruby.network.ext_links1.int_node
 eventq_index=0
 latency=1
 link_id=0
-node_a=system.ruby.network.ext_links0.int_node
-node_b=system.ruby.network.ext_links1.int_node
+src_node=system.ruby.network.ext_links0.int_node
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=512
+dst_inport=
+dst_node=system.ruby.network.ext_links0.int_node
 eventq_index=0
 latency=1
 link_id=1
-node_a=system.ruby.network.ext_links0.int_node
-node_b=system.ruby.network.ext_links2.int_node
+src_node=system.ruby.network.ext_links1.int_node
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=512
+dst_inport=
+dst_node=system.ruby.network.ext_links2.int_node
+eventq_index=0
+latency=1
+link_id=2
+src_node=system.ruby.network.ext_links0.int_node
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=512
+dst_inport=
+dst_node=system.ruby.network.ext_links0.int_node
+eventq_index=0
+latency=1
+link_id=3
+src_node=system.ruby.network.ext_links2.int_node
+src_outport=
 weight=1
 
 [system.ruby.phys_mem]
@@ -3695,12 +4251,18 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.ruby.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=false
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
-range=0:536870911
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+range=0:536870911:0:0:0:0
 
 [system.sqc_cntrl0]
 type=SQC_Controller
@@ -3710,11 +4272,16 @@ TCC_select_num_bits=0
 buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=80
 l2_hit_latency=18
 mandatoryQueue=system.sqc_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 probeToSQC=system.sqc_cntrl0.probeToSQC
 recycle_latency=10
 requestFromSQC=system.sqc_cntrl0.requestFromSQC
@@ -3797,17 +4364,22 @@ coreid=99
 dcache=system.sqc_cntrl0.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.sqc_cntrl0.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=false
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=6
 slave=system.cpu1.CUs0.sqc_port system.cpu1.CUs1.sqc_port
@@ -3825,8 +4397,13 @@ type=TLBCoalescer
 children=clk_domain
 clk_domain=system.sqc_coalescer.clk_domain
 coalescingWindow=1
+default_p_state=UNDEFINED
 disableCoalescing=false
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 probesPerCycle=2
 master=system.sqc_tlb.slave[0]
 slave=system.cpu1.CUs0.sqc_tlb_port system.cpu1.CUs1.sqc_tlb_port
@@ -3852,11 +4429,16 @@ accessDistance=false
 allocationPolicy=true
 assoc=32
 clk_domain=system.sqc_tlb.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hitLatency=1
 maxOutstandingReqs=64
 missLatency1=5
 missLatency2=750
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 size=32
 master=system.l2_coalescer.slave[0]
 slave=system.sqc_coalescer.master[0]
@@ -3878,9 +4460,14 @@ voltage=1.000000
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -3897,10 +4484,15 @@ TCC_select_num_bits=0
 buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 l2_request_latency=1
 l2_response_latency=16
 number_of_TBEs=2048
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 recycle_latency=10
 responseFromTCC=system.tcc_cntrl0.responseFromTCC
 responseToTCC=system.tcc_cntrl0.responseToTCC
@@ -3992,11 +4584,16 @@ TCC_select_num_bits=0
 buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.tccdir_cntrl0.directory
 directory_latency=6
 eventq_index=0
 issue_latency=120
 number_of_TBEs=1024
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 probeFromNB=system.tccdir_cntrl0.probeFromNB
 probeToCore=system.tccdir_cntrl0.probeToCore
 recycle_latency=10
@@ -4141,11 +4738,16 @@ buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
 coalescer=system.tcp_cntrl0.coalescer
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=40
 l2_hit_latency=18
 mandatoryQueue=system.tcp_cntrl0.mandatoryQueue
 number_of_TBEs=2560
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 probeToTCP=system.tcp_cntrl0.probeToTCP
 recycle_latency=10
 requestFromTCP=system.tcp_cntrl0.requestFromTCP
@@ -4191,17 +4793,22 @@ coreid=99
 dcache=system.tcp_cntrl0.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl0.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=2048
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=false
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=2
 slave=system.cpu1.CUs0.memory_port[0] system.cpu1.CUs0.memory_port[1] system.cpu1.CUs0.memory_port[2] system.cpu1.CUs0.memory_port[3] system.cpu1.CUs0.memory_port[4] system.cpu1.CUs0.memory_port[5] system.cpu1.CUs0.memory_port[6] system.cpu1.CUs0.memory_port[7] system.cpu1.CUs0.memory_port[8] system.cpu1.CUs0.memory_port[9] system.cpu1.CUs0.memory_port[10] system.cpu1.CUs0.memory_port[11] system.cpu1.CUs0.memory_port[12] system.cpu1.CUs0.memory_port[13] system.cpu1.CUs0.memory_port[14] system.cpu1.CUs0.memory_port[15] system.cpu1.CUs0.memory_port[16] system.cpu1.CUs0.memory_port[17] system.cpu1.CUs0.memory_port[18] system.cpu1.CUs0.memory_port[19] system.cpu1.CUs0.memory_port[20] system.cpu1.CUs0.memory_port[21] system.cpu1.CUs0.memory_port[22] system.cpu1.CUs0.memory_port[23] system.cpu1.CUs0.memory_port[24] system.cpu1.CUs0.memory_port[25] system.cpu1.CUs0.memory_port[26] system.cpu1.CUs0.memory_port[27] system.cpu1.CUs0.memory_port[28] system.cpu1.CUs0.memory_port[29] system.cpu1.CUs0.memory_port[30] system.cpu1.CUs0.memory_port[31] system.cpu1.CUs0.memory_port[32] system.cpu1.CUs0.memory_port[33] system.cpu1.CUs0.memory_port[34] system.cpu1.CUs0.memory_port[35] system.cpu1.CUs0.memory_port[36] system.cpu1.CUs0.memory_port[37] system.cpu1.CUs0.memory_port[38] system.cpu1.CUs0.memory_port[39] system.cpu1.CUs0.memory_port[40] system.cpu1.CUs0.memory_port[41] system.cpu1.CUs0.memory_port[42] system.cpu1.CUs0.memory_port[43] system.cpu1.CUs0.memory_port[44] system.cpu1.CUs0.memory_port[45] system.cpu1.CUs0.memory_port[46] system.cpu1.CUs0.memory_port[47] system.cpu1.CUs0.memory_port[48] system.cpu1.CUs0.memory_port[49] system.cpu1.CUs0.memory_port[50] system.cpu1.CUs0.memory_port[51] system.cpu1.CUs0.memory_port[52] system.cpu1.CUs0.memory_port[53] system.cpu1.CUs0.memory_port[54] system.cpu1.CUs0.memory_port[55] system.cpu1.CUs0.memory_port[56] system.cpu1.CUs0.memory_port[57] system.cpu1.CUs0.memory_port[58] system.cpu1.CUs0.memory_port[59] system.cpu1.CUs0.memory_port[60] system.cpu1.CUs0.memory_port[61] system.cpu1.CUs0.memory_port[62] system.cpu1.CUs0.memory_port[63]
@@ -4252,17 +4859,22 @@ coreid=99
 dcache=system.tcp_cntrl0.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl0.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=3
 
@@ -4283,11 +4895,16 @@ buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
 coalescer=system.tcp_cntrl1.coalescer
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=40
 l2_hit_latency=18
 mandatoryQueue=system.tcp_cntrl1.mandatoryQueue
 number_of_TBEs=2560
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 probeToTCP=system.tcp_cntrl1.probeToTCP
 recycle_latency=10
 requestFromTCP=system.tcp_cntrl1.requestFromTCP
@@ -4333,17 +4950,22 @@ coreid=99
 dcache=system.tcp_cntrl1.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl1.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=2048
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=false
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=4
 slave=system.cpu1.CUs1.memory_port[0] system.cpu1.CUs1.memory_port[1] system.cpu1.CUs1.memory_port[2] system.cpu1.CUs1.memory_port[3] system.cpu1.CUs1.memory_port[4] system.cpu1.CUs1.memory_port[5] system.cpu1.CUs1.memory_port[6] system.cpu1.CUs1.memory_port[7] system.cpu1.CUs1.memory_port[8] system.cpu1.CUs1.memory_port[9] system.cpu1.CUs1.memory_port[10] system.cpu1.CUs1.memory_port[11] system.cpu1.CUs1.memory_port[12] system.cpu1.CUs1.memory_port[13] system.cpu1.CUs1.memory_port[14] system.cpu1.CUs1.memory_port[15] system.cpu1.CUs1.memory_port[16] system.cpu1.CUs1.memory_port[17] system.cpu1.CUs1.memory_port[18] system.cpu1.CUs1.memory_port[19] system.cpu1.CUs1.memory_port[20] system.cpu1.CUs1.memory_port[21] system.cpu1.CUs1.memory_port[22] system.cpu1.CUs1.memory_port[23] system.cpu1.CUs1.memory_port[24] system.cpu1.CUs1.memory_port[25] system.cpu1.CUs1.memory_port[26] system.cpu1.CUs1.memory_port[27] system.cpu1.CUs1.memory_port[28] system.cpu1.CUs1.memory_port[29] system.cpu1.CUs1.memory_port[30] system.cpu1.CUs1.memory_port[31] system.cpu1.CUs1.memory_port[32] system.cpu1.CUs1.memory_port[33] system.cpu1.CUs1.memory_port[34] system.cpu1.CUs1.memory_port[35] system.cpu1.CUs1.memory_port[36] system.cpu1.CUs1.memory_port[37] system.cpu1.CUs1.memory_port[38] system.cpu1.CUs1.memory_port[39] system.cpu1.CUs1.memory_port[40] system.cpu1.CUs1.memory_port[41] system.cpu1.CUs1.memory_port[42] system.cpu1.CUs1.memory_port[43] system.cpu1.CUs1.memory_port[44] system.cpu1.CUs1.memory_port[45] system.cpu1.CUs1.memory_port[46] system.cpu1.CUs1.memory_port[47] system.cpu1.CUs1.memory_port[48] system.cpu1.CUs1.memory_port[49] system.cpu1.CUs1.memory_port[50] system.cpu1.CUs1.memory_port[51] system.cpu1.CUs1.memory_port[52] system.cpu1.CUs1.memory_port[53] system.cpu1.CUs1.memory_port[54] system.cpu1.CUs1.memory_port[55] system.cpu1.CUs1.memory_port[56] system.cpu1.CUs1.memory_port[57] system.cpu1.CUs1.memory_port[58] system.cpu1.CUs1.memory_port[59] system.cpu1.CUs1.memory_port[60] system.cpu1.CUs1.memory_port[61] system.cpu1.CUs1.memory_port[62] system.cpu1.CUs1.memory_port[63]
@@ -4394,17 +5016,22 @@ coreid=99
 dcache=system.tcp_cntrl1.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl1.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=5
 
diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr
index 1e2b8911e..4afc5c233 100755
--- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr
+++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr
@@ -2,4 +2,5 @@ warn: system.ruby.network adopting orphan SimObject param 'int_links'
 warn: system.ruby.network adopting orphan SimObject param 'ext_links'
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout
index 62281f3ae..c30fce800 100755
--- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout
+++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO/simout
+Redirecting stderr to build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 10 2016 12:22:56
-gem5 started Mar 10 2016 12:23:20
-gem5 executing on phenom, pid 9635
-command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO
+gem5 compiled Oct 13 2016 21:24:38
+gem5 started Oct 13 2016 21:24:54
+gem5 executing on e108600-lin, pid 29892
+command line: /work/curdun01/gem5-external.hg/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO
 
-Using GPU kernel code file(s) /home/stever/hg/m5sim.org/gem5/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
+Using GPU kernel code file(s) /arm/projectscratch/randd/systems/dist/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
 Global frequency set at 1000000000000 ticks per second
 Forcing maxCoalescedReqs to 32 (TLB assoc.) 
 Forcing maxCoalescedReqs to 32 (TLB assoc.) 
@@ -18,4 +20,4 @@ info: Entering event queue @ 0.  Starting simulation...
 keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23
 the gpu says:
 elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe
-Exiting @ tick 663454500 because target called exit()
+Exiting @ tick 668137500 because target called exit()
diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt
index bde6c8cac..be5cb8048 100644
--- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt
+++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt
@@ -1,27 +1,27 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000663                       # Number of seconds simulated
-sim_ticks                                   663454500                       # Number of ticks simulated
-final_tick                                  663454500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000668                       # Number of seconds simulated
+sim_ticks                                   668137500                       # Number of ticks simulated
+final_tick                                  668137500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 237471                       # Simulator instruction rate (inst/s)
-host_op_rate                                   488329                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2352682974                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1358064                       # Number of bytes of host memory used
-host_seconds                                     0.28                       # Real time elapsed on the host
+host_inst_rate                                 112893                       # Simulator instruction rate (inst/s)
+host_op_rate                                   232149                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1126339333                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1312868                       # Number of bytes of host memory used
+host_seconds                                     0.59                       # Real time elapsed on the host
 sim_insts                                       66963                       # Number of instructions simulated
 sim_ops                                        137705                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.mem_ctrls.bytes_read::dir_cntrl0         99264                       # Number of bytes read from this memory
 system.mem_ctrls.bytes_read::total              99264                       # Number of bytes read from this memory
 system.mem_ctrls.num_reads::dir_cntrl0           1551                       # Number of read requests responded to by this memory
 system.mem_ctrls.num_reads::total                1551                       # Number of read requests responded to by this memory
-system.mem_ctrls.bw_read::dir_cntrl0        149616892                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             149616892                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::dir_cntrl0       149616892                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total            149616892                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::dir_cntrl0        148568221                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             148568221                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::dir_cntrl0       148568221                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total            148568221                       # Total bandwidth to/from this memory (bytes/s)
 system.mem_ctrls.readReqs                        1551                       # Number of read requests accepted
 system.mem_ctrls.writeReqs                          0                       # Number of write requests accepted
 system.mem_ctrls.readBursts                      1551                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -68,7 +68,7 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                     663221000                       # Total gap between requests
+system.mem_ctrls.totGap                     667904000                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
@@ -87,10 +87,10 @@ system.mem_ctrls.rdQLenPdf::0                    1542                       # Wh
 system.mem_ctrls.rdQLenPdf::1                       2                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       1                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       1                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4                       2                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5                       2                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6                       1                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::4                       1                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::5                       1                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::6                       2                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::7                       1                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
@@ -179,33 +179,33 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          485                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    204.008247                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   145.772769                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   192.306659                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127          178     36.70%     36.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255          156     32.16%     68.87% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           70     14.43%     83.30% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           40      8.25%     91.55% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           15      3.09%     94.64% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767           10      2.06%     96.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            9      1.86%     98.56% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples          484                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    203.636364                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   145.087483                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   194.740960                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127          177     36.57%     36.57% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255          167     34.50%     71.07% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           64     13.22%     84.30% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           29      5.99%     90.29% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639           20      4.13%     94.42% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767           10      2.07%     96.49% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895           10      2.07%     98.55% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::896-1023            2      0.41%     98.97% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::1024-1151            5      1.03%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          485                       # Bytes accessed per row activation
-system.mem_ctrls.totQLat                     15500495                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                44581745                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.bytesPerActivate::total          484                       # Bytes accessed per row activation
+system.mem_ctrls.totQLat                     31097995                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                60179245                       # Total ticks spent from burst creation until serviced by the DRAM
 system.mem_ctrls.totBusLat                    7755000                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                      9993.87                       # Average queueing delay per DRAM burst
+system.mem_ctrls.avgQLat                     20050.29                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                28743.87                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       149.62                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                38800.29                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       148.57                       # Average DRAM read bandwidth in MiByte/s
 system.mem_ctrls.avgWrBW                         0.00                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    149.62                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    148.57                       # Average system read bandwidth in MiByte/s
 system.mem_ctrls.avgWrBWSys                      0.00                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         1.17                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     1.17                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtil                         1.16                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     1.16                       # Data bus utilization in percentage for reads
 system.mem_ctrls.busUtilWrite                    0.00                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
 system.mem_ctrls.avgWrQLen                       0.00                       # Average write queue length when enqueuing
@@ -213,38 +213,48 @@ system.mem_ctrls.readRowHits                     1062                       # Nu
 system.mem_ctrls.writeRowHits                       0                       # Number of row buffer hits during writes
 system.mem_ctrls.readRowHitRate                 68.47                       # Row buffer hit rate for reads
 system.mem_ctrls.writeRowHitRate                  nan                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                     427608.64                       # Average gap between requests
+system.mem_ctrls.avgGap                     430627.98                       # Average gap between requests
 system.mem_ctrls.pageHitRate                    68.47                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                  1391040                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   759000                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 5335200                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.actEnergy                  1320900                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   694485                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 4890900                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy             43227600                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy            335485755                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy            102969000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy              489167595                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            738.822020                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE    170399250                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF      22100000                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT     470741750                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                  2275560                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                  1241625                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 6723600                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         51629760.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             18618480                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy              1670400                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy       210199470                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy        42511680                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy         15622140                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy              347158215                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            519.590975                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime            622801252                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE      2030000                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF      21876000                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF     51287000                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN    110705750                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT      21255248                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN    460983502                       # Time in different power states
+system.mem_ctrls_1.actEnergy                  2170560                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                  1142295                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 6183240                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy             43227600                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy            371983995                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy             70953000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy              496405380                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            749.753724                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE    115859750                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF      22100000                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT     524145250                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_1.refreshEnergy         52244400.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             21589320                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              1299360                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy       243172830                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy        28283040                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy          3067740                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy              359152785                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            537.543223                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime            616852750                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE       980000                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF      22106000                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF     10481250                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN     73643500                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT      27629000                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN    533297750                       # Time in different power states
 system.ruby.clk_domain.clock                      500                       # Clock period in ticks
-system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.ruby.phys_mem.bytes_read::cpu0.inst       696760                       # Number of bytes read from this memory
 system.ruby.phys_mem.bytes_read::cpu0.data       119832                       # Number of bytes read from this memory
 system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit         3280                       # Number of bytes read from this memory
@@ -267,26 +277,26 @@ system.ruby.phys_mem.num_writes::cpu0.data        10422                       #
 system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit          256                       # Number of write requests responded to by this memory
 system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit          256                       # Number of write requests responded to by this memory
 system.ruby.phys_mem.num_writes::total          10934                       # Number of write requests responded to by this memory
-system.ruby.phys_mem.bw_read::cpu0.inst    1050200127                       # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu0.data     180618264                       # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit      4943821                       # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit      4943821                       # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::total        1240706032                       # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu0.inst   1050200127                       # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit      3014525                       # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit      3014525                       # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::total   1056229176                       # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu0.data    109678961                       # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit       385859                       # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit       385859                       # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::total        110450679                       # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu0.inst   1050200127                       # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu0.data    290297225                       # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit      5329680                       # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit      5329680                       # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::total       1351156711                       # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.ruby.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.ruby.phys_mem.bw_read::cpu0.inst    1042839236                       # Total read bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_read::cpu0.data     179352304                       # Total read bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit      4909169                       # Total read bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit      4909169                       # Total read bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_read::total        1232009878                       # Total read bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_inst_read::cpu0.inst   1042839236                       # Instruction read bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit      2993396                       # Instruction read bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit      2993396                       # Instruction read bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_inst_read::total   1048826028                       # Instruction read bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_write::cpu0.data    108910217                       # Write bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit       383155                       # Write bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit       383155                       # Write bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_write::total        109676526                       # Write bandwidth from this memory (bytes/s)
+system.ruby.phys_mem.bw_total::cpu0.inst   1042839236                       # Total bandwidth to/from this memory (bytes/s)
+system.ruby.phys_mem.bw_total::cpu0.data    288262521                       # Total bandwidth to/from this memory (bytes/s)
+system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit      5292324                       # Total bandwidth to/from this memory (bytes/s)
+system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit      5292324                       # Total bandwidth to/from this memory (bytes/s)
+system.ruby.phys_mem.bw_total::total       1341686404                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.ruby.outstanding_req_hist_seqr::bucket_size            1                      
 system.ruby.outstanding_req_hist_seqr::max_bucket            9                      
 system.ruby.outstanding_req_hist_seqr::samples       114203                      
@@ -306,26 +316,26 @@ system.ruby.outstanding_req_hist_coalsr::total           27
 system.ruby.latency_hist_seqr::bucket_size           64                      
 system.ruby.latency_hist_seqr::max_bucket          639                      
 system.ruby.latency_hist_seqr::samples         114203                      
-system.ruby.latency_hist_seqr::mean          4.784165                      
-system.ruby.latency_hist_seqr::gmean         2.131364                      
-system.ruby.latency_hist_seqr::stdev        23.846473                      
-system.ruby.latency_hist_seqr            |      112668     98.66%     98.66% |           0      0.00%     98.66% |           0      0.00%     98.66% |        1506      1.32%     99.97% |          19      0.02%     99.99% |          10      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean          4.823332                      
+system.ruby.latency_hist_seqr::gmean         2.131609                      
+system.ruby.latency_hist_seqr::stdev        24.449444                      
+system.ruby.latency_hist_seqr            |      112668     98.66%     98.66% |           0      0.00%     98.66% |           0      0.00%     98.66% |        1490      1.30%     99.96% |          18      0.02%     99.98% |          18      0.02%     99.99% |           2      0.00%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           7      0.01%    100.00%
 system.ruby.latency_hist_seqr::total           114203                      
 system.ruby.latency_hist_coalsr::bucket_size           64                      
 system.ruby.latency_hist_coalsr::max_bucket          639                      
 system.ruby.latency_hist_coalsr::samples           27                      
-system.ruby.latency_hist_coalsr::mean      141.296296                      
-system.ruby.latency_hist_coalsr::gmean      21.202698                      
-system.ruby.latency_hist_coalsr::stdev     140.217089                      
-system.ruby.latency_hist_coalsr          |          13     48.15%     48.15% |           0      0.00%     48.15% |           0      0.00%     48.15% |          10     37.04%     85.19% |           1      3.70%     88.89% |           3     11.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_coalsr::mean             171                      
+system.ruby.latency_hist_coalsr::gmean      22.942606                      
+system.ruby.latency_hist_coalsr::stdev     184.818206                      
+system.ruby.latency_hist_coalsr          |          13     48.15%     48.15% |           0      0.00%     48.15% |           0      0.00%     48.15% |           7     25.93%     74.07% |           2      7.41%     81.48% |           1      3.70%     85.19% |           1      3.70%     88.89% |           1      3.70%     92.59% |           2      7.41%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist_coalsr::total             27                      
 system.ruby.hit_latency_hist_seqr::bucket_size           64                      
 system.ruby.hit_latency_hist_seqr::max_bucket          639                      
 system.ruby.hit_latency_hist_seqr::samples         1535                      
-system.ruby.hit_latency_hist_seqr::mean    208.448208                      
-system.ruby.hit_latency_hist_seqr::gmean   208.002202                      
-system.ruby.hit_latency_hist_seqr::stdev    15.833423                      
-system.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1506     98.11%     98.11% |          19      1.24%     99.35% |          10      0.65%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist_seqr::mean    211.362215                      
+system.ruby.hit_latency_hist_seqr::gmean   209.793806                      
+system.ruby.hit_latency_hist_seqr::stdev    34.965177                      
+system.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1490     97.07%     97.07% |          18      1.17%     98.24% |          18      1.17%     99.41% |           2      0.13%     99.54% |           0      0.00%     99.54% |           0      0.00%     99.54% |           7      0.46%    100.00%
 system.ruby.hit_latency_hist_seqr::total         1535                      
 system.ruby.miss_latency_hist_seqr::bucket_size            4                      
 system.ruby.miss_latency_hist_seqr::max_bucket           39                      
@@ -338,10 +348,10 @@ system.ruby.miss_latency_hist_seqr::total       112668
 system.ruby.miss_latency_hist_coalsr::bucket_size           64                      
 system.ruby.miss_latency_hist_coalsr::max_bucket          639                      
 system.ruby.miss_latency_hist_coalsr::samples           27                      
-system.ruby.miss_latency_hist_coalsr::mean   141.296296                      
-system.ruby.miss_latency_hist_coalsr::gmean    21.202698                      
-system.ruby.miss_latency_hist_coalsr::stdev   140.217089                      
-system.ruby.miss_latency_hist_coalsr     |          13     48.15%     48.15% |           0      0.00%     48.15% |           0      0.00%     48.15% |          10     37.04%     85.19% |           1      3.70%     88.89% |           3     11.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_coalsr::mean          171                      
+system.ruby.miss_latency_hist_coalsr::gmean    22.942606                      
+system.ruby.miss_latency_hist_coalsr::stdev   184.818206                      
+system.ruby.miss_latency_hist_coalsr     |          13     48.15%     48.15% |           0      0.00%     48.15% |           0      0.00%     48.15% |           7     25.93%     74.07% |           2      7.41%     81.48% |           1      3.70%     85.19% |           1      3.70%     88.89% |           1      3.70%     92.59% |           2      7.41%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist_coalsr::total           27                      
 system.ruby.L1Cache.incomplete_times_seqr       112609                      
 system.ruby.L2Cache.incomplete_times_seqr           59                      
@@ -369,25 +379,25 @@ system.cp_cntrl0.L2cache.num_data_array_reads          120
 system.cp_cntrl0.L2cache.num_data_array_writes        11982                       # number of data array writes
 system.cp_cntrl0.L2cache.num_tag_array_reads        12059                       # number of tag array reads
 system.cp_cntrl0.L2cache.num_tag_array_writes         1649                       # number of tag array writes
-system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.cpu0.clk_domain.clock                      500                       # Clock period in ticks
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.cpu0.workload.num_syscalls                  21                       # Number of system calls
 system.cpu0.numPwrStateTransitions                  2                       # Number of power state transitions
 system.cpu0.pwrStateClkGateDist::samples            1                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean         2615501                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean         2825501                       # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::1000-5e+10            1    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value      2615501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value      2615501                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value      2825501                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value      2825501                       # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::total              1                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON      660838999                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED      2615501                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                         1326909                       # number of cpu cycles simulated
+system.cpu0.pwrStateResidencyTicks::ON      665311999                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED      2825501                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                         1336275                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.committedInsts                      66963                       # Number of instructions committed
@@ -407,10 +417,10 @@ system.cpu0.num_cc_register_writes              42183                       # nu
 system.cpu0.num_mem_refs                        27198                       # number of memory refs
 system.cpu0.num_load_insts                      16684                       # Number of load instructions
 system.cpu0.num_store_insts                     10514                       # Number of store instructions
-system.cpu0.num_idle_cycles               5231.003992                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1321677.996008                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.996058                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.003942                       # Percentage of idle cycles
+system.cpu0.num_idle_cycles               5651.003992                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1330623.996008                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.995771                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.004229                       # Percentage of idle cycles
 system.cpu0.Branches                            16199                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                  615      0.45%      0.45% # Class of executed instruction
 system.cpu0.op_class::IntAlu                   108791     79.00%     79.45% # Class of executed instruction
@@ -449,10 +459,10 @@ system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Cl
 system.cpu0.op_class::total                    137705                       # Class of executed instruction
 system.cpu1.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.cpu1.clk_domain.clock                     1000                       # Clock period in ticks
-system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
 system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies          307                       # number of times the wf's instructions are blocked due to RAW dependencies
+system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies          498                       # number of times the wf's instructions are blocked due to RAW dependencies
 system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples           39                       # number of executed instructions with N source register operands
 system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean     0.794872                       # number of executed instructions with N source register operands
 system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev     0.863880                       # number of executed instructions with N source register operands
@@ -644,7 +654,7 @@ system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value            0
 system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
 system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
 system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies          279                       # number of times the wf's instructions are blocked due to RAW dependencies
+system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies          470                       # number of times the wf's instructions are blocked due to RAW dependencies
 system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
 system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
 system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
@@ -836,7 +846,7 @@ system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value            0
 system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
 system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
 system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies          282                       # number of times the wf's instructions are blocked due to RAW dependencies
+system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies          473                       # number of times the wf's instructions are blocked due to RAW dependencies
 system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
 system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
 system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
@@ -1028,7 +1038,7 @@ system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value            0
 system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
 system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
 system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies          276                       # number of times the wf's instructions are blocked due to RAW dependencies
+system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies          467                       # number of times the wf's instructions are blocked due to RAW dependencies
 system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
 system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
 system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
@@ -1218,7 +1228,7 @@ system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows            0
 system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
 system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
 system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
-system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples           43                       # For each instruction fetch request recieved record how many instructions you got from it
 system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean     5.813953                       # For each instruction fetch request recieved record how many instructions you got from it
 system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev     2.683777                       # For each instruction fetch request recieved record how many instructions you got from it
@@ -1259,7 +1269,7 @@ system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows            0
 system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value            2                       # For each instruction fetch request recieved record how many instructions you got from it
 system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value            8                       # For each instruction fetch request recieved record how many instructions you got from it
 system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total           43                       # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue         3261                       # number of cycles the CU issues nothing
+system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue         3471                       # number of cycles the CU issues nothing
 system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued           99                       # number of cycles the CU issued at least one instruction
 system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0           30                       # Number of cycles at least one instruction of specific type issued
 system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1           29                       # Number of cycles at least one instruction of specific type issued
@@ -1267,19 +1277,19 @@ system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2           29
 system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3           29                       # Number of cycles at least one instruction of specific type issued
 system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM           18                       # Number of cycles at least one instruction of specific type issued
 system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM            6                       # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0          769                       # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1          357                       # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2          375                       # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3          332                       # Number of cycles no instruction of specific type issued
+system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0          970                       # Number of cycles no instruction of specific type issued
+system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1          548                       # Number of cycles no instruction of specific type issued
+system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2          566                       # Number of cycles no instruction of specific type issued
+system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3          523                       # Number of cycles no instruction of specific type issued
 system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM          398                       # Number of cycles no instruction of specific type issued
 system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM           22                       # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.spc::samples          3360                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::mean         0.041964                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::stdev        0.257708                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs0.ExecStage.spc::samples          3570                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs0.ExecStage.spc::mean         0.039496                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs0.ExecStage.spc::stdev        0.250206                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs0.ExecStage.spc::underflows            0      0.00%      0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::0                3261     97.05%     97.05% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::1                  59      1.76%     98.81% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::2                  38      1.13%     99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs0.ExecStage.spc::0                3471     97.23%     97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs0.ExecStage.spc::1                  59      1.65%     98.88% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs0.ExecStage.spc::2                  38      1.06%     99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs0.ExecStage.spc::3                   2      0.06%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs0.ExecStage.spc::4                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs0.ExecStage.spc::5                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
@@ -1287,11 +1297,11 @@ system.cpu1.CUs0.ExecStage.spc::6                   0      0.00%    100.00% # Ex
 system.cpu1.CUs0.ExecStage.spc::overflows            0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs0.ExecStage.spc::min_value            0                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs0.ExecStage.spc::max_value            3                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::total            3360                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs0.ExecStage.spc::total            3570                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle           93                       # number of CU transitions from active to idle
 system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples           93                       # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean    34.967742                       # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev   149.478110                       # duration of idle periods in cycles
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean    37.225806                       # duration of idle periods in cycles
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev   154.644552                       # duration of idle periods in cycles
 system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows            0      0.00%      0.00% # duration of idle periods in cycles
 system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4           74     79.57%     79.57% # duration of idle periods in cycles
 system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9            7      7.53%     87.10% # duration of idle periods in cycles
@@ -1311,13 +1321,13 @@ system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74            0      0.00
 system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75            0      0.00%     92.47% # duration of idle periods in cycles
 system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows            7      7.53%    100.00% # duration of idle periods in cycles
 system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value            1                       # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value         1285                       # duration of idle periods in cycles
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value         1291                       # duration of idle periods in cycles
 system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total           93                       # duration of idle periods in cycles
 system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles            0                       # total number of cycles GM data are delayed before updating the VRF
 system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles            0                       # total number of cycles LDS data are delayed before updating the VRF
 system.cpu1.CUs0.tlb_requests                     769                       # number of uncoalesced requests
-system.cpu1.CUs0.tlb_cycles              -452453001000                       # total number of cycles for all uncoalesced requests
-system.cpu1.CUs0.avg_translation_latency -588365410.923277                       # Avg. translation latency for data translations
+system.cpu1.CUs0.tlb_cycles              -455223738000                       # total number of cycles for all uncoalesced requests
+system.cpu1.CUs0.avg_translation_latency -591968449.934981                       # Avg. translation latency for data translations
 system.cpu1.CUs0.TLB_hits_distribution::page_table          769                       # TLB hits distribution (0 for page table, x for Lx-TLB
 system.cpu1.CUs0.TLB_hits_distribution::L1_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
 system.cpu1.CUs0.TLB_hits_distribution::L2_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
@@ -1393,8 +1403,8 @@ system.cpu1.CUs0.local_mem_instr_cnt                6                       # dy
 system.cpu1.CUs0.wg_blocked_due_lds_alloc            0                       # Workgroup blocked due to LDS capacity
 system.cpu1.CUs0.num_instr_executed               141                       # number of instructions executed
 system.cpu1.CUs0.inst_exec_rate::samples          141                       # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::mean       86.382979                       # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::stdev     229.706697                       # Instruction Execution Rate: Number of executed vector instructions per cycle
+system.cpu1.CUs0.inst_exec_rate::mean       92.127660                       # Instruction Execution Rate: Number of executed vector instructions per cycle
+system.cpu1.CUs0.inst_exec_rate::stdev     237.147810                       # Instruction Execution Rate: Number of executed vector instructions per cycle
 system.cpu1.CUs0.inst_exec_rate::underflows            0      0.00%      0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
 system.cpu1.CUs0.inst_exec_rate::0-1                0      0.00%      0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
 system.cpu1.CUs0.inst_exec_rate::2-3               12      8.51%      8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle
@@ -1404,12 +1414,12 @@ system.cpu1.CUs0.inst_exec_rate::8-9                3      2.13%     69.50% # In
 system.cpu1.CUs0.inst_exec_rate::10                 3      2.13%     71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
 system.cpu1.CUs0.inst_exec_rate::overflows           40     28.37%    100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
 system.cpu1.CUs0.inst_exec_rate::min_value            2                       # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::max_value         1291                       # Instruction Execution Rate: Number of executed vector instructions per cycle
+system.cpu1.CUs0.inst_exec_rate::max_value         1297                       # Instruction Execution Rate: Number of executed vector instructions per cycle
 system.cpu1.CUs0.inst_exec_rate::total            141                       # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.num_vec_ops_executed            6769                       # number of vec ops executed (e.g. VSZ/inst)
-system.cpu1.CUs0.num_total_cycles                3360                       # number of cycles the CU ran for
-system.cpu1.CUs0.vpc                         2.014583                       # Vector Operations per cycle (this CU only)
-system.cpu1.CUs0.ipc                         0.041964                       # Instructions per cycle (this CU only)
+system.cpu1.CUs0.num_vec_ops_executed            6769                       # number of vec ops executed (e.g. WF size/inst)
+system.cpu1.CUs0.num_total_cycles                3570                       # number of cycles the CU ran for
+system.cpu1.CUs0.vpc                         1.896078                       # Vector Operations per cycle (this CU only)
+system.cpu1.CUs0.ipc                         0.039496                       # Instructions per cycle (this CU only)
 system.cpu1.CUs0.warp_execution_dist::samples          141                       # number of lanes active per instruction (oval all instructions)
 system.cpu1.CUs0.warp_execution_dist::mean    48.007092                       # number of lanes active per instruction (oval all instructions)
 system.cpu1.CUs0.warp_execution_dist::stdev    23.719942                       # number of lanes active per instruction (oval all instructions)
@@ -1487,10 +1497,10 @@ system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc            0
 system.cpu1.CUs0.num_CAS_ops                        0                       # number of compare and swap operations
 system.cpu1.CUs0.num_failed_CAS_ops                 0                       # number of compare and swap operations that failed
 system.cpu1.CUs0.num_completed_wfs                  4                       # number of completed wavefronts
-system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
 system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies          401                       # number of times the wf's instructions are blocked due to RAW dependencies
+system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies          591                       # number of times the wf's instructions are blocked due to RAW dependencies
 system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples           39                       # number of executed instructions with N source register operands
 system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean     0.794872                       # number of executed instructions with N source register operands
 system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev     0.863880                       # number of executed instructions with N source register operands
@@ -1682,7 +1692,7 @@ system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value            0
 system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
 system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
 system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies          372                       # number of times the wf's instructions are blocked due to RAW dependencies
+system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies          562                       # number of times the wf's instructions are blocked due to RAW dependencies
 system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
 system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
 system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
@@ -1874,7 +1884,7 @@ system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value            0
 system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
 system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
 system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies          371                       # number of times the wf's instructions are blocked due to RAW dependencies
+system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies          561                       # number of times the wf's instructions are blocked due to RAW dependencies
 system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
 system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
 system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
@@ -2066,7 +2076,7 @@ system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value            0
 system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
 system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
 system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies          361                       # number of times the wf's instructions are blocked due to RAW dependencies
+system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies          551                       # number of times the wf's instructions are blocked due to RAW dependencies
 system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
 system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
 system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
@@ -2256,7 +2266,7 @@ system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows            0
 system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
 system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
 system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
-system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples           43                       # For each instruction fetch request recieved record how many instructions you got from it
 system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean     5.813953                       # For each instruction fetch request recieved record how many instructions you got from it
 system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev     2.683777                       # For each instruction fetch request recieved record how many instructions you got from it
@@ -2297,7 +2307,7 @@ system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows            0
 system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value            2                       # For each instruction fetch request recieved record how many instructions you got from it
 system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value            8                       # For each instruction fetch request recieved record how many instructions you got from it
 system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total           43                       # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue         3261                       # number of cycles the CU issues nothing
+system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue         3471                       # number of cycles the CU issues nothing
 system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued           99                       # number of cycles the CU issued at least one instruction
 system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0           30                       # Number of cycles at least one instruction of specific type issued
 system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1           29                       # Number of cycles at least one instruction of specific type issued
@@ -2305,19 +2315,19 @@ system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2           29
 system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3           29                       # Number of cycles at least one instruction of specific type issued
 system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM           18                       # Number of cycles at least one instruction of specific type issued
 system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM            6                       # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0          777                       # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1          472                       # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2          444                       # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3          416                       # Number of cycles no instruction of specific type issued
+system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0          973                       # Number of cycles no instruction of specific type issued
+system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1          662                       # Number of cycles no instruction of specific type issued
+system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2          634                       # Number of cycles no instruction of specific type issued
+system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3          606                       # Number of cycles no instruction of specific type issued
 system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM          404                       # Number of cycles no instruction of specific type issued
 system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM           22                       # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.spc::samples          3360                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::mean         0.041964                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::stdev        0.256550                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs1.ExecStage.spc::samples          3570                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs1.ExecStage.spc::mean         0.039496                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs1.ExecStage.spc::stdev        0.249084                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs1.ExecStage.spc::underflows            0      0.00%      0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::0                3261     97.05%     97.05% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::1                  58      1.73%     98.78% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::2                  40      1.19%     99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs1.ExecStage.spc::0                3471     97.23%     97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs1.ExecStage.spc::1                  58      1.62%     98.85% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs1.ExecStage.spc::2                  40      1.12%     99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs1.ExecStage.spc::3                   1      0.03%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs1.ExecStage.spc::4                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs1.ExecStage.spc::5                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
@@ -2325,11 +2335,11 @@ system.cpu1.CUs1.ExecStage.spc::6                   0      0.00%    100.00% # Ex
 system.cpu1.CUs1.ExecStage.spc::overflows            0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs1.ExecStage.spc::min_value            0                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs1.ExecStage.spc::max_value            3                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::total            3360                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
+system.cpu1.CUs1.ExecStage.spc::total            3570                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
 system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle           94                       # number of CU transitions from active to idle
 system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples           94                       # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean    33.585106                       # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev   147.747562                       # duration of idle periods in cycles
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean    35.776596                       # duration of idle periods in cycles
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev   153.908027                       # duration of idle periods in cycles
 system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows            0      0.00%      0.00% # duration of idle periods in cycles
 system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4           75     79.79%     79.79% # duration of idle periods in cycles
 system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9            8      8.51%     88.30% # duration of idle periods in cycles
@@ -2349,13 +2359,13 @@ system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74            0      0.00
 system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75            0      0.00%     92.55% # duration of idle periods in cycles
 system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows            7      7.45%    100.00% # duration of idle periods in cycles
 system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value            1                       # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value         1293                       # duration of idle periods in cycles
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value         1299                       # duration of idle periods in cycles
 system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total           94                       # duration of idle periods in cycles
 system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles            0                       # total number of cycles GM data are delayed before updating the VRF
 system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles            0                       # total number of cycles LDS data are delayed before updating the VRF
 system.cpu1.CUs1.tlb_requests                     769                       # number of uncoalesced requests
-system.cpu1.CUs1.tlb_cycles              -452459838000                       # total number of cycles for all uncoalesced requests
-system.cpu1.CUs1.avg_translation_latency -588374301.690507                       # Avg. translation latency for data translations
+system.cpu1.CUs1.tlb_cycles              -455230572000                       # total number of cycles for all uncoalesced requests
+system.cpu1.CUs1.avg_translation_latency -591977336.801040                       # Avg. translation latency for data translations
 system.cpu1.CUs1.TLB_hits_distribution::page_table          769                       # TLB hits distribution (0 for page table, x for Lx-TLB
 system.cpu1.CUs1.TLB_hits_distribution::L1_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
 system.cpu1.CUs1.TLB_hits_distribution::L2_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
@@ -2431,8 +2441,8 @@ system.cpu1.CUs1.local_mem_instr_cnt                6                       # dy
 system.cpu1.CUs1.wg_blocked_due_lds_alloc            0                       # Workgroup blocked due to LDS capacity
 system.cpu1.CUs1.num_instr_executed               141                       # number of instructions executed
 system.cpu1.CUs1.inst_exec_rate::samples          141                       # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::mean       85.553191                       # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::stdev     230.829913                       # Instruction Execution Rate: Number of executed vector instructions per cycle
+system.cpu1.CUs1.inst_exec_rate::mean       91.269504                       # Instruction Execution Rate: Number of executed vector instructions per cycle
+system.cpu1.CUs1.inst_exec_rate::stdev     240.230451                       # Instruction Execution Rate: Number of executed vector instructions per cycle
 system.cpu1.CUs1.inst_exec_rate::underflows            0      0.00%      0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
 system.cpu1.CUs1.inst_exec_rate::0-1                0      0.00%      0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
 system.cpu1.CUs1.inst_exec_rate::2-3               13      9.22%      9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
@@ -2442,12 +2452,12 @@ system.cpu1.CUs1.inst_exec_rate::8-9                6      4.26%     73.76% # In
 system.cpu1.CUs1.inst_exec_rate::10                 0      0.00%     73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle
 system.cpu1.CUs1.inst_exec_rate::overflows           37     26.24%    100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
 system.cpu1.CUs1.inst_exec_rate::min_value            2                       # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::max_value         1299                       # Instruction Execution Rate: Number of executed vector instructions per cycle
+system.cpu1.CUs1.inst_exec_rate::max_value         1305                       # Instruction Execution Rate: Number of executed vector instructions per cycle
 system.cpu1.CUs1.inst_exec_rate::total            141                       # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.num_vec_ops_executed            6762                       # number of vec ops executed (e.g. VSZ/inst)
-system.cpu1.CUs1.num_total_cycles                3360                       # number of cycles the CU ran for
-system.cpu1.CUs1.vpc                         2.012500                       # Vector Operations per cycle (this CU only)
-system.cpu1.CUs1.ipc                         0.041964                       # Instructions per cycle (this CU only)
+system.cpu1.CUs1.num_vec_ops_executed            6762                       # number of vec ops executed (e.g. WF size/inst)
+system.cpu1.CUs1.num_total_cycles                3570                       # number of cycles the CU ran for
+system.cpu1.CUs1.vpc                         1.894118                       # Vector Operations per cycle (this CU only)
+system.cpu1.CUs1.ipc                         0.039496                       # Instructions per cycle (this CU only)
 system.cpu1.CUs1.warp_execution_dist::samples          141                       # number of lanes active per instruction (oval all instructions)
 system.cpu1.CUs1.warp_execution_dist::mean    47.957447                       # number of lanes active per instruction (oval all instructions)
 system.cpu1.CUs1.warp_execution_dist::stdev    23.818022                       # number of lanes active per instruction (oval all instructions)
@@ -2525,9 +2535,9 @@ system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc            0
 system.cpu1.CUs1.num_CAS_ops                        0                       # number of compare and swap operations
 system.cpu1.CUs1.num_failed_CAS_ops                 0                       # number of compare and swap operations that failed
 system.cpu1.CUs1.num_completed_wfs                  4                       # number of completed wavefronts
-system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.cpu2.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.cpu2.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.cpu2.num_kernel_launched                     1                       # number of kernel launched
 system.dir_cntrl0.L3CacheMemory.demand_hits            0                       # Number of cache demand hits
 system.dir_cntrl0.L3CacheMemory.demand_misses            0                       # Number of cache demand misses
@@ -2535,10 +2545,10 @@ system.dir_cntrl0.L3CacheMemory.demand_accesses            0
 system.dir_cntrl0.L3CacheMemory.num_data_array_writes         1551                       # number of data array writes
 system.dir_cntrl0.L3CacheMemory.num_tag_array_reads         1551                       # number of tag array reads
 system.dir_cntrl0.L3CacheMemory.num_tag_array_writes         1551                       # number of tag array writes
-system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.dispatcher_coalescer.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.dispatcher_coalescer.clk_domain.clock         1000                       # Clock period in ticks
-system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.dispatcher_coalescer.uncoalesced_accesses            0                       # Number of uncoalesced TLB accesses
 system.dispatcher_coalescer.coalesced_accesses            0                       # Number of coalesced TLB accesses
 system.dispatcher_coalescer.queuing_cycles            0                       # Number of cycles spent in queue
@@ -2546,7 +2556,7 @@ system.dispatcher_coalescer.local_queuing_cycles            0
 system.dispatcher_coalescer.local_latency          nan                       # Avg. latency over all incoming pkts
 system.dispatcher_tlb.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.dispatcher_tlb.clk_domain.clock           1000                       # Clock period in ticks
-system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.dispatcher_tlb.local_TLB_accesses            0                       # Number of TLB accesses
 system.dispatcher_tlb.local_TLB_hits                0                       # Number of TLB hits
 system.dispatcher_tlb.local_TLB_misses              0                       # Number of TLB misses
@@ -2563,7 +2573,7 @@ system.dispatcher_tlb.local_latency               nan                       # Av
 system.dispatcher_tlb.avg_reuse_distance            0                       # avg. reuse distance over all pages (in ticks)
 system.l1_coalescer0.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.l1_coalescer0.clk_domain.clock            1000                       # Clock period in ticks
-system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.l1_coalescer0.uncoalesced_accesses          778                       # Number of uncoalesced TLB accesses
 system.l1_coalescer0.coalesced_accesses             0                       # Number of coalesced TLB accesses
 system.l1_coalescer0.queuing_cycles                 0                       # Number of cycles spent in queue
@@ -2571,7 +2581,7 @@ system.l1_coalescer0.local_queuing_cycles            0                       # N
 system.l1_coalescer0.local_latency                  0                       # Avg. latency over all incoming pkts
 system.l1_coalescer1.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.l1_coalescer1.clk_domain.clock            1000                       # Clock period in ticks
-system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.l1_coalescer1.uncoalesced_accesses          769                       # Number of uncoalesced TLB accesses
 system.l1_coalescer1.coalesced_accesses             0                       # Number of coalesced TLB accesses
 system.l1_coalescer1.queuing_cycles                 0                       # Number of cycles spent in queue
@@ -2579,7 +2589,7 @@ system.l1_coalescer1.local_queuing_cycles            0                       # N
 system.l1_coalescer1.local_latency                  0                       # Avg. latency over all incoming pkts
 system.l1_tlb0.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.l1_tlb0.clk_domain.clock                  1000                       # Clock period in ticks
-system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.l1_tlb0.local_TLB_accesses                 778                       # Number of TLB accesses
 system.l1_tlb0.local_TLB_hits                     774                       # Number of TLB hits
 system.l1_tlb0.local_TLB_misses                     4                       # Number of TLB misses
@@ -2596,7 +2606,7 @@ system.l1_tlb0.local_latency                        0                       # Av
 system.l1_tlb0.avg_reuse_distance                   0                       # avg. reuse distance over all pages (in ticks)
 system.l1_tlb1.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.l1_tlb1.clk_domain.clock                  1000                       # Clock period in ticks
-system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.l1_tlb1.local_TLB_accesses                 769                       # Number of TLB accesses
 system.l1_tlb1.local_TLB_hits                     766                       # Number of TLB hits
 system.l1_tlb1.local_TLB_misses                     3                       # Number of TLB misses
@@ -2613,7 +2623,7 @@ system.l1_tlb1.local_latency                        0                       # Av
 system.l1_tlb1.avg_reuse_distance                   0                       # avg. reuse distance over all pages (in ticks)
 system.l2_coalescer.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.l2_coalescer.clk_domain.clock             1000                       # Clock period in ticks
-system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.l2_coalescer.uncoalesced_accesses            8                       # Number of uncoalesced TLB accesses
 system.l2_coalescer.coalesced_accesses              1                       # Number of coalesced TLB accesses
 system.l2_coalescer.queuing_cycles               8000                       # Number of cycles spent in queue
@@ -2621,7 +2631,7 @@ system.l2_coalescer.local_queuing_cycles         1000                       # Nu
 system.l2_coalescer.local_latency                 125                       # Avg. latency over all incoming pkts
 system.l2_tlb.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.l2_tlb.clk_domain.clock                   1000                       # Clock period in ticks
-system.l2_tlb.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.l2_tlb.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.l2_tlb.local_TLB_accesses                    8                       # Number of TLB accesses
 system.l2_tlb.local_TLB_hits                        3                       # Number of TLB hits
 system.l2_tlb.local_TLB_misses                      5                       # Number of TLB misses
@@ -2638,7 +2648,7 @@ system.l2_tlb.local_latency               8625.125000                       # Av
 system.l2_tlb.avg_reuse_distance                    0                       # avg. reuse distance over all pages (in ticks)
 system.l3_coalescer.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.l3_coalescer.clk_domain.clock             1000                       # Clock period in ticks
-system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.l3_coalescer.uncoalesced_accesses            5                       # Number of uncoalesced TLB accesses
 system.l3_coalescer.coalesced_accesses              1                       # Number of coalesced TLB accesses
 system.l3_coalescer.queuing_cycles               8000                       # Number of cycles spent in queue
@@ -2646,7 +2656,7 @@ system.l3_coalescer.local_queuing_cycles         1000                       # Nu
 system.l3_coalescer.local_latency                 200                       # Avg. latency over all incoming pkts
 system.l3_tlb.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.l3_tlb.clk_domain.clock                   1000                       # Clock period in ticks
-system.l3_tlb.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.l3_tlb.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.l3_tlb.local_TLB_accesses                    5                       # Number of TLB accesses
 system.l3_tlb.local_TLB_hits                        0                       # Number of TLB hits
 system.l3_tlb.local_TLB_misses                      5                       # Number of TLB misses
@@ -2661,7 +2671,7 @@ system.l3_tlb.unique_pages                          5                       # Nu
 system.l3_tlb.local_cycles                     150000                       # Number of cycles spent in queue for all incoming reqs
 system.l3_tlb.local_latency                     30000                       # Avg. latency over incoming coalesced reqs
 system.l3_tlb.avg_reuse_distance                    0                       # avg. reuse distance over all pages (in ticks)
-system.piobus.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.piobus.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.piobus.trans_dist::WriteReq                 94                       # Transaction distribution
 system.piobus.trans_dist::WriteResp                94                       # Transaction distribution
 system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio          188                       # Packet count per connected master and slave (bytes)
@@ -2672,8 +2682,8 @@ system.piobus.reqLayer0.occupancy              188000                       # La
 system.piobus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.piobus.respLayer0.occupancy              94000                       # Layer occupancy (ticks)
 system.piobus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links0.int_node.percent_links_utilized     0.007952                      
+system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links0.int_node.percent_links_utilized     0.007896                      
 system.ruby.network.ext_links0.int_node.msg_count.Control::0         1551                      
 system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0         1551                      
 system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2         1563                      
@@ -2684,8 +2694,8 @@ system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0        1240
 system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2       112536                      
 system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2        12312                      
 system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4        12408                      
-system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links1.int_node.percent_links_utilized     0.009970                      
+system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links1.int_node.percent_links_utilized     0.009900                      
 system.ruby.network.ext_links1.int_node.msg_count.Control::0           16                      
 system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0         1535                      
 system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2         1537                      
@@ -2704,7 +2714,7 @@ system.tcp_cntrl0.L1cache.num_data_array_writes           11
 system.tcp_cntrl0.L1cache.num_tag_array_reads           26                       # number of tag array reads
 system.tcp_cntrl0.L1cache.num_tag_array_writes           18                       # number of tag array writes
 system.tcp_cntrl0.L1cache.num_data_array_stalls            2                       # number of stalls caused by data array
-system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits            2                       # loads that hit in the TCP
 system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers            0                       # TCP to TCP load transfers
 system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
@@ -2721,10 +2731,10 @@ system.tcp_cntrl0.coalescer.cp_tcp_st_hits            0                       #
 system.tcp_cntrl0.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
 system.tcp_cntrl0.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl0.coalescer.cp_st_misses            0                       # stores that miss in the GPU
-system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links2.int_node.percent_links_utilized     0.000721                      
+system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links2.int_node.percent_links_utilized     0.000716                      
 system.ruby.network.ext_links2.int_node.msg_count.Control::0         1535                      
 system.ruby.network.ext_links2.int_node.msg_count.Control::1           14                      
 system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0           16                      
@@ -2752,7 +2762,7 @@ system.tcp_cntrl1.L1cache.num_tag_array_reads           25
 system.tcp_cntrl1.L1cache.num_tag_array_writes           18                       # number of tag array writes
 system.tcp_cntrl1.L1cache.num_tag_array_stalls            2                       # number of stalls caused by tag array
 system.tcp_cntrl1.L1cache.num_data_array_stalls            2                       # number of stalls caused by data array
-system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits            3                       # loads that hit in the TCP
 system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers            2                       # TCP to TCP load transfers
 system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
@@ -2769,8 +2779,8 @@ system.tcp_cntrl1.coalescer.cp_tcp_st_hits            0                       #
 system.tcp_cntrl1.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
 system.tcp_cntrl1.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl1.coalescer.cp_st_misses            0                       # stores that miss in the GPU
-system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.sqc_cntrl0.L1cache.demand_hits               0                       # Number of cache demand hits
 system.sqc_cntrl0.L1cache.demand_misses             0                       # Number of cache demand misses
 system.sqc_cntrl0.L1cache.demand_accesses            0                       # Number of cache demand accesses
@@ -2779,20 +2789,20 @@ system.sqc_cntrl0.L1cache.num_data_array_writes            5
 system.sqc_cntrl0.L1cache.num_tag_array_reads           86                       # number of tag array reads
 system.sqc_cntrl0.L1cache.num_tag_array_writes            5                       # number of tag array writes
 system.sqc_cntrl0.L1cache.num_data_array_stalls           47                       # number of stalls caused by data array
-system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.sqc_cntrl0.sequencer.load_waiting_on_load          120                       # Number of times a load aliased with a pending load
-system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.tcc_cntrl0.L2cache.demand_hits               0                       # Number of cache demand hits
 system.tcc_cntrl0.L2cache.demand_misses             0                       # Number of cache demand misses
 system.tcc_cntrl0.L2cache.demand_accesses            0                       # Number of cache demand accesses
-system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.tccdir_cntrl0.directory.demand_hits            0                       # Number of cache demand hits
 system.tccdir_cntrl0.directory.demand_misses            0                       # Number of cache demand misses
 system.tccdir_cntrl0.directory.demand_accesses            0                       # Number of cache demand accesses
 system.tccdir_cntrl0.directory.num_tag_array_reads         1554                       # number of tag array reads
 system.tccdir_cntrl0.directory.num_tag_array_writes           27                       # number of tag array writes
-system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.ruby.network.msg_count.Control            3116                      
 system.ruby.network.msg_count.Request_Control         3121                      
 system.ruby.network.msg_count.Response_Data         3159                      
@@ -2805,7 +2815,7 @@ system.ruby.network.msg_byte.Response_Control        24624
 system.ruby.network.msg_byte.Unblock_Control        24968                      
 system.sqc_coalescer.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.sqc_coalescer.clk_domain.clock            1000                       # Clock period in ticks
-system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.sqc_coalescer.uncoalesced_accesses           86                       # Number of uncoalesced TLB accesses
 system.sqc_coalescer.coalesced_accesses            60                       # Number of coalesced TLB accesses
 system.sqc_coalescer.queuing_cycles            108000                       # Number of cycles spent in queue
@@ -2813,7 +2823,7 @@ system.sqc_coalescer.local_queuing_cycles       108000                       # N
 system.sqc_coalescer.local_latency        1255.813953                       # Avg. latency over all incoming pkts
 system.sqc_tlb.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.sqc_tlb.clk_domain.clock                  1000                       # Clock period in ticks
-system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
+system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
 system.sqc_tlb.local_TLB_accesses                  60                       # Number of TLB accesses
 system.sqc_tlb.local_TLB_hits                      59                       # Number of TLB hits
 system.sqc_tlb.local_TLB_misses                     1                       # Number of TLB misses
@@ -2828,8 +2838,8 @@ system.sqc_tlb.unique_pages                         1                       # Nu
 system.sqc_tlb.local_cycles                     60001                       # Number of cycles spent in queue for all incoming reqs
 system.sqc_tlb.local_latency              1000.016667                       # Avg. latency over incoming coalesced reqs
 system.sqc_tlb.avg_reuse_distance                   0                       # avg. reuse distance over all pages (in ticks)
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED    663454500                       # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links0.int_node.throttle0.link_utilization     0.005592                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED    668137500                       # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links0.int_node.throttle0.link_utilization     0.005553                      
 system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0         1551                      
 system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2           12                      
 system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2         1539                      
@@ -2838,22 +2848,22 @@ system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0
 system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2          864                      
 system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2        12312                      
 system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4        12408                      
-system.ruby.network.ext_links0.int_node.throttle1.link_utilization     0.016287                      
+system.ruby.network.ext_links0.int_node.throttle1.link_utilization     0.016173                      
 system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0           16                      
 system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2         1535                      
 system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0          128                      
 system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2       110520                      
-system.ruby.network.ext_links0.int_node.throttle2.link_utilization     0.001977                      
+system.ruby.network.ext_links0.int_node.throttle2.link_utilization     0.001963                      
 system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0         1535                      
 system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2           16                      
 system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0        12280                      
 system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2         1152                      
-system.ruby.network.ext_links1.int_node.throttle0.link_utilization     0.016287                      
+system.ruby.network.ext_links1.int_node.throttle0.link_utilization     0.016173                      
 system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0           16                      
 system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2         1535                      
 system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0          128                      
 system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2       110520                      
-system.ruby.network.ext_links1.int_node.throttle1.link_utilization     0.003653                      
+system.ruby.network.ext_links1.int_node.throttle1.link_utilization     0.003627                      
 system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0         1535                      
 system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2            2                      
 system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2           14                      
@@ -2862,7 +2872,7 @@ system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0
 system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2          144                      
 system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2          112                      
 system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4        12280                      
-system.ruby.network.ext_links2.int_node.throttle0.link_utilization     0.000084                      
+system.ruby.network.ext_links2.int_node.throttle0.link_utilization     0.000083                      
 system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::1            8                      
 system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3            7                      
 system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::1           64                      
@@ -2873,7 +2883,7 @@ system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3
 system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Control::1           48                      
 system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3          504                      
 system.ruby.network.ext_links2.int_node.throttle2.link_utilization            0                      
-system.ruby.network.ext_links2.int_node.throttle3.link_utilization     0.002170                      
+system.ruby.network.ext_links2.int_node.throttle3.link_utilization     0.002155                      
 system.ruby.network.ext_links2.int_node.throttle3.msg_count.Control::0         1535                      
 system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1           19                      
 system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2           16                      
@@ -2887,7 +2897,7 @@ system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5
 system.ruby.network.ext_links2.int_node.throttle4.link_utilization     0.000053                      
 system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3            5                      
 system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3          360                      
-system.ruby.network.ext_links2.int_node.throttle5.link_utilization     0.001939                      
+system.ruby.network.ext_links2.int_node.throttle5.link_utilization     0.001926                      
 system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0           16                      
 system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Data::2           10                      
 system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Control::2         1525                      
@@ -2951,48 +2961,48 @@ system.ruby.Directory_Controller.CoreUnblock         1551      0.00%      0.00%
 system.ruby.Directory_Controller.U.RdBlkS         1039      0.00%      0.00%
 system.ruby.Directory_Controller.U.RdBlkM          335      0.00%      0.00%
 system.ruby.Directory_Controller.U.RdBlk          177      0.00%      0.00%
-system.ruby.Directory_Controller.BS_M.MemData           30      0.00%      0.00%
-system.ruby.Directory_Controller.BM_M.MemData           11      0.00%      0.00%
-system.ruby.Directory_Controller.B_M.MemData            1      0.00%      0.00%
-system.ruby.Directory_Controller.BS_PM.CPUPrbResp           30      0.00%      0.00%
-system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete           30      0.00%      0.00%
-system.ruby.Directory_Controller.BS_PM.MemData         1009      0.00%      0.00%
-system.ruby.Directory_Controller.BM_PM.CPUPrbResp           11      0.00%      0.00%
-system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete           11      0.00%      0.00%
-system.ruby.Directory_Controller.BM_PM.MemData          324      0.00%      0.00%
-system.ruby.Directory_Controller.B_PM.CPUPrbResp            1      0.00%      0.00%
-system.ruby.Directory_Controller.B_PM.ProbeAcksComplete            1      0.00%      0.00%
-system.ruby.Directory_Controller.B_PM.MemData          176      0.00%      0.00%
-system.ruby.Directory_Controller.BS_Pm.CPUPrbResp         1009      0.00%      0.00%
-system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete         1009      0.00%      0.00%
-system.ruby.Directory_Controller.BM_Pm.CPUPrbResp          324      0.00%      0.00%
-system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete          324      0.00%      0.00%
-system.ruby.Directory_Controller.B_Pm.CPUPrbResp          176      0.00%      0.00%
-system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete          176      0.00%      0.00%
+system.ruby.Directory_Controller.BS_M.MemData           36      0.00%      0.00%
+system.ruby.Directory_Controller.BM_M.MemData           13      0.00%      0.00%
+system.ruby.Directory_Controller.B_M.MemData           12      0.00%      0.00%
+system.ruby.Directory_Controller.BS_PM.CPUPrbResp           36      0.00%      0.00%
+system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete           36      0.00%      0.00%
+system.ruby.Directory_Controller.BS_PM.MemData         1003      0.00%      0.00%
+system.ruby.Directory_Controller.BM_PM.CPUPrbResp           14      0.00%      0.00%
+system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete           13      0.00%      0.00%
+system.ruby.Directory_Controller.BM_PM.MemData          322      0.00%      0.00%
+system.ruby.Directory_Controller.B_PM.CPUPrbResp           12      0.00%      0.00%
+system.ruby.Directory_Controller.B_PM.ProbeAcksComplete           12      0.00%      0.00%
+system.ruby.Directory_Controller.B_PM.MemData          165      0.00%      0.00%
+system.ruby.Directory_Controller.BS_Pm.CPUPrbResp         1003      0.00%      0.00%
+system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete         1003      0.00%      0.00%
+system.ruby.Directory_Controller.BM_Pm.CPUPrbResp          321      0.00%      0.00%
+system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete          322      0.00%      0.00%
+system.ruby.Directory_Controller.B_Pm.CPUPrbResp          165      0.00%      0.00%
+system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete          165      0.00%      0.00%
 system.ruby.Directory_Controller.B.CoreUnblock         1551      0.00%      0.00%
-system.ruby.LD.latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.latency_hist_seqr::samples        16335                      
-system.ruby.LD.latency_hist_seqr::mean       4.217447                      
-system.ruby.LD.latency_hist_seqr::gmean      2.103537                      
-system.ruby.LD.latency_hist_seqr::stdev     21.286370                      
-system.ruby.LD.latency_hist_seqr         |       16160     98.93%     98.93% |           0      0.00%     98.93% |           0      0.00%     98.93% |           0      0.00%     98.93% |           0      0.00%     98.93% |           0      0.00%     98.93% |         166      1.02%     99.94% |           9      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::mean       4.314539                      
+system.ruby.LD.latency_hist_seqr::gmean      2.104196                      
+system.ruby.LD.latency_hist_seqr::stdev     22.794494                      
+system.ruby.LD.latency_hist_seqr         |       16160     98.93%     98.93% |           0      0.00%     98.93% |           0      0.00%     98.93% |         166      1.02%     99.94% |           6      0.04%     99.98% |           1      0.01%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           2      0.01%    100.00%
 system.ruby.LD.latency_hist_seqr::total         16335                      
 system.ruby.LD.latency_hist_coalsr::bucket_size           64                      
 system.ruby.LD.latency_hist_coalsr::max_bucket          639                      
 system.ruby.LD.latency_hist_coalsr::samples            9                      
-system.ruby.LD.latency_hist_coalsr::mean          133                      
-system.ruby.LD.latency_hist_coalsr::gmean    19.809210                      
-system.ruby.LD.latency_hist_coalsr::stdev   158.221364                      
-system.ruby.LD.latency_hist_coalsr       |           5     55.56%     55.56% |           0      0.00%     55.56% |           0      0.00%     55.56% |           2     22.22%     77.78% |           0      0.00%     77.78% |           2     22.22%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_coalsr::mean   219.555556                      
+system.ruby.LD.latency_hist_coalsr::gmean    24.880500                      
+system.ruby.LD.latency_hist_coalsr::stdev   259.591078                      
+system.ruby.LD.latency_hist_coalsr       |           5     55.56%     55.56% |           0      0.00%     55.56% |           0      0.00%     55.56% |           0      0.00%     55.56% |           0      0.00%     55.56% |           0      0.00%     55.56% |           1     11.11%     66.67% |           1     11.11%     77.78% |           2     22.22%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_coalsr::total            9                      
-system.ruby.LD.hit_latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.hit_latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.hit_latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.hit_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.hit_latency_hist_seqr::samples          175                      
-system.ruby.LD.hit_latency_hist_seqr::mean   208.468571                      
-system.ruby.LD.hit_latency_hist_seqr::gmean   208.231054                      
-system.ruby.LD.hit_latency_hist_seqr::stdev    10.632194                      
-system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         166     94.86%     94.86% |           9      5.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist_seqr::mean   217.531429                      
+system.ruby.LD.hit_latency_hist_seqr::gmean   214.409561                      
+system.ruby.LD.hit_latency_hist_seqr::stdev    50.482703                      
+system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         166     94.86%     94.86% |           6      3.43%     98.29% |           1      0.57%     98.86% |           0      0.00%     98.86% |           0      0.00%     98.86% |           0      0.00%     98.86% |           2      1.14%    100.00%
 system.ruby.LD.hit_latency_hist_seqr::total          175                      
 system.ruby.LD.miss_latency_hist_seqr::bucket_size            4                      
 system.ruby.LD.miss_latency_hist_seqr::max_bucket           39                      
@@ -3005,34 +3015,34 @@ system.ruby.LD.miss_latency_hist_seqr::total        16160
 system.ruby.LD.miss_latency_hist_coalsr::bucket_size           64                      
 system.ruby.LD.miss_latency_hist_coalsr::max_bucket          639                      
 system.ruby.LD.miss_latency_hist_coalsr::samples            9                      
-system.ruby.LD.miss_latency_hist_coalsr::mean          133                      
-system.ruby.LD.miss_latency_hist_coalsr::gmean    19.809210                      
-system.ruby.LD.miss_latency_hist_coalsr::stdev   158.221364                      
-system.ruby.LD.miss_latency_hist_coalsr  |           5     55.56%     55.56% |           0      0.00%     55.56% |           0      0.00%     55.56% |           2     22.22%     77.78% |           0      0.00%     77.78% |           2     22.22%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_coalsr::mean   219.555556                      
+system.ruby.LD.miss_latency_hist_coalsr::gmean    24.880500                      
+system.ruby.LD.miss_latency_hist_coalsr::stdev   259.591078                      
+system.ruby.LD.miss_latency_hist_coalsr  |           5     55.56%     55.56% |           0      0.00%     55.56% |           0      0.00%     55.56% |           0      0.00%     55.56% |           0      0.00%     55.56% |           0      0.00%     55.56% |           1     11.11%     66.67% |           1     11.11%     77.78% |           2     22.22%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist_coalsr::total            9                      
 system.ruby.ST.latency_hist_seqr::bucket_size           64                      
 system.ruby.ST.latency_hist_seqr::max_bucket          639                      
 system.ruby.ST.latency_hist_seqr::samples        10412                      
-system.ruby.ST.latency_hist_seqr::mean       8.385709                      
-system.ruby.ST.latency_hist_seqr::gmean      2.308923                      
-system.ruby.ST.latency_hist_seqr::stdev     35.862445                      
-system.ruby.ST.latency_hist_seqr         |       10090     96.91%     96.91% |           0      0.00%     96.91% |           0      0.00%     96.91% |         316      3.03%     99.94% |           3      0.03%     99.97% |           3      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::mean       8.469939                      
+system.ruby.ST.latency_hist_seqr::gmean      2.309412                      
+system.ruby.ST.latency_hist_seqr::stdev     36.833690                      
+system.ruby.ST.latency_hist_seqr         |       10090     96.91%     96.91% |           0      0.00%     96.91% |           0      0.00%     96.91% |         314      3.02%     99.92% |           1      0.01%     99.93% |           5      0.05%     99.98% |           0      0.00%     99.98% |           0      0.00%     99.98% |           0      0.00%     99.98% |           2      0.02%    100.00%
 system.ruby.ST.latency_hist_seqr::total         10412                      
 system.ruby.ST.latency_hist_coalsr::bucket_size           32                      
 system.ruby.ST.latency_hist_coalsr::max_bucket          319                      
 system.ruby.ST.latency_hist_coalsr::samples           16                      
-system.ruby.ST.latency_hist_coalsr::mean   124.937500                      
-system.ruby.ST.latency_hist_coalsr::gmean    15.775436                      
-system.ruby.ST.latency_hist_coalsr::stdev   128.013264                      
-system.ruby.ST.latency_hist_coalsr       |           8     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           8     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_coalsr::mean   125.375000                      
+system.ruby.ST.latency_hist_coalsr::gmean    15.802815                      
+system.ruby.ST.latency_hist_coalsr::stdev   128.476133                      
+system.ruby.ST.latency_hist_coalsr       |           8     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           7     43.75%     93.75% |           1      6.25%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist_coalsr::total           16                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size           64                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket          639                      
 system.ruby.ST.hit_latency_hist_seqr::samples          322                      
-system.ruby.ST.hit_latency_hist_seqr::mean   208.484472                      
-system.ruby.ST.hit_latency_hist_seqr::gmean   208.014366                      
-system.ruby.ST.hit_latency_hist_seqr::stdev    16.327683                      
-system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         316     98.14%     98.14% |           3      0.93%     99.07% |           3      0.93%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist_seqr::mean   211.208075                      
+system.ruby.ST.hit_latency_hist_seqr::gmean   209.444324                      
+system.ruby.ST.hit_latency_hist_seqr::stdev    38.157121                      
+system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         314     97.52%     97.52% |           1      0.31%     97.83% |           5      1.55%     99.38% |           0      0.00%     99.38% |           0      0.00%     99.38% |           0      0.00%     99.38% |           2      0.62%    100.00%
 system.ruby.ST.hit_latency_hist_seqr::total          322                      
 system.ruby.ST.miss_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket            9                      
@@ -3044,42 +3054,42 @@ system.ruby.ST.miss_latency_hist_seqr::total        10090
 system.ruby.ST.miss_latency_hist_coalsr::bucket_size           32                      
 system.ruby.ST.miss_latency_hist_coalsr::max_bucket          319                      
 system.ruby.ST.miss_latency_hist_coalsr::samples           16                      
-system.ruby.ST.miss_latency_hist_coalsr::mean   124.937500                      
-system.ruby.ST.miss_latency_hist_coalsr::gmean    15.775436                      
-system.ruby.ST.miss_latency_hist_coalsr::stdev   128.013264                      
-system.ruby.ST.miss_latency_hist_coalsr  |           8     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           8     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_coalsr::mean   125.375000                      
+system.ruby.ST.miss_latency_hist_coalsr::gmean    15.802815                      
+system.ruby.ST.miss_latency_hist_coalsr::stdev   128.476133                      
+system.ruby.ST.miss_latency_hist_coalsr  |           8     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           7     43.75%     93.75% |           1      6.25%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist_coalsr::total           16                      
 system.ruby.ATOMIC.latency_hist_coalsr::bucket_size           64                      
 system.ruby.ATOMIC.latency_hist_coalsr::max_bucket          639                      
 system.ruby.ATOMIC.latency_hist_coalsr::samples            2                      
-system.ruby.ATOMIC.latency_hist_coalsr::mean   309.500000                      
-system.ruby.ATOMIC.latency_hist_coalsr::gmean   306.568100                      
-system.ruby.ATOMIC.latency_hist_coalsr::stdev    60.104076                      
+system.ruby.ATOMIC.latency_hist_coalsr::mean   317.500000                      
+system.ruby.ATOMIC.latency_hist_coalsr::gmean   314.366029                      
+system.ruby.ATOMIC.latency_hist_coalsr::stdev    62.932504                      
 system.ruby.ATOMIC.latency_hist_coalsr   |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ATOMIC.latency_hist_coalsr::total            2                      
 system.ruby.ATOMIC.miss_latency_hist_coalsr::bucket_size           64                      
 system.ruby.ATOMIC.miss_latency_hist_coalsr::max_bucket          639                      
 system.ruby.ATOMIC.miss_latency_hist_coalsr::samples            2                      
-system.ruby.ATOMIC.miss_latency_hist_coalsr::mean   309.500000                      
-system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean   306.568100                      
-system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev    60.104076                      
+system.ruby.ATOMIC.miss_latency_hist_coalsr::mean   317.500000                      
+system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean   314.366029                      
+system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev    62.932504                      
 system.ruby.ATOMIC.miss_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ATOMIC.miss_latency_hist_coalsr::total            2                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.latency_hist_seqr::samples        87095                      
-system.ruby.IFETCH.latency_hist_seqr::mean     4.462070                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     2.116390                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    22.434900                      
-system.ruby.IFETCH.latency_hist_seqr     |       86061     98.81%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |        1011      1.16%     99.97% |          16      0.02%     99.99% |           7      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean     4.485148                      
+system.ruby.IFETCH.latency_hist_seqr::gmean     2.116532                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    22.815865                      
+system.ruby.IFETCH.latency_hist_seqr     |       86061     98.81%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |        1006      1.16%     99.97% |          11      0.01%     99.98% |          12      0.01%     99.99% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           3      0.00%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total        87095                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.hit_latency_hist_seqr::samples         1034                      
-system.ruby.IFETCH.hit_latency_hist_seqr::mean   208.442940                      
-system.ruby.IFETCH.hit_latency_hist_seqr::gmean   207.967489                      
-system.ruby.IFETCH.hit_latency_hist_seqr::stdev    16.443135                      
-system.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1011     97.78%     97.78% |          16      1.55%     99.32% |           7      0.68%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist_seqr::mean   210.386847                      
+system.ruby.IFETCH.hit_latency_hist_seqr::gmean   209.145816                      
+system.ruby.IFETCH.hit_latency_hist_seqr::stdev    30.434753                      
+system.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1006     97.29%     97.29% |          11      1.06%     98.36% |          12      1.16%     99.52% |           2      0.19%     99.71% |           0      0.00%     99.71% |           0      0.00%     99.71% |           3      0.29%    100.00%
 system.ruby.IFETCH.hit_latency_hist_seqr::total         1034                      
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size            4                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket           39                      
@@ -3156,18 +3166,18 @@ system.ruby.L2Cache.miss_mach_latency_hist_seqr::total           59
 system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.Directory.hit_mach_latency_hist_seqr::samples         1535                      
-system.ruby.Directory.hit_mach_latency_hist_seqr::mean   208.448208                      
-system.ruby.Directory.hit_mach_latency_hist_seqr::gmean   208.002202                      
-system.ruby.Directory.hit_mach_latency_hist_seqr::stdev    15.833423                      
-system.ruby.Directory.hit_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1506     98.11%     98.11% |          19      1.24%     99.35% |          10      0.65%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.hit_mach_latency_hist_seqr::mean   211.362215                      
+system.ruby.Directory.hit_mach_latency_hist_seqr::gmean   209.793806                      
+system.ruby.Directory.hit_mach_latency_hist_seqr::stdev    34.965177                      
+system.ruby.Directory.hit_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1490     97.07%     97.07% |          18      1.17%     98.24% |          18      1.17%     99.41% |           2      0.13%     99.54% |           0      0.00%     99.54% |           0      0.00%     99.54% |           7      0.46%    100.00%
 system.ruby.Directory.hit_mach_latency_hist_seqr::total         1535                      
 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size           64                      
 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket          639                      
 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples            3                      
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean   345.333333                      
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean   345.301362                      
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev     5.773503                      
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean   478.666667                      
+system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean   470.839796                      
+system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev   101.159939                      
+system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           2     66.67%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total            3                      
 system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size            1                      
 system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket            9                      
@@ -3177,13 +3187,13 @@ system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean     1.377009
 system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev     0.877058                      
 system.ruby.TCP.miss_mach_latency_hist_coalsr |           0      0.00%      0.00% |           8     61.54%     61.54% |           4     30.77%     92.31% |           0      0.00%     92.31% |           1      7.69%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.TCP.miss_mach_latency_hist_coalsr::total           13                      
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size           32                      
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket          319                      
+system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size           64                      
+system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket          639                      
 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples           11                      
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean   250.818182                      
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean   250.757089                      
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev     5.896070                      
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          10     90.91%     90.91% |           1      9.09%    100.00% |           0      0.00%    100.00%
+system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean   287.363636                      
+system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean   279.637814                      
+system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev    78.345737                      
+system.ruby.TCCdir.miss_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           7     63.64%     63.64% |           2     18.18%     81.82% |           0      0.00%     81.82% |           1      9.09%     90.91% |           1      9.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total           11                      
 system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket            9                      
@@ -3199,20 +3209,21 @@ system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::mean           20
 system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::gmean    20.000000                      
 system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::total            5                      
-system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size           32                      
-system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket          319                      
+system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples          175                      
-system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean   208.468571                      
-system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean   208.231054                      
-system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev    10.632194                      
-system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         166     94.86%     94.86% |           9      5.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean   217.531429                      
+system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean   214.409561                      
+system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev    50.482703                      
+system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         166     94.86%     94.86% |           6      3.43%     98.29% |           1      0.57%     98.86% |           0      0.00%     98.86% |           0      0.00%     98.86% |           0      0.00%     98.86% |           2      1.14%    100.00%
 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total          175                      
 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size           64                      
 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket          639                      
 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples            2                      
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean          342                      
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean   342.000000                      
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean          537                      
+system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean   536.976722                      
+system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev     7.071068                      
+system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total            2                      
 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size            1                      
 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket            9                      
@@ -3222,13 +3233,13 @@ system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean     2.297397
 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev     0.894427                      
 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           4     80.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total            5                      
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size           32                      
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket          319                      
+system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size           64                      
+system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket          639                      
 system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples            2                      
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean   250.500000                      
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean   250.487525                      
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev     3.535534                      
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean          445                      
+system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean   444.959549                      
+system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev     8.485281                      
+system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total            2                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket            9                      
@@ -3240,10 +3251,10 @@ system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total        10090
 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples          322                      
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean   208.484472                      
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean   208.014366                      
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev    16.327683                      
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         316     98.14%     98.14% |           3      0.93%     99.07% |           3      0.93%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean   211.208075                      
+system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean   209.444324                      
+system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev    38.157121                      
+system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         314     97.52%     97.52% |           1      0.31%     97.83% |           5      1.55%     99.38% |           0      0.00%     99.38% |           0      0.00%     99.38% |           0      0.00%     99.38% |           2      0.62%    100.00%
 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total          322                      
 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size            1                      
 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket            9                      
@@ -3255,24 +3266,24 @@ system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total            8
 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size           32                      
 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket          319                      
 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples            8                      
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean   248.875000                      
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean   248.864382                      
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev     2.474874                      
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           8    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean   249.750000                      
+system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean   249.728954                      
+system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev     3.494894                      
+system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           7     87.50%     87.50% |           1     12.50%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total            8                      
 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size           64                      
 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket          639                      
 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples            1                      
-system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean          352                      
-system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean   352.000000                      
+system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean          362                      
+system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean   362.000000                      
 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev          nan                      
 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total            1                      
 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size           32                      
 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket          319                      
 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples            1                      
-system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean          267                      
-system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean   267.000000                      
+system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean          273                      
+system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean          273                      
 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev          nan                      
 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total            1                      
@@ -3293,10 +3304,10 @@ system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::total           54
 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket          639                      
 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples         1034                      
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean   208.442940                      
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean   207.967489                      
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev    16.443135                      
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1011     97.78%     97.78% |          16      1.55%     99.32% |           7      0.68%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean   210.386847                      
+system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean   209.145816                      
+system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev    30.434753                      
+system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1006     97.29%     97.29% |          11      1.06%     98.36% |          12      1.16%     99.52% |           2      0.19%     99.71% |           0      0.00%     99.71% |           0      0.00%     99.71% |           3      0.29%    100.00%
 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total         1034                      
 system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket            9                      
@@ -3331,8 +3342,8 @@ system.ruby.SQC_Controller.TCC_AckS                 5      0.00%      0.00%
 system.ruby.SQC_Controller.I.Fetch                  5      0.00%      0.00%
 system.ruby.SQC_Controller.S.Fetch                 81      0.00%      0.00%
 system.ruby.SQC_Controller.I_S.TCC_AckS             5      0.00%      0.00%
-system.ruby.TCCdir_Controller.RdBlk                54      0.00%      0.00%
-system.ruby.TCCdir_Controller.RdBlkM               36      0.00%      0.00%
+system.ruby.TCCdir_Controller.RdBlk                93      0.00%      0.00%
+system.ruby.TCCdir_Controller.RdBlkM               37      0.00%      0.00%
 system.ruby.TCCdir_Controller.RdBlkS                5      0.00%      0.00%
 system.ruby.TCCdir_Controller.CPUPrbResp           14      0.00%      0.00%
 system.ruby.TCCdir_Controller.ProbeAcksComplete           13      0.00%      0.00%
@@ -3357,7 +3368,7 @@ system.ruby.TCCdir_Controller.CP_O.CPUPrbResp            9      0.00%      0.00%
 system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete            9      0.00%      0.00%
 system.ruby.TCCdir_Controller.I_M.RdBlkM           22      0.00%      0.00%
 system.ruby.TCCdir_Controller.I_M.NB_AckM            9      0.00%      0.00%
-system.ruby.TCCdir_Controller.I_ES.RdBlk           41      0.00%      0.00%
+system.ruby.TCCdir_Controller.I_ES.RdBlk           79      0.00%      0.00%
 system.ruby.TCCdir_Controller.I_ES.NB_AckS            2      0.00%      0.00%
 system.ruby.TCCdir_Controller.I_S.NB_AckS            5      0.00%      0.00%
 system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp            2      0.00%      0.00%
@@ -3366,9 +3377,9 @@ system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp            1      0.00%      0.00
 system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete            1      0.00%      0.00%
 system.ruby.TCCdir_Controller.BB_M.CoreUnblock            1      0.00%      0.00%
 system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock            2      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBB_S.RdBlk            9      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBB_S.RdBlk           10      0.00%      0.00%
 system.ruby.TCCdir_Controller.BBB_S.CoreUnblock            7      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBB_M.RdBlkM            4      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBB_M.RdBlkM            5      0.00%      0.00%
 system.ruby.TCCdir_Controller.BBB_M.CoreUnblock            9      0.00%      0.00%
 system.ruby.TCP_Controller.Load          |           4     44.44%     44.44% |           5     55.56%    100.00%
 system.ruby.TCP_Controller.Load::total              9                      
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 0109ebfd6..5f60d059c 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
 [system.cpu0.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
 [system.cpu0.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -734,7 +734,7 @@ useIndirect=true
 [system.cpu1.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1092,7 +1092,7 @@ pipelined=false
 [system.cpu1.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1272,7 +1272,7 @@ useIndirect=true
 [system.cpu2.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1630,7 +1630,7 @@ pipelined=false
 [system.cpu2.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -1810,7 +1810,7 @@ useIndirect=true
 [system.cpu3.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -2168,7 +2168,7 @@ pipelined=false
 [system.cpu3.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -2247,7 +2247,7 @@ transition_latency=100000000
 [system.l2c]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
@@ -2321,27 +2321,27 @@ system=system
 
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -2361,6 +2361,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -2370,7 +2371,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -2392,9 +2393,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 64591e1c0..a478b858e 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 21 2016 14:30:06
-gem5 started Jul 21 2016 14:30:37
-gem5 executing on e108600-lin, pid 38681
+gem5 compiled Oct 13 2016 20:43:27
+gem5 started Oct 13 2016 20:47:19
+gem5 executing on e108600-lin, pid 17423
 command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 
 Global frequency set at 1000000000000 ticks per second
@@ -13,73 +13,73 @@ info: Entering event queue @ 0.  Starting simulation...
 Init done
 [Iteration 1, Thread 1] Got lock
 [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
 [Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 1, Thread 2] Got lock
+[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 1 completed
-[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 2, Thread 3] Got lock
 [Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 2, Thread 1] Got lock
+[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 2 completed
 [Iteration 3, Thread 3] Got lock
 [Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 3 completed
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
 [Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 4 completed
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
 [Iteration 5, Thread 3] Got lock
 [Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 5 completed
-[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
 [Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 6, Thread 2] Got lock
+[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 6 completed
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 7 completed
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 8 completed
 [Iteration 9, Thread 2] Got lock
 [Iteration 9, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
 [Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 9 completed
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 10, Thread 2] Got lock
 [Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 124523000 because target called exit()
+Exiting @ tick 124830000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 10d3d1f6f..d8e803150 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,91 +1,91 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000124                       # Number of seconds simulated
-sim_ticks                                   123936000                       # Number of ticks simulated
-final_tick                                  123936000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000125                       # Number of seconds simulated
+sim_ticks                                   124830000                       # Number of ticks simulated
+final_tick                                  124830000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 188054                       # Simulator instruction rate (inst/s)
-host_op_rate                                   188053                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               20091950                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 268856                       # Number of bytes of host memory used
-host_seconds                                     6.17                       # Real time elapsed on the host
-sim_insts                                     1159992                       # Number of instructions simulated
-sim_ops                                       1159992                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 147575                       # Simulator instruction rate (inst/s)
+host_op_rate                                   147575                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               15906234                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266768                       # Number of bytes of host memory used
+host_seconds                                     7.85                       # Real time elapsed on the host
+sim_insts                                     1158143                       # Number of instructions simulated
+sim_ops                                       1158143                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.inst            24064                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.inst            24000                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst             5696                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data             1344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst             5888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data             1408                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.inst              896                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.data              960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst              896                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.data              896                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                45376                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        24064                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst         5696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total                45824                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst        24000                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst         5888                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu2.inst          896                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          640                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           31296                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               376                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu3.inst          896                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           31680                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst               375                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.data               170                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                89                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data                21                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst                92                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data                22                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.inst                14                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.data                15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                10                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst                14                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data                14                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   709                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           194164730                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            87787245                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            45959205                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            10844307                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst             7229538                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             7745933                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             5163956                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             7229538                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               366124451                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      194164730                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       45959205                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst        7229538                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        5163956                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          252517428                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          194164730                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           87787245                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           45959205                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           10844307                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst            7229538                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            7745933                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            5163956                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            7229538                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              366124451                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           709                       # Number of read requests accepted
+system.physmem.num_reads::total                   716                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst           192261476                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            87158536                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            47168149                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            11279340                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst             7177762                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             7690459                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             7177762                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             7177762                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               367091244                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      192261476                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       47168149                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst        7177762                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        7177762                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          253785148                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          192261476                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           87158536                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           47168149                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           11279340                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst            7177762                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            7690459                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            7177762                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            7177762                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              367091244                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           716                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         709                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         716                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    45376                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    45824                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     45376                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     45824                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 120                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                  44                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  31                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  62                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                  33                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                  63                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  69                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                  28                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  19                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  28                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                  27                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                  31                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                 13                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                 69                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                 45                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                 72                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                 47                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                 19                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                101                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
@@ -106,14 +106,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                       123701000                       # Total gap between requests
+system.physmem.totGap                       124590000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     709                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     716                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -121,10 +121,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       430                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       203                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        55                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        16                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       416                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       218                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        59                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -217,211 +217,221 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          169                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      251.076923                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     166.451829                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     245.101340                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             63     37.28%     37.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           39     23.08%     60.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           28     16.57%     76.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           13      7.69%     84.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            8      4.73%     89.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            8      4.73%     94.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      1.78%     95.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      0.59%     96.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            6      3.55%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            169                       # Bytes accessed per row activation
-system.physmem.totQLat                        6766000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  20059750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      3545000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9543.02                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          174                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      246.436782                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     161.758718                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     247.924177                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             67     38.51%     38.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           43     24.71%     63.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           26     14.94%     78.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           12      6.90%     85.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            7      4.02%     89.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            8      4.60%     93.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      1.72%     95.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      1.15%     96.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            6      3.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            174                       # Bytes accessed per row activation
+system.physmem.totQLat                       12446750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  25871750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      3580000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       17383.73                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28293.02                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         366.12                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  36133.73                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         367.09                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      366.12                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      367.09                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.86                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.86                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           2.87                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.87                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.23                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.26                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        528                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        530                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.47                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   74.02                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                       174472.50                       # Average gap between requests
-system.physmem.pageHitRate                      74.47                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     831600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     453750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2925000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                       174008.38                       # Average gap between requests
+system.physmem.pageHitRate                      74.02                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     856800                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     432630                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2877420                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy                7628400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               49377960                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy               26918250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 88134960                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              752.944352                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE       47288500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF         3900000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        68692500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     408240                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     222750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   2184000                       # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy           9834240.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                6410790                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                 304320                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy          34392090                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy          13115040                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy       649140.000000                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy                 68872470                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              551.730113                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime              109416750                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE         358500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF         4166000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF         403000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN     34152000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        10318500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN     75432000                       # Time in different power states
+system.physmem_1.actEnergy                     471240                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     227700                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   2234820                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy                7628400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               42901335                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy               32591250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 85935975                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              734.244489                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE       54352750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF         3900000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        59251250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.cpu0.branchPred.lookups                  98531                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted            94014                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect             1575                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups               95788                       # Number of BTB lookups
+system.physmem_1.refreshEnergy           9834240.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                5188140                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 617280                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy          32401650                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy          11725440                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy            3565380                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy                 66265890                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              530.849075                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime              111659250                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE        1125500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF         4172000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF       10253750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN     30535250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         7679500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN     71064000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.cpu0.branchPred.lookups                  98509                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted            93993                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect             1599                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups               95823                       # Number of BTB lookups
 system.cpu0.branchPred.BTBHits                      0                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu0.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                   1142                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.usedRAS                   1115                       # Number of times the RAS was used to get a target.
 system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups          95788                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits             88519                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses            7269                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted         1054                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.indirectLookups          95823                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits             88367                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses            7456                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted         1077                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.pwrStateResidencyTicks::ON      123936000                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                          247873                       # number of cpu cycles simulated
+system.cpu0.pwrStateResidencyTicks::ON      124830000                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                          249661                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles             23367                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                        581451                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                      98531                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches             89661                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                       193123                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                   3449                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                        66                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.icacheStallCycles             22650                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                        581099                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                      98509                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches             89482                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                       193985                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                   3497                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                        78                       # Number of cycles fetch has spent waiting for tlb
 system.cpu0.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles         2208                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingTrapStallCycles         2191                       # Number of stall cycles due to pending traps
 system.cpu0.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                     7997                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes                  861                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.CacheLines                     7995                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes                  871                       # Number of outstanding Icache misses that were squashed
 system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples            220500                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             2.636966                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.261585                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::samples            220664                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             2.633411                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.264413                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                   33425     15.16%     15.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                   91538     41.51%     56.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                     694      0.31%     56.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                    1015      0.46%     57.45% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                     497      0.23%     57.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                   87060     39.48%     97.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                     731      0.33%     97.49% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                     514      0.23%     97.72% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                    5026      2.28%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                   33866     15.35%     15.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                   91353     41.40%     56.75% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                     668      0.30%     57.05% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                     983      0.45%     57.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                     516      0.23%     57.73% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                   86959     39.41%     97.14% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                     734      0.33%     97.47% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                     482      0.22%     97.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                    5103      2.31%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total              220500                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.397506                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       2.345762                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                   17843                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles                18591                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                   181526                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles                  816                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                  1724                       # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts                563984                       # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles                  1724                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                   18505                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                   1935                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles         15328                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                   181668                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles                 1340                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts                558880                       # Number of instructions processed by rename
+system.cpu0.fetch.rateDist::total              220664                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.394571                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       2.327552                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                   17658                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles                19166                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                   181260                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles                  832                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                  1748                       # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts                563638                       # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles                  1748                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                   18349                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                   2015                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles         15764                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                   181386                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles                 1402                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts                558452                       # Number of instructions processed by rename
 system.cpu0.rename.IQFullEvents                    11                       # Number of times rename has blocked due to IQ full
 system.cpu0.rename.LQFullEvents                    11                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents                   869                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands             382489                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups              1113780                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups          841332                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups                2                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps               363591                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                   18898                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts              1094                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts          1121                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                     5347                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads              178321                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores              90063                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads            86944                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores           86670                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                    466208                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded               1118                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                   462266                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued              112                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined          16406                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined        13115                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved           559                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples       220500                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        2.096444                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.103875                       # Number of insts issued each cycle
+system.cpu0.rename.SQFullEvents                   925                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands             382172                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups              1112707                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups          840550                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups                4                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps               362927                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                   19245                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts              1073                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts          1102                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                     5312                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads              178069                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores              89965                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads            86828                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores           86540                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                    465662                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded               1094                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                   461556                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued              118                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined          16666                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined        13597                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved           535                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples       220664                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        2.091669                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.110492                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0              36239     16.43%     16.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1               4459      2.02%     18.46% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2              88275     40.03%     58.49% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3              87972     39.90%     98.39% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4               1699      0.77%     99.16% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                988      0.45%     99.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                572      0.26%     99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7                195      0.09%     99.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8                101      0.05%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0              36803     16.68%     16.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1               4402      1.99%     18.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2              88094     39.92%     58.60% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3              87764     39.77%     98.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4               1699      0.77%     99.14% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                985      0.45%     99.58% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                568      0.26%     99.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7                247      0.11%     99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8                102      0.05%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total         220500                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total         220664                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                    126     38.77%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     38.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                    78     24.00%     62.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite                  121     37.23%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                    129     39.09%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     39.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                    77     23.33%     62.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite                  124     37.58%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu               195215     42.23%     42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu               194924     42.23%     42.23% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.23% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.23% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.23% # Type of FU issued
@@ -450,94 +460,94 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.23% # Ty
 system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.23% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.23% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead              177740     38.45%     80.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite              89311     19.32%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead              177454     38.45%     80.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite              89178     19.32%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total                462266                       # Type of FU issued
-system.cpu0.iq.rate                          1.864931                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                        325                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.000703                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads           1145469                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes           483779                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses       459725                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total                461556                       # Type of FU issued
+system.cpu0.iq.rate                          1.848731                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                        330                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.000715                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads           1144224                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes           483466                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses       458888                       # Number of integer instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes                 4                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_writes                 8                       # Number of floating instruction queue writes
 system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses                462591                       # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses                461886                       # Number of integer alu accesses
 system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads           86430                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads           86265                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads         2936                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses           13                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation           53                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores         1864                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads         3016                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses            7                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation           54                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores         1932                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked           11                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.cacheBlocked           12                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                  1724                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                   1933                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles                   27                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts             554898                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts              123                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts               178321                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts               90063                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts              1001                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                    27                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles                  1748                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                   2015                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles                   29                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts             554202                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts              154                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts               178069                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts               89965                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts               980                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                    30                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents            53                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect           229                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect         1693                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts                1922                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts               460834                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts               177384                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts             1432                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.memOrderViolationEvents            54                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect           232                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect         1714                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts                1946                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts               460023                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts               177079                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts             1533                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                        87572                       # number of nop insts executed
-system.cpu0.iew.exec_refs                      266499                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                   91565                       # Number of branches executed
-system.cpu0.iew.exec_stores                     89115                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.859154                       # Inst execution rate
-system.cpu0.iew.wb_sent                        460184                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                       459725                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                   272583                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                   276120                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      1.854680                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.987190                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts          17076                       # The number of squashed insts skipped by commit
+system.cpu0.iew.exec_nop                        87446                       # number of nop insts executed
+system.cpu0.iew.exec_refs                      266047                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                   91396                       # Number of branches executed
+system.cpu0.iew.exec_stores                     88968                       # Number of stores executed
+system.cpu0.iew.exec_rate                    1.842591                       # Inst execution rate
+system.cpu0.iew.wb_sent                        459364                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                       458888                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                   272127                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                   275688                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      1.838044                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.987083                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts          17379                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts             1575                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples       217161                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     2.476218                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     2.140669                       # Number of insts commited each cycle
+system.cpu0.commit.branchMispredicts             1599                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples       217244                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     2.470687                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     2.142582                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0        36214     16.68%     16.68% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1        90367     41.61%     58.29% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2         2049      0.94%     59.23% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3          624      0.29%     59.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4          510      0.23%     59.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5        86212     39.70%     99.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6          445      0.20%     99.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7          289      0.13%     99.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8          451      0.21%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0        36715     16.90%     16.90% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1        90144     41.49%     58.39% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2         2018      0.93%     59.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3          613      0.28%     59.61% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4          486      0.22%     59.83% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5        86051     39.61%     99.44% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6          459      0.21%     99.65% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7          294      0.14%     99.79% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8          464      0.21%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total       217161                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts              537738                       # Number of instructions committed
-system.cpu0.commit.committedOps                537738                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total       217244                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts              536742                       # Number of instructions committed
+system.cpu0.commit.committedOps                536742                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                        263584                       # Number of memory references committed
-system.cpu0.commit.loads                       175385                       # Number of loads committed
+system.cpu0.commit.refs                        263086                       # Number of memory references committed
+system.cpu0.commit.loads                       175053                       # Number of loads committed
 system.cpu0.commit.membars                         84                       # Number of memory barriers committed
-system.cpu0.commit.branches                     90086                       # Number of branches committed
+system.cpu0.commit.branches                     89920                       # Number of branches committed
 system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                   361922                       # Number of committed integer instructions.
+system.cpu0.commit.int_insts                   361258                       # Number of committed integer instructions.
 system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass        86818     16.15%     16.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu          187252     34.82%     50.97% # Class of committed instruction
+system.cpu0.commit.op_class_0::No_OpClass        86652     16.14%     16.14% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu          186920     34.82%     50.97% # Class of committed instruction
 system.cpu0.commit.op_class_0::IntMult              0      0.00%     50.97% # Class of committed instruction
 system.cpu0.commit.op_class_0::IntDiv               0      0.00%     50.97% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     50.97% # Class of committed instruction
@@ -566,2071 +576,2071 @@ system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     50.97%
 system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     50.97% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     50.97% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     50.97% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead         175469     32.63%     83.60% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite         88199     16.40%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead         175137     32.63%     83.60% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite         88033     16.40%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total           537738                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events                  451                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                      770363                       # The number of ROB reads
-system.cpu0.rob.rob_writes                    1113018                       # The number of ROB writes
-system.cpu0.timesIdled                            321                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                          27373                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                     450836                       # Number of Instructions Simulated
-system.cpu0.committedOps                       450836                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              0.549807                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.549807                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.818819                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.818819                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  823745                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 371341                       # number of integer regfile writes
+system.cpu0.commit.op_class_0::total           536742                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events                  464                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                      769740                       # The number of ROB reads
+system.cpu0.rob.rob_writes                    1111721                       # The number of ROB writes
+system.cpu0.timesIdled                            320                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                          28997                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts                     450006                       # Number of Instructions Simulated
+system.cpu0.committedOps                       450006                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              0.554795                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.554795                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              1.802468                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.802468                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                  822274                       # number of integer regfile reads
+system.cpu0.int_regfile_writes                 370684                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
-system.cpu0.misc_regfile_reads                 268638                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads                 268168                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          142.669467                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs             177790                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse          142.144997                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs             177494                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs              172                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs          1033.662791                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs          1031.941860                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   142.669467                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.278651                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.278651                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   142.144997                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277627                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.277627                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          170                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2          143                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.332031                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           716504                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          716504                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data        90267                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          90267                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        87606                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         87606                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data           22                       # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total             22                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       177873                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          177873                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       177873                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         177873                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          580                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          580                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          551                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          551                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data           20                       # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total           20                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data         1131                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total          1131                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data         1131                       # number of overall misses
-system.cpu0.dcache.overall_misses::total         1131                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     15004000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     15004000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     35761990                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total     35761990                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       487500                       # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total       487500                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     50765990                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     50765990                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     50765990                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     50765990                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        90847                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        90847                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        88157                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        88157                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.tags.tag_accesses           715284                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          715284                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data        90136                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          90136                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        87436                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         87436                       # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits::cpu0.data           24                       # number of SwapReq hits
+system.cpu0.dcache.SwapReq_hits::total             24                       # number of SwapReq hits
+system.cpu0.dcache.demand_hits::cpu0.data       177572                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total          177572                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data       177572                       # number of overall hits
+system.cpu0.dcache.overall_hits::total         177572                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          571                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          571                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data          555                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total          555                       # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses::cpu0.data           18                       # number of SwapReq misses
+system.cpu0.dcache.SwapReq_misses::total           18                       # number of SwapReq misses
+system.cpu0.dcache.demand_misses::cpu0.data         1126                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total          1126                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data         1126                       # number of overall misses
+system.cpu0.dcache.overall_misses::total         1126                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     16338000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total     16338000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     35699989                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total     35699989                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       501500                       # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total       501500                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data     52037989                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     52037989                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     52037989                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     52037989                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        90707                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        90707                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        87991                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        87991                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       179004                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       179004                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       179004                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       179004                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006384                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.006384                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006250                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.006250                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.476190                       # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total     0.476190                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006318                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.006318                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006318                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.006318                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25868.965517                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 25868.965517                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64903.793103                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 64903.793103                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data        24375                       # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total        24375                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44885.932803                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 44885.932803                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44885.932803                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 44885.932803                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs          832                       # number of cycles access was blocked
+system.cpu0.dcache.demand_accesses::cpu0.data       178698                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total       178698                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data       178698                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total       178698                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006295                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.006295                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006307                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.006307                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.428571                       # miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::total     0.428571                       # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006301                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.006301                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006301                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.006301                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28612.959720                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 28612.959720                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64324.304505                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 64324.304505                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27861.111111                       # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::total 27861.111111                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46214.910302                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 46214.910302                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46214.910302                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 46214.910302                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs          885                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               22                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    37.818182                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    42.142857                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          378                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          378                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          383                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total          383                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          761                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          761                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          761                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          761                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          369                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          369                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          385                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total          385                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          754                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          754                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          754                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total          754                       # number of overall MSHR hits
 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          202                       # number of ReadReq MSHR misses
 system.cpu0.dcache.ReadReq_mshr_misses::total          202                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          168                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          168                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           20                       # number of SwapReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::total           20                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          370                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          370                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          370                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          370                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6835500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6835500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8076500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8076500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       467500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       467500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     14912000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     14912000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     14912000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     14912000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002224                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002224                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.001906                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.001906                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.476190                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.476190                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002067                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.002067                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002067                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.002067                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33839.108911                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33839.108911                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48074.404762                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48074.404762                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data        23375                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total        23375                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40302.702703                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40302.702703                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40302.702703                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40302.702703                       # average overall mshr miss latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements              413                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          250.106503                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs               7058                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs              712                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             9.912921                       # Average number of references to valid blocks.
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          170                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total          170                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           18                       # number of SwapReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::total           18                       # number of SwapReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data          372                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total          372                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data          372                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total          372                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      7501000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      7501000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8169500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8169500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       483500                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total       483500                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     15670500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     15670500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     15670500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     15670500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002227                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002227                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.001932                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.001932                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.428571                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002082                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.002082                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002082                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.002082                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37133.663366                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37133.663366                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48055.882353                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48055.882353                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26861.111111                       # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26861.111111                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data        42125                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total        42125                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data        42125                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total        42125                       # average overall mshr miss latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements              393                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          248.700617                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs               7078                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs              695                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.184173                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   250.106503                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.488489                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.488489                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          299                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           41                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          190                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.583984                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses             8709                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses            8709                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst         7058                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total           7058                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst         7058                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total            7058                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst         7058                       # number of overall hits
-system.cpu0.icache.overall_hits::total           7058                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          939                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          939                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          939                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           939                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          939                       # number of overall misses
-system.cpu0.icache.overall_misses::total          939                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     44243500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     44243500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     44243500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     44243500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     44243500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     44243500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst         7997                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total         7997                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst         7997                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total         7997                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst         7997                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total         7997                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.117419                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.117419                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.117419                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.117419                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.117419                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.117419                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47117.678381                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 47117.678381                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47117.678381                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 47117.678381                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47117.678381                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 47117.678381                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs          117                       # number of cycles access was blocked
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   248.700617                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.485743                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.485743                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          302                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           44                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          188                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.589844                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses             8690                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses            8690                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst         7078                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total           7078                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst         7078                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total            7078                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst         7078                       # number of overall hits
+system.cpu0.icache.overall_hits::total           7078                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          917                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          917                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          917                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           917                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          917                       # number of overall misses
+system.cpu0.icache.overall_misses::total          917                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     47775500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     47775500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     47775500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     47775500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     47775500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     47775500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst         7995                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total         7995                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst         7995                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total         7995                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst         7995                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total         7995                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.114697                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.114697                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.114697                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.114697                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.114697                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.114697                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 52099.781897                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 52099.781897                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 52099.781897                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 52099.781897                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 52099.781897                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 52099.781897                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs          151                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                4                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    29.250000                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    37.750000                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks          413                       # number of writebacks
-system.cpu0.icache.writebacks::total              413                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          226                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total          226                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst          226                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total          226                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst          226                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total          226                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          713                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          713                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          713                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          713                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          713                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          713                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     34164500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     34164500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     34164500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     34164500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     34164500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     34164500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.089158                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.089158                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.089158                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.089158                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.089158                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.089158                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47916.549790                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47916.549790                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47916.549790                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 47916.549790                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47916.549790                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 47916.549790                       # average overall mshr miss latency
-system.cpu1.branchPred.lookups                  73042                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted            65659                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect             2238                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups               64943                       # Number of BTB lookups
+system.cpu0.icache.writebacks::writebacks          393                       # number of writebacks
+system.cpu0.icache.writebacks::total              393                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          221                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total          221                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst          221                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total          221                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst          221                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total          221                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          696                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total          696                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst          696                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total          696                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst          696                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total          696                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     36615000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     36615000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     36615000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     36615000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     36615000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     36615000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.087054                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.087054                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.087054                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.087054                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.087054                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.087054                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 52607.758621                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 52607.758621                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 52607.758621                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 52607.758621                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 52607.758621                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 52607.758621                       # average overall mshr miss latency
+system.cpu1.branchPred.lookups                  69942                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted            62611                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect             2168                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups               62876                       # Number of BTB lookups
 system.cpu1.branchPred.BTBHits                      0                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu1.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                   1989                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.usedRAS                   1880                       # Number of times the RAS was used to get a target.
 system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups          64943                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits             55241                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses            9702                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted         1128                       # Number of mispredicted indirect branches.
-system.cpu1.pwrStateResidencyTicks::ON      123936000                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                          192502                       # number of cpu cycles simulated
+system.cpu1.branchPred.indirectLookups          62876                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits             52518                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses           10358                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted         1122                       # Number of mispredicted indirect branches.
+system.cpu1.pwrStateResidencyTicks::ON      124830000                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                          191834                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles             33710                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                        406560                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                      73042                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches             57230                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                       148689                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                   4633                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.icacheStallCycles             35275                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                        386727                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                      69942                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches             54398                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                       146033                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                   4493                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.MiscStallCycles                   6                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu1.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles         1669                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.IcacheWaitRetryStallCycles           15                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                    22180                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                  918                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples            186413                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             2.180964                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.381342                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.PendingTrapStallCycles         1374                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.IcacheWaitRetryStallCycles           38                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                    23469                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                  905                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples            184982                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             2.090620                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.368236                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                   54977     29.49%     29.49% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   63721     34.18%     63.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                    5493      2.95%     66.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                    3499      1.88%     68.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                     651      0.35%     68.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   47493     25.48%     94.32% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                     995      0.53%     94.86% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                    1355      0.73%     95.59% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                    8229      4.41%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                   58784     31.78%     31.78% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                   61509     33.25%     65.03% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                    6216      3.36%     68.39% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                    3423      1.85%     70.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                     694      0.38%     70.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   43897     23.73%     94.35% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                    1064      0.58%     94.92% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                    1288      0.70%     95.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                    8107      4.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total              186413                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.379435                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       2.111978                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                   22012                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles                48189                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                   110683                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                 3203                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                  2316                       # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts                375249                       # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles                  2316                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                   23003                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                  21046                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles         13565                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                   110960                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles                15513                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts                369118                       # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents                 12808                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                    18                       # Number of times rename has blocked due to LQ full
+system.cpu1.fetch.rateDist::total              184982                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.364596                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       2.015946                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                   21795                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles                53545                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                   103882                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                 3504                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                  2246                       # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts                357234                       # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles                  2246                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                   22757                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                  24349                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles         13357                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                   104467                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles                17796                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts                350958                       # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents                 15108                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
 system.cpu1.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands             260404                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups               717496                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups          555302                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups               32                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps               234261                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                   26143                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts              1622                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts          1759                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                    20875                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads              105786                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores              51568                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads            49714                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           45358                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                    305985                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded               5880                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                   304555                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued               84                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined          23105                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined        18122                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved          1124                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples       186413                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.633765                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.368784                       # Number of insts issued each cycle
+system.cpu1.rename.RenamedOperands             246923                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups               678000                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups          525614                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups               22                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps               220975                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                   25948                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts              1579                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts          1706                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                    23252                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads               99419                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores              48107                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads            46982                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           41894                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                    289725                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded               6510                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                   288968                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued               96                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined          22905                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined        18076                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved          1082                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples       184982                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.562141                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.375121                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0              59464     31.90%     31.90% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1              19554     10.49%     42.39% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2              50315     26.99%     69.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3              50093     26.87%     96.25% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4               3572      1.92%     98.17% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               1698      0.91%     99.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6               1008      0.54%     99.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7                406      0.22%     99.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8                303      0.16%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0              62949     34.03%     34.03% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1              21563     11.66%     45.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2              46877     25.34%     71.03% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3              46716     25.25%     96.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4               3504      1.89%     98.18% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               1701      0.92%     99.10% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                999      0.54%     99.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7                396      0.21%     99.85% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8                277      0.15%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total         186413                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total         184982                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                    182     38.89%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     38.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                    58     12.39%     51.28% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                  228     48.72%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                    191     40.04%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     40.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                    60     12.58%     52.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                  226     47.38%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu               145063     47.63%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead              108861     35.74%     83.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite              50631     16.62%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu               138690     47.99%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead              103154     35.70%     83.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite              47124     16.31%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total                304555                       # Type of FU issued
-system.cpu1.iq.rate                          1.582087                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                        468                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.001537                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads            796075                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes           334945                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses       300973                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total                288968                       # Type of FU issued
+system.cpu1.iq.rate                          1.506344                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                        477                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.001651                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads            763491                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes           319139                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses       285378                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes                64                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_writes                44                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses                305023                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses                289445                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           45252                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           41785                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads         4194                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses           25                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores         2536                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads         4131                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses           40                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation           43                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores         2566                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                  2316                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                   6366                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                   55                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts             362764                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts              272                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts               105786                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts               51568                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts              1528                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles                  2246                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                   7047                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                   53                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts             344310                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts              276                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts                99419                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts               48107                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts              1464                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                    36                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents            39                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect           443                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect         2397                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts                2840                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts               302276                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts               104291                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts             2279                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents            43                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect           462                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect         2268                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts                2730                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts               286645                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts                97925                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts             2323                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        50899                       # number of nop insts executed
-system.cpu1.iew.exec_refs                      154635                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                   61121                       # Number of branches executed
-system.cpu1.iew.exec_stores                     50344                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.570249                       # Inst execution rate
-system.cpu1.iew.wb_sent                        301460                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                       300973                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                   172395                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                   179828                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      1.563480                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.958666                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts          24140                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls           4756                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts             2238                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples       181815                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.862272                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     2.110451                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                        48075                       # number of nop insts executed
+system.cpu1.iew.exec_refs                      144750                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                   58305                       # Number of branches executed
+system.cpu1.iew.exec_stores                     46825                       # Number of stores executed
+system.cpu1.iew.exec_rate                    1.494235                       # Inst execution rate
+system.cpu1.iew.wb_sent                        285841                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                       285378                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                   162569                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                   170014                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      1.487630                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.956209                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts          23932                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls           5428                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts             2168                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples       180468                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.775063                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     2.087699                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0        63682     35.03%     35.03% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1        57506     31.63%     66.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2         5445      2.99%     69.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3         5412      2.98%     72.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4         1312      0.72%     73.35% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        45472     25.01%     98.36% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6          770      0.42%     98.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7          999      0.55%     99.33% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8         1217      0.67%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0        67886     37.62%     37.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1        54714     30.32%     67.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2         5489      3.04%     70.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3         6162      3.41%     74.39% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4         1291      0.72%     75.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        41971     23.26%     98.36% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6          718      0.40%     98.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7         1059      0.59%     99.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8         1178      0.65%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total       181815                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts              338589                       # Number of instructions committed
-system.cpu1.commit.committedOps                338589                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total       180468                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts              320342                       # Number of instructions committed
+system.cpu1.commit.committedOps                320342                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                        150624                       # Number of memory references committed
-system.cpu1.commit.loads                       101592                       # Number of loads committed
-system.cpu1.commit.membars                       4041                       # Number of memory barriers committed
-system.cpu1.commit.branches                     59040                       # Number of branches committed
+system.cpu1.commit.refs                        140829                       # Number of memory references committed
+system.cpu1.commit.loads                        95288                       # Number of loads committed
+system.cpu1.commit.membars                       4715                       # Number of memory barriers committed
+system.cpu1.commit.branches                     56221                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                   231783                       # Number of committed integer instructions.
+system.cpu1.commit.int_insts                   219172                       # Number of committed integer instructions.
 system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass        49829     14.72%     14.72% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu          134095     39.60%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult              0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     54.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead         105633     31.20%     85.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite         49032     14.48%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::No_OpClass        47012     14.68%     14.68% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu          127786     39.89%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult              0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     54.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead         100003     31.22%     85.78% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite         45541     14.22%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total           338589                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events                 1217                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                      542741                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     730091                       # The number of ROB writes
-system.cpu1.timesIdled                            236                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                           6089                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                       47433                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                     284719                       # Number of Instructions Simulated
-system.cpu1.committedOps                       284719                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              0.676112                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        0.676112                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              1.479044                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        1.479044                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                  527704                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 245054                       # number of integer regfile writes
+system.cpu1.commit.op_class_0::total           320342                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events                 1178                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                      522978                       # The number of ROB reads
+system.cpu1.rob.rob_writes                     693117                       # The number of ROB writes
+system.cpu1.timesIdled                            233                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                           6852                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                       49387                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                     268615                       # Number of Instructions Simulated
+system.cpu1.committedOps                       268615                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              0.714160                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        0.714160                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              1.400247                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        1.400247                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                  497951                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                 231611                       # number of integer regfile writes
 system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 156484                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads                 146596                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           26.869792                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              56025                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs          1931.896552                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse           26.433606                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs              52423                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs          1747.433333                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    26.869792                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.052480                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.052480                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           432447                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          432447                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data        58508                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          58508                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        48814                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         48814                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           11                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data       107322                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total          107322                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data       107322                       # number of overall hits
-system.cpu1.dcache.overall_hits::total         107322                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          507                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          507                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          149                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          149                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           58                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          656                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           656                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          656                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          656                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      4815500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      4815500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3532500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      3532500                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       364000                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       364000                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data      8348000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total      8348000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data      8348000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total      8348000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        59015                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        59015                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        48963                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        48963                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           69                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data       107978                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total       107978                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data       107978                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total       107978                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.008591                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.008591                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003043                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.003043                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.840580                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.840580                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006075                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.006075                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006075                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.006075                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data  9498.027613                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total  9498.027613                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23708.053691                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 23708.053691                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  6275.862069                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total  6275.862069                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12725.609756                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 12725.609756                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12725.609756                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 12725.609756                       # average overall miss latency
+system.cpu1.dcache.tags.occ_blocks::cpu1.data    26.433606                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.051628                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.051628                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           406876                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          406876                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data        55612                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          55612                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        45312                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         45312                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           12                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data       100924                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total          100924                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data       100924                       # number of overall hits
+system.cpu1.dcache.overall_hits::total         100924                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          502                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          502                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          162                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          162                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data           55                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          664                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           664                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          664                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          664                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      5584500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total      5584500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3659500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      3659500                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       374500                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total       374500                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data      9244000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total      9244000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data      9244000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total      9244000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        56114                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        56114                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        45474                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        45474                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           67                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           67                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data       101588                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total       101588                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data       101588                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total       101588                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.008946                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.008946                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003562                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.003562                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.820896                       # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total     0.820896                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006536                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.006536                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006536                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.006536                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11124.501992                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 11124.501992                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22589.506173                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22589.506173                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  6809.090909                       # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total  6809.090909                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13921.686747                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 13921.686747                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13921.686747                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 13921.686747                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          344                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          344                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           43                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total           43                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          387                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          387                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          387                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          387                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          163                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          106                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           58                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          340                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          340                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           55                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total           55                       # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          395                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          395                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          395                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          395                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          162                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           55                       # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
 system.cpu1.dcache.demand_mshr_misses::cpu1.data          269                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.demand_mshr_misses::total          269                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.overall_mshr_misses::cpu1.data          269                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_misses::total          269                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1494500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1494500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1455500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1455500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       306000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       306000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2950000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      2950000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2950000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      2950000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002762                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.002762                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002165                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002165                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.840580                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.840580                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002491                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.002491                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002491                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.002491                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  9168.711656                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  9168.711656                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13731.132075                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13731.132075                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  5275.862069                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  5275.862069                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10966.542751                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10966.542751                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10966.542751                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10966.542751                       # average overall mshr miss latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2129000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2129000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1532000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1532000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       319500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total       319500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3661000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      3661000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3661000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      3661000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002887                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.002887                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002353                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002353                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.820896                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.820896                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002648                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.002648                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002648                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.002648                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13141.975309                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13141.975309                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14317.757009                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14317.757009                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  5809.090909                       # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  5809.090909                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13609.665428                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13609.665428                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13609.665428                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13609.665428                       # average overall mshr miss latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
 system.cpu1.icache.tags.replacements              556                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           97.374754                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs              21335                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs              687                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            31.055313                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.tagsinuse           97.753950                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs              22636                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs              690                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            32.805797                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    97.374754                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.190185                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.190185                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          131                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          111                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.255859                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses            22867                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses           22867                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst        21335                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total          21335                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst        21335                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total           21335                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst        21335                       # number of overall hits
-system.cpu1.icache.overall_hits::total          21335                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          845                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          845                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          845                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           845                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          845                       # number of overall misses
-system.cpu1.icache.overall_misses::total          845                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     18952000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total     18952000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst     18952000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total     18952000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst     18952000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total     18952000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst        22180                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total        22180                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst        22180                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total        22180                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst        22180                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total        22180                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.038097                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.038097                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.038097                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.038097                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.038097                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.038097                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22428.402367                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 22428.402367                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22428.402367                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 22428.402367                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22428.402367                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 22428.402367                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs          141                       # number of cycles access was blocked
+system.cpu1.icache.tags.occ_blocks::cpu1.inst    97.753950                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.190926                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.190926                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          134                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           14                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.261719                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses            24159                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses           24159                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst        22636                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total          22636                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst        22636                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total           22636                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst        22636                       # number of overall hits
+system.cpu1.icache.overall_hits::total          22636                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          833                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          833                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          833                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           833                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          833                       # number of overall misses
+system.cpu1.icache.overall_misses::total          833                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     20006500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total     20006500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst     20006500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total     20006500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst     20006500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total     20006500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst        23469                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total        23469                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst        23469                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total        23469                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst        23469                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total        23469                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.035494                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.035494                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.035494                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.035494                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.035494                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.035494                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24017.406963                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 24017.406963                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24017.406963                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 24017.406963                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24017.406963                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 24017.406963                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs          207                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                4                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                6                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    35.250000                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    34.500000                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.writebacks::writebacks          556                       # number of writebacks
 system.cpu1.icache.writebacks::total              556                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst          158                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total          158                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst          158                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total          158                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst          158                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total          158                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          687                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total          687                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst          687                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total          687                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst          687                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total          687                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     14723000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total     14723000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     14723000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total     14723000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     14723000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total     14723000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.030974                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.030974                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.030974                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.030974                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.030974                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.030974                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21430.858806                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21430.858806                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21430.858806                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 21430.858806                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21430.858806                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 21430.858806                       # average overall mshr miss latency
-system.cpu2.branchPred.lookups                  66096                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted            57926                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect             2486                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups               57464                       # Number of BTB lookups
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst          143                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total          143                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst          143                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total          143                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst          143                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total          143                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          690                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total          690                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst          690                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total          690                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst          690                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total          690                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     15540500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total     15540500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     15540500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total     15540500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     15540500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total     15540500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.029400                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.029400                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.029400                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.029400                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.029400                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.029400                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22522.463768                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22522.463768                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22522.463768                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 22522.463768                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22522.463768                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 22522.463768                       # average overall mshr miss latency
+system.cpu2.branchPred.lookups                  60250                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted            52369                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect             2399                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups               52178                       # Number of BTB lookups
 system.cpu2.branchPred.BTBHits                      0                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu2.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                   2115                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.usedRAS                   1981                       # Number of times the RAS was used to get a target.
 system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu2.branchPred.indirectLookups          57464                       # Number of indirect predictor lookups.
-system.cpu2.branchPred.indirectHits             46751                       # Number of indirect target hits.
-system.cpu2.branchPred.indirectMisses           10713                       # Number of indirect misses.
-system.cpu2.branchPredindirectMispredicted         1349                       # Number of mispredicted indirect branches.
-system.cpu2.pwrStateResidencyTicks::ON      123936000                       # Cumulative time (in ticks) in various power states
-system.cpu2.numCycles                          192112                       # number of cpu cycles simulated
+system.cpu2.branchPred.indirectLookups          52178                       # Number of indirect predictor lookups.
+system.cpu2.branchPred.indirectHits             41452                       # Number of indirect target hits.
+system.cpu2.branchPred.indirectMisses           10726                       # Number of indirect misses.
+system.cpu2.branchPredindirectMispredicted         1295                       # Number of mispredicted indirect branches.
+system.cpu2.pwrStateResidencyTicks::ON      124830000                       # Cumulative time (in ticks) in various power states
+system.cpu2.numCycles                          191431                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles             39817                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                        356778                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                      66096                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches             48866                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                       146191                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                   5129                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.icacheStallCycles             42696                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                        319764                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                      60250                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches             43433                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                       142400                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                   4955                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu2.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles         1920                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.IcacheWaitRetryStallCycles            3                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                    28579                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                  972                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples            190509                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.872762                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.344982                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.PendingTrapStallCycles         2218                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines                    31580                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                  988                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples            189804                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.684706                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.290533                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                   72004     37.80%     37.80% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                   58377     30.64%     68.44% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                    8422      4.42%     72.86% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                    3406      1.79%     74.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                     670      0.35%     75.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                   36267     19.04%     94.04% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                    1053      0.55%     94.59% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                    1474      0.77%     95.36% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                    8836      4.64%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                   80855     42.60%     42.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                   54436     28.68%     71.28% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                    9994      5.27%     76.54% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                    3383      1.78%     78.33% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                     680      0.36%     78.69% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                   29156     15.36%     94.05% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                    1157      0.61%     94.66% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                    1395      0.73%     95.39% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                    8748      4.61%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total              190509                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.344049                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.857135                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                   22990                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles                70899                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                    89451                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles                 4595                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                  2564                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts                324452                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                  2564                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                   24019                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                  34614                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles         13407                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                    89996                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles                25899                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts                317685                       # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents                 22128                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                    16                       # Number of times rename has blocked due to LQ full
+system.cpu2.fetch.rateDist::total              189804                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.314735                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.670388                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                   22561                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles                83775                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                    75624                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles                 5357                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                  2477                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts                288545                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                  2477                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                   23562                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                  41928                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles         13956                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                    76490                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles                31381                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts                281938                       # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents                 27181                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                    13                       # Number of times rename has blocked due to LQ full
 system.cpu2.rename.FullRegisterEvents               2                       # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands             221990                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups               601950                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups          469192                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups               40                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps               192480                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                   29510                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts              1686                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts          1819                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                    31415                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads               86703                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores              40578                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads            41384                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores           34173                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                    258235                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded               8782                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                   258833                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued               83                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined          25653                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined        20039                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved          1265                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples       190509                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.358639                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.384430                       # Number of insts issued each cycle
+system.cpu2.rename.RenamedOperands             195781                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups               524561                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups          411315                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups               32                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps               166026                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                   29755                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts              1653                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts          1783                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                    36818                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads               74139                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores              33614                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads            35848                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores           27180                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                    226553                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded              10243                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                   228568                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued              140                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined          25915                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined        20426                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved          1250                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples       189804                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.204232                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.376602                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0              76931     40.38%     40.38% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1              28046     14.72%     55.10% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2              39341     20.65%     75.75% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3              39028     20.49%     96.24% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4               3604      1.89%     98.13% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5               1759      0.92%     99.06% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6               1073      0.56%     99.62% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7                444      0.23%     99.85% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8                283      0.15%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0              85980     45.30%     45.30% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1              32313     17.02%     62.32% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2              32235     16.98%     79.31% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3              31990     16.85%     96.16% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4               3688      1.94%     98.10% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5               1698      0.89%     99.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6               1058      0.56%     99.56% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7                511      0.27%     99.83% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8                331      0.17%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total         190509                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total         189804                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                    204     42.15%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     42.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                    51     10.54%     52.69% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                  229     47.31%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                    232     44.96%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     44.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                    58     11.24%     56.20% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                  226     43.80%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu               126867     49.02%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead               92395     35.70%     84.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite              39571     15.29%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu               114651     50.16%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     50.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead               81333     35.58%     85.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite              32584     14.26%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total                258833                       # Type of FU issued
-system.cpu2.iq.rate                          1.347303                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                        484                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001870                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads            708742                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes           292626                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses       254835                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total                228568                       # Type of FU issued
+system.cpu2.iq.rate                          1.193997                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                        516                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.002258                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads            647596                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes           262684                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses       224391                       # Number of integer instruction queue wakeup accesses
 system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes                80                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_writes                64                       # Number of floating instruction queue writes
 system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses                259317                       # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses                229084                       # Number of integer alu accesses
 system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads           34129                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads           27120                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads         4624                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses           33                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation           36                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores         2677                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads         4546                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses           31                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation           37                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores         2695                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                  2564                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                   9290                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles                   55                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts             309688                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts              288                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts                86703                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts               40578                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts              1561                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                    34                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles                  2477                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                  10821                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles                   53                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts             273857                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts              388                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts                74139                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts               33614                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts              1537                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                    28                       # Number of times the IQ has become full, causing a stall
 system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents            36                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect           443                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect         2684                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts                3127                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts               256258                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts                85016                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts             2575                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents            37                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect           461                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect         2611                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts                3072                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts               225860                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts                72453                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts             2708                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        42671                       # number of nop insts executed
-system.cpu2.iew.exec_refs                      124288                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                   53042                       # Number of branches executed
-system.cpu2.iew.exec_stores                     39272                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.333899                       # Inst execution rate
-system.cpu2.iew.wb_sent                        255341                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                       254835                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                   142252                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                   149928                       # num instructions consuming a value
-system.cpu2.iew.wb_rate                      1.326492                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.948802                       # average fanout of values written-back
-system.cpu2.commit.commitSquashedInsts          26847                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls           7517                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts             2486                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples       185379                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.525604                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.006612                       # Number of insts commited each cycle
+system.cpu2.iew.exec_nop                        37061                       # number of nop insts executed
+system.cpu2.iew.exec_refs                      104703                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                   47570                       # Number of branches executed
+system.cpu2.iew.exec_stores                     32250                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.179851                       # Inst execution rate
+system.cpu2.iew.wb_sent                        224905                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                       224391                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                   122751                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                   130504                       # num instructions consuming a value
+system.cpu2.iew.wb_rate                      1.172177                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.940592                       # average fanout of values written-back
+system.cpu2.commit.commitSquashedInsts          27003                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls           8993                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts             2399                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples       184731                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.336127                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.921991                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0        83888     45.25%     45.25% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1        49216     26.55%     71.80% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2         5545      2.99%     74.79% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3         8151      4.40%     79.19% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4         1274      0.69%     79.88% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5        34338     18.52%     98.40% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6          700      0.38%     98.78% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7         1066      0.58%     99.35% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8         1201      0.65%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0        94349     51.07%     51.07% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1        43685     23.65%     74.72% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2         5440      2.94%     77.67% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3         9609      5.20%     82.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4         1281      0.69%     83.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5        27371     14.82%     98.38% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6          737      0.40%     98.78% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7         1041      0.56%     99.34% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8         1218      0.66%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total       185379                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts              282815                       # Number of instructions committed
-system.cpu2.commit.committedOps                282815                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total       184731                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts              246824                       # Number of instructions committed
+system.cpu2.commit.committedOps                246824                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                        119980                       # Number of memory references committed
-system.cpu2.commit.loads                        82079                       # Number of loads committed
-system.cpu2.commit.membars                       6800                       # Number of memory barriers committed
-system.cpu2.commit.branches                     50664                       # Number of branches committed
+system.cpu2.commit.refs                        100512                       # Number of memory references committed
+system.cpu2.commit.loads                        69593                       # Number of loads committed
+system.cpu2.commit.membars                       8278                       # Number of memory barriers committed
+system.cpu2.commit.branches                     45154                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                   192763                       # Number of committed integer instructions.
+system.cpu2.commit.int_insts                   167790                       # Number of committed integer instructions.
 system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        41451     14.66%     14.66% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu          114584     40.52%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult              0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.17% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead          88879     31.43%     86.60% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite         37901     13.40%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::No_OpClass        35943     14.56%     14.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu          102091     41.36%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult              0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead          77871     31.55%     87.47% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite         30919     12.53%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total           282815                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events                 1201                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                      493254                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     624500                       # The number of ROB writes
-system.cpu2.timesIdled                            220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                           1603                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                       47823                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                     234564                       # Number of Instructions Simulated
-system.cpu2.committedOps                       234564                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              0.819017                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.819017                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.220975                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.220975                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                  437605                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 204427                       # number of integer regfile writes
+system.cpu2.commit.op_class_0::total           246824                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events                 1218                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                      456754                       # The number of ROB reads
+system.cpu2.rob.rob_writes                     552779                       # The number of ROB writes
+system.cpu2.timesIdled                            204                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                           1627                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                       49789                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                     202603                       # Number of Instructions Simulated
+system.cpu2.committedOps                       202603                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              0.944858                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.944858                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.058360                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.058360                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                  379324                       # number of integer regfile reads
+system.cpu2.int_regfile_writes                 178066                       # number of integer regfile writes
 system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                 126238                       # number of misc regfile reads
+system.cpu2.misc_regfile_reads                 106600                       # number of misc regfile reads
 system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
-system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
+system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
 system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           26.114184                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              45075                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs          1502.500000                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse           24.613342                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs              38229                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs               31                       # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs          1233.193548                       # Average number of references to valid blocks.
 system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.114184                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.051004                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.051004                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_blocks::cpu2.data    24.613342                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.048073                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.048073                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024           31                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           355312                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          355312                       # Number of data accesses
-system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.cpu2.dcache.ReadReq_hits::cpu2.data        50364                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          50364                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        37691                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         37691                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        88055                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           88055                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        88055                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          88055                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          498                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          498                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           58                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          637                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           637                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          637                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          637                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      3990000                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      3990000                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2835500                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      2835500                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       366500                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       366500                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data      6825500                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total      6825500                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data      6825500                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total      6825500                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        50862                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        50862                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        37830                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        37830                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           71                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        88692                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        88692                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        88692                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        88692                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.009791                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.009791                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003674                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.003674                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.816901                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.816901                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.007182                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.007182                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.007182                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.007182                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data  8012.048193                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total  8012.048193                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20399.280576                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 20399.280576                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  6318.965517                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total  6318.965517                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10715.070644                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 10715.070644                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10715.070644                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 10715.070644                       # average overall miss latency
+system.cpu2.dcache.tags.occ_task_id_percent::1024     0.060547                       # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses           305153                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          305153                       # Number of data accesses
+system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.cpu2.dcache.ReadReq_hits::cpu2.data        44839                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          44839                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        30714                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         30714                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           16                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        75553                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           75553                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        75553                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          75553                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          467                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          467                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          136                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          136                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           53                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           53                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          603                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           603                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          603                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          603                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      3772500                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total      3772500                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3722500                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      3722500                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       339500                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total       339500                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data      7495000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total      7495000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data      7495000                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total      7495000                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        45306                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        45306                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        30850                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        30850                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           69                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        76156                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        76156                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        76156                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        76156                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.010308                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.010308                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004408                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.004408                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.768116                       # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total     0.768116                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.007918                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.007918                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.007918                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.007918                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data  8078.158458                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total  8078.158458                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 27371.323529                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 27371.323529                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  6405.660377                       # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total  6405.660377                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 12429.519071                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 12429.519071                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 12429.519071                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 12429.519071                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          331                       # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total          331                       # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          301                       # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total          301                       # number of ReadReq MSHR hits
 system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           34                       # number of WriteReq MSHR hits
 system.cpu2.dcache.WriteReq_mshr_hits::total           34                       # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data          365                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total          365                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data          365                       # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total          365                       # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          167                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          167                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          105                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           58                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          272                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          272                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          272                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          272                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1193000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1193000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1388000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1388000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       308500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       308500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      2581000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      2581000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      2581000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      2581000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003283                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003283                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002776                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002776                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.816901                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.816901                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003067                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.003067                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003067                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.003067                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  7143.712575                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  7143.712575                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13219.047619                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13219.047619                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  5318.965517                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  5318.965517                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data  9488.970588                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total  9488.970588                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data  9488.970588                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total  9488.970588                       # average overall mshr miss latency
-system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.cpu2.icache.tags.replacements              578                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           95.404705                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs              27742                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs              710                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs            39.073239                       # Average number of references to valid blocks.
+system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data            1                       # number of SwapReq MSHR hits
+system.cpu2.dcache.SwapReq_mshr_hits::total            1                       # number of SwapReq MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data          335                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total          335                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data          335                       # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total          335                       # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          166                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          166                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          102                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total          102                       # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           52                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total           52                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          268                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          268                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1217000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1217000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1941500                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1941500                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       286500                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total       286500                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3158500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      3158500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3158500                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      3158500                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003664                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003664                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003306                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003306                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.753623                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.753623                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003519                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.003519                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003519                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.003519                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  7331.325301                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  7331.325301                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19034.313725                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19034.313725                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  5509.615385                       # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  5509.615385                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11785.447761                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11785.447761                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11785.447761                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11785.447761                       # average overall mshr miss latency
+system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.cpu2.icache.tags.replacements              564                       # number of replacements
+system.cpu2.icache.tags.tagsinuse           92.356205                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs              30734                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs              702                       # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs            43.780627                       # Average number of references to valid blocks.
 system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    95.404705                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.186337                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.186337                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024          132                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_blocks::cpu2.inst    92.356205                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.180383                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.180383                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024     0.257812                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses            29289                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses           29289                       # Number of data accesses
-system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.cpu2.icache.ReadReq_hits::cpu2.inst        27742                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total          27742                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst        27742                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total           27742                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst        27742                       # number of overall hits
-system.cpu2.icache.overall_hits::total          27742                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          837                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          837                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          837                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           837                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          837                       # number of overall misses
-system.cpu2.icache.overall_misses::total          837                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     12852000                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total     12852000                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst     12852000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total     12852000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst     12852000                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total     12852000                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst        28579                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total        28579                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst        28579                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total        28579                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst        28579                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total        28579                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.029287                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.029287                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.029287                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.029287                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.029287                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.029287                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15354.838710                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 15354.838710                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15354.838710                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 15354.838710                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15354.838710                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 15354.838710                       # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs           69                       # number of cycles access was blocked
+system.cpu2.icache.tags.occ_task_id_percent::1024     0.269531                       # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses            32282                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses           32282                       # Number of data accesses
+system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.cpu2.icache.ReadReq_hits::cpu2.inst        30734                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total          30734                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst        30734                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total           30734                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst        30734                       # number of overall hits
+system.cpu2.icache.overall_hits::total          30734                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          846                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          846                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          846                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           846                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          846                       # number of overall misses
+system.cpu2.icache.overall_misses::total          846                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     12713000                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total     12713000                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst     12713000                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total     12713000                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst     12713000                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total     12713000                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst        31580                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total        31580                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst        31580                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total        31580                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst        31580                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total        31580                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.026789                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.026789                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.026789                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.026789                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.026789                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.026789                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15027.186761                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 15027.186761                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15027.186761                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 15027.186761                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15027.186761                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 15027.186761                       # average overall miss latency
+system.cpu2.icache.blocked_cycles::no_mshrs           48                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                3                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs           23                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs           24                       # average number of cycles each access was blocked
 system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.writebacks::writebacks          578                       # number of writebacks
-system.cpu2.icache.writebacks::total              578                       # number of writebacks
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst          127                       # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total          127                       # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst          127                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total          127                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst          127                       # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total          127                       # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          710                       # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total          710                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst          710                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total          710                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst          710                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total          710                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     10853000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total     10853000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     10853000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total     10853000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     10853000                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total     10853000                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.024843                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.024843                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.024843                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.024843                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.024843                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.024843                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15285.915493                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15285.915493                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15285.915493                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 15285.915493                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15285.915493                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 15285.915493                       # average overall mshr miss latency
-system.cpu3.branchPred.lookups                  58058                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted            50256                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect             2406                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups               50211                       # Number of BTB lookups
+system.cpu2.icache.writebacks::writebacks          564                       # number of writebacks
+system.cpu2.icache.writebacks::total              564                       # number of writebacks
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst          144                       # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total          144                       # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst          144                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total          144                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst          144                       # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total          144                       # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          702                       # number of ReadReq MSHR misses
+system.cpu2.icache.ReadReq_mshr_misses::total          702                       # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst          702                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total          702                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses::cpu2.inst          702                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_misses::total          702                       # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     10591000                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total     10591000                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     10591000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total     10591000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     10591000                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total     10591000                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.022229                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.022229                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.022229                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.022229                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.022229                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.022229                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15086.894587                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15086.894587                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15086.894587                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 15086.894587                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15086.894587                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 15086.894587                       # average overall mshr miss latency
+system.cpu3.branchPred.lookups                  65607                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted            57989                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect             2329                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups               57945                       # Number of BTB lookups
 system.cpu3.branchPred.BTBHits                      0                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu3.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                   1984                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.usedRAS                   1972                       # Number of times the RAS was used to get a target.
 system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu3.branchPred.indirectLookups          50211                       # Number of indirect predictor lookups.
-system.cpu3.branchPred.indirectHits             39339                       # Number of indirect target hits.
-system.cpu3.branchPred.indirectMisses           10872                       # Number of indirect misses.
-system.cpu3.branchPredindirectMispredicted         1290                       # Number of mispredicted indirect branches.
-system.cpu3.pwrStateResidencyTicks::ON      123936000                       # Cumulative time (in ticks) in various power states
-system.cpu3.numCycles                          191755                       # number of cpu cycles simulated
+system.cpu3.branchPred.indirectLookups          57945                       # Number of indirect predictor lookups.
+system.cpu3.branchPred.indirectHits             47394                       # Number of indirect target hits.
+system.cpu3.branchPred.indirectMisses           10551                       # Number of indirect misses.
+system.cpu3.branchPredindirectMispredicted         1239                       # Number of mispredicted indirect branches.
+system.cpu3.pwrStateResidencyTicks::ON      124830000                       # Cumulative time (in ticks) in various power states
+system.cpu3.numCycles                          191064                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles             44345                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                        305380                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                      58058                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches             41323                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                       141573                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                   4965                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.icacheStallCycles             38959                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                        355945                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                      65607                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches             49366                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                       146283                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                   4811                       # Number of cycles fetch has spent squashing
 system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu3.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles         1720                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines                    32940                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes                  916                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples            190133                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.606139                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.261267                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.PendingTrapStallCycles         1648                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines                    27872                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes                  954                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples            189308                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.880243                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.334212                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                   84706     44.55%     44.55% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                   53051     27.90%     72.45% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                   10689      5.62%     78.07% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                    3433      1.81%     79.88% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                     679      0.36%     80.24% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                   26352     13.86%     94.10% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                    1085      0.57%     94.67% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                    1438      0.76%     95.42% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                    8700      4.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                   70601     37.29%     37.29% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                   58551     30.93%     68.22% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                    8289      4.38%     72.60% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                    3543      1.87%     74.47% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                     620      0.33%     74.80% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                   36795     19.44%     94.24% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                    1123      0.59%     94.83% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                    1294      0.68%     95.51% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                    8492      4.49%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total              190133                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.302772                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       1.592553                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                   22846                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles                89002                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                    70141                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles                 5652                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                  2482                       # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts                273868                       # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles                  2482                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                   23847                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                  45287                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles         13384                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                    70737                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles                34386                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts                267452                       # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents                 29592                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                    13                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.RenamedOperands             184677                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups               492576                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups          387264                       # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups               20                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps               155405                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                   29272                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts              1682                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts          1811                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                    39856                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads               69050                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores              30771                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads            33750                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores           24332                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                    213083                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded              11008                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                   216315                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued               53                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined          25213                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined        19048                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved          1289                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples       190133                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        1.137704                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.357547                       # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total              189308                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.343377                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       1.862962                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                   22011                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles                70196                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                    90137                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles                 4549                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                  2405                       # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts                325577                       # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles                  2405                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                   23040                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                  34162                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles         13425                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                    90919                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles                25347                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts                318974                       # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents                 21885                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
+system.cpu3.rename.RenamedOperands             222576                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups               605183                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups          471258                       # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups               38                       # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps               194403                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                   28173                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts              1623                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts          1757                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                    30798                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads               87479                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores              41118                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads            41854                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores           34728                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                    259350                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded               8662                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                   260097                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued              100                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined          24362                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined        19655                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved          1213                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples       189308                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        1.373936                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.388628                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0              89784     47.22%     47.22% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1              34463     18.13%     65.35% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2              29348     15.44%     80.78% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3              29336     15.43%     96.21% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4               3681      1.94%     98.15% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5               1744      0.92%     99.07% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6               1040      0.55%     99.61% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7                432      0.23%     99.84% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8                305      0.16%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0              75622     39.95%     39.95% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1              27531     14.54%     54.49% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2              39579     20.91%     75.40% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3              39359     20.79%     96.19% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4               3671      1.94%     98.13% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5               1727      0.91%     99.04% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6               1045      0.55%     99.59% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7                450      0.24%     99.83% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8                324      0.17%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total         190133                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total         189308                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                    189     39.38%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     39.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                    53     11.04%     50.42% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite                  238     49.58%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                    198     41.42%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     41.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                    48     10.04%     51.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite                  232     48.54%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu               109511     50.63%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     50.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead               77010     35.60%     86.23% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite              29794     13.77%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu               126919     48.80%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.80% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead               93130     35.81%     84.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite              40048     15.40%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total                216315                       # Type of FU issued
-system.cpu3.iq.rate                          1.128080                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                        480                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.002219                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads            623296                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes           249298                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses       212257                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total                260097                       # Type of FU issued
+system.cpu3.iq.rate                          1.361308                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                        478                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.001838                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads            710080                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes           292336                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses       256163                       # Number of integer instruction queue wakeup accesses
 system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes                40                       # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_writes                76                       # Number of floating instruction queue writes
 system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses                216795                       # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses                260575                       # Number of integer alu accesses
 system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads           24283                       # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads           34620                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads         4403                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses           27                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation           34                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores         2689                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads         4474                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses           40                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation           38                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores         2718                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                  2482                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                  11408                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles                   53                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts             259073                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts              473                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts                69050                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts               30771                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts              1541                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                    26                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles                  2405                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                   9114                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles                   55                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts             311067                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts              408                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts                87479                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts               41118                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts              1508                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                    34                       # Number of times the IQ has become full, causing a stall
 system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents            34                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect           490                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect         2580                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts                3070                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts               213662                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts                67471                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts             2653                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents            38                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect           450                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect         2479                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts                2929                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts               257518                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts                85797                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts             2579                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        34982                       # number of nop insts executed
-system.cpu3.iew.exec_refs                       96956                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                   45328                       # Number of branches executed
-system.cpu3.iew.exec_stores                     29485                       # Number of stores executed
-system.cpu3.iew.exec_rate                    1.114245                       # Inst execution rate
-system.cpu3.iew.wb_sent                        212766                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                       212257                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                   115033                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                   122695                       # num instructions consuming a value
-system.cpu3.iew.wb_rate                      1.106918                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.937552                       # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts          26335                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls           9719                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts             2406                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples       185183                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     1.256660                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.878907                       # Number of insts commited each cycle
+system.cpu3.iew.exec_nop                        43055                       # number of nop insts executed
+system.cpu3.iew.exec_refs                      125534                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                   53219                       # Number of branches executed
+system.cpu3.iew.exec_stores                     39737                       # Number of stores executed
+system.cpu3.iew.exec_rate                    1.347810                       # Inst execution rate
+system.cpu3.iew.wb_sent                        256666                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                       256163                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                   143359                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                   150866                       # num instructions consuming a value
+system.cpu3.iew.wb_rate                      1.340718                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.950241                       # average fanout of values written-back
+system.cpu3.commit.commitSquashedInsts          25509                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls           7449                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts             2329                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples       184454                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     1.547985                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     2.017686                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0        99076     53.50%     53.50% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1        41559     22.44%     75.94% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2         5388      2.91%     78.85% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3        10319      5.57%     84.43% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4         1252      0.68%     85.10% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5        24567     13.27%     98.37% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6          787      0.42%     98.79% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7         1025      0.55%     99.35% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8         1210      0.65%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0        82386     44.66%     44.66% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1        49463     26.82%     71.48% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2         5369      2.91%     74.39% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3         8071      4.38%     78.77% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4         1252      0.68%     79.45% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5        34869     18.90%     98.35% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6          786      0.43%     98.78% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7         1015      0.55%     99.33% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8         1243      0.67%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total       185183                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts              232712                       # Number of instructions committed
-system.cpu3.commit.committedOps                232712                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total       184454                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts              285532                       # Number of instructions committed
+system.cpu3.commit.committedOps                285532                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                         92729                       # Number of memory references committed
-system.cpu3.commit.loads                        64647                       # Number of loads committed
-system.cpu3.commit.membars                       9005                       # Number of memory barriers committed
-system.cpu3.commit.branches                     43044                       # Number of branches committed
+system.cpu3.commit.refs                        121405                       # Number of memory references committed
+system.cpu3.commit.loads                        83005                       # Number of loads committed
+system.cpu3.commit.membars                       6731                       # Number of memory barriers committed
+system.cpu3.commit.branches                     51096                       # Number of branches committed
 system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                   157897                       # Number of committed integer instructions.
+system.cpu3.commit.int_insts                   194617                       # Number of committed integer instructions.
 system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu3.commit.op_class_0::No_OpClass        33834     14.54%     14.54% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu           97144     41.74%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult              0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv               0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.28% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead          73652     31.65%     87.93% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite         28082     12.07%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::No_OpClass        41882     14.67%     14.67% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu          115514     40.46%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult              0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv               0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead          89736     31.43%     86.55% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite         38400     13.45%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total           232712                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events                 1210                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                      442434                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     523106                       # The number of ROB writes
-system.cpu3.timesIdled                            214                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                           1622                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                       48179                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                     189873                       # Number of Instructions Simulated
-system.cpu3.committedOps                       189873                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.009912                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.009912                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.990185                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.990185                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                  355771                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 167240                       # number of integer regfile writes
+system.cpu3.commit.op_class_0::total           285532                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events                 1243                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                      493666                       # The number of ROB reads
+system.cpu3.rob.rob_writes                     626988                       # The number of ROB writes
+system.cpu3.timesIdled                            229                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                           1756                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                       50157                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                     236919                       # Number of Instructions Simulated
+system.cpu3.committedOps                       236919                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              0.806453                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        0.806453                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              1.239998                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        1.239998                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                  440410                       # number of integer regfile reads
+system.cpu3.int_regfile_writes                 205469                       # number of integer regfile writes
 system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu3.misc_regfile_reads                  98845                       # number of misc regfile reads
+system.cpu3.misc_regfile_reads                 127408                       # number of misc regfile reads
 system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
-system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
+system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
 system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           24.519752                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              35385                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs          1179.500000                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse           25.184575                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs              45468                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs          1567.862069                       # Average number of references to valid blocks.
 system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.519752                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.047890                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.047890                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
+system.cpu3.dcache.tags.occ_blocks::cpu3.data    25.184575                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data     0.049189                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.049189                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
 system.cpu3.dcache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           285185                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          285185                       # Number of data accesses
-system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.cpu3.dcache.ReadReq_hits::cpu3.data        42713                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          42713                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        27877                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         27877                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           16                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        70590                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           70590                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        70590                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          70590                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          439                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          439                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          137                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          137                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           52                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           52                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          576                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           576                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          576                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          576                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      3185500                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      3185500                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2743000                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      2743000                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       334000                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       334000                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data      5928500                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total      5928500                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data      5928500                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total      5928500                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        43152                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        43152                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        28014                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        28014                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           68                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        71166                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        71166                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        71166                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        71166                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.010173                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.010173                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004890                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.004890                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.764706                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.764706                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.008094                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.008094                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.008094                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.008094                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data  7256.264237                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total  7256.264237                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20021.897810                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 20021.897810                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  6423.076923                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total  6423.076923                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10292.534722                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 10292.534722                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10292.534722                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 10292.534722                       # average overall miss latency
+system.cpu3.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
+system.cpu3.dcache.tags.tag_accesses           358446                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          358446                       # Number of data accesses
+system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.cpu3.dcache.ReadReq_hits::cpu3.data        50650                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          50650                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        38188                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         38188                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           12                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        88838                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           88838                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        88838                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          88838                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          496                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          496                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          140                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           60                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           60                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          636                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           636                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          636                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          636                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      3601500                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      3601500                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2913500                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      2913500                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       356500                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total       356500                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data      6515000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total      6515000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data      6515000                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total      6515000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        51146                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        51146                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        38328                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        38328                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           72                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           72                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        89474                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        89474                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        89474                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        89474                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.009698                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.009698                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003653                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.003653                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.833333                       # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total     0.833333                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.007108                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.007108                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.007108                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.007108                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data  7261.088710                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total  7261.088710                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20810.714286                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 20810.714286                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  5941.666667                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total  5941.666667                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10243.710692                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 10243.710692                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10243.710692                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 10243.710692                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          281                       # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_hits::total          281                       # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           33                       # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          326                       # number of ReadReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_hits::total          326                       # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           35                       # number of WriteReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::total           35                       # number of WriteReq MSHR hits
 system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data            1                       # number of SwapReq MSHR hits
 system.cpu3.dcache.SwapReq_mshr_hits::total            1                       # number of SwapReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits::cpu3.data          314                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_hits::total          314                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits::cpu3.data          314                       # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_hits::total          314                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          158                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          158                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          104                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           51                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           51                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          262                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          262                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          262                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          262                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1084000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1084000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1390500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1390500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       282000                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       282000                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2474500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      2474500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2474500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      2474500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003661                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003661                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003712                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003712                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.750000                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.750000                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003682                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.003682                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003682                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.003682                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  6860.759494                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  6860.759494                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13370.192308                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13370.192308                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  5529.411765                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  5529.411765                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9444.656489                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9444.656489                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9444.656489                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9444.656489                       # average overall mshr miss latency
-system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.cpu3.icache.tags.replacements              578                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           92.680953                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs              32101                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs              713                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs            45.022440                       # Average number of references to valid blocks.
+system.cpu3.dcache.demand_mshr_hits::cpu3.data          361                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_hits::total          361                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits::cpu3.data          361                       # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_hits::total          361                       # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          170                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          170                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          105                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           59                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           59                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          275                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          275                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          275                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          275                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1125000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1125000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1450500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1450500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       296500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total       296500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2575500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      2575500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2575500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      2575500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003324                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003324                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002740                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002740                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.819444                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.819444                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003074                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.003074                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003074                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.003074                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  6617.647059                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  6617.647059                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13814.285714                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13814.285714                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  5025.423729                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  5025.423729                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9365.454545                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9365.454545                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9365.454545                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9365.454545                       # average overall mshr miss latency
+system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.cpu3.icache.tags.replacements              586                       # number of replacements
+system.cpu3.icache.tags.tagsinuse           96.347148                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs              27016                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.sampled_refs              724                       # Sample count of references to valid blocks.
+system.cpu3.icache.tags.avg_refs            37.314917                       # Average number of references to valid blocks.
 system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    92.680953                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.181017                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.181017                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024     0.263672                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses            33653                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses           33653                       # Number of data accesses
-system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.cpu3.icache.ReadReq_hits::cpu3.inst        32101                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total          32101                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst        32101                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total           32101                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst        32101                       # number of overall hits
-system.cpu3.icache.overall_hits::total          32101                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          839                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          839                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          839                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           839                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          839                       # number of overall misses
-system.cpu3.icache.overall_misses::total          839                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     11633500                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total     11633500                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst     11633500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total     11633500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst     11633500                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total     11633500                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst        32940                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total        32940                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst        32940                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total        32940                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst        32940                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total        32940                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.025471                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.025471                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.025471                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.025471                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.025471                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.025471                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13865.911800                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 13865.911800                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13865.911800                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 13865.911800                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13865.911800                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 13865.911800                       # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.icache.tags.occ_blocks::cpu3.inst    96.347148                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.188178                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.188178                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024     0.269531                       # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses            28596                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses           28596                       # Number of data accesses
+system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.cpu3.icache.ReadReq_hits::cpu3.inst        27016                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total          27016                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst        27016                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total           27016                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst        27016                       # number of overall hits
+system.cpu3.icache.overall_hits::total          27016                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          856                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          856                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          856                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           856                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          856                       # number of overall misses
+system.cpu3.icache.overall_misses::total          856                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     12888000                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total     12888000                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst     12888000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total     12888000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst     12888000                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total     12888000                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst        27872                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total        27872                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst        27872                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total        27872                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst        27872                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total        27872                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.030712                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.030712                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.030712                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.030712                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.030712                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.030712                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15056.074766                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 15056.074766                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15056.074766                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 15056.074766                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15056.074766                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 15056.074766                       # average overall miss latency
+system.cpu3.icache.blocked_cycles::no_mshrs           17                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs           17                       # average number of cycles each access was blocked
 system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.writebacks::writebacks          578                       # number of writebacks
-system.cpu3.icache.writebacks::total              578                       # number of writebacks
-system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst          126                       # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_hits::total          126                       # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits::cpu3.inst          126                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_hits::total          126                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits::cpu3.inst          126                       # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_hits::total          126                       # number of overall MSHR hits
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          713                       # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total          713                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst          713                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total          713                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst          713                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total          713                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     10107000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total     10107000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     10107000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total     10107000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     10107000                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total     10107000                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.021645                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.021645                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.021645                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.021645                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.021645                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.021645                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 14175.315568                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 14175.315568                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 14175.315568                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 14175.315568                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 14175.315568                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 14175.315568                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
+system.cpu3.icache.writebacks::writebacks          586                       # number of writebacks
+system.cpu3.icache.writebacks::total              586                       # number of writebacks
+system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst          132                       # number of ReadReq MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::total          132                       # number of ReadReq MSHR hits
+system.cpu3.icache.demand_mshr_hits::cpu3.inst          132                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_hits::total          132                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits::cpu3.inst          132                       # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_hits::total          132                       # number of overall MSHR hits
+system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          724                       # number of ReadReq MSHR misses
+system.cpu3.icache.ReadReq_mshr_misses::total          724                       # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses::cpu3.inst          724                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.demand_mshr_misses::total          724                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses::cpu3.inst          724                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_misses::total          724                       # number of overall MSHR misses
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     11106000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total     11106000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     11106000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total     11106000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     11106000                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total     11106000                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.025976                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.025976                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.025976                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.025976                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.025976                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.025976                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 15339.779006                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 15339.779006                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 15339.779006                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 15339.779006                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 15339.779006                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 15339.779006                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
 system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  567.287206                       # Cycle average of tags in use
-system.l2c.tags.total_refs                       3156                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                      709                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.451340                       # Average number of references to valid blocks.
+system.l2c.tags.tagsinuse                  566.391309                       # Cycle average of tags in use
+system.l2c.tags.total_refs                       3152                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                      716                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.402235                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::cpu0.inst      303.185096                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data      145.120224                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst       69.165941                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       16.093016                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst        8.947029                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data       10.727803                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        4.254567                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        9.793531                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::cpu0.inst       0.004626                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.002214                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.001055                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.000246                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.000137                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.000164                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.000065                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.000149                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.008656                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          709                       # Occupied blocks per task id
+system.l2c.tags.occ_blocks::cpu0.inst      300.631868                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data      144.597180                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst       70.863487                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data       15.770640                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst        7.294857                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data       10.082216                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst        7.192526                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data        9.958536                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::cpu0.inst       0.004587                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.002206                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.001081                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.000241                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.000111                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.000154                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.000110                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data       0.000152                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.008642                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          716                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          487                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.010818                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    31781                       # Number of tag accesses
-system.l2c.tags.data_accesses                   31781                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.age_task_id_blocks_1024::1          177                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          484                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.010925                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                    31812                       # Number of tag accesses
+system.l2c.tags.data_accesses                   31812                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
 system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
 system.l2c.WritebackDirty_hits::total               1                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks          719                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total             719                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data              24                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              19                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              22                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3.data              23                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  88                       # number of UpgradeReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst           334                       # number of ReadCleanReq hits
+system.l2c.WritebackClean_hits::writebacks          730                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total             730                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data              23                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              22                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data              25                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3.data              20                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  90                       # number of UpgradeReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst           318                       # number of ReadCleanReq hits
 system.l2c.ReadCleanReq_hits::cpu1.inst           594                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst           687                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst           700                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total              2315                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst           679                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst           707                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total              2298                       # number of ReadCleanReq hits
 system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu1.data            5                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu2.data           11                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu3.data           11                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::total               32                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst                 334                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst                 318                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.inst                 594                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 687                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                 679                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                 700                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst                 707                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    2347                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                334                       # number of overall hits
+system.l2c.demand_hits::total                    2330                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst                318                       # number of overall hits
 system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
 system.l2c.overall_hits::cpu1.inst                594                       # number of overall hits
 system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                687                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                679                       # number of overall hits
 system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                700                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst                707                       # number of overall hits
 system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
-system.l2c.overall_hits::total                   2347                       # number of overall hits
+system.l2c.overall_hits::total                   2330                       # number of overall hits
 system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst          379                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst           93                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst          378                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst           96                       # number of ReadCleanReq misses
 system.l2c.ReadCleanReq_misses::cpu2.inst           23                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst           13                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total             508                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst           17                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total             514                       # number of ReadCleanReq misses
 system.l2c.ReadSharedReq_misses::cpu0.data           76                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data            8                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data            9                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu2.data            3                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu3.data            2                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total             89                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst               379                       # number of demand (read+write) misses
+system.l2c.ReadSharedReq_misses::total             90                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.inst               378                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.data               170                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                93                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data                21                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst                96                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data                22                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu2.inst                23                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu2.data                15                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                13                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst                17                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu3.data                14                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   728                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              379                       # number of overall misses
+system.l2c.demand_misses::total                   735                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst              378                       # number of overall misses
 system.l2c.overall_misses::cpu0.data              170                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               93                       # number of overall misses
-system.l2c.overall_misses::cpu1.data               21                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst               96                       # number of overall misses
+system.l2c.overall_misses::cpu1.data               22                       # number of overall misses
 system.l2c.overall_misses::cpu2.inst               23                       # number of overall misses
 system.l2c.overall_misses::cpu2.data               15                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst               13                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst               17                       # number of overall misses
 system.l2c.overall_misses::cpu3.data               14                       # number of overall misses
-system.l2c.overall_misses::total                  728                       # number of overall misses
-system.l2c.ReadExReq_miss_latency::cpu0.data      7826500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data      1039500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data       940000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data       937000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total     10743000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst     29388500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst      6947000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst      2007500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst      1084500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total     39427500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data      6119500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data       658500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data       265000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data       181000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total      7224000                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     29388500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data     13946000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst      6947000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data      1698000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst      2007500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data      1205000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst      1084500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data      1118000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        57394500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     29388500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data     13946000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst      6947000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data      1698000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst      2007500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data      1205000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst      1084500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data      1118000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       57394500                       # number of overall miss cycles
+system.l2c.overall_misses::total                  735                       # number of overall misses
+system.l2c.ReadExReq_miss_latency::cpu0.data      7962000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data      1092000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data      1485500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data      1007500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total     11547000                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst     32045000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst      7767000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst      1841000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst      2001000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total     43654000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data      6727000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data      1292500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data       289000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data       179500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total      8488000                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     32045000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data     14689000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst      7767000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data      2384500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst      1841000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data      1774500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst      2001000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data      1187000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total        63689000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     32045000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data     14689000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst      7767000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data      2384500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst      1841000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data      1774500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst      2001000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data      1187000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total       63689000                       # number of overall miss cycles
 system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
 system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks          719                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total          719                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           24                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           19                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           22                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           23                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              88                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks          730                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total          730                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data           23                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           25                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           20                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              90                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst          713                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst          687                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst          710                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst          713                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total          2823                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst          696                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst          690                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst          702                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst          724                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total          2812                       # number of ReadCleanReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu0.data           81                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data           13                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data           14                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu2.data           14                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu3.data           13                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total          121                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             713                       # number of demand (read+write) accesses
+system.l2c.ReadSharedReq_accesses::total          122                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst             696                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.data             175                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             687                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data              26                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             710                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst             690                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data              27                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst             702                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu2.data              26                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             713                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             724                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                3075                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            713                       # number of overall (read+write) accesses
+system.l2c.demand_accesses::total                3065                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            696                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.data            175                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            687                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data             26                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            710                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst            690                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data             27                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst            702                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu2.data             26                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            713                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            724                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               3075                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               3065                       # number of overall (read+write) accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.531557                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.135371                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.032394                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.018233                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.179950                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.543103                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.139130                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.032764                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.023481                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.182788                       # miss rate for ReadCleanReq accesses
 system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.938272                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.615385                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.642857                       # miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.214286                       # miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.153846                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.735537                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.531557                       # miss rate for demand accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.737705                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.543103                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.data       0.971429                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.135371                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.807692                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.032394                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.139130                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.814815                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.032764                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu2.data       0.576923                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.018233                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.023481                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu3.data       0.560000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.236748                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.531557                       # miss rate for overall accesses
+system.l2c.demand_miss_rate::total           0.239804                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.543103                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.data      0.971429                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.135371                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.807692                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.032394                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.139130                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.814815                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.032764                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu2.data      0.576923                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.018233                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.023481                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.data      0.560000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.236748                       # miss rate for overall accesses
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83260.638298                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79961.538462                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 78333.333333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 78083.333333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 82007.633588                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 77542.216359                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74698.924731                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 87282.608696                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 83423.076923                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 77613.188976                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80519.736842                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82312.500000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 88333.333333                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        90500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 81168.539326                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 77542.216359                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 82035.294118                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 74698.924731                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 80857.142857                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 87282.608696                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 80333.333333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 83423.076923                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 79857.142857                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 78838.598901                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 77542.216359                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 82035.294118                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 74698.924731                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 80857.142857                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 87282.608696                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 80333.333333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 83423.076923                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 79857.142857                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 78838.598901                       # average overall miss latency
+system.l2c.overall_miss_rate::total          0.239804                       # miss rate for overall accesses
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84702.127660                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data        84000                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 123791.666667                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 83958.333333                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 88145.038168                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84775.132275                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80906.250000                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 80043.478261                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 117705.882353                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 84929.961089                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88513.157895                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143611.111111                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 96333.333333                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        89750                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 94311.111111                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 84775.132275                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 86405.882353                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 80906.250000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 108386.363636                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 80043.478261                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data       118300                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 117705.882353                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 84785.714286                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 86651.700680                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 84775.132275                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 86405.882353                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 80906.250000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 108386.363636                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 80043.478261                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data       118300                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 117705.882353                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 84785.714286                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 86651.700680                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2657,211 +2667,211 @@ system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       #
 system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          377                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           89                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          376                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           92                       # number of ReadCleanReq MSHR misses
 system.l2c.ReadCleanReq_mshr_misses::cpu2.inst           14                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst           10                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total          490                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu3.inst           14                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total          496                       # number of ReadCleanReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.data           76                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data            8                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data            9                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu2.data            3                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu3.data            2                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total           89                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst          377                       # number of demand (read+write) MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total           90                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst          376                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.data          170                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst           89                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data           21                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst           92                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data           22                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu2.inst           14                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu2.data           15                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst           10                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst           14                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu3.data           14                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total              710                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst          377                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::total              717                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst          376                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.data          170                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst           89                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data           21                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst           92                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data           22                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu2.inst           14                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu2.data           15                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst           10                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst           14                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu3.data           14                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total             710                       # number of overall MSHR misses
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      6886500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       909500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       820000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       817000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total      9433000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     25557000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      5847000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      1317000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       764500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total     33485500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      5359500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data       578500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       235000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data       161000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total      6334000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     25557000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data     12246000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst      5847000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data      1488000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst      1317000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data      1055000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst       764500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data       978000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     49252500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     25557000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data     12246000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst      5847000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data      1488000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst      1317000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data      1055000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst       764500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data       978000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     49252500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_misses::total             717                       # number of overall MSHR misses
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      7022000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       962000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      1365500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       887500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total     10237000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     28190500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      6632500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      1096000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst      1627000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total     37546000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      5967000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data      1202500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       259000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data       159500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total      7588000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     28190500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data     12989000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst      6632500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data      2164500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst      1096000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data      1624500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst      1627000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data      1047000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     55371000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     28190500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data     12989000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst      6632500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data      2164500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst      1096000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data      1624500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst      1627000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data      1047000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     55371000                       # number of overall MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.528752                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.129549                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.019718                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.014025                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.173574                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.540230                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.133333                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.019943                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.019337                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.176387                       # mshr miss rate for ReadCleanReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.938272                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.615385                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.642857                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.214286                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.153846                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.735537                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.528752                       # mshr miss rate for demand accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.737705                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.540230                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu0.data     0.971429                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.129549                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.807692                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.019718                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.133333                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.814815                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.019943                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu2.data     0.576923                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.014025                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.019337                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu3.data     0.560000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.230894                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.528752                       # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::total      0.233931                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.540230                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.data     0.971429                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.129549                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.807692                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.019718                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.133333                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.814815                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.019943                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu2.data     0.576923                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.014025                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.019337                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.data     0.560000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.230894                       # mshr miss rate for overall accesses
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73260.638298                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69961.538462                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68333.333333                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 68083.333333                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 72007.633588                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67790.450928                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 65696.629213                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 94071.428571                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst        76450                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 68337.755102                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70519.736842                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72312.500000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 78333.333333                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        80500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71168.539326                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67790.450928                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72035.294118                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65696.629213                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70857.142857                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 94071.428571                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70333.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        76450                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 69857.142857                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 69369.718310                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67790.450928                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72035.294118                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65696.629213                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70857.142857                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 94071.428571                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70333.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        76450                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69857.142857                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 69369.718310                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests           957                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests          248                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.l2c.overall_mshr_miss_rate::total     0.233931                       # mshr miss rate for overall accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74702.127660                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data        74000                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 113791.666667                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 73958.333333                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 78145.038168                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74974.734043                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72092.391304                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 78285.714286                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 116214.285714                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75697.580645                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78513.157895                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133611.111111                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 86333.333333                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        79750                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84311.111111                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74974.734043                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76405.882353                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72092.391304                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98386.363636                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 78285.714286                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data       108300                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 116214.285714                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 74785.714286                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 77225.941423                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74974.734043                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76405.882353                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72092.391304                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98386.363636                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 78285.714286                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data       108300                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 116214.285714                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 74785.714286                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 77225.941423                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests           969                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests          253                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp                578                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              196                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               183                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp                585                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              194                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               190                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           578                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1666                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1666                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        45376                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   45376                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              248                       # Total snoops (count)
+system.membus.trans_dist::ReadSharedReq           585                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1685                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1685                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        45824                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   45824                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              253                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples               957                       # Request fanout histogram
+system.membus.snoop_fanout::samples               969                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     957    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     969    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 957                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              877500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 969                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              889500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3778750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              3.0                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests         6322                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests         1727                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         3289                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.respLayer1.occupancy            3809250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              3.1                       # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests         6292                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests         1720                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         3250                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED    123936000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadResp              3509                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadResp              3503                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate            8                       # Transaction distribution
 system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean         2125                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean         2099                       # Transaction distribution
 system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq             284                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp            284                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              398                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             398                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq          2823                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq          690                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1838                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          602                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1930                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          372                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1998                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          378                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         2004                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          362                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  9484                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        72000                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.trans_dist::ReadExReq              395                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp             395                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq          2812                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq          700                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1784                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          599                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1936                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          373                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1968                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          372                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         2034                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          380                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  9446                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        69632                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11264                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        79552                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        82432                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        79744                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1728                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        81024                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        82624                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        83840                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total                 332800                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                            1032                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                     53504                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples             4195                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.291538                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           1.103863                       # Request fanout histogram
+system.toL2Bus.pkt_size::total                 330496                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                            1036                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                     53888                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples             4191                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.288475                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           1.109326                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                   1306     31.13%     31.13% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                   1176     28.03%     59.17% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    897     21.38%     80.55% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                    816     19.45%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                   1322     31.54%     31.54% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                   1164     27.77%     59.32% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    879     20.97%     80.29% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                    826     19.71%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
@@ -2870,24 +2880,24 @@ system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Re
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               4195                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy            5296980                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              4.3                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy           1068997                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.9                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy            528987                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total               4191                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy            5261968                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              4.2                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy           1043496                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.8                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy            528992                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           1032995                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy           1037993                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.8                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy            438456                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy           1069486                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization             0.9                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy            439965                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy           1070997                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy            434459                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             0.3                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy           1056988                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization             0.8                       # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy            424982                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization             0.3                       # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy           1087497                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.9                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy            415480                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             0.3                       # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy            445966                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization             0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini
index 5ac78b2ee..5e98acfda 100644
--- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini
+++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cp_cntrl0 cpu dir_cntrl0 dvfs_handler mem_ctrls ruby sqc_cnt
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -58,11 +63,16 @@ L2cache=system.cp_cntrl0.L2cache
 buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=15
 l2_hit_latency=18
 mandatoryQueue=system.cp_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeToCore=system.cp_cntrl0.probeToCore
 recycle_latency=10
 requestFromCore=system.cp_cntrl0.requestFromCore
@@ -220,17 +230,22 @@ coreid=0
 dcache=system.cp_cntrl0.L1D0cache
 dcache_hit_latency=2
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.cp_cntrl0.L1Icache
 icache_hit_latency=2
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=0
 slave=system.cpu.cpuInstDataPort[0]
@@ -242,17 +257,22 @@ coreid=1
 dcache=system.cp_cntrl0.L1D1cache
 dcache_hit_latency=2
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.cp_cntrl0.L1Icache
 icache_hit_latency=2
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=1
 slave=system.cpu.cpuInstDataPort[1]
@@ -278,8 +298,13 @@ check_flush=false
 checks_to_complete=100
 clk_domain=system.clk_domain
 deadlock_threshold=50000
+default_p_state=UNDEFINED
 eventq_index=0
 num_cpus=12
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 system=system
 wakeup_frequency=10
 cpuDataPort=system.tcp_cntrl0.coalescer.slave[0] system.tcp_cntrl1.coalescer.slave[0] system.tcp_cntrl2.coalescer.slave[0] system.tcp_cntrl3.coalescer.slave[0] system.tcp_cntrl4.coalescer.slave[0] system.tcp_cntrl5.coalescer.slave[0] system.tcp_cntrl6.coalescer.slave[0] system.tcp_cntrl7.coalescer.slave[0]
@@ -296,11 +321,16 @@ TCC_select_num_bits=0
 buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.dir_cntrl0.directory
 eventq_index=0
 l3_hit_latency=15
 noTCCdir=false
 number_of_TBEs=20480
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeToCore=system.dir_cntrl0.probeToCore
 recycle_latency=10
 requestFromCores=system.dir_cntrl0.requestFromCores
@@ -420,27 +450,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -452,6 +482,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -459,12 +490,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -486,9 +522,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -502,12 +538,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=12
 number_of_virtual_networks=10
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=true
 
 [system.ruby.clk_domain]
@@ -520,18 +561,23 @@ voltage_domain=system.voltage_domain
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links00 ext_links01 ext_links02 ext_links03 ext_links04 ext_links05 ext_links06 ext_links07 ext_links08 ext_links09 ext_links10 ext_links11 ext_links12 ext_links13 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1
+children=ext_links00 ext_links01 ext_links02 ext_links03 ext_links04 ext_links05 ext_links06 ext_links07 ext_links08 ext_links09 ext_links10 ext_links11 ext_links12 ext_links13 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_link_buffers72 int_link_buffers73 int_link_buffers74 int_link_buffers75 int_link_buffers76 int_link_buffers77 int_link_buffers78 int_link_buffers79 int_links0 int_links1 int_links2 int_links3
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links00 system.ruby.network.ext_links01 system.ruby.network.ext_links02 system.ruby.network.ext_links03 system.ruby.network.ext_links04 system.ruby.network.ext_links05 system.ruby.network.ext_links06 system.ruby.network.ext_links07 system.ruby.network.ext_links08 system.ruby.network.ext_links09 system.ruby.network.ext_links10 system.ruby.network.ext_links11 system.ruby.network.ext_links12 system.ruby.network.ext_links13
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 system.ruby.network.int_link_buffers72 system.ruby.network.int_link_buffers73 system.ruby.network.int_link_buffers74 system.ruby.network.int_link_buffers75 system.ruby.network.int_link_buffers76 system.ruby.network.int_link_buffers77 system.ruby.network.int_link_buffers78 system.ruby.network.int_link_buffers79
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
 netifs=
 number_of_virtual_networks=10
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.ext_links00.int_node system.ruby.network.ext_links01.int_node system.ruby.network.ext_links02.int_node
 ruby_system=system.ruby
 topology=Crossbar
@@ -553,8 +599,14 @@ weight=1
 type=Switch
 children=port_buffers000 port_buffers001 port_buffers002 port_buffers003 port_buffers004 port_buffers005 port_buffers006 port_buffers007 port_buffers008 port_buffers009 port_buffers010 port_buffers011 port_buffers012 port_buffers013 port_buffers014 port_buffers015 port_buffers016 port_buffers017 port_buffers018 port_buffers019 port_buffers020 port_buffers021 port_buffers022 port_buffers023 port_buffers024 port_buffers025 port_buffers026 port_buffers027 port_buffers028 port_buffers029 port_buffers030 port_buffers031 port_buffers032 port_buffers033 port_buffers034 port_buffers035 port_buffers036 port_buffers037 port_buffers038 port_buffers039 port_buffers040 port_buffers041 port_buffers042 port_buffers043 port_buffers044 port_buffers045 port_buffers046 port_buffers047 port_buffers048 port_buffers049 port_buffers050 port_buffers051 port_buffers052 port_buffers053 port_buffers054 port_buffers055 port_buffers056 port_buffers057 port_buffers058 port_buffers059 port_buffers060 port_buffers061 port_buffers062 port_buffers063 port_buffers064 port_buffers065 port_buffers066 port_buffers067 port_buffers068 port_buffers069 port_buffers070 port_buffers071 port_buffers072 port_buffers073 port_buffers074 port_buffers075 port_buffers076 port_buffers077 port_buffers078 port_buffers079 port_buffers080 port_buffers081 port_buffers082 port_buffers083 port_buffers084 port_buffers085 port_buffers086 port_buffers087 port_buffers088 port_buffers089 port_buffers090 port_buffers091 port_buffers092 port_buffers093 port_buffers094 port_buffers095 port_buffers096 port_buffers097 port_buffers098 port_buffers099 port_buffers100 port_buffers101 port_buffers102 port_buffers103 port_buffers104 port_buffers105 port_buffers106 port_buffers107 port_buffers108 port_buffers109 port_buffers110 port_buffers111 port_buffers112 port_buffers113 port_buffers114 port_buffers115 port_buffers116 port_buffers117 port_buffers118 port_buffers119 port_buffers120 port_buffers121 port_buffers122 port_buffers123 port_buffers124 port_buffers125 port_buffers126 port_buffers127 port_buffers128 port_buffers129 port_buffers130 port_buffers131 port_buffers132 port_buffers133 port_buffers134 port_buffers135 port_buffers136 port_buffers137 port_buffers138 port_buffers139 port_buffers140 port_buffers141 port_buffers142 port_buffers143 port_buffers144 port_buffers145 port_buffers146 port_buffers147 port_buffers148 port_buffers149 port_buffers150 port_buffers151 port_buffers152 port_buffers153 port_buffers154 port_buffers155 port_buffers156 port_buffers157 port_buffers158 port_buffers159
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.ext_links00.int_node.port_buffers000 system.ruby.network.ext_links00.int_node.port_buffers001 system.ruby.network.ext_links00.int_node.port_buffers002 system.ruby.network.ext_links00.int_node.port_buffers003 system.ruby.network.ext_links00.int_node.port_buffers004 system.ruby.network.ext_links00.int_node.port_buffers005 system.ruby.network.ext_links00.int_node.port_buffers006 system.ruby.network.ext_links00.int_node.port_buffers007 system.ruby.network.ext_links00.int_node.port_buffers008 system.ruby.network.ext_links00.int_node.port_buffers009 system.ruby.network.ext_links00.int_node.port_buffers010 system.ruby.network.ext_links00.int_node.port_buffers011 system.ruby.network.ext_links00.int_node.port_buffers012 system.ruby.network.ext_links00.int_node.port_buffers013 system.ruby.network.ext_links00.int_node.port_buffers014 system.ruby.network.ext_links00.int_node.port_buffers015 system.ruby.network.ext_links00.int_node.port_buffers016 system.ruby.network.ext_links00.int_node.port_buffers017 system.ruby.network.ext_links00.int_node.port_buffers018 system.ruby.network.ext_links00.int_node.port_buffers019 system.ruby.network.ext_links00.int_node.port_buffers020 system.ruby.network.ext_links00.int_node.port_buffers021 system.ruby.network.ext_links00.int_node.port_buffers022 system.ruby.network.ext_links00.int_node.port_buffers023 system.ruby.network.ext_links00.int_node.port_buffers024 system.ruby.network.ext_links00.int_node.port_buffers025 system.ruby.network.ext_links00.int_node.port_buffers026 system.ruby.network.ext_links00.int_node.port_buffers027 system.ruby.network.ext_links00.int_node.port_buffers028 system.ruby.network.ext_links00.int_node.port_buffers029 system.ruby.network.ext_links00.int_node.port_buffers030 system.ruby.network.ext_links00.int_node.port_buffers031 system.ruby.network.ext_links00.int_node.port_buffers032 system.ruby.network.ext_links00.int_node.port_buffers033 system.ruby.network.ext_links00.int_node.port_buffers034 system.ruby.network.ext_links00.int_node.port_buffers035 system.ruby.network.ext_links00.int_node.port_buffers036 system.ruby.network.ext_links00.int_node.port_buffers037 system.ruby.network.ext_links00.int_node.port_buffers038 system.ruby.network.ext_links00.int_node.port_buffers039 system.ruby.network.ext_links00.int_node.port_buffers040 system.ruby.network.ext_links00.int_node.port_buffers041 system.ruby.network.ext_links00.int_node.port_buffers042 system.ruby.network.ext_links00.int_node.port_buffers043 system.ruby.network.ext_links00.int_node.port_buffers044 system.ruby.network.ext_links00.int_node.port_buffers045 system.ruby.network.ext_links00.int_node.port_buffers046 system.ruby.network.ext_links00.int_node.port_buffers047 system.ruby.network.ext_links00.int_node.port_buffers048 system.ruby.network.ext_links00.int_node.port_buffers049 system.ruby.network.ext_links00.int_node.port_buffers050 system.ruby.network.ext_links00.int_node.port_buffers051 system.ruby.network.ext_links00.int_node.port_buffers052 system.ruby.network.ext_links00.int_node.port_buffers053 system.ruby.network.ext_links00.int_node.port_buffers054 system.ruby.network.ext_links00.int_node.port_buffers055 system.ruby.network.ext_links00.int_node.port_buffers056 system.ruby.network.ext_links00.int_node.port_buffers057 system.ruby.network.ext_links00.int_node.port_buffers058 system.ruby.network.ext_links00.int_node.port_buffers059 system.ruby.network.ext_links00.int_node.port_buffers060 system.ruby.network.ext_links00.int_node.port_buffers061 system.ruby.network.ext_links00.int_node.port_buffers062 system.ruby.network.ext_links00.int_node.port_buffers063 system.ruby.network.ext_links00.int_node.port_buffers064 system.ruby.network.ext_links00.int_node.port_buffers065 system.ruby.network.ext_links00.int_node.port_buffers066 system.ruby.network.ext_links00.int_node.port_buffers067 system.ruby.network.ext_links00.int_node.port_buffers068 system.ruby.network.ext_links00.int_node.port_buffers069 system.ruby.network.ext_links00.int_node.port_buffers070 system.ruby.network.ext_links00.int_node.port_buffers071 system.ruby.network.ext_links00.int_node.port_buffers072 system.ruby.network.ext_links00.int_node.port_buffers073 system.ruby.network.ext_links00.int_node.port_buffers074 system.ruby.network.ext_links00.int_node.port_buffers075 system.ruby.network.ext_links00.int_node.port_buffers076 system.ruby.network.ext_links00.int_node.port_buffers077 system.ruby.network.ext_links00.int_node.port_buffers078 system.ruby.network.ext_links00.int_node.port_buffers079 system.ruby.network.ext_links00.int_node.port_buffers080 system.ruby.network.ext_links00.int_node.port_buffers081 system.ruby.network.ext_links00.int_node.port_buffers082 system.ruby.network.ext_links00.int_node.port_buffers083 system.ruby.network.ext_links00.int_node.port_buffers084 system.ruby.network.ext_links00.int_node.port_buffers085 system.ruby.network.ext_links00.int_node.port_buffers086 system.ruby.network.ext_links00.int_node.port_buffers087 system.ruby.network.ext_links00.int_node.port_buffers088 system.ruby.network.ext_links00.int_node.port_buffers089 system.ruby.network.ext_links00.int_node.port_buffers090 system.ruby.network.ext_links00.int_node.port_buffers091 system.ruby.network.ext_links00.int_node.port_buffers092 system.ruby.network.ext_links00.int_node.port_buffers093 system.ruby.network.ext_links00.int_node.port_buffers094 system.ruby.network.ext_links00.int_node.port_buffers095 system.ruby.network.ext_links00.int_node.port_buffers096 system.ruby.network.ext_links00.int_node.port_buffers097 system.ruby.network.ext_links00.int_node.port_buffers098 system.ruby.network.ext_links00.int_node.port_buffers099 system.ruby.network.ext_links00.int_node.port_buffers100 system.ruby.network.ext_links00.int_node.port_buffers101 system.ruby.network.ext_links00.int_node.port_buffers102 system.ruby.network.ext_links00.int_node.port_buffers103 system.ruby.network.ext_links00.int_node.port_buffers104 system.ruby.network.ext_links00.int_node.port_buffers105 system.ruby.network.ext_links00.int_node.port_buffers106 system.ruby.network.ext_links00.int_node.port_buffers107 system.ruby.network.ext_links00.int_node.port_buffers108 system.ruby.network.ext_links00.int_node.port_buffers109 system.ruby.network.ext_links00.int_node.port_buffers110 system.ruby.network.ext_links00.int_node.port_buffers111 system.ruby.network.ext_links00.int_node.port_buffers112 system.ruby.network.ext_links00.int_node.port_buffers113 system.ruby.network.ext_links00.int_node.port_buffers114 system.ruby.network.ext_links00.int_node.port_buffers115 system.ruby.network.ext_links00.int_node.port_buffers116 system.ruby.network.ext_links00.int_node.port_buffers117 system.ruby.network.ext_links00.int_node.port_buffers118 system.ruby.network.ext_links00.int_node.port_buffers119 system.ruby.network.ext_links00.int_node.port_buffers120 system.ruby.network.ext_links00.int_node.port_buffers121 system.ruby.network.ext_links00.int_node.port_buffers122 system.ruby.network.ext_links00.int_node.port_buffers123 system.ruby.network.ext_links00.int_node.port_buffers124 system.ruby.network.ext_links00.int_node.port_buffers125 system.ruby.network.ext_links00.int_node.port_buffers126 system.ruby.network.ext_links00.int_node.port_buffers127 system.ruby.network.ext_links00.int_node.port_buffers128 system.ruby.network.ext_links00.int_node.port_buffers129 system.ruby.network.ext_links00.int_node.port_buffers130 system.ruby.network.ext_links00.int_node.port_buffers131 system.ruby.network.ext_links00.int_node.port_buffers132 system.ruby.network.ext_links00.int_node.port_buffers133 system.ruby.network.ext_links00.int_node.port_buffers134 system.ruby.network.ext_links00.int_node.port_buffers135 system.ruby.network.ext_links00.int_node.port_buffers136 system.ruby.network.ext_links00.int_node.port_buffers137 system.ruby.network.ext_links00.int_node.port_buffers138 system.ruby.network.ext_links00.int_node.port_buffers139 system.ruby.network.ext_links00.int_node.port_buffers140 system.ruby.network.ext_links00.int_node.port_buffers141 system.ruby.network.ext_links00.int_node.port_buffers142 system.ruby.network.ext_links00.int_node.port_buffers143 system.ruby.network.ext_links00.int_node.port_buffers144 system.ruby.network.ext_links00.int_node.port_buffers145 system.ruby.network.ext_links00.int_node.port_buffers146 system.ruby.network.ext_links00.int_node.port_buffers147 system.ruby.network.ext_links00.int_node.port_buffers148 system.ruby.network.ext_links00.int_node.port_buffers149 system.ruby.network.ext_links00.int_node.port_buffers150 system.ruby.network.ext_links00.int_node.port_buffers151 system.ruby.network.ext_links00.int_node.port_buffers152 system.ruby.network.ext_links00.int_node.port_buffers153 system.ruby.network.ext_links00.int_node.port_buffers154 system.ruby.network.ext_links00.int_node.port_buffers155 system.ruby.network.ext_links00.int_node.port_buffers156 system.ruby.network.ext_links00.int_node.port_buffers157 system.ruby.network.ext_links00.int_node.port_buffers158 system.ruby.network.ext_links00.int_node.port_buffers159
+power_model=Null
 router_id=0
 virt_nets=10
 
@@ -1693,8 +1745,14 @@ weight=1
 type=Switch
 children=port_buffers000 port_buffers001 port_buffers002 port_buffers003 port_buffers004 port_buffers005 port_buffers006 port_buffers007 port_buffers008 port_buffers009 port_buffers010 port_buffers011 port_buffers012 port_buffers013 port_buffers014 port_buffers015 port_buffers016 port_buffers017 port_buffers018 port_buffers019 port_buffers020 port_buffers021 port_buffers022 port_buffers023 port_buffers024 port_buffers025 port_buffers026 port_buffers027 port_buffers028 port_buffers029 port_buffers030 port_buffers031 port_buffers032 port_buffers033 port_buffers034 port_buffers035 port_buffers036 port_buffers037 port_buffers038 port_buffers039 port_buffers040 port_buffers041 port_buffers042 port_buffers043 port_buffers044 port_buffers045 port_buffers046 port_buffers047 port_buffers048 port_buffers049 port_buffers050 port_buffers051 port_buffers052 port_buffers053 port_buffers054 port_buffers055 port_buffers056 port_buffers057 port_buffers058 port_buffers059 port_buffers060 port_buffers061 port_buffers062 port_buffers063 port_buffers064 port_buffers065 port_buffers066 port_buffers067 port_buffers068 port_buffers069 port_buffers070 port_buffers071 port_buffers072 port_buffers073 port_buffers074 port_buffers075 port_buffers076 port_buffers077 port_buffers078 port_buffers079 port_buffers080 port_buffers081 port_buffers082 port_buffers083 port_buffers084 port_buffers085 port_buffers086 port_buffers087 port_buffers088 port_buffers089 port_buffers090 port_buffers091 port_buffers092 port_buffers093 port_buffers094 port_buffers095 port_buffers096 port_buffers097 port_buffers098 port_buffers099 port_buffers100 port_buffers101 port_buffers102 port_buffers103 port_buffers104 port_buffers105 port_buffers106 port_buffers107 port_buffers108 port_buffers109 port_buffers110 port_buffers111 port_buffers112 port_buffers113 port_buffers114 port_buffers115 port_buffers116 port_buffers117 port_buffers118 port_buffers119 port_buffers120 port_buffers121 port_buffers122 port_buffers123 port_buffers124 port_buffers125 port_buffers126 port_buffers127 port_buffers128 port_buffers129 port_buffers130 port_buffers131 port_buffers132 port_buffers133 port_buffers134 port_buffers135 port_buffers136 port_buffers137 port_buffers138 port_buffers139 port_buffers140 port_buffers141 port_buffers142 port_buffers143 port_buffers144 port_buffers145 port_buffers146 port_buffers147 port_buffers148 port_buffers149
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.ext_links01.int_node.port_buffers000 system.ruby.network.ext_links01.int_node.port_buffers001 system.ruby.network.ext_links01.int_node.port_buffers002 system.ruby.network.ext_links01.int_node.port_buffers003 system.ruby.network.ext_links01.int_node.port_buffers004 system.ruby.network.ext_links01.int_node.port_buffers005 system.ruby.network.ext_links01.int_node.port_buffers006 system.ruby.network.ext_links01.int_node.port_buffers007 system.ruby.network.ext_links01.int_node.port_buffers008 system.ruby.network.ext_links01.int_node.port_buffers009 system.ruby.network.ext_links01.int_node.port_buffers010 system.ruby.network.ext_links01.int_node.port_buffers011 system.ruby.network.ext_links01.int_node.port_buffers012 system.ruby.network.ext_links01.int_node.port_buffers013 system.ruby.network.ext_links01.int_node.port_buffers014 system.ruby.network.ext_links01.int_node.port_buffers015 system.ruby.network.ext_links01.int_node.port_buffers016 system.ruby.network.ext_links01.int_node.port_buffers017 system.ruby.network.ext_links01.int_node.port_buffers018 system.ruby.network.ext_links01.int_node.port_buffers019 system.ruby.network.ext_links01.int_node.port_buffers020 system.ruby.network.ext_links01.int_node.port_buffers021 system.ruby.network.ext_links01.int_node.port_buffers022 system.ruby.network.ext_links01.int_node.port_buffers023 system.ruby.network.ext_links01.int_node.port_buffers024 system.ruby.network.ext_links01.int_node.port_buffers025 system.ruby.network.ext_links01.int_node.port_buffers026 system.ruby.network.ext_links01.int_node.port_buffers027 system.ruby.network.ext_links01.int_node.port_buffers028 system.ruby.network.ext_links01.int_node.port_buffers029 system.ruby.network.ext_links01.int_node.port_buffers030 system.ruby.network.ext_links01.int_node.port_buffers031 system.ruby.network.ext_links01.int_node.port_buffers032 system.ruby.network.ext_links01.int_node.port_buffers033 system.ruby.network.ext_links01.int_node.port_buffers034 system.ruby.network.ext_links01.int_node.port_buffers035 system.ruby.network.ext_links01.int_node.port_buffers036 system.ruby.network.ext_links01.int_node.port_buffers037 system.ruby.network.ext_links01.int_node.port_buffers038 system.ruby.network.ext_links01.int_node.port_buffers039 system.ruby.network.ext_links01.int_node.port_buffers040 system.ruby.network.ext_links01.int_node.port_buffers041 system.ruby.network.ext_links01.int_node.port_buffers042 system.ruby.network.ext_links01.int_node.port_buffers043 system.ruby.network.ext_links01.int_node.port_buffers044 system.ruby.network.ext_links01.int_node.port_buffers045 system.ruby.network.ext_links01.int_node.port_buffers046 system.ruby.network.ext_links01.int_node.port_buffers047 system.ruby.network.ext_links01.int_node.port_buffers048 system.ruby.network.ext_links01.int_node.port_buffers049 system.ruby.network.ext_links01.int_node.port_buffers050 system.ruby.network.ext_links01.int_node.port_buffers051 system.ruby.network.ext_links01.int_node.port_buffers052 system.ruby.network.ext_links01.int_node.port_buffers053 system.ruby.network.ext_links01.int_node.port_buffers054 system.ruby.network.ext_links01.int_node.port_buffers055 system.ruby.network.ext_links01.int_node.port_buffers056 system.ruby.network.ext_links01.int_node.port_buffers057 system.ruby.network.ext_links01.int_node.port_buffers058 system.ruby.network.ext_links01.int_node.port_buffers059 system.ruby.network.ext_links01.int_node.port_buffers060 system.ruby.network.ext_links01.int_node.port_buffers061 system.ruby.network.ext_links01.int_node.port_buffers062 system.ruby.network.ext_links01.int_node.port_buffers063 system.ruby.network.ext_links01.int_node.port_buffers064 system.ruby.network.ext_links01.int_node.port_buffers065 system.ruby.network.ext_links01.int_node.port_buffers066 system.ruby.network.ext_links01.int_node.port_buffers067 system.ruby.network.ext_links01.int_node.port_buffers068 system.ruby.network.ext_links01.int_node.port_buffers069 system.ruby.network.ext_links01.int_node.port_buffers070 system.ruby.network.ext_links01.int_node.port_buffers071 system.ruby.network.ext_links01.int_node.port_buffers072 system.ruby.network.ext_links01.int_node.port_buffers073 system.ruby.network.ext_links01.int_node.port_buffers074 system.ruby.network.ext_links01.int_node.port_buffers075 system.ruby.network.ext_links01.int_node.port_buffers076 system.ruby.network.ext_links01.int_node.port_buffers077 system.ruby.network.ext_links01.int_node.port_buffers078 system.ruby.network.ext_links01.int_node.port_buffers079 system.ruby.network.ext_links01.int_node.port_buffers080 system.ruby.network.ext_links01.int_node.port_buffers081 system.ruby.network.ext_links01.int_node.port_buffers082 system.ruby.network.ext_links01.int_node.port_buffers083 system.ruby.network.ext_links01.int_node.port_buffers084 system.ruby.network.ext_links01.int_node.port_buffers085 system.ruby.network.ext_links01.int_node.port_buffers086 system.ruby.network.ext_links01.int_node.port_buffers087 system.ruby.network.ext_links01.int_node.port_buffers088 system.ruby.network.ext_links01.int_node.port_buffers089 system.ruby.network.ext_links01.int_node.port_buffers090 system.ruby.network.ext_links01.int_node.port_buffers091 system.ruby.network.ext_links01.int_node.port_buffers092 system.ruby.network.ext_links01.int_node.port_buffers093 system.ruby.network.ext_links01.int_node.port_buffers094 system.ruby.network.ext_links01.int_node.port_buffers095 system.ruby.network.ext_links01.int_node.port_buffers096 system.ruby.network.ext_links01.int_node.port_buffers097 system.ruby.network.ext_links01.int_node.port_buffers098 system.ruby.network.ext_links01.int_node.port_buffers099 system.ruby.network.ext_links01.int_node.port_buffers100 system.ruby.network.ext_links01.int_node.port_buffers101 system.ruby.network.ext_links01.int_node.port_buffers102 system.ruby.network.ext_links01.int_node.port_buffers103 system.ruby.network.ext_links01.int_node.port_buffers104 system.ruby.network.ext_links01.int_node.port_buffers105 system.ruby.network.ext_links01.int_node.port_buffers106 system.ruby.network.ext_links01.int_node.port_buffers107 system.ruby.network.ext_links01.int_node.port_buffers108 system.ruby.network.ext_links01.int_node.port_buffers109 system.ruby.network.ext_links01.int_node.port_buffers110 system.ruby.network.ext_links01.int_node.port_buffers111 system.ruby.network.ext_links01.int_node.port_buffers112 system.ruby.network.ext_links01.int_node.port_buffers113 system.ruby.network.ext_links01.int_node.port_buffers114 system.ruby.network.ext_links01.int_node.port_buffers115 system.ruby.network.ext_links01.int_node.port_buffers116 system.ruby.network.ext_links01.int_node.port_buffers117 system.ruby.network.ext_links01.int_node.port_buffers118 system.ruby.network.ext_links01.int_node.port_buffers119 system.ruby.network.ext_links01.int_node.port_buffers120 system.ruby.network.ext_links01.int_node.port_buffers121 system.ruby.network.ext_links01.int_node.port_buffers122 system.ruby.network.ext_links01.int_node.port_buffers123 system.ruby.network.ext_links01.int_node.port_buffers124 system.ruby.network.ext_links01.int_node.port_buffers125 system.ruby.network.ext_links01.int_node.port_buffers126 system.ruby.network.ext_links01.int_node.port_buffers127 system.ruby.network.ext_links01.int_node.port_buffers128 system.ruby.network.ext_links01.int_node.port_buffers129 system.ruby.network.ext_links01.int_node.port_buffers130 system.ruby.network.ext_links01.int_node.port_buffers131 system.ruby.network.ext_links01.int_node.port_buffers132 system.ruby.network.ext_links01.int_node.port_buffers133 system.ruby.network.ext_links01.int_node.port_buffers134 system.ruby.network.ext_links01.int_node.port_buffers135 system.ruby.network.ext_links01.int_node.port_buffers136 system.ruby.network.ext_links01.int_node.port_buffers137 system.ruby.network.ext_links01.int_node.port_buffers138 system.ruby.network.ext_links01.int_node.port_buffers139 system.ruby.network.ext_links01.int_node.port_buffers140 system.ruby.network.ext_links01.int_node.port_buffers141 system.ruby.network.ext_links01.int_node.port_buffers142 system.ruby.network.ext_links01.int_node.port_buffers143 system.ruby.network.ext_links01.int_node.port_buffers144 system.ruby.network.ext_links01.int_node.port_buffers145 system.ruby.network.ext_links01.int_node.port_buffers146 system.ruby.network.ext_links01.int_node.port_buffers147 system.ruby.network.ext_links01.int_node.port_buffers148 system.ruby.network.ext_links01.int_node.port_buffers149
+power_model=Null
 router_id=1
 virt_nets=10
 
@@ -2763,8 +2821,14 @@ weight=1
 type=Switch
 children=port_buffers000 port_buffers001 port_buffers002 port_buffers003 port_buffers004 port_buffers005 port_buffers006 port_buffers007 port_buffers008 port_buffers009 port_buffers010 port_buffers011 port_buffers012 port_buffers013 port_buffers014 port_buffers015 port_buffers016 port_buffers017 port_buffers018 port_buffers019 port_buffers020 port_buffers021 port_buffers022 port_buffers023 port_buffers024 port_buffers025 port_buffers026 port_buffers027 port_buffers028 port_buffers029 port_buffers030 port_buffers031 port_buffers032 port_buffers033 port_buffers034 port_buffers035 port_buffers036 port_buffers037 port_buffers038 port_buffers039 port_buffers040 port_buffers041 port_buffers042 port_buffers043 port_buffers044 port_buffers045 port_buffers046 port_buffers047 port_buffers048 port_buffers049 port_buffers050 port_buffers051 port_buffers052 port_buffers053 port_buffers054 port_buffers055 port_buffers056 port_buffers057 port_buffers058 port_buffers059 port_buffers060 port_buffers061 port_buffers062 port_buffers063 port_buffers064 port_buffers065 port_buffers066 port_buffers067 port_buffers068 port_buffers069 port_buffers070 port_buffers071 port_buffers072 port_buffers073 port_buffers074 port_buffers075 port_buffers076 port_buffers077 port_buffers078 port_buffers079 port_buffers080 port_buffers081 port_buffers082 port_buffers083 port_buffers084 port_buffers085 port_buffers086 port_buffers087 port_buffers088 port_buffers089 port_buffers090 port_buffers091 port_buffers092 port_buffers093 port_buffers094 port_buffers095 port_buffers096 port_buffers097 port_buffers098 port_buffers099 port_buffers100 port_buffers101 port_buffers102 port_buffers103 port_buffers104 port_buffers105 port_buffers106 port_buffers107 port_buffers108 port_buffers109 port_buffers110 port_buffers111 port_buffers112 port_buffers113 port_buffers114 port_buffers115 port_buffers116 port_buffers117 port_buffers118 port_buffers119 port_buffers120 port_buffers121 port_buffers122 port_buffers123 port_buffers124 port_buffers125 port_buffers126 port_buffers127 port_buffers128 port_buffers129 port_buffers130 port_buffers131 port_buffers132 port_buffers133 port_buffers134 port_buffers135 port_buffers136 port_buffers137 port_buffers138 port_buffers139 port_buffers140 port_buffers141 port_buffers142 port_buffers143 port_buffers144 port_buffers145 port_buffers146 port_buffers147 port_buffers148 port_buffers149
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.ext_links02.int_node.port_buffers000 system.ruby.network.ext_links02.int_node.port_buffers001 system.ruby.network.ext_links02.int_node.port_buffers002 system.ruby.network.ext_links02.int_node.port_buffers003 system.ruby.network.ext_links02.int_node.port_buffers004 system.ruby.network.ext_links02.int_node.port_buffers005 system.ruby.network.ext_links02.int_node.port_buffers006 system.ruby.network.ext_links02.int_node.port_buffers007 system.ruby.network.ext_links02.int_node.port_buffers008 system.ruby.network.ext_links02.int_node.port_buffers009 system.ruby.network.ext_links02.int_node.port_buffers010 system.ruby.network.ext_links02.int_node.port_buffers011 system.ruby.network.ext_links02.int_node.port_buffers012 system.ruby.network.ext_links02.int_node.port_buffers013 system.ruby.network.ext_links02.int_node.port_buffers014 system.ruby.network.ext_links02.int_node.port_buffers015 system.ruby.network.ext_links02.int_node.port_buffers016 system.ruby.network.ext_links02.int_node.port_buffers017 system.ruby.network.ext_links02.int_node.port_buffers018 system.ruby.network.ext_links02.int_node.port_buffers019 system.ruby.network.ext_links02.int_node.port_buffers020 system.ruby.network.ext_links02.int_node.port_buffers021 system.ruby.network.ext_links02.int_node.port_buffers022 system.ruby.network.ext_links02.int_node.port_buffers023 system.ruby.network.ext_links02.int_node.port_buffers024 system.ruby.network.ext_links02.int_node.port_buffers025 system.ruby.network.ext_links02.int_node.port_buffers026 system.ruby.network.ext_links02.int_node.port_buffers027 system.ruby.network.ext_links02.int_node.port_buffers028 system.ruby.network.ext_links02.int_node.port_buffers029 system.ruby.network.ext_links02.int_node.port_buffers030 system.ruby.network.ext_links02.int_node.port_buffers031 system.ruby.network.ext_links02.int_node.port_buffers032 system.ruby.network.ext_links02.int_node.port_buffers033 system.ruby.network.ext_links02.int_node.port_buffers034 system.ruby.network.ext_links02.int_node.port_buffers035 system.ruby.network.ext_links02.int_node.port_buffers036 system.ruby.network.ext_links02.int_node.port_buffers037 system.ruby.network.ext_links02.int_node.port_buffers038 system.ruby.network.ext_links02.int_node.port_buffers039 system.ruby.network.ext_links02.int_node.port_buffers040 system.ruby.network.ext_links02.int_node.port_buffers041 system.ruby.network.ext_links02.int_node.port_buffers042 system.ruby.network.ext_links02.int_node.port_buffers043 system.ruby.network.ext_links02.int_node.port_buffers044 system.ruby.network.ext_links02.int_node.port_buffers045 system.ruby.network.ext_links02.int_node.port_buffers046 system.ruby.network.ext_links02.int_node.port_buffers047 system.ruby.network.ext_links02.int_node.port_buffers048 system.ruby.network.ext_links02.int_node.port_buffers049 system.ruby.network.ext_links02.int_node.port_buffers050 system.ruby.network.ext_links02.int_node.port_buffers051 system.ruby.network.ext_links02.int_node.port_buffers052 system.ruby.network.ext_links02.int_node.port_buffers053 system.ruby.network.ext_links02.int_node.port_buffers054 system.ruby.network.ext_links02.int_node.port_buffers055 system.ruby.network.ext_links02.int_node.port_buffers056 system.ruby.network.ext_links02.int_node.port_buffers057 system.ruby.network.ext_links02.int_node.port_buffers058 system.ruby.network.ext_links02.int_node.port_buffers059 system.ruby.network.ext_links02.int_node.port_buffers060 system.ruby.network.ext_links02.int_node.port_buffers061 system.ruby.network.ext_links02.int_node.port_buffers062 system.ruby.network.ext_links02.int_node.port_buffers063 system.ruby.network.ext_links02.int_node.port_buffers064 system.ruby.network.ext_links02.int_node.port_buffers065 system.ruby.network.ext_links02.int_node.port_buffers066 system.ruby.network.ext_links02.int_node.port_buffers067 system.ruby.network.ext_links02.int_node.port_buffers068 system.ruby.network.ext_links02.int_node.port_buffers069 system.ruby.network.ext_links02.int_node.port_buffers070 system.ruby.network.ext_links02.int_node.port_buffers071 system.ruby.network.ext_links02.int_node.port_buffers072 system.ruby.network.ext_links02.int_node.port_buffers073 system.ruby.network.ext_links02.int_node.port_buffers074 system.ruby.network.ext_links02.int_node.port_buffers075 system.ruby.network.ext_links02.int_node.port_buffers076 system.ruby.network.ext_links02.int_node.port_buffers077 system.ruby.network.ext_links02.int_node.port_buffers078 system.ruby.network.ext_links02.int_node.port_buffers079 system.ruby.network.ext_links02.int_node.port_buffers080 system.ruby.network.ext_links02.int_node.port_buffers081 system.ruby.network.ext_links02.int_node.port_buffers082 system.ruby.network.ext_links02.int_node.port_buffers083 system.ruby.network.ext_links02.int_node.port_buffers084 system.ruby.network.ext_links02.int_node.port_buffers085 system.ruby.network.ext_links02.int_node.port_buffers086 system.ruby.network.ext_links02.int_node.port_buffers087 system.ruby.network.ext_links02.int_node.port_buffers088 system.ruby.network.ext_links02.int_node.port_buffers089 system.ruby.network.ext_links02.int_node.port_buffers090 system.ruby.network.ext_links02.int_node.port_buffers091 system.ruby.network.ext_links02.int_node.port_buffers092 system.ruby.network.ext_links02.int_node.port_buffers093 system.ruby.network.ext_links02.int_node.port_buffers094 system.ruby.network.ext_links02.int_node.port_buffers095 system.ruby.network.ext_links02.int_node.port_buffers096 system.ruby.network.ext_links02.int_node.port_buffers097 system.ruby.network.ext_links02.int_node.port_buffers098 system.ruby.network.ext_links02.int_node.port_buffers099 system.ruby.network.ext_links02.int_node.port_buffers100 system.ruby.network.ext_links02.int_node.port_buffers101 system.ruby.network.ext_links02.int_node.port_buffers102 system.ruby.network.ext_links02.int_node.port_buffers103 system.ruby.network.ext_links02.int_node.port_buffers104 system.ruby.network.ext_links02.int_node.port_buffers105 system.ruby.network.ext_links02.int_node.port_buffers106 system.ruby.network.ext_links02.int_node.port_buffers107 system.ruby.network.ext_links02.int_node.port_buffers108 system.ruby.network.ext_links02.int_node.port_buffers109 system.ruby.network.ext_links02.int_node.port_buffers110 system.ruby.network.ext_links02.int_node.port_buffers111 system.ruby.network.ext_links02.int_node.port_buffers112 system.ruby.network.ext_links02.int_node.port_buffers113 system.ruby.network.ext_links02.int_node.port_buffers114 system.ruby.network.ext_links02.int_node.port_buffers115 system.ruby.network.ext_links02.int_node.port_buffers116 system.ruby.network.ext_links02.int_node.port_buffers117 system.ruby.network.ext_links02.int_node.port_buffers118 system.ruby.network.ext_links02.int_node.port_buffers119 system.ruby.network.ext_links02.int_node.port_buffers120 system.ruby.network.ext_links02.int_node.port_buffers121 system.ruby.network.ext_links02.int_node.port_buffers122 system.ruby.network.ext_links02.int_node.port_buffers123 system.ruby.network.ext_links02.int_node.port_buffers124 system.ruby.network.ext_links02.int_node.port_buffers125 system.ruby.network.ext_links02.int_node.port_buffers126 system.ruby.network.ext_links02.int_node.port_buffers127 system.ruby.network.ext_links02.int_node.port_buffers128 system.ruby.network.ext_links02.int_node.port_buffers129 system.ruby.network.ext_links02.int_node.port_buffers130 system.ruby.network.ext_links02.int_node.port_buffers131 system.ruby.network.ext_links02.int_node.port_buffers132 system.ruby.network.ext_links02.int_node.port_buffers133 system.ruby.network.ext_links02.int_node.port_buffers134 system.ruby.network.ext_links02.int_node.port_buffers135 system.ruby.network.ext_links02.int_node.port_buffers136 system.ruby.network.ext_links02.int_node.port_buffers137 system.ruby.network.ext_links02.int_node.port_buffers138 system.ruby.network.ext_links02.int_node.port_buffers139 system.ruby.network.ext_links02.int_node.port_buffers140 system.ruby.network.ext_links02.int_node.port_buffers141 system.ruby.network.ext_links02.int_node.port_buffers142 system.ruby.network.ext_links02.int_node.port_buffers143 system.ruby.network.ext_links02.int_node.port_buffers144 system.ruby.network.ext_links02.int_node.port_buffers145 system.ruby.network.ext_links02.int_node.port_buffers146 system.ruby.network.ext_links02.int_node.port_buffers147 system.ruby.network.ext_links02.int_node.port_buffers148 system.ruby.network.ext_links02.int_node.port_buffers149
+power_model=Null
 router_id=2
 virt_nets=10
 
@@ -4208,24 +4272,332 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers40]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers41]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers42]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers43]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers44]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers45]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers46]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers47]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers48]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers49]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers50]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers51]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers52]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers53]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers54]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers55]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers56]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers57]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers58]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers59]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers60]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers61]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers62]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers63]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers64]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers65]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers66]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers67]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers68]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers69]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers70]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers71]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers72]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers73]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers74]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers75]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers76]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers77]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers78]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers79]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=512
+dst_inport=
+dst_node=system.ruby.network.ext_links01.int_node
 eventq_index=0
 latency=1
 link_id=0
-node_a=system.ruby.network.ext_links00.int_node
-node_b=system.ruby.network.ext_links01.int_node
+src_node=system.ruby.network.ext_links00.int_node
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=512
+dst_inport=
+dst_node=system.ruby.network.ext_links00.int_node
 eventq_index=0
 latency=1
 link_id=1
-node_a=system.ruby.network.ext_links00.int_node
-node_b=system.ruby.network.ext_links02.int_node
+src_node=system.ruby.network.ext_links01.int_node
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=512
+dst_inport=
+dst_node=system.ruby.network.ext_links02.int_node
+eventq_index=0
+latency=1
+link_id=2
+src_node=system.ruby.network.ext_links00.int_node
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=512
+dst_inport=
+dst_node=system.ruby.network.ext_links00.int_node
+eventq_index=0
+latency=1
+link_id=3
+src_node=system.ruby.network.ext_links02.int_node
+src_outport=
 weight=1
 
 [system.sqc_cntrl0]
@@ -4236,11 +4608,16 @@ TCC_select_num_bits=0
 buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=80
 l2_hit_latency=18
 mandatoryQueue=system.sqc_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeToSQC=system.sqc_cntrl0.probeToSQC
 recycle_latency=10
 requestFromSQC=system.sqc_cntrl0.requestFromSQC
@@ -4323,17 +4700,22 @@ coreid=99
 dcache=system.sqc_cntrl0.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.sqc_cntrl0.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=16
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=false
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=18
 slave=system.cpu.cpuInstPort[0]
@@ -4354,11 +4736,16 @@ TCC_select_num_bits=0
 buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=80
 l2_hit_latency=18
 mandatoryQueue=system.sqc_cntrl1.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeToSQC=system.sqc_cntrl1.probeToSQC
 recycle_latency=10
 requestFromSQC=system.sqc_cntrl1.requestFromSQC
@@ -4441,17 +4828,22 @@ coreid=99
 dcache=system.sqc_cntrl1.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.sqc_cntrl1.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=16
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=false
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=19
 slave=system.cpu.cpuInstPort[1]
@@ -4467,9 +4859,14 @@ master=system.ruby.network.slave[34]
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -4486,10 +4883,15 @@ TCC_select_num_bits=0
 buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 l2_request_latency=1
 l2_response_latency=16
 number_of_TBEs=2048
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 responseFromTCC=system.tcc_cntrl0.responseFromTCC
 responseToTCC=system.tcc_cntrl0.responseToTCC
@@ -4581,11 +4983,16 @@ TCC_select_num_bits=0
 buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.tccdir_cntrl0.directory
 directory_latency=6
 eventq_index=0
 issue_latency=120
 number_of_TBEs=1024
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeFromNB=system.tccdir_cntrl0.probeFromNB
 probeToCore=system.tccdir_cntrl0.probeToCore
 recycle_latency=10
@@ -4730,11 +5137,16 @@ buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
 coalescer=system.tcp_cntrl0.coalescer
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=40
 l2_hit_latency=18
 mandatoryQueue=system.tcp_cntrl0.mandatoryQueue
 number_of_TBEs=2560
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeToTCP=system.tcp_cntrl0.probeToTCP
 recycle_latency=10
 requestFromTCP=system.tcp_cntrl0.requestFromTCP
@@ -4780,17 +5192,22 @@ coreid=99
 dcache=system.tcp_cntrl0.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl0.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=2560
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=false
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=2
 slave=system.cpu.cpuDataPort[0]
@@ -4841,17 +5258,22 @@ coreid=99
 dcache=system.tcp_cntrl0.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl0.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=3
 
@@ -4872,11 +5294,16 @@ buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
 coalescer=system.tcp_cntrl1.coalescer
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=40
 l2_hit_latency=18
 mandatoryQueue=system.tcp_cntrl1.mandatoryQueue
 number_of_TBEs=2560
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeToTCP=system.tcp_cntrl1.probeToTCP
 recycle_latency=10
 requestFromTCP=system.tcp_cntrl1.requestFromTCP
@@ -4922,17 +5349,22 @@ coreid=99
 dcache=system.tcp_cntrl1.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl1.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=2560
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=false
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=4
 slave=system.cpu.cpuDataPort[1]
@@ -4983,17 +5415,22 @@ coreid=99
 dcache=system.tcp_cntrl1.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl1.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=5
 
@@ -5014,11 +5451,16 @@ buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
 coalescer=system.tcp_cntrl2.coalescer
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=40
 l2_hit_latency=18
 mandatoryQueue=system.tcp_cntrl2.mandatoryQueue
 number_of_TBEs=2560
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeToTCP=system.tcp_cntrl2.probeToTCP
 recycle_latency=10
 requestFromTCP=system.tcp_cntrl2.requestFromTCP
@@ -5064,17 +5506,22 @@ coreid=99
 dcache=system.tcp_cntrl2.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl2.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=2560
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=false
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=6
 slave=system.cpu.cpuDataPort[2]
@@ -5125,17 +5572,22 @@ coreid=99
 dcache=system.tcp_cntrl2.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl2.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=7
 
@@ -5156,11 +5608,16 @@ buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
 coalescer=system.tcp_cntrl3.coalescer
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=40
 l2_hit_latency=18
 mandatoryQueue=system.tcp_cntrl3.mandatoryQueue
 number_of_TBEs=2560
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeToTCP=system.tcp_cntrl3.probeToTCP
 recycle_latency=10
 requestFromTCP=system.tcp_cntrl3.requestFromTCP
@@ -5206,17 +5663,22 @@ coreid=99
 dcache=system.tcp_cntrl3.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl3.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=2560
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=false
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=8
 slave=system.cpu.cpuDataPort[3]
@@ -5267,17 +5729,22 @@ coreid=99
 dcache=system.tcp_cntrl3.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl3.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=9
 
@@ -5298,11 +5765,16 @@ buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
 coalescer=system.tcp_cntrl4.coalescer
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=40
 l2_hit_latency=18
 mandatoryQueue=system.tcp_cntrl4.mandatoryQueue
 number_of_TBEs=2560
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeToTCP=system.tcp_cntrl4.probeToTCP
 recycle_latency=10
 requestFromTCP=system.tcp_cntrl4.requestFromTCP
@@ -5348,17 +5820,22 @@ coreid=99
 dcache=system.tcp_cntrl4.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl4.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=2560
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=false
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=10
 slave=system.cpu.cpuDataPort[4]
@@ -5409,17 +5886,22 @@ coreid=99
 dcache=system.tcp_cntrl4.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl4.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=11
 
@@ -5440,11 +5922,16 @@ buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
 coalescer=system.tcp_cntrl5.coalescer
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=40
 l2_hit_latency=18
 mandatoryQueue=system.tcp_cntrl5.mandatoryQueue
 number_of_TBEs=2560
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeToTCP=system.tcp_cntrl5.probeToTCP
 recycle_latency=10
 requestFromTCP=system.tcp_cntrl5.requestFromTCP
@@ -5490,17 +5977,22 @@ coreid=99
 dcache=system.tcp_cntrl5.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl5.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=2560
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=false
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=12
 slave=system.cpu.cpuDataPort[5]
@@ -5551,17 +6043,22 @@ coreid=99
 dcache=system.tcp_cntrl5.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl5.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=13
 
@@ -5582,11 +6079,16 @@ buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
 coalescer=system.tcp_cntrl6.coalescer
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=40
 l2_hit_latency=18
 mandatoryQueue=system.tcp_cntrl6.mandatoryQueue
 number_of_TBEs=2560
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeToTCP=system.tcp_cntrl6.probeToTCP
 recycle_latency=10
 requestFromTCP=system.tcp_cntrl6.requestFromTCP
@@ -5632,17 +6134,22 @@ coreid=99
 dcache=system.tcp_cntrl6.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl6.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=2560
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=false
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=14
 slave=system.cpu.cpuDataPort[6]
@@ -5693,17 +6200,22 @@ coreid=99
 dcache=system.tcp_cntrl6.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl6.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=15
 
@@ -5724,11 +6236,16 @@ buffer_size=0
 clk_domain=system.clk_domain
 cluster_id=0
 coalescer=system.tcp_cntrl7.coalescer
+default_p_state=UNDEFINED
 eventq_index=0
 issue_latency=40
 l2_hit_latency=18
 mandatoryQueue=system.tcp_cntrl7.mandatoryQueue
 number_of_TBEs=2560
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeToTCP=system.tcp_cntrl7.probeToTCP
 recycle_latency=10
 requestFromTCP=system.tcp_cntrl7.requestFromTCP
@@ -5774,17 +6291,22 @@ coreid=99
 dcache=system.tcp_cntrl7.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl7.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=false
 max_outstanding_requests=2560
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=false
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=16
 slave=system.cpu.cpuDataPort[7]
@@ -5835,17 +6357,22 @@ coreid=99
 dcache=system.tcp_cntrl7.L1cache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.tcp_cntrl7.L1cache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=false
 version=17
 
diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr
index 74f33c417..13060c953 100755
--- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr
+++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr
@@ -6,7 +6,5 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout
index bb54d1884..c3cb1df0a 100755
--- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout
+++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout
+Redirecting stderr to build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:58:44
-gem5 started Jan 21 2016 14:59:07
-gem5 executing on zizzer, pid 26197
-command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO
+gem5 compiled Oct 13 2016 21:24:38
+gem5 started Oct 13 2016 21:24:54
+gem5 executing on e108600-lin, pid 29891
+command line: /work/curdun01/gem5-external.hg/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 14181 because Ruby Tester completed
+Exiting @ tick 13821 because Ruby Tester completed
diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt
index 40be86e31..7dd43386c 100644
--- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt
+++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt
@@ -1,44 +1,44 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000014                       # Number of seconds simulated
-sim_ticks                                       14181                       # Number of ticks simulated
-final_tick                                      14181                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                       13821                       # Number of ticks simulated
+final_tick                                      13821                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 238683                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 530468                       # Number of bytes of host memory used
+host_tick_rate                                 213268                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 483832                       # Number of bytes of host memory used
 host_seconds                                     0.06                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::dir_cntrl0         16576                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total              16576                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::dir_cntrl0          576                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total             576                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::dir_cntrl0            259                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total                 259                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::dir_cntrl0             9                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total                  9                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::dir_cntrl0       1168887949                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            1168887949                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::dir_cntrl0        40617728                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total             40617728                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::dir_cntrl0      1209505677                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1209505677                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                         259                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                          9                       # Number of write requests accepted
-system.mem_ctrls.readBursts                       259                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                        9                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  15936                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                     640                       # Total number of bytes read from write queue
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.bytes_read::dir_cntrl0         16384                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total              16384                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::dir_cntrl0          896                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total             896                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::dir_cntrl0            256                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total                 256                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::dir_cntrl0            14                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total                 14                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::dir_cntrl0       1185442443                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total            1185442443                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::dir_cntrl0        64828884                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total             64828884                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::dir_cntrl0      1250271326                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1250271326                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                         256                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                         14                       # Number of write requests accepted
+system.mem_ctrls.readBursts                       256                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                       14                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM                  15488                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                     896                       # Total number of bytes read from write queue
 system.mem_ctrls.bytesWritten                       0                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                   16576                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys                  576                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                     10                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.bytesReadSys                   16384                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys                  896                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                     14                       # Number of DRAM read bursts serviced by the write queue
 system.mem_ctrls.mergedWrBursts                     0                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0               100                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1                71                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2                66                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0                99                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1                69                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2                62                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::3                12                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                 0                       # Per bank write bursts
@@ -70,24 +70,24 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         13941                       # Total gap between requests
+system.mem_ctrls.totGap                         13710                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                   259                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                   256                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6                    9                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     214                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                      27                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2                       7                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6                   14                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                     199                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                      36                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2                       6                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       1                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
@@ -126,11 +126,11 @@ system.mem_ctrls.wrQLenPdf::5                       1                       # Wh
 system.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9                       0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13                      0                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::15                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::16                      0                       # What write queue length does an incoming req see
@@ -189,206 +189,214 @@ system.mem_ctrls.bytesPerActivate::512-639            3     20.00%     20.00% #
 system.mem_ctrls.bytesPerActivate::896-1023            1      6.67%     26.67% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::1024-1151           11     73.33%    100.00% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::total           15                       # Bytes accessed per row activation
-system.mem_ctrls.totQLat                          973                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                    5704                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       1245                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         3.91                       # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat                         2184                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                    6782                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       1210                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                         9.02                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   22.91                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                      1123.76                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   28.02                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                      1120.61                       # Average DRAM read bandwidth in MiByte/s
 system.mem_ctrls.avgWrBW                         0.00                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   1168.89                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                     40.62                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                   1185.44                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                     64.83                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         8.78                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     8.78                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtil                         8.75                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     8.75                       # Data bus utilization in percentage for reads
 system.mem_ctrls.busUtilWrite                    0.00                       # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen                       1.17                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                       2.63                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      230                       # Number of row buffer hits during reads
+system.mem_ctrls.avgRdQLen                       1.20                       # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen                       3.35                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      223                       # Number of row buffer hits during reads
 system.mem_ctrls.writeRowHits                       0                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 92.37                       # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate                 92.15                       # Row buffer hit rate for reads
 system.mem_ctrls.writeRowHitRate                 0.00                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         52.02                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    89.15                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                    83160                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                    46200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 1872000                       # Energy for read commands per rank (pJ)
+system.mem_ctrls.avgGap                         50.78                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    87.11                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   135660                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                    57960                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 2764608                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy               508560                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy              5437116                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy                58200                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy                8005236                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            994.933632                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE           83                       # Time in different power states
+system.mem_ctrls_0.refreshEnergy         614640.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              2757888                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy                44928                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy         3490680                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy             384                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy                9866748                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            713.895377                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                 7568                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE           89                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF           260                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT          7717                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            1                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT          5816                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN         7655                       # Time in different power states
 system.mem_ctrls_1.actEnergy                        0                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_1.preEnergy                        0                       # Energy for precharge commands per rank (pJ)
 system.mem_ctrls_1.readEnergy                       0                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy               508560                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy               168264                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy              4671600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy                5348424                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            665.889442                       # Core power per rank (mW)
+system.mem_ctrls_1.refreshEnergy         614640.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy               112176                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              2995200                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy               0                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy         2217600                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy                5939616                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            429.752985                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                    0                       # Total Idle time Per DRAM Rank
 system.mem_ctrls_1.memoryStateTime::IDLE         7786                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::REF           260                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         5775                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT             0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.ruby.outstanding_req_hist_seqr::bucket_size            2                      
 system.ruby.outstanding_req_hist_seqr::max_bucket           19                      
 system.ruby.outstanding_req_hist_seqr::samples           63                      
-system.ruby.outstanding_req_hist_seqr::mean    12.920635                      
-system.ruby.outstanding_req_hist_seqr::gmean    11.694862                      
-system.ruby.outstanding_req_hist_seqr::stdev     4.228557                      
-system.ruby.outstanding_req_hist_seqr    |           1      1.59%      1.59% |           2      3.17%      4.76% |           2      3.17%      7.94% |           5      7.94%     15.87% |           4      6.35%     22.22% |           3      4.76%     26.98% |           5      7.94%     34.92% |          14     22.22%     57.14% |          27     42.86%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist_seqr::mean    12.873016                      
+system.ruby.outstanding_req_hist_seqr::gmean    11.658152                      
+system.ruby.outstanding_req_hist_seqr::stdev     4.202503                      
+system.ruby.outstanding_req_hist_seqr    |           1      1.59%      1.59% |           2      3.17%      4.76% |           2      3.17%      7.94% |           5      7.94%     15.87% |           4      6.35%     22.22% |           3      4.76%     26.98% |           5      7.94%     34.92% |          16     25.40%     60.32% |          25     39.68%    100.00% |           0      0.00%    100.00%
 system.ruby.outstanding_req_hist_seqr::total           63                      
 system.ruby.outstanding_req_hist_coalsr::bucket_size            2                      
 system.ruby.outstanding_req_hist_coalsr::max_bucket           19                      
-system.ruby.outstanding_req_hist_coalsr::samples          885                      
-system.ruby.outstanding_req_hist_coalsr::mean     2.610169                      
-system.ruby.outstanding_req_hist_coalsr::gmean     2.223354                      
-system.ruby.outstanding_req_hist_coalsr::stdev     1.538535                      
-system.ruby.outstanding_req_hist_coalsr  |         219     24.75%     24.75% |         478     54.01%     78.76% |         135     15.25%     94.01% |          43      4.86%     98.87% |           9      1.02%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist_coalsr::total          885                      
+system.ruby.outstanding_req_hist_coalsr::samples          872                      
+system.ruby.outstanding_req_hist_coalsr::mean     2.547018                      
+system.ruby.outstanding_req_hist_coalsr::gmean     2.158955                      
+system.ruby.outstanding_req_hist_coalsr::stdev     1.537168                      
+system.ruby.outstanding_req_hist_coalsr  |         236     27.06%     27.06% |         460     52.75%     79.82% |         126     14.45%     94.27% |          40      4.59%     98.85% |           9      1.03%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist_coalsr::total          872                      
 system.ruby.latency_hist_seqr::bucket_size         1024                      
 system.ruby.latency_hist_seqr::max_bucket        10239                      
 system.ruby.latency_hist_seqr::samples             48                      
-system.ruby.latency_hist_seqr::mean       3351.354167                      
-system.ruby.latency_hist_seqr::gmean      1865.352879                      
-system.ruby.latency_hist_seqr::stdev      1934.275107                      
-system.ruby.latency_hist_seqr            |          11     22.92%     22.92% |           3      6.25%     29.17% |           3      6.25%     35.42% |           7     14.58%     50.00% |          18     37.50%     87.50% |           6     12.50%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::mean       3315.854167                      
+system.ruby.latency_hist_seqr::gmean      1841.298781                      
+system.ruby.latency_hist_seqr::stdev      1907.716848                      
+system.ruby.latency_hist_seqr            |          11     22.92%     22.92% |           3      6.25%     29.17% |           3      6.25%     35.42% |           7     14.58%     50.00% |          20     41.67%     91.67% |           4      8.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.latency_hist_seqr::total               48                      
 system.ruby.latency_hist_coalsr::bucket_size          128                      
 system.ruby.latency_hist_coalsr::max_bucket         1279                      
-system.ruby.latency_hist_coalsr::samples          872                      
-system.ruby.latency_hist_coalsr::mean      222.089450                      
-system.ruby.latency_hist_coalsr::gmean     114.436171                      
-system.ruby.latency_hist_coalsr::stdev     241.512900                      
-system.ruby.latency_hist_coalsr          |         580     66.51%     66.51% |          30      3.44%     69.95% |         110     12.61%     82.57% |          39      4.47%     87.04% |          33      3.78%     90.83% |          20      2.29%     93.12% |          33      3.78%     96.90% |          23      2.64%     99.54% |           4      0.46%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist_coalsr::total            872                      
+system.ruby.latency_hist_coalsr::samples          858                      
+system.ruby.latency_hist_coalsr::mean      215.358974                      
+system.ruby.latency_hist_coalsr::gmean     107.894342                      
+system.ruby.latency_hist_coalsr::stdev     237.470134                      
+system.ruby.latency_hist_coalsr          |         573     66.78%     66.78% |          36      4.20%     70.98% |         111     12.94%     83.92% |          37      4.31%     88.23% |          24      2.80%     91.03% |          19      2.21%     93.24% |          32      3.73%     96.97% |          23      2.68%     99.65% |           3      0.35%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_coalsr::total            858                      
 system.ruby.hit_latency_hist_seqr::bucket_size         1024                      
 system.ruby.hit_latency_hist_seqr::max_bucket        10239                      
 system.ruby.hit_latency_hist_seqr::samples           42                      
-system.ruby.hit_latency_hist_seqr::mean   3684.428571                      
-system.ruby.hit_latency_hist_seqr::gmean  2778.454716                      
-system.ruby.hit_latency_hist_seqr::stdev  1783.107224                      
-system.ruby.hit_latency_hist_seqr        |           7     16.67%     16.67% |           3      7.14%     23.81% |           1      2.38%     26.19% |           7     16.67%     42.86% |          18     42.86%     85.71% |           6     14.29%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist_seqr::mean   3644.142857                      
+system.ruby.hit_latency_hist_seqr::gmean  2737.850881                      
+system.ruby.hit_latency_hist_seqr::stdev  1757.652877                      
+system.ruby.hit_latency_hist_seqr        |           7     16.67%     16.67% |           3      7.14%     23.81% |           1      2.38%     26.19% |           7     16.67%     42.86% |          20     47.62%     90.48% |           4      9.52%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.hit_latency_hist_seqr::total           42                      
 system.ruby.miss_latency_hist_seqr::bucket_size          512                      
 system.ruby.miss_latency_hist_seqr::max_bucket         5119                      
 system.ruby.miss_latency_hist_seqr::samples            6                      
-system.ruby.miss_latency_hist_seqr::mean  1019.833333                      
-system.ruby.miss_latency_hist_seqr::gmean   114.673945                      
-system.ruby.miss_latency_hist_seqr::stdev  1281.644790                      
-system.ruby.miss_latency_hist_seqr       |           3     50.00%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           2     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::mean  1017.833333                      
+system.ruby.miss_latency_hist_seqr::gmean   114.584426                      
+system.ruby.miss_latency_hist_seqr::stdev  1278.753677                      
+system.ruby.miss_latency_hist_seqr       |           3     50.00%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     16.67%     83.33% |           1     16.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist_seqr::total            6                      
 system.ruby.miss_latency_hist_coalsr::bucket_size          128                      
 system.ruby.miss_latency_hist_coalsr::max_bucket         1279                      
-system.ruby.miss_latency_hist_coalsr::samples          872                      
-system.ruby.miss_latency_hist_coalsr::mean   222.089450                      
-system.ruby.miss_latency_hist_coalsr::gmean   114.436171                      
-system.ruby.miss_latency_hist_coalsr::stdev   241.512900                      
-system.ruby.miss_latency_hist_coalsr     |         580     66.51%     66.51% |          30      3.44%     69.95% |         110     12.61%     82.57% |          39      4.47%     87.04% |          33      3.78%     90.83% |          20      2.29%     93.12% |          33      3.78%     96.90% |          23      2.64%     99.54% |           4      0.46%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist_coalsr::total          872                      
+system.ruby.miss_latency_hist_coalsr::samples          858                      
+system.ruby.miss_latency_hist_coalsr::mean   215.358974                      
+system.ruby.miss_latency_hist_coalsr::gmean   107.894342                      
+system.ruby.miss_latency_hist_coalsr::stdev   237.470134                      
+system.ruby.miss_latency_hist_coalsr     |         573     66.78%     66.78% |          36      4.20%     70.98% |         111     12.94%     83.92% |          37      4.31%     88.23% |          24      2.80%     91.03% |          19      2.21%     93.24% |          32      3.73%     96.97% |          23      2.68%     99.65% |           3      0.35%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_coalsr::total          858                      
 system.ruby.L1Cache.incomplete_times_seqr            6                      
 system.cp_cntrl0.L1D0cache.demand_hits              0                       # Number of cache demand hits
 system.cp_cntrl0.L1D0cache.demand_misses           45                       # Number of cache demand misses
 system.cp_cntrl0.L1D0cache.demand_accesses           45                       # Number of cache demand accesses
 system.cp_cntrl0.L1D0cache.num_data_array_writes           43                       # number of data array writes
-system.cp_cntrl0.L1D0cache.num_tag_array_reads          154                       # number of tag array reads
+system.cp_cntrl0.L1D0cache.num_tag_array_reads          155                       # number of tag array reads
 system.cp_cntrl0.L1D0cache.num_tag_array_writes           41                       # number of tag array writes
 system.cp_cntrl0.L1D1cache.demand_hits              0                       # Number of cache demand hits
-system.cp_cntrl0.L1D1cache.demand_misses           43                       # Number of cache demand misses
-system.cp_cntrl0.L1D1cache.demand_accesses           43                       # Number of cache demand accesses
-system.cp_cntrl0.L1D1cache.num_data_array_writes           41                       # number of data array writes
-system.cp_cntrl0.L1D1cache.num_tag_array_reads           73                       # number of tag array reads
-system.cp_cntrl0.L1D1cache.num_tag_array_writes           41                       # number of tag array writes
+system.cp_cntrl0.L1D1cache.demand_misses           45                       # Number of cache demand misses
+system.cp_cntrl0.L1D1cache.demand_accesses           45                       # Number of cache demand accesses
+system.cp_cntrl0.L1D1cache.num_data_array_writes           42                       # number of data array writes
+system.cp_cntrl0.L1D1cache.num_tag_array_reads           74                       # number of tag array reads
+system.cp_cntrl0.L1D1cache.num_tag_array_writes           42                       # number of tag array writes
 system.cp_cntrl0.L1Icache.demand_hits               0                       # Number of cache demand hits
 system.cp_cntrl0.L1Icache.demand_misses             3                       # Number of cache demand misses
 system.cp_cntrl0.L1Icache.demand_accesses            3                       # Number of cache demand accesses
 system.cp_cntrl0.L1Icache.num_tag_array_reads            3                       # number of tag array reads
 system.cp_cntrl0.L2cache.demand_hits                0                       # Number of cache demand hits
-system.cp_cntrl0.L2cache.demand_misses             91                       # Number of cache demand misses
-system.cp_cntrl0.L2cache.demand_accesses           91                       # Number of cache demand accesses
+system.cp_cntrl0.L2cache.demand_misses             93                       # Number of cache demand misses
+system.cp_cntrl0.L2cache.demand_accesses           93                       # Number of cache demand accesses
 system.cp_cntrl0.L2cache.num_data_array_reads           81                       # number of data array reads
-system.cp_cntrl0.L2cache.num_data_array_writes           84                       # number of data array writes
-system.cp_cntrl0.L2cache.num_tag_array_reads          380                       # number of tag array reads
-system.cp_cntrl0.L2cache.num_tag_array_writes          371                       # number of tag array writes
-system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.cp_cntrl0.sequencer.store_waiting_on_load            2                       # Number of times a store aliased with a pending load
-system.cp_cntrl0.sequencer.store_waiting_on_store            3                       # Number of times a store aliased with a pending store
-system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.cp_cntrl0.sequencer1.store_waiting_on_load            1                       # Number of times a store aliased with a pending load
+system.cp_cntrl0.L2cache.num_data_array_writes           85                       # number of data array writes
+system.cp_cntrl0.L2cache.num_tag_array_reads          372                       # number of tag array reads
+system.cp_cntrl0.L2cache.num_tag_array_writes          362                       # number of tag array writes
+system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.cp_cntrl0.sequencer.store_waiting_on_load            1                       # Number of times a store aliased with a pending load
+system.cp_cntrl0.sequencer.store_waiting_on_store            4                       # Number of times a store aliased with a pending store
+system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.cp_cntrl0.sequencer1.store_waiting_on_store            4                       # Number of times a store aliased with a pending store
-system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.cp_cntrl0.fully_busy_cycles                  2                       # cycles for which number of transistions == max transitions
-system.cpu.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.dir_cntrl0.L3CacheMemory.demand_hits            0                       # Number of cache demand hits
 system.dir_cntrl0.L3CacheMemory.demand_misses            0                       # Number of cache demand misses
 system.dir_cntrl0.L3CacheMemory.demand_accesses            0                       # Number of cache demand accesses
-system.dir_cntrl0.L3CacheMemory.num_data_array_writes          374                       # number of data array writes
-system.dir_cntrl0.L3CacheMemory.num_tag_array_reads          378                       # number of tag array reads
-system.dir_cntrl0.L3CacheMemory.num_tag_array_writes          378                       # number of tag array writes
-system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls        10169                       # number of stalls caused by tag array
-system.dir_cntrl0.L3CacheMemory.num_data_array_stalls         5502                       # number of stalls caused by data array
-system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links00.int_node.percent_links_utilized     0.199210                      
-system.ruby.network.ext_links00.int_node.msg_count.Control::0          308                      
-system.ruby.network.ext_links00.int_node.msg_count.Request_Control::0          385                      
-system.ruby.network.ext_links00.int_node.msg_count.Response_Data::2          393                      
-system.ruby.network.ext_links00.int_node.msg_count.Response_Control::2          227                      
-system.ruby.network.ext_links00.int_node.msg_count.Writeback_Data::2           66                      
-system.ruby.network.ext_links00.int_node.msg_count.Writeback_Control::2           70                      
-system.ruby.network.ext_links00.int_node.msg_count.Unblock_Control::4          303                      
-system.ruby.network.ext_links00.int_node.msg_bytes.Control::0         2464                      
-system.ruby.network.ext_links00.int_node.msg_bytes.Request_Control::0         3080                      
-system.ruby.network.ext_links00.int_node.msg_bytes.Response_Data::2        28296                      
-system.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2         1816                      
-system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2         4752                      
-system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2          560                      
-system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4         2424                      
-system.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links01.int_node.percent_links_utilized     0.120981                      
-system.ruby.network.ext_links01.int_node.msg_count.Control::0          227                      
-system.ruby.network.ext_links01.int_node.msg_count.Request_Control::0          153                      
+system.dir_cntrl0.L3CacheMemory.num_data_array_writes          365                       # number of data array writes
+system.dir_cntrl0.L3CacheMemory.num_tag_array_reads          372                       # number of tag array reads
+system.dir_cntrl0.L3CacheMemory.num_tag_array_writes          369                       # number of tag array writes
+system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls         9126                       # number of stalls caused by tag array
+system.dir_cntrl0.L3CacheMemory.num_data_array_stalls         4922                       # number of stalls caused by data array
+system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links00.int_node.percent_links_utilized     0.199915                      
+system.ruby.network.ext_links00.int_node.msg_count.Control::0          300                      
+system.ruby.network.ext_links00.int_node.msg_count.Request_Control::0          372                      
+system.ruby.network.ext_links00.int_node.msg_count.Response_Data::2          383                      
+system.ruby.network.ext_links00.int_node.msg_count.Response_Control::2          217                      
+system.ruby.network.ext_links00.int_node.msg_count.Writeback_Data::2           67                      
+system.ruby.network.ext_links00.int_node.msg_count.Writeback_Control::2           71                      
+system.ruby.network.ext_links00.int_node.msg_count.Unblock_Control::4          295                      
+system.ruby.network.ext_links00.int_node.msg_bytes.Control::0         2400                      
+system.ruby.network.ext_links00.int_node.msg_bytes.Request_Control::0         2976                      
+system.ruby.network.ext_links00.int_node.msg_bytes.Response_Data::2        27576                      
+system.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2         1736                      
+system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2         4824                      
+system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2          568                      
+system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4         2360                      
+system.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links01.int_node.percent_links_utilized     0.123680                      
+system.ruby.network.ext_links01.int_node.msg_count.Control::0          216                      
+system.ruby.network.ext_links01.int_node.msg_count.Request_Control::0          155                      
 system.ruby.network.ext_links01.int_node.msg_count.Response_Data::2           95                      
-system.ruby.network.ext_links01.int_node.msg_count.Response_Control::2          217                      
-system.ruby.network.ext_links01.int_node.msg_count.Writeback_Data::2           66                      
-system.ruby.network.ext_links01.int_node.msg_count.Writeback_Control::2           70                      
-system.ruby.network.ext_links01.int_node.msg_count.Unblock_Control::4           80                      
-system.ruby.network.ext_links01.int_node.msg_bytes.Control::0         1816                      
-system.ruby.network.ext_links01.int_node.msg_bytes.Request_Control::0         1224                      
+system.ruby.network.ext_links01.int_node.msg_count.Response_Control::2          207                      
+system.ruby.network.ext_links01.int_node.msg_count.Writeback_Data::2           67                      
+system.ruby.network.ext_links01.int_node.msg_count.Writeback_Control::2           71                      
+system.ruby.network.ext_links01.int_node.msg_count.Unblock_Control::4           81                      
+system.ruby.network.ext_links01.int_node.msg_bytes.Control::0         1728                      
+system.ruby.network.ext_links01.int_node.msg_bytes.Request_Control::0         1240                      
 system.ruby.network.ext_links01.int_node.msg_bytes.Response_Data::2         6840                      
-system.ruby.network.ext_links01.int_node.msg_bytes.Response_Control::2         1736                      
-system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Data::2         4752                      
-system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Control::2          560                      
-system.ruby.network.ext_links01.int_node.msg_bytes.Unblock_Control::4          640                      
+system.ruby.network.ext_links01.int_node.msg_bytes.Response_Control::2         1656                      
+system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Data::2         4824                      
+system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Control::2          568                      
+system.ruby.network.ext_links01.int_node.msg_bytes.Unblock_Control::4          648                      
 system.tcp_cntrl0.L1cache.demand_hits               0                       # Number of cache demand hits
 system.tcp_cntrl0.L1cache.demand_misses             0                       # Number of cache demand misses
 system.tcp_cntrl0.L1cache.demand_accesses            0                       # Number of cache demand accesses
-system.tcp_cntrl0.L1cache.num_data_array_reads           14                       # number of data array reads
-system.tcp_cntrl0.L1cache.num_data_array_writes          116                       # number of data array writes
-system.tcp_cntrl0.L1cache.num_tag_array_reads          314                       # number of tag array reads
-system.tcp_cntrl0.L1cache.num_tag_array_writes          305                       # number of tag array writes
-system.tcp_cntrl0.L1cache.num_tag_array_stalls           38                       # number of stalls caused by tag array
-system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl0.L1cache.num_data_array_reads           16                       # number of data array reads
+system.tcp_cntrl0.L1cache.num_data_array_writes          112                       # number of data array writes
+system.tcp_cntrl0.L1cache.num_tag_array_reads          309                       # number of tag array reads
+system.tcp_cntrl0.L1cache.num_tag_array_writes          300                       # number of tag array writes
+system.tcp_cntrl0.L1cache.num_tag_array_stalls           28                       # number of stalls caused by tag array
+system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits            0                       # loads that hit in the TCP
-system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers            5                       # TCP to TCP load transfers
+system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers            9                       # TCP to TCP load transfers
 system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
-system.tcp_cntrl0.coalescer.gpu_ld_misses            0                       # loads that miss in the GPU
+system.tcp_cntrl0.coalescer.gpu_ld_misses            1                       # loads that miss in the GPU
 system.tcp_cntrl0.coalescer.gpu_tcp_st_hits            9                       # stores that hit in the TCP
-system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers           79                       # TCP to TCP store transfers
+system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers           74                       # TCP to TCP store transfers
 system.tcp_cntrl0.coalescer.gpu_tcc_st_hits            0                       # stores that hit in the TCC
-system.tcp_cntrl0.coalescer.gpu_st_misses           21                       # stores that miss in the GPU
+system.tcp_cntrl0.coalescer.gpu_st_misses           19                       # stores that miss in the GPU
 system.tcp_cntrl0.coalescer.cp_tcp_ld_hits            0                       # loads that hit in the TCP
 system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers            0                       # TCP to TCP load transfers
 system.tcp_cntrl0.coalescer.cp_tcc_ld_hits            0                       # loads that hit in the TCC
@@ -397,45 +405,45 @@ system.tcp_cntrl0.coalescer.cp_tcp_st_hits            0                       #
 system.tcp_cntrl0.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
 system.tcp_cntrl0.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl0.coalescer.cp_st_misses            0                       # stores that miss in the GPU
-system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links02.int_node.percent_links_utilized     0.173894                      
-system.ruby.network.ext_links02.int_node.msg_count.Control::0           81                      
-system.ruby.network.ext_links02.int_node.msg_count.Control::1          814                      
-system.ruby.network.ext_links02.int_node.msg_count.Request_Control::0          232                      
-system.ruby.network.ext_links02.int_node.msg_count.Request_Control::1          846                      
-system.ruby.network.ext_links02.int_node.msg_count.Response_Data::2          298                      
-system.ruby.network.ext_links02.int_node.msg_count.Response_Data::3         1644                      
+system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links02.int_node.percent_links_utilized     0.172944                      
+system.ruby.network.ext_links02.int_node.msg_count.Control::0           84                      
+system.ruby.network.ext_links02.int_node.msg_count.Control::1          789                      
+system.ruby.network.ext_links02.int_node.msg_count.Request_Control::0          217                      
+system.ruby.network.ext_links02.int_node.msg_count.Request_Control::1          823                      
+system.ruby.network.ext_links02.int_node.msg_count.Response_Data::2          288                      
+system.ruby.network.ext_links02.int_node.msg_count.Response_Data::3         1594                      
 system.ruby.network.ext_links02.int_node.msg_count.Response_Control::2           10                      
 system.ruby.network.ext_links02.int_node.msg_count.Response_Control::3            2                      
-system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::4          223                      
-system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::5          831                      
-system.ruby.network.ext_links02.int_node.msg_bytes.Control::0          648                      
-system.ruby.network.ext_links02.int_node.msg_bytes.Control::1         6512                      
-system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::0         1856                      
-system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::1         6768                      
-system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::2        21456                      
-system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::3       118368                      
+system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::4          214                      
+system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::5          810                      
+system.ruby.network.ext_links02.int_node.msg_bytes.Control::0          672                      
+system.ruby.network.ext_links02.int_node.msg_bytes.Control::1         6312                      
+system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::0         1736                      
+system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::1         6584                      
+system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::2        20736                      
+system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::3       114768                      
 system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::2           80                      
 system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::3           16                      
-system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::4         1784                      
-system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::5         6648                      
+system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::4         1712                      
+system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::5         6480                      
 system.tcp_cntrl1.L1cache.demand_hits               0                       # Number of cache demand hits
 system.tcp_cntrl1.L1cache.demand_misses             0                       # Number of cache demand misses
 system.tcp_cntrl1.L1cache.demand_accesses            0                       # Number of cache demand accesses
-system.tcp_cntrl1.L1cache.num_data_array_reads           10                       # number of data array reads
+system.tcp_cntrl1.L1cache.num_data_array_reads           11                       # number of data array reads
 system.tcp_cntrl1.L1cache.num_data_array_writes          108                       # number of data array writes
-system.tcp_cntrl1.L1cache.num_tag_array_reads          300                       # number of tag array reads
-system.tcp_cntrl1.L1cache.num_tag_array_writes          289                       # number of tag array writes
-system.tcp_cntrl1.L1cache.num_tag_array_stalls           44                       # number of stalls caused by tag array
-system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl1.L1cache.num_tag_array_reads          298                       # number of tag array reads
+system.tcp_cntrl1.L1cache.num_tag_array_writes          285                       # number of tag array writes
+system.tcp_cntrl1.L1cache.num_tag_array_stalls           43                       # number of stalls caused by tag array
+system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits            1                       # loads that hit in the TCP
-system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers            4                       # TCP to TCP load transfers
+system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers            8                       # TCP to TCP load transfers
 system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
-system.tcp_cntrl1.coalescer.gpu_ld_misses            1                       # loads that miss in the GPU
-system.tcp_cntrl1.coalescer.gpu_tcp_st_hits            9                       # stores that hit in the TCP
-system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers           74                       # TCP to TCP store transfers
+system.tcp_cntrl1.coalescer.gpu_ld_misses            0                       # loads that miss in the GPU
+system.tcp_cntrl1.coalescer.gpu_tcp_st_hits           11                       # stores that hit in the TCP
+system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers           69                       # TCP to TCP store transfers
 system.tcp_cntrl1.coalescer.gpu_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl1.coalescer.gpu_st_misses           20                       # stores that miss in the GPU
 system.tcp_cntrl1.coalescer.cp_tcp_ld_hits            0                       # loads that hit in the TCP
@@ -446,24 +454,23 @@ system.tcp_cntrl1.coalescer.cp_tcp_st_hits            0                       #
 system.tcp_cntrl1.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
 system.tcp_cntrl1.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl1.coalescer.cp_st_misses            0                       # stores that miss in the GPU
-system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl2.L1cache.demand_hits               0                       # Number of cache demand hits
 system.tcp_cntrl2.L1cache.demand_misses             0                       # Number of cache demand misses
 system.tcp_cntrl2.L1cache.demand_accesses            0                       # Number of cache demand accesses
-system.tcp_cntrl2.L1cache.num_data_array_reads           19                       # number of data array reads
-system.tcp_cntrl2.L1cache.num_data_array_writes          108                       # number of data array writes
-system.tcp_cntrl2.L1cache.num_tag_array_reads          302                       # number of tag array reads
-system.tcp_cntrl2.L1cache.num_tag_array_writes          292                       # number of tag array writes
-system.tcp_cntrl2.L1cache.num_tag_array_stalls           36                       # number of stalls caused by tag array
-system.tcp_cntrl2.L1cache.num_data_array_stalls            3                       # number of stalls caused by data array
-system.tcp_cntrl2.coalescer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl2.coalescer.gpu_tcp_ld_hits            1                       # loads that hit in the TCP
-system.tcp_cntrl2.coalescer.gpu_tcp_ld_transfers            9                       # TCP to TCP load transfers
+system.tcp_cntrl2.L1cache.num_data_array_reads           11                       # number of data array reads
+system.tcp_cntrl2.L1cache.num_data_array_writes          106                       # number of data array writes
+system.tcp_cntrl2.L1cache.num_tag_array_reads          286                       # number of tag array reads
+system.tcp_cntrl2.L1cache.num_tag_array_writes          275                       # number of tag array writes
+system.tcp_cntrl2.L1cache.num_tag_array_stalls           42                       # number of stalls caused by tag array
+system.tcp_cntrl2.coalescer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl2.coalescer.gpu_tcp_ld_hits            2                       # loads that hit in the TCP
+system.tcp_cntrl2.coalescer.gpu_tcp_ld_transfers            8                       # TCP to TCP load transfers
 system.tcp_cntrl2.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
-system.tcp_cntrl2.coalescer.gpu_ld_misses            0                       # loads that miss in the GPU
-system.tcp_cntrl2.coalescer.gpu_tcp_st_hits            7                       # stores that hit in the TCP
-system.tcp_cntrl2.coalescer.gpu_tcp_st_transfers           72                       # TCP to TCP store transfers
+system.tcp_cntrl2.coalescer.gpu_ld_misses            1                       # loads that miss in the GPU
+system.tcp_cntrl2.coalescer.gpu_tcp_st_hits            9                       # stores that hit in the TCP
+system.tcp_cntrl2.coalescer.gpu_tcp_st_transfers           69                       # TCP to TCP store transfers
 system.tcp_cntrl2.coalescer.gpu_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl2.coalescer.gpu_st_misses           18                       # stores that miss in the GPU
 system.tcp_cntrl2.coalescer.cp_tcp_ld_hits            0                       # loads that hit in the TCP
@@ -474,26 +481,26 @@ system.tcp_cntrl2.coalescer.cp_tcp_st_hits            0                       #
 system.tcp_cntrl2.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
 system.tcp_cntrl2.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl2.coalescer.cp_st_misses            0                       # stores that miss in the GPU
-system.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl3.L1cache.demand_hits               0                       # Number of cache demand hits
 system.tcp_cntrl3.L1cache.demand_misses             0                       # Number of cache demand misses
 system.tcp_cntrl3.L1cache.demand_accesses            0                       # Number of cache demand accesses
-system.tcp_cntrl3.L1cache.num_data_array_reads            7                       # number of data array reads
-system.tcp_cntrl3.L1cache.num_data_array_writes          104                       # number of data array writes
-system.tcp_cntrl3.L1cache.num_tag_array_reads          272                       # number of tag array reads
-system.tcp_cntrl3.L1cache.num_tag_array_writes          262                       # number of tag array writes
-system.tcp_cntrl3.L1cache.num_tag_array_stalls           16                       # number of stalls caused by tag array
+system.tcp_cntrl3.L1cache.num_data_array_reads            8                       # number of data array reads
+system.tcp_cntrl3.L1cache.num_data_array_writes           95                       # number of data array writes
+system.tcp_cntrl3.L1cache.num_tag_array_reads          260                       # number of tag array reads
+system.tcp_cntrl3.L1cache.num_tag_array_writes          253                       # number of tag array writes
+system.tcp_cntrl3.L1cache.num_tag_array_stalls           29                       # number of stalls caused by tag array
 system.tcp_cntrl3.L1cache.num_data_array_stalls            3                       # number of stalls caused by data array
-system.tcp_cntrl3.coalescer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl3.coalescer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl3.coalescer.gpu_tcp_ld_hits            0                       # loads that hit in the TCP
-system.tcp_cntrl3.coalescer.gpu_tcp_ld_transfers           13                       # TCP to TCP load transfers
+system.tcp_cntrl3.coalescer.gpu_tcp_ld_transfers           12                       # TCP to TCP load transfers
 system.tcp_cntrl3.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
 system.tcp_cntrl3.coalescer.gpu_ld_misses            0                       # loads that miss in the GPU
-system.tcp_cntrl3.coalescer.gpu_tcp_st_hits           10                       # stores that hit in the TCP
-system.tcp_cntrl3.coalescer.gpu_tcp_st_transfers           63                       # TCP to TCP store transfers
+system.tcp_cntrl3.coalescer.gpu_tcp_st_hits            7                       # stores that hit in the TCP
+system.tcp_cntrl3.coalescer.gpu_tcp_st_transfers           59                       # TCP to TCP store transfers
 system.tcp_cntrl3.coalescer.gpu_tcc_st_hits            0                       # stores that hit in the TCC
-system.tcp_cntrl3.coalescer.gpu_st_misses           18                       # stores that miss in the GPU
+system.tcp_cntrl3.coalescer.gpu_st_misses           17                       # stores that miss in the GPU
 system.tcp_cntrl3.coalescer.cp_tcp_ld_hits            0                       # loads that hit in the TCP
 system.tcp_cntrl3.coalescer.cp_tcp_ld_transfers            0                       # TCP to TCP load transfers
 system.tcp_cntrl3.coalescer.cp_tcc_ld_hits            0                       # loads that hit in the TCC
@@ -502,23 +509,24 @@ system.tcp_cntrl3.coalescer.cp_tcp_st_hits            0                       #
 system.tcp_cntrl3.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
 system.tcp_cntrl3.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl3.coalescer.cp_st_misses            0                       # stores that miss in the GPU
-system.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl4.L1cache.demand_hits               0                       # Number of cache demand hits
 system.tcp_cntrl4.L1cache.demand_misses             0                       # Number of cache demand misses
 system.tcp_cntrl4.L1cache.demand_accesses            0                       # Number of cache demand accesses
-system.tcp_cntrl4.L1cache.num_data_array_reads           14                       # number of data array reads
-system.tcp_cntrl4.L1cache.num_data_array_writes          115                       # number of data array writes
-system.tcp_cntrl4.L1cache.num_tag_array_reads          317                       # number of tag array reads
-system.tcp_cntrl4.L1cache.num_tag_array_writes          309                       # number of tag array writes
-system.tcp_cntrl4.L1cache.num_tag_array_stalls           29                       # number of stalls caused by tag array
-system.tcp_cntrl4.coalescer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl4.coalescer.gpu_tcp_ld_hits            0                       # loads that hit in the TCP
-system.tcp_cntrl4.coalescer.gpu_tcp_ld_transfers            4                       # TCP to TCP load transfers
+system.tcp_cntrl4.L1cache.num_data_array_reads           16                       # number of data array reads
+system.tcp_cntrl4.L1cache.num_data_array_writes          117                       # number of data array writes
+system.tcp_cntrl4.L1cache.num_tag_array_reads          309                       # number of tag array reads
+system.tcp_cntrl4.L1cache.num_tag_array_writes          299                       # number of tag array writes
+system.tcp_cntrl4.L1cache.num_tag_array_stalls           31                       # number of stalls caused by tag array
+system.tcp_cntrl4.L1cache.num_data_array_stalls            4                       # number of stalls caused by data array
+system.tcp_cntrl4.coalescer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl4.coalescer.gpu_tcp_ld_hits            1                       # loads that hit in the TCP
+system.tcp_cntrl4.coalescer.gpu_tcp_ld_transfers            5                       # TCP to TCP load transfers
 system.tcp_cntrl4.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
 system.tcp_cntrl4.coalescer.gpu_ld_misses            0                       # loads that miss in the GPU
-system.tcp_cntrl4.coalescer.gpu_tcp_st_hits            6                       # stores that hit in the TCP
-system.tcp_cntrl4.coalescer.gpu_tcp_st_transfers           76                       # TCP to TCP store transfers
+system.tcp_cntrl4.coalescer.gpu_tcp_st_hits            9                       # stores that hit in the TCP
+system.tcp_cntrl4.coalescer.gpu_tcp_st_transfers           72                       # TCP to TCP store transfers
 system.tcp_cntrl4.coalescer.gpu_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl4.coalescer.gpu_st_misses           26                       # stores that miss in the GPU
 system.tcp_cntrl4.coalescer.cp_tcp_ld_hits            0                       # loads that hit in the TCP
@@ -529,25 +537,25 @@ system.tcp_cntrl4.coalescer.cp_tcp_st_hits            0                       #
 system.tcp_cntrl4.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
 system.tcp_cntrl4.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl4.coalescer.cp_st_misses            0                       # stores that miss in the GPU
-system.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl5.L1cache.demand_hits               0                       # Number of cache demand hits
 system.tcp_cntrl5.L1cache.demand_misses             0                       # Number of cache demand misses
 system.tcp_cntrl5.L1cache.demand_accesses            0                       # Number of cache demand accesses
-system.tcp_cntrl5.L1cache.num_data_array_reads           10                       # number of data array reads
-system.tcp_cntrl5.L1cache.num_data_array_writes          107                       # number of data array writes
-system.tcp_cntrl5.L1cache.num_tag_array_reads          295                       # number of tag array reads
-system.tcp_cntrl5.L1cache.num_tag_array_writes          287                       # number of tag array writes
-system.tcp_cntrl5.L1cache.num_tag_array_stalls           31                       # number of stalls caused by tag array
-system.tcp_cntrl5.coalescer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl5.L1cache.num_data_array_reads            9                       # number of data array reads
+system.tcp_cntrl5.L1cache.num_data_array_writes          101                       # number of data array writes
+system.tcp_cntrl5.L1cache.num_tag_array_reads          276                       # number of tag array reads
+system.tcp_cntrl5.L1cache.num_tag_array_writes          266                       # number of tag array writes
+system.tcp_cntrl5.L1cache.num_tag_array_stalls           22                       # number of stalls caused by tag array
+system.tcp_cntrl5.coalescer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl5.coalescer.gpu_tcp_ld_hits            0                       # loads that hit in the TCP
-system.tcp_cntrl5.coalescer.gpu_tcp_ld_transfers            6                       # TCP to TCP load transfers
+system.tcp_cntrl5.coalescer.gpu_tcp_ld_transfers            3                       # TCP to TCP load transfers
 system.tcp_cntrl5.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
 system.tcp_cntrl5.coalescer.gpu_ld_misses            0                       # loads that miss in the GPU
 system.tcp_cntrl5.coalescer.gpu_tcp_st_hits            8                       # stores that hit in the TCP
-system.tcp_cntrl5.coalescer.gpu_tcp_st_transfers           69                       # TCP to TCP store transfers
+system.tcp_cntrl5.coalescer.gpu_tcp_st_transfers           67                       # TCP to TCP store transfers
 system.tcp_cntrl5.coalescer.gpu_tcc_st_hits            0                       # stores that hit in the TCC
-system.tcp_cntrl5.coalescer.gpu_st_misses           23                       # stores that miss in the GPU
+system.tcp_cntrl5.coalescer.gpu_st_misses           22                       # stores that miss in the GPU
 system.tcp_cntrl5.coalescer.cp_tcp_ld_hits            0                       # loads that hit in the TCP
 system.tcp_cntrl5.coalescer.cp_tcp_ld_transfers            0                       # TCP to TCP load transfers
 system.tcp_cntrl5.coalescer.cp_tcc_ld_hits            0                       # loads that hit in the TCC
@@ -556,25 +564,25 @@ system.tcp_cntrl5.coalescer.cp_tcp_st_hits            0                       #
 system.tcp_cntrl5.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
 system.tcp_cntrl5.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl5.coalescer.cp_st_misses            0                       # stores that miss in the GPU
-system.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl6.L1cache.demand_hits               0                       # Number of cache demand hits
 system.tcp_cntrl6.L1cache.demand_misses             0                       # Number of cache demand misses
 system.tcp_cntrl6.L1cache.demand_accesses            0                       # Number of cache demand accesses
-system.tcp_cntrl6.L1cache.num_data_array_reads           13                       # number of data array reads
-system.tcp_cntrl6.L1cache.num_data_array_writes          123                       # number of data array writes
-system.tcp_cntrl6.L1cache.num_tag_array_reads          342                       # number of tag array reads
-system.tcp_cntrl6.L1cache.num_tag_array_writes          335                       # number of tag array writes
-system.tcp_cntrl6.L1cache.num_tag_array_stalls           49                       # number of stalls caused by tag array
-system.tcp_cntrl6.coalescer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl6.L1cache.num_data_array_reads           15                       # number of data array reads
+system.tcp_cntrl6.L1cache.num_data_array_writes          120                       # number of data array writes
+system.tcp_cntrl6.L1cache.num_tag_array_reads          336                       # number of tag array reads
+system.tcp_cntrl6.L1cache.num_tag_array_writes          330                       # number of tag array writes
+system.tcp_cntrl6.L1cache.num_tag_array_stalls           44                       # number of stalls caused by tag array
+system.tcp_cntrl6.coalescer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl6.coalescer.gpu_tcp_ld_hits            1                       # loads that hit in the TCP
-system.tcp_cntrl6.coalescer.gpu_tcp_ld_transfers           11                       # TCP to TCP load transfers
+system.tcp_cntrl6.coalescer.gpu_tcp_ld_transfers            8                       # TCP to TCP load transfers
 system.tcp_cntrl6.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
 system.tcp_cntrl6.coalescer.gpu_ld_misses            1                       # loads that miss in the GPU
-system.tcp_cntrl6.coalescer.gpu_tcp_st_hits            5                       # stores that hit in the TCP
+system.tcp_cntrl6.coalescer.gpu_tcp_st_hits            4                       # stores that hit in the TCP
 system.tcp_cntrl6.coalescer.gpu_tcp_st_transfers           86                       # TCP to TCP store transfers
 system.tcp_cntrl6.coalescer.gpu_tcc_st_hits            0                       # stores that hit in the TCC
-system.tcp_cntrl6.coalescer.gpu_st_misses           19                       # stores that miss in the GPU
+system.tcp_cntrl6.coalescer.gpu_st_misses           20                       # stores that miss in the GPU
 system.tcp_cntrl6.coalescer.cp_tcp_ld_hits            0                       # loads that hit in the TCP
 system.tcp_cntrl6.coalescer.cp_tcp_ld_transfers            0                       # TCP to TCP load transfers
 system.tcp_cntrl6.coalescer.cp_tcc_ld_hits            0                       # loads that hit in the TCC
@@ -583,25 +591,25 @@ system.tcp_cntrl6.coalescer.cp_tcp_st_hits            0                       #
 system.tcp_cntrl6.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
 system.tcp_cntrl6.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl6.coalescer.cp_st_misses            0                       # stores that miss in the GPU
-system.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tcp_cntrl7.L1cache.demand_hits               0                       # Number of cache demand hits
 system.tcp_cntrl7.L1cache.demand_misses             0                       # Number of cache demand misses
 system.tcp_cntrl7.L1cache.demand_accesses            0                       # Number of cache demand accesses
-system.tcp_cntrl7.L1cache.num_data_array_reads           10                       # number of data array reads
-system.tcp_cntrl7.L1cache.num_data_array_writes           97                       # number of data array writes
-system.tcp_cntrl7.L1cache.num_tag_array_reads          263                       # number of tag array reads
-system.tcp_cntrl7.L1cache.num_tag_array_writes          256                       # number of tag array writes
+system.tcp_cntrl7.L1cache.num_data_array_reads           13                       # number of data array reads
+system.tcp_cntrl7.L1cache.num_data_array_writes          101                       # number of data array writes
+system.tcp_cntrl7.L1cache.num_tag_array_reads          275                       # number of tag array reads
+system.tcp_cntrl7.L1cache.num_tag_array_writes          266                       # number of tag array writes
 system.tcp_cntrl7.L1cache.num_tag_array_stalls           11                       # number of stalls caused by tag array
-system.tcp_cntrl7.coalescer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl7.coalescer.gpu_tcp_ld_hits            1                       # loads that hit in the TCP
-system.tcp_cntrl7.coalescer.gpu_tcp_ld_transfers           10                       # TCP to TCP load transfers
+system.tcp_cntrl7.coalescer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl7.coalescer.gpu_tcp_ld_hits            2                       # loads that hit in the TCP
+system.tcp_cntrl7.coalescer.gpu_tcp_ld_transfers            9                       # TCP to TCP load transfers
 system.tcp_cntrl7.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
-system.tcp_cntrl7.coalescer.gpu_ld_misses            1                       # loads that miss in the GPU
-system.tcp_cntrl7.coalescer.gpu_tcp_st_hits            6                       # stores that hit in the TCP
-system.tcp_cntrl7.coalescer.gpu_tcp_st_transfers           63                       # TCP to TCP store transfers
+system.tcp_cntrl7.coalescer.gpu_ld_misses            0                       # loads that miss in the GPU
+system.tcp_cntrl7.coalescer.gpu_tcp_st_hits            7                       # stores that hit in the TCP
+system.tcp_cntrl7.coalescer.gpu_tcp_st_transfers           66                       # TCP to TCP store transfers
 system.tcp_cntrl7.coalescer.gpu_tcc_st_hits            0                       # stores that hit in the TCC
-system.tcp_cntrl7.coalescer.gpu_st_misses           16                       # stores that miss in the GPU
+system.tcp_cntrl7.coalescer.gpu_st_misses           18                       # stores that miss in the GPU
 system.tcp_cntrl7.coalescer.cp_tcp_ld_hits            0                       # loads that hit in the TCP
 system.tcp_cntrl7.coalescer.cp_tcp_ld_transfers            0                       # TCP to TCP load transfers
 system.tcp_cntrl7.coalescer.cp_tcc_ld_hits            0                       # loads that hit in the TCC
@@ -610,633 +618,625 @@ system.tcp_cntrl7.coalescer.cp_tcp_st_hits            0                       #
 system.tcp_cntrl7.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
 system.tcp_cntrl7.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
 system.tcp_cntrl7.coalescer.cp_st_misses            0                       # stores that miss in the GPU
-system.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.sqc_cntrl0.L1cache.demand_hits               0                       # Number of cache demand hits
 system.sqc_cntrl0.L1cache.demand_misses             0                       # Number of cache demand misses
 system.sqc_cntrl0.L1cache.demand_accesses            0                       # Number of cache demand accesses
 system.sqc_cntrl0.L1cache.num_data_array_reads           12                       # number of data array reads
 system.sqc_cntrl0.L1cache.num_data_array_writes           12                       # number of data array writes
-system.sqc_cntrl0.L1cache.num_tag_array_reads           22                       # number of tag array reads
-system.sqc_cntrl0.L1cache.num_tag_array_writes           22                       # number of tag array writes
-system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.sqc_cntrl0.L1cache.num_tag_array_reads           23                       # number of tag array reads
+system.sqc_cntrl0.L1cache.num_tag_array_writes           23                       # number of tag array writes
+system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.sqc_cntrl1.L1cache.demand_hits               0                       # Number of cache demand hits
 system.sqc_cntrl1.L1cache.demand_misses             0                       # Number of cache demand misses
 system.sqc_cntrl1.L1cache.demand_accesses            0                       # Number of cache demand accesses
-system.sqc_cntrl1.L1cache.num_data_array_reads           15                       # number of data array reads
-system.sqc_cntrl1.L1cache.num_data_array_writes           15                       # number of data array writes
-system.sqc_cntrl1.L1cache.num_tag_array_reads           29                       # number of tag array reads
-system.sqc_cntrl1.L1cache.num_tag_array_writes           29                       # number of tag array writes
-system.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.sqc_cntrl1.L1cache.num_data_array_reads           12                       # number of data array reads
+system.sqc_cntrl1.L1cache.num_data_array_writes           12                       # number of data array writes
+system.sqc_cntrl1.L1cache.num_tag_array_reads           23                       # number of tag array reads
+system.sqc_cntrl1.L1cache.num_tag_array_writes           23                       # number of tag array writes
+system.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tcc_cntrl0.L2cache.demand_hits               0                       # Number of cache demand hits
 system.tcc_cntrl0.L2cache.demand_misses             0                       # Number of cache demand misses
 system.tcc_cntrl0.L2cache.demand_accesses            0                       # Number of cache demand accesses
-system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
+system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
 system.tccdir_cntrl0.directory.demand_hits            0                       # Number of cache demand hits
 system.tccdir_cntrl0.directory.demand_misses            0                       # Number of cache demand misses
 system.tccdir_cntrl0.directory.demand_accesses            0                       # Number of cache demand accesses
-system.tccdir_cntrl0.directory.num_tag_array_reads          917                       # number of tag array reads
-system.tccdir_cntrl0.directory.num_tag_array_writes          902                       # number of tag array writes
-system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Control            1430                      
-system.ruby.network.msg_count.Request_Control         1616                      
-system.ruby.network.msg_count.Response_Data         2430                      
-system.ruby.network.msg_count.Response_Control          456                      
-system.ruby.network.msg_count.Writeback_Data          132                      
-system.ruby.network.msg_count.Writeback_Control          140                      
-system.ruby.network.msg_count.Unblock_Control         1437                      
-system.ruby.network.msg_byte.Control            11440                      
-system.ruby.network.msg_byte.Request_Control        12928                      
-system.ruby.network.msg_byte.Response_Data       174960                      
-system.ruby.network.msg_byte.Response_Control         3648                      
-system.ruby.network.msg_byte.Writeback_Data         9504                      
-system.ruby.network.msg_byte.Writeback_Control         1120                      
-system.ruby.network.msg_byte.Unblock_Control        11496                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        14181                       # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links00.int_node.throttle0.link_utilization     0.250555                      
-system.ruby.network.ext_links00.int_node.throttle0.msg_count.Request_Control::0          385                      
+system.tccdir_cntrl0.directory.num_tag_array_reads          896                       # number of tag array reads
+system.tccdir_cntrl0.directory.num_tag_array_writes          882                       # number of tag array writes
+system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.ruby.network.msg_count.Control            1389                      
+system.ruby.network.msg_count.Request_Control         1567                      
+system.ruby.network.msg_count.Response_Data         2360                      
+system.ruby.network.msg_count.Response_Control          436                      
+system.ruby.network.msg_count.Writeback_Data          134                      
+system.ruby.network.msg_count.Writeback_Control          142                      
+system.ruby.network.msg_count.Unblock_Control         1400                      
+system.ruby.network.msg_byte.Control            11112                      
+system.ruby.network.msg_byte.Request_Control        12536                      
+system.ruby.network.msg_byte.Response_Data       169920                      
+system.ruby.network.msg_byte.Response_Control         3488                      
+system.ruby.network.msg_byte.Writeback_Data         9648                      
+system.ruby.network.msg_byte.Writeback_Control         1136                      
+system.ruby.network.msg_byte.Unblock_Control        11200                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        13821                       # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links00.int_node.throttle0.link_utilization     0.254594                      
+system.ruby.network.ext_links00.int_node.throttle0.msg_count.Request_Control::0          372                      
 system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Data::2           85                      
-system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Control::2          227                      
-system.ruby.network.ext_links00.int_node.throttle0.msg_count.Writeback_Data::2           66                      
-system.ruby.network.ext_links00.int_node.throttle0.msg_count.Unblock_Control::4          303                      
-system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Request_Control::0         3080                      
+system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Control::2          217                      
+system.ruby.network.ext_links00.int_node.throttle0.msg_count.Writeback_Data::2           67                      
+system.ruby.network.ext_links00.int_node.throttle0.msg_count.Unblock_Control::4          295                      
+system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Request_Control::0         2976                      
 system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Data::2         6120                      
-system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Control::2         1816                      
-system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Writeback_Data::2         4752                      
-system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Unblock_Control::4         2424                      
-system.ruby.network.ext_links00.int_node.throttle1.link_utilization     0.113047                      
-system.ruby.network.ext_links00.int_node.throttle1.msg_count.Control::0          227                      
-system.ruby.network.ext_links00.int_node.throttle1.msg_count.Response_Data::2           81                      
-system.ruby.network.ext_links00.int_node.throttle1.msg_count.Writeback_Control::2           70                      
-system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Control::0         1816                      
-system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Response_Data::2         5832                      
-system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Writeback_Control::2          560                      
-system.ruby.network.ext_links00.int_node.throttle2.link_utilization     0.234028                      
-system.ruby.network.ext_links00.int_node.throttle2.msg_count.Control::0           81                      
-system.ruby.network.ext_links00.int_node.throttle2.msg_count.Response_Data::2          227                      
-system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Control::0          648                      
-system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Response_Data::2        16344                      
-system.ruby.network.ext_links01.int_node.throttle0.link_utilization     0.113047                      
-system.ruby.network.ext_links01.int_node.throttle0.msg_count.Control::0          227                      
-system.ruby.network.ext_links01.int_node.throttle0.msg_count.Response_Data::2           81                      
-system.ruby.network.ext_links01.int_node.throttle0.msg_count.Writeback_Control::2           70                      
-system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Control::0         1816                      
-system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Response_Data::2         5832                      
-system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Writeback_Control::2          560                      
-system.ruby.network.ext_links01.int_node.throttle1.link_utilization     0.128914                      
-system.ruby.network.ext_links01.int_node.throttle1.msg_count.Request_Control::0          153                      
-system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Data::2           14                      
-system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Control::2          217                      
-system.ruby.network.ext_links01.int_node.throttle1.msg_count.Writeback_Data::2           66                      
-system.ruby.network.ext_links01.int_node.throttle1.msg_count.Unblock_Control::4           80                      
-system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Request_Control::0         1224                      
-system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Data::2         1008                      
-system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Control::2         1736                      
-system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Writeback_Data::2         4752                      
-system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Unblock_Control::4          640                      
-system.ruby.network.ext_links02.int_node.throttle0.link_utilization     0.115361                      
-system.ruby.network.ext_links02.int_node.throttle0.msg_count.Control::1          102                      
-system.ruby.network.ext_links02.int_node.throttle0.msg_count.Response_Data::3          105                      
-system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Control::1          816                      
-system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Response_Data::3         7560                      
-system.ruby.network.ext_links02.int_node.throttle1.link_utilization     0.108750                      
-system.ruby.network.ext_links02.int_node.throttle1.msg_count.Control::1           96                      
-system.ruby.network.ext_links02.int_node.throttle1.msg_count.Response_Data::3           99                      
-system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Control::1          768                      
-system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Response_Data::3         7128                      
-system.ruby.network.ext_links02.int_node.throttle2.link_utilization     0.109742                      
-system.ruby.network.ext_links02.int_node.throttle2.msg_count.Control::1          105                      
-system.ruby.network.ext_links02.int_node.throttle2.msg_count.Response_Data::3           99                      
-system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Control::1          840                      
-system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Response_Data::3         7128                      
-system.ruby.network.ext_links02.int_node.throttle3.link_utilization     0.102690                      
+system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Control::2         1736                      
+system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Writeback_Data::2         4824                      
+system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Unblock_Control::4         2360                      
+system.ruby.network.ext_links00.int_node.throttle1.link_utilization     0.115879                      
+system.ruby.network.ext_links00.int_node.throttle1.msg_count.Control::0          216                      
+system.ruby.network.ext_links00.int_node.throttle1.msg_count.Response_Data::2           82                      
+system.ruby.network.ext_links00.int_node.throttle1.msg_count.Writeback_Control::2           71                      
+system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Control::0         1728                      
+system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Response_Data::2         5904                      
+system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Writeback_Control::2          568                      
+system.ruby.network.ext_links00.int_node.throttle2.link_utilization     0.229271                      
+system.ruby.network.ext_links00.int_node.throttle2.msg_count.Control::0           84                      
+system.ruby.network.ext_links00.int_node.throttle2.msg_count.Response_Data::2          216                      
+system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Control::0          672                      
+system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Response_Data::2        15552                      
+system.ruby.network.ext_links01.int_node.throttle0.link_utilization     0.115879                      
+system.ruby.network.ext_links01.int_node.throttle0.msg_count.Control::0          216                      
+system.ruby.network.ext_links01.int_node.throttle0.msg_count.Response_Data::2           82                      
+system.ruby.network.ext_links01.int_node.throttle0.msg_count.Writeback_Control::2           71                      
+system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Control::0         1728                      
+system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Response_Data::2         5904                      
+system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Writeback_Control::2          568                      
+system.ruby.network.ext_links01.int_node.throttle1.link_utilization     0.131480                      
+system.ruby.network.ext_links01.int_node.throttle1.msg_count.Request_Control::0          155                      
+system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Data::2           13                      
+system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Control::2          207                      
+system.ruby.network.ext_links01.int_node.throttle1.msg_count.Writeback_Data::2           67                      
+system.ruby.network.ext_links01.int_node.throttle1.msg_count.Unblock_Control::4           81                      
+system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Request_Control::0         1240                      
+system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Data::2          936                      
+system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Control::2         1656                      
+system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Writeback_Data::2         4824                      
+system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Unblock_Control::4          648                      
+system.ruby.network.ext_links02.int_node.throttle0.link_utilization     0.116105                      
+system.ruby.network.ext_links02.int_node.throttle0.msg_count.Control::1          100                      
+system.ruby.network.ext_links02.int_node.throttle0.msg_count.Response_Data::3          103                      
+system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Control::1          800                      
+system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Response_Data::3         7416                      
+system.ruby.network.ext_links02.int_node.throttle1.link_utilization     0.109661                      
+system.ruby.network.ext_links02.int_node.throttle1.msg_count.Control::1           97                      
+system.ruby.network.ext_links02.int_node.throttle1.msg_count.Response_Data::3           97                      
+system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Control::1          776                      
+system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Response_Data::3         6984                      
+system.ruby.network.ext_links02.int_node.throttle2.link_utilization     0.108078                      
+system.ruby.network.ext_links02.int_node.throttle2.msg_count.Control::1           92                      
+system.ruby.network.ext_links02.int_node.throttle2.msg_count.Response_Data::3           96                      
+system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Control::1          736                      
+system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Response_Data::3         6912                      
+system.ruby.network.ext_links02.int_node.throttle3.link_utilization     0.099260                      
 system.ruby.network.ext_links02.int_node.throttle3.msg_count.Control::1           86                      
-system.ruby.network.ext_links02.int_node.throttle3.msg_count.Response_Data::3           94                      
+system.ruby.network.ext_links02.int_node.throttle3.msg_count.Response_Data::3           88                      
 system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Control::1          688                      
-system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Response_Data::3         6768                      
-system.ruby.network.ext_links02.int_node.throttle4.link_utilization     0.116573                      
+system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Response_Data::3         6336                      
+system.ruby.network.ext_links02.int_node.throttle4.link_utilization     0.116557                      
 system.ruby.network.ext_links02.int_node.throttle4.msg_count.Control::1          104                      
-system.ruby.network.ext_links02.int_node.throttle4.msg_count.Response_Data::3          106                      
+system.ruby.network.ext_links02.int_node.throttle4.msg_count.Response_Data::3          103                      
 system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Control::1          832                      
-system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Response_Data::3         7632                      
-system.ruby.network.ext_links02.int_node.throttle5.link_utilization     0.107759                      
-system.ruby.network.ext_links02.int_node.throttle5.msg_count.Control::1           96                      
-system.ruby.network.ext_links02.int_node.throttle5.msg_count.Response_Data::3           98                      
-system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Control::1          768                      
-system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Response_Data::3         7056                      
-system.ruby.network.ext_links02.int_node.throttle6.link_utilization     0.128473                      
-system.ruby.network.ext_links02.int_node.throttle6.msg_count.Control::1          113                      
-system.ruby.network.ext_links02.int_node.throttle6.msg_count.Response_Data::3          117                      
-system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Control::1          904                      
-system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Response_Data::3         8424                      
-system.ruby.network.ext_links02.int_node.throttle7.link_utilization     0.098944                      
-system.ruby.network.ext_links02.int_node.throttle7.msg_count.Control::1           88                      
-system.ruby.network.ext_links02.int_node.throttle7.msg_count.Response_Data::3           90                      
-system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Control::1          704                      
-system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Response_Data::3         6480                      
+system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Response_Data::3         7416                      
+system.ruby.network.ext_links02.int_node.throttle5.link_utilization     0.103556                      
+system.ruby.network.ext_links02.int_node.throttle5.msg_count.Control::1           88                      
+system.ruby.network.ext_links02.int_node.throttle5.msg_count.Response_Data::3           92                      
+system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Control::1          704                      
+system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Response_Data::3         6624                      
+system.ruby.network.ext_links02.int_node.throttle6.link_utilization     0.129558                      
+system.ruby.network.ext_links02.int_node.throttle6.msg_count.Control::1          111                      
+system.ruby.network.ext_links02.int_node.throttle6.msg_count.Response_Data::3          115                      
+system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Control::1          888                      
+system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Response_Data::3         8280                      
+system.ruby.network.ext_links02.int_node.throttle7.link_utilization     0.104687                      
+system.ruby.network.ext_links02.int_node.throttle7.msg_count.Control::1           89                      
+system.ruby.network.ext_links02.int_node.throttle7.msg_count.Response_Data::3           93                      
+system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Control::1          712                      
+system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Response_Data::3         6696                      
 system.ruby.network.ext_links02.int_node.throttle8.link_utilization            0                      
-system.ruby.network.ext_links02.int_node.throttle9.link_utilization     1.221264                      
-system.ruby.network.ext_links02.int_node.throttle9.msg_count.Control::0           81                      
-system.ruby.network.ext_links02.int_node.throttle9.msg_count.Request_Control::1          846                      
-system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::2          227                      
-system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::3          809                      
+system.ruby.network.ext_links02.int_node.throttle9.link_utilization     1.210793                      
+system.ruby.network.ext_links02.int_node.throttle9.msg_count.Control::0           84                      
+system.ruby.network.ext_links02.int_node.throttle9.msg_count.Request_Control::1          823                      
+system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::2          216                      
+system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::3          783                      
 system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Control::3            2                      
-system.ruby.network.ext_links02.int_node.throttle9.msg_count.Unblock_Control::5          831                      
-system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Control::0          648                      
-system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Request_Control::1         6768                      
-system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::2        16344                      
-system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::3        58248                      
+system.ruby.network.ext_links02.int_node.throttle9.msg_count.Unblock_Control::5          810                      
+system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Control::0          672                      
+system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Request_Control::1         6584                      
+system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::2        15552                      
+system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::3        56376                      
 system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Control::3           16                      
-system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Unblock_Control::5         6648                      
-system.ruby.network.ext_links02.int_node.throttle10.link_utilization     0.013002                      
-system.ruby.network.ext_links02.int_node.throttle10.msg_count.Control::1           10                      
+system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Unblock_Control::5         6480                      
+system.ruby.network.ext_links02.int_node.throttle10.link_utilization     0.013453                      
+system.ruby.network.ext_links02.int_node.throttle10.msg_count.Control::1           11                      
 system.ruby.network.ext_links02.int_node.throttle10.msg_count.Response_Data::3           12                      
-system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Control::1           80                      
+system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Control::1           88                      
 system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Response_Data::3          864                      
-system.ruby.network.ext_links02.int_node.throttle11.link_utilization     0.016417                      
-system.ruby.network.ext_links02.int_node.throttle11.msg_count.Control::1           14                      
-system.ruby.network.ext_links02.int_node.throttle11.msg_count.Response_Data::3           15                      
-system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Control::1          112                      
-system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Response_Data::3         1080                      
-system.ruby.network.ext_links02.int_node.throttle12.link_utilization     0.121642                      
-system.ruby.network.ext_links02.int_node.throttle12.msg_count.Request_Control::0          232                      
-system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Data::2           71                      
+system.ruby.network.ext_links02.int_node.throttle11.link_utilization     0.013453                      
+system.ruby.network.ext_links02.int_node.throttle11.msg_count.Control::1           11                      
+system.ruby.network.ext_links02.int_node.throttle11.msg_count.Response_Data::3           12                      
+system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Control::1           88                      
+system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Response_Data::3          864                      
+system.ruby.network.ext_links02.int_node.throttle12.link_utilization     0.123114                      
+system.ruby.network.ext_links02.int_node.throttle12.msg_count.Request_Control::0          217                      
+system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Data::2           72                      
 system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Control::2           10                      
-system.ruby.network.ext_links02.int_node.throttle12.msg_count.Unblock_Control::4          223                      
-system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Request_Control::0         1856                      
-system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Data::2         5112                      
+system.ruby.network.ext_links02.int_node.throttle12.msg_count.Unblock_Control::4          214                      
+system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Request_Control::0         1736                      
+system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Data::2         5184                      
 system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Control::2           80                      
-system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Unblock_Control::4         1784                      
+system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Unblock_Control::4         1712                      
 system.ruby.CorePair_Controller.C0_Load_L1miss            1      0.00%      0.00%
-system.ruby.CorePair_Controller.C1_Load_L1miss            1      0.00%      0.00%
+system.ruby.CorePair_Controller.C1_Load_L1miss            2      0.00%      0.00%
 system.ruby.CorePair_Controller.Ifetch0_L1miss            2      0.00%      0.00%
 system.ruby.CorePair_Controller.Ifetch1_L1miss            1      0.00%      0.00%
 system.ruby.CorePair_Controller.C0_Store_L1miss           45      0.00%      0.00%
 system.ruby.CorePair_Controller.C0_Store_L1hit            2      0.00%      0.00%
-system.ruby.CorePair_Controller.C1_Store_L1miss           73      0.00%      0.00%
+system.ruby.CorePair_Controller.C1_Store_L1miss           72      0.00%      0.00%
 system.ruby.CorePair_Controller.NB_AckS             4      0.00%      0.00%
-system.ruby.CorePair_Controller.NB_AckM            77      0.00%      0.00%
-system.ruby.CorePair_Controller.NB_AckWB           70      0.00%      0.00%
-system.ruby.CorePair_Controller.L1D0_Repl           19      0.00%      0.00%
-system.ruby.CorePair_Controller.L2_Repl         36624      0.00%      0.00%
-system.ruby.CorePair_Controller.PrbInvData          223      0.00%      0.00%
+system.ruby.CorePair_Controller.NB_AckM            78      0.00%      0.00%
+system.ruby.CorePair_Controller.NB_AckWB           71      0.00%      0.00%
+system.ruby.CorePair_Controller.L1D0_Repl           11      0.00%      0.00%
+system.ruby.CorePair_Controller.L2_Repl         35555      0.00%      0.00%
+system.ruby.CorePair_Controller.PrbInvData          212      0.00%      0.00%
 system.ruby.CorePair_Controller.PrbShrData            4      0.00%      0.00%
 system.ruby.CorePair_Controller.I.C0_Load_L1miss            1      0.00%      0.00%
-system.ruby.CorePair_Controller.I.C1_Load_L1miss            1      0.00%      0.00%
+system.ruby.CorePair_Controller.I.C1_Load_L1miss            2      0.00%      0.00%
 system.ruby.CorePair_Controller.I.Ifetch0_L1miss            2      0.00%      0.00%
 system.ruby.CorePair_Controller.I.Ifetch1_L1miss            1      0.00%      0.00%
 system.ruby.CorePair_Controller.I.C0_Store_L1miss           41      0.00%      0.00%
-system.ruby.CorePair_Controller.I.C1_Store_L1miss           37      0.00%      0.00%
-system.ruby.CorePair_Controller.I.PrbInvData          209      0.00%      0.00%
-system.ruby.CorePair_Controller.I.PrbShrData            3      0.00%      0.00%
+system.ruby.CorePair_Controller.I.C1_Store_L1miss           38      0.00%      0.00%
+system.ruby.CorePair_Controller.I.PrbInvData          198      0.00%      0.00%
+system.ruby.CorePair_Controller.I.PrbShrData            4      0.00%      0.00%
 system.ruby.CorePair_Controller.S.L2_Repl            3      0.00%      0.00%
 system.ruby.CorePair_Controller.S.PrbInvData            1      0.00%      0.00%
-system.ruby.CorePair_Controller.O.PrbInvData            1      0.00%      0.00%
 system.ruby.CorePair_Controller.M0.C0_Store_L1hit            2      0.00%      0.00%
 system.ruby.CorePair_Controller.M0.L2_Repl           33      0.00%      0.00%
-system.ruby.CorePair_Controller.M0.PrbInvData            5      0.00%      0.00%
-system.ruby.CorePair_Controller.M0.PrbShrData            1      0.00%      0.00%
+system.ruby.CorePair_Controller.M0.PrbInvData            6      0.00%      0.00%
 system.ruby.CorePair_Controller.M1.C0_Store_L1miss            1      0.00%      0.00%
 system.ruby.CorePair_Controller.M1.L2_Repl           36      0.00%      0.00%
-system.ruby.CorePair_Controller.M1.PrbInvData            2      0.00%      0.00%
+system.ruby.CorePair_Controller.M1.PrbInvData            3      0.00%      0.00%
 system.ruby.CorePair_Controller.I_M0.C1_Store_L1miss            5      0.00%      0.00%
 system.ruby.CorePair_Controller.I_M0.NB_AckM           35      0.00%      0.00%
 system.ruby.CorePair_Controller.I_M0.L1D0_Repl           11      0.00%      0.00%
-system.ruby.CorePair_Controller.I_M0.L2_Repl        16208      0.00%      0.00%
+system.ruby.CorePair_Controller.I_M0.L2_Repl        15350      0.00%      0.00%
 system.ruby.CorePair_Controller.I_M1.C0_Store_L1miss            3      0.00%      0.00%
-system.ruby.CorePair_Controller.I_M1.NB_AckM           34      0.00%      0.00%
-system.ruby.CorePair_Controller.I_M1.L2_Repl        14782      0.00%      0.00%
+system.ruby.CorePair_Controller.I_M1.NB_AckM           35      0.00%      0.00%
+system.ruby.CorePair_Controller.I_M1.L2_Repl        14410      0.00%      0.00%
 system.ruby.CorePair_Controller.I_M0M1.NB_AckM            5      0.00%      0.00%
-system.ruby.CorePair_Controller.I_M0M1.L2_Repl         3020      0.00%      0.00%
+system.ruby.CorePair_Controller.I_M0M1.L2_Repl         3283      0.00%      0.00%
 system.ruby.CorePair_Controller.I_M1M0.NB_AckM            3      0.00%      0.00%
-system.ruby.CorePair_Controller.I_M1M0.L2_Repl         1059      0.00%      0.00%
+system.ruby.CorePair_Controller.I_M1M0.L2_Repl         1200      0.00%      0.00%
 system.ruby.CorePair_Controller.I_E0S.NB_AckS            1      0.00%      0.00%
-system.ruby.CorePair_Controller.I_E0S.L1D0_Repl            8      0.00%      0.00%
-system.ruby.CorePair_Controller.I_E0S.L2_Repl          493      0.00%      0.00%
+system.ruby.CorePair_Controller.I_E0S.L2_Repl          404      0.00%      0.00%
 system.ruby.CorePair_Controller.I_E1S.NB_AckS            1      0.00%      0.00%
-system.ruby.CorePair_Controller.I_E1S.L2_Repl          638      0.00%      0.00%
+system.ruby.CorePair_Controller.I_E1S.L2_Repl          392      0.00%      0.00%
 system.ruby.CorePair_Controller.ES_I.NB_AckWB            2      0.00%      0.00%
-system.ruby.CorePair_Controller.MO_I.NB_AckWB           64      0.00%      0.00%
-system.ruby.CorePair_Controller.MO_I.PrbInvData            5      0.00%      0.00%
-system.ruby.CorePair_Controller.S0.C1_Store_L1miss           31      0.00%      0.00%
+system.ruby.CorePair_Controller.MO_I.NB_AckWB           65      0.00%      0.00%
+system.ruby.CorePair_Controller.MO_I.PrbInvData            4      0.00%      0.00%
+system.ruby.CorePair_Controller.S0.C1_Store_L1miss           29      0.00%      0.00%
 system.ruby.CorePair_Controller.S0.NB_AckS            1      0.00%      0.00%
-system.ruby.CorePair_Controller.S0.L2_Repl          352      0.00%      0.00%
+system.ruby.CorePair_Controller.S0.L2_Repl          444      0.00%      0.00%
 system.ruby.CorePair_Controller.S1.NB_AckS            1      0.00%      0.00%
 system.ruby.CorePair_Controller.I_C.NB_AckWB            4      0.00%      0.00%
-system.ruby.Directory_Controller.RdBlkS             3      0.00%      0.00%
-system.ruby.Directory_Controller.RdBlkM           309      0.00%      0.00%
+system.ruby.Directory_Controller.RdBlkS             4      0.00%      0.00%
+system.ruby.Directory_Controller.RdBlkM           297      0.00%      0.00%
 system.ruby.Directory_Controller.RdBlk              6      0.00%      0.00%
-system.ruby.Directory_Controller.VicDirty           68      0.00%      0.00%
+system.ruby.Directory_Controller.VicDirty           69      0.00%      0.00%
 system.ruby.Directory_Controller.VicClean            2      0.00%      0.00%
-system.ruby.Directory_Controller.CPUData           66      0.00%      0.00%
+system.ruby.Directory_Controller.CPUData           67      0.00%      0.00%
 system.ruby.Directory_Controller.StaleWB            4      0.00%      0.00%
-system.ruby.Directory_Controller.CPUPrbResp          308      0.00%      0.00%
-system.ruby.Directory_Controller.ProbeAcksComplete          308      0.00%      0.00%
-system.ruby.Directory_Controller.L3Hit             49      0.00%      0.00%
-system.ruby.Directory_Controller.MemData          259      0.00%      0.00%
-system.ruby.Directory_Controller.WBAck              9      0.00%      0.00%
-system.ruby.Directory_Controller.CoreUnblock          303      0.00%      0.00%
-system.ruby.Directory_Controller.U.RdBlkS            3      0.00%      0.00%
-system.ruby.Directory_Controller.U.RdBlkM          300      0.00%      0.00%
-system.ruby.Directory_Controller.U.RdBlk            5      0.00%      0.00%
-system.ruby.Directory_Controller.U.VicDirty           68      0.00%      0.00%
+system.ruby.Directory_Controller.CPUPrbResp          298      0.00%      0.00%
+system.ruby.Directory_Controller.ProbeAcksComplete          298      0.00%      0.00%
+system.ruby.Directory_Controller.L3Hit             45      0.00%      0.00%
+system.ruby.Directory_Controller.MemData          256      0.00%      0.00%
+system.ruby.Directory_Controller.WBAck             14      0.00%      0.00%
+system.ruby.Directory_Controller.CoreUnblock          295      0.00%      0.00%
+system.ruby.Directory_Controller.U.RdBlkS            4      0.00%      0.00%
+system.ruby.Directory_Controller.U.RdBlkM          291      0.00%      0.00%
+system.ruby.Directory_Controller.U.RdBlk            6      0.00%      0.00%
+system.ruby.Directory_Controller.U.VicDirty           69      0.00%      0.00%
 system.ruby.Directory_Controller.U.VicClean            2      0.00%      0.00%
-system.ruby.Directory_Controller.U.WBAck            9      0.00%      0.00%
-system.ruby.Directory_Controller.BL.RdBlkM            1      0.00%      0.00%
-system.ruby.Directory_Controller.BL.CPUData           66      0.00%      0.00%
+system.ruby.Directory_Controller.U.WBAck           14      0.00%      0.00%
+system.ruby.Directory_Controller.BL.CPUData           67      0.00%      0.00%
 system.ruby.Directory_Controller.BL.StaleWB            4      0.00%      0.00%
-system.ruby.Directory_Controller.BM_M.MemData            8      0.00%      0.00%
+system.ruby.Directory_Controller.BM_M.MemData            9      0.00%      0.00%
 system.ruby.Directory_Controller.BS_PM.L3Hit            1      0.00%      0.00%
-system.ruby.Directory_Controller.BS_PM.MemData            2      0.00%      0.00%
+system.ruby.Directory_Controller.BS_PM.MemData            3      0.00%      0.00%
 system.ruby.Directory_Controller.BM_PM.RdBlkM            1      0.00%      0.00%
-system.ruby.Directory_Controller.BM_PM.CPUPrbResp           12      0.00%      0.00%
-system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete            8      0.00%      0.00%
-system.ruby.Directory_Controller.BM_PM.L3Hit           46      0.00%      0.00%
-system.ruby.Directory_Controller.BM_PM.MemData          246      0.00%      0.00%
-system.ruby.Directory_Controller.B_PM.L3Hit            2      0.00%      0.00%
+system.ruby.Directory_Controller.BM_PM.CPUPrbResp           13      0.00%      0.00%
+system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete            9      0.00%      0.00%
+system.ruby.Directory_Controller.BM_PM.L3Hit           41      0.00%      0.00%
+system.ruby.Directory_Controller.BM_PM.MemData          241      0.00%      0.00%
+system.ruby.Directory_Controller.B_PM.L3Hit            3      0.00%      0.00%
 system.ruby.Directory_Controller.B_PM.MemData            3      0.00%      0.00%
 system.ruby.Directory_Controller.BS_Pm.CPUPrbResp            3      0.00%      0.00%
 system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete            3      0.00%      0.00%
 system.ruby.Directory_Controller.BM_Pm.RdBlkM            3      0.00%      0.00%
-system.ruby.Directory_Controller.BM_Pm.CPUPrbResp          288      0.00%      0.00%
-system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete          292      0.00%      0.00%
+system.ruby.Directory_Controller.BM_Pm.CPUPrbResp          277      0.00%      0.00%
+system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete          281      0.00%      0.00%
 system.ruby.Directory_Controller.B_Pm.CPUPrbResp            5      0.00%      0.00%
 system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete            5      0.00%      0.00%
-system.ruby.Directory_Controller.B.RdBlkM            4      0.00%      0.00%
-system.ruby.Directory_Controller.B.RdBlk            1      0.00%      0.00%
-system.ruby.Directory_Controller.B.CoreUnblock          303      0.00%      0.00%
+system.ruby.Directory_Controller.B.RdBlkM            2      0.00%      0.00%
+system.ruby.Directory_Controller.B.CoreUnblock          295      0.00%      0.00%
 system.ruby.LD.latency_hist_seqr::bucket_size         1024                      
 system.ruby.LD.latency_hist_seqr::max_bucket        10239                      
 system.ruby.LD.latency_hist_seqr::samples            1                      
-system.ruby.LD.latency_hist_seqr::mean           5324                      
-system.ruby.LD.latency_hist_seqr::gmean   5324.000000                      
+system.ruby.LD.latency_hist_seqr::mean           5256                      
+system.ruby.LD.latency_hist_seqr::gmean   5256.000000                      
 system.ruby.LD.latency_hist_seqr::stdev           nan                      
 system.ruby.LD.latency_hist_seqr         |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist_seqr::total             1                      
-system.ruby.LD.latency_hist_coalsr::bucket_size          128                      
-system.ruby.LD.latency_hist_coalsr::max_bucket         1279                      
-system.ruby.LD.latency_hist_coalsr::samples           69                      
-system.ruby.LD.latency_hist_coalsr::mean   111.289855                      
-system.ruby.LD.latency_hist_coalsr::gmean    81.460116                      
-system.ruby.LD.latency_hist_coalsr::stdev    88.701101                      
-system.ruby.LD.latency_hist_coalsr       |          63     91.30%     91.30% |           2      2.90%     94.20% |           2      2.90%     97.10% |           1      1.45%     98.55% |           0      0.00%     98.55% |           1      1.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist_coalsr::total           69                      
+system.ruby.LD.latency_hist_coalsr::bucket_size           64                      
+system.ruby.LD.latency_hist_coalsr::max_bucket          639                      
+system.ruby.LD.latency_hist_coalsr::samples           72                      
+system.ruby.LD.latency_hist_coalsr::mean   101.402778                      
+system.ruby.LD.latency_hist_coalsr::gmean    68.071118                      
+system.ruby.LD.latency_hist_coalsr::stdev    67.272969                      
+system.ruby.LD.latency_hist_coalsr       |           7      9.72%      9.72% |          60     83.33%     93.06% |           1      1.39%     94.44% |           0      0.00%     94.44% |           3      4.17%     98.61% |           0      0.00%     98.61% |           0      0.00%     98.61% |           1      1.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_coalsr::total           72                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size         1024                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket        10239                      
 system.ruby.LD.hit_latency_hist_seqr::samples            1                      
-system.ruby.LD.hit_latency_hist_seqr::mean         5324                      
-system.ruby.LD.hit_latency_hist_seqr::gmean  5324.000000                      
+system.ruby.LD.hit_latency_hist_seqr::mean         5256                      
+system.ruby.LD.hit_latency_hist_seqr::gmean  5256.000000                      
 system.ruby.LD.hit_latency_hist_seqr::stdev          nan                      
 system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.hit_latency_hist_seqr::total            1                      
-system.ruby.LD.miss_latency_hist_coalsr::bucket_size          128                      
-system.ruby.LD.miss_latency_hist_coalsr::max_bucket         1279                      
-system.ruby.LD.miss_latency_hist_coalsr::samples           69                      
-system.ruby.LD.miss_latency_hist_coalsr::mean   111.289855                      
-system.ruby.LD.miss_latency_hist_coalsr::gmean    81.460116                      
-system.ruby.LD.miss_latency_hist_coalsr::stdev    88.701101                      
-system.ruby.LD.miss_latency_hist_coalsr  |          63     91.30%     91.30% |           2      2.90%     94.20% |           2      2.90%     97.10% |           1      1.45%     98.55% |           0      0.00%     98.55% |           1      1.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist_coalsr::total           69                      
+system.ruby.LD.miss_latency_hist_coalsr::bucket_size           64                      
+system.ruby.LD.miss_latency_hist_coalsr::max_bucket          639                      
+system.ruby.LD.miss_latency_hist_coalsr::samples           72                      
+system.ruby.LD.miss_latency_hist_coalsr::mean   101.402778                      
+system.ruby.LD.miss_latency_hist_coalsr::gmean    68.071118                      
+system.ruby.LD.miss_latency_hist_coalsr::stdev    67.272969                      
+system.ruby.LD.miss_latency_hist_coalsr  |           7      9.72%      9.72% |          60     83.33%     93.06% |           1      1.39%     94.44% |           0      0.00%     94.44% |           3      4.17%     98.61% |           0      0.00%     98.61% |           0      0.00%     98.61% |           1      1.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_coalsr::total           72                      
 system.ruby.ST.latency_hist_seqr::bucket_size         1024                      
 system.ruby.ST.latency_hist_seqr::max_bucket        10239                      
 system.ruby.ST.latency_hist_seqr::samples           46                      
-system.ruby.ST.latency_hist_seqr::mean    3269.239130                      
-system.ruby.ST.latency_hist_seqr::gmean   1783.447677                      
-system.ruby.ST.latency_hist_seqr::stdev   1934.416354                      
-system.ruby.ST.latency_hist_seqr         |          11     23.91%     23.91% |           3      6.52%     30.43% |           3      6.52%     36.96% |           7     15.22%     52.17% |          18     39.13%     91.30% |           4      8.70%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::mean    3234.260870                      
+system.ruby.ST.latency_hist_seqr::gmean   1760.149244                      
+system.ruby.ST.latency_hist_seqr::stdev   1907.255858                      
+system.ruby.ST.latency_hist_seqr         |          11     23.91%     23.91% |           3      6.52%     30.43% |           3      6.52%     36.96% |           7     15.22%     52.17% |          20     43.48%     95.65% |           2      4.35%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist_seqr::total            46                      
 system.ruby.ST.latency_hist_coalsr::bucket_size          128                      
 system.ruby.ST.latency_hist_coalsr::max_bucket         1279                      
-system.ruby.ST.latency_hist_coalsr::samples          803                      
-system.ruby.ST.latency_hist_coalsr::mean   231.610212                      
-system.ruby.ST.latency_hist_coalsr::gmean   117.827816                      
-system.ruby.ST.latency_hist_coalsr::stdev   248.057845                      
-system.ruby.ST.latency_hist_coalsr       |         517     64.38%     64.38% |          28      3.49%     67.87% |         108     13.45%     81.32% |          38      4.73%     86.05% |          33      4.11%     90.16% |          19      2.37%     92.53% |          33      4.11%     96.64% |          23      2.86%     99.50% |           4      0.50%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist_coalsr::total          803                      
+system.ruby.ST.latency_hist_coalsr::samples          786                      
+system.ruby.ST.latency_hist_coalsr::mean   225.797710                      
+system.ruby.ST.latency_hist_coalsr::gmean   112.544056                      
+system.ruby.ST.latency_hist_coalsr::stdev   244.652456                      
+system.ruby.ST.latency_hist_coalsr       |         506     64.38%     64.38% |          35      4.45%     68.83% |         108     13.74%     82.57% |          36      4.58%     87.15% |          24      3.05%     90.20% |          19      2.42%     92.62% |          32      4.07%     96.69% |          23      2.93%     99.62% |           3      0.38%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_coalsr::total          786                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size         1024                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket        10239                      
 system.ruby.ST.hit_latency_hist_seqr::samples           40                      
-system.ruby.ST.hit_latency_hist_seqr::mean  3606.650000                      
-system.ruby.ST.hit_latency_hist_seqr::gmean  2691.718970                      
-system.ruby.ST.hit_latency_hist_seqr::stdev  1792.166924                      
-system.ruby.ST.hit_latency_hist_seqr     |           7     17.50%     17.50% |           3      7.50%     25.00% |           1      2.50%     27.50% |           7     17.50%     45.00% |          18     45.00%     90.00% |           4     10.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist_seqr::mean  3566.725000                      
+system.ruby.ST.hit_latency_hist_seqr::gmean  2651.630943                      
+system.ruby.ST.hit_latency_hist_seqr::stdev  1765.919997                      
+system.ruby.ST.hit_latency_hist_seqr     |           7     17.50%     17.50% |           3      7.50%     25.00% |           1      2.50%     27.50% |           7     17.50%     45.00% |          20     50.00%     95.00% |           2      5.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.hit_latency_hist_seqr::total           40                      
 system.ruby.ST.miss_latency_hist_seqr::bucket_size          512                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket         5119                      
 system.ruby.ST.miss_latency_hist_seqr::samples            6                      
-system.ruby.ST.miss_latency_hist_seqr::mean  1019.833333                      
-system.ruby.ST.miss_latency_hist_seqr::gmean   114.673945                      
-system.ruby.ST.miss_latency_hist_seqr::stdev  1281.644790                      
-system.ruby.ST.miss_latency_hist_seqr    |           3     50.00%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           2     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean  1017.833333                      
+system.ruby.ST.miss_latency_hist_seqr::gmean   114.584426                      
+system.ruby.ST.miss_latency_hist_seqr::stdev  1278.753677                      
+system.ruby.ST.miss_latency_hist_seqr    |           3     50.00%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     16.67%     83.33% |           1     16.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist_seqr::total            6                      
 system.ruby.ST.miss_latency_hist_coalsr::bucket_size          128                      
 system.ruby.ST.miss_latency_hist_coalsr::max_bucket         1279                      
-system.ruby.ST.miss_latency_hist_coalsr::samples          803                      
-system.ruby.ST.miss_latency_hist_coalsr::mean   231.610212                      
-system.ruby.ST.miss_latency_hist_coalsr::gmean   117.827816                      
-system.ruby.ST.miss_latency_hist_coalsr::stdev   248.057845                      
-system.ruby.ST.miss_latency_hist_coalsr  |         517     64.38%     64.38% |          28      3.49%     67.87% |         108     13.45%     81.32% |          38      4.73%     86.05% |          33      4.11%     90.16% |          19      2.37%     92.53% |          33      4.11%     96.64% |          23      2.86%     99.50% |           4      0.50%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist_coalsr::total          803                      
+system.ruby.ST.miss_latency_hist_coalsr::samples          786                      
+system.ruby.ST.miss_latency_hist_coalsr::mean   225.797710                      
+system.ruby.ST.miss_latency_hist_coalsr::gmean   112.544056                      
+system.ruby.ST.miss_latency_hist_coalsr::stdev   244.652456                      
+system.ruby.ST.miss_latency_hist_coalsr  |         506     64.38%     64.38% |          35      4.45%     68.83% |         108     13.74%     82.57% |          36      4.58%     87.15% |          24      3.05%     90.20% |          19      2.42%     92.62% |          32      4.07%     96.69% |          23      2.93%     99.62% |           3      0.38%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_coalsr::total          786                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size         1024                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket        10239                      
 system.ruby.IFETCH.latency_hist_seqr::samples            1                      
-system.ruby.IFETCH.latency_hist_seqr::mean         5156                      
-system.ruby.IFETCH.latency_hist_seqr::gmean  5156.000000                      
+system.ruby.IFETCH.latency_hist_seqr::mean         5129                      
+system.ruby.IFETCH.latency_hist_seqr::gmean         5129                      
 system.ruby.IFETCH.latency_hist_seqr::stdev          nan                      
 system.ruby.IFETCH.latency_hist_seqr     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist_seqr::total            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size         1024                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket        10239                      
 system.ruby.IFETCH.hit_latency_hist_seqr::samples            1                      
-system.ruby.IFETCH.hit_latency_hist_seqr::mean         5156                      
-system.ruby.IFETCH.hit_latency_hist_seqr::gmean  5156.000000                      
+system.ruby.IFETCH.hit_latency_hist_seqr::mean         5129                      
+system.ruby.IFETCH.hit_latency_hist_seqr::gmean         5129                      
 system.ruby.IFETCH.hit_latency_hist_seqr::stdev          nan                      
 system.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.hit_latency_hist_seqr::total            1                      
 system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size          512                      
 system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket         5119                      
 system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples            6                      
-system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean  1019.833333                      
-system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean   114.673945                      
-system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev  1281.644790                      
-system.ruby.L1Cache.miss_mach_latency_hist_seqr |           3     50.00%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           2     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean  1017.833333                      
+system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean   114.584426                      
+system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev  1278.753677                      
+system.ruby.L1Cache.miss_mach_latency_hist_seqr |           3     50.00%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     16.67%     83.33% |           1     16.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache.miss_mach_latency_hist_seqr::total            6                      
 system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size         1024                      
 system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket        10239                      
 system.ruby.Directory.hit_mach_latency_hist_seqr::samples           42                      
-system.ruby.Directory.hit_mach_latency_hist_seqr::mean  3684.428571                      
-system.ruby.Directory.hit_mach_latency_hist_seqr::gmean  2778.454716                      
-system.ruby.Directory.hit_mach_latency_hist_seqr::stdev  1783.107224                      
-system.ruby.Directory.hit_mach_latency_hist_seqr |           7     16.67%     16.67% |           3      7.14%     23.81% |           1      2.38%     26.19% |           7     16.67%     42.86% |          18     42.86%     85.71% |           6     14.29%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.hit_mach_latency_hist_seqr::mean  3644.142857                      
+system.ruby.Directory.hit_mach_latency_hist_seqr::gmean  2737.850881                      
+system.ruby.Directory.hit_mach_latency_hist_seqr::stdev  1757.652877                      
+system.ruby.Directory.hit_mach_latency_hist_seqr |           7     16.67%     16.67% |           3      7.14%     23.81% |           1      2.38%     26.19% |           7     16.67%     42.86% |          20     47.62%     90.48% |           4      9.52%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.hit_mach_latency_hist_seqr::total           42                      
 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size          128                      
 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket         1279                      
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples          644                      
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean   154.992236                      
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean   124.686138                      
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev   142.628867                      
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr |         516     80.12%     80.12% |          30      4.66%     84.78% |          42      6.52%     91.30% |          26      4.04%     95.34% |          17      2.64%     97.98% |           7      1.09%     99.07% |           4      0.62%     99.69% |           1      0.16%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total          644                      
+system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples          624                      
+system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean   148.483974                      
+system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean   122.381501                      
+system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev   128.958613                      
+system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr |         502     80.45%     80.45% |          36      5.77%     86.22% |          40      6.41%     92.63% |          24      3.85%     96.47% |          12      1.92%     98.40% |           6      0.96%     99.36% |           3      0.48%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total          624                      
 system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size            1                      
 system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket            9                      
-system.ruby.TCP.miss_mach_latency_hist_coalsr::samples           64                      
-system.ruby.TCP.miss_mach_latency_hist_coalsr::mean     1.109375                      
-system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean     1.055645                      
-system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev     0.537991                      
-system.ruby.TCP.miss_mach_latency_hist_coalsr |           0      0.00%      0.00% |          61     95.31%     95.31% |           1      1.56%     96.88% |           0      0.00%     96.88% |           2      3.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.TCP.miss_mach_latency_hist_coalsr::total           64                      
+system.ruby.TCP.miss_mach_latency_hist_coalsr::samples           71                      
+system.ruby.TCP.miss_mach_latency_hist_coalsr::mean     1.126761                      
+system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean     1.060325                      
+system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev     0.607796                      
+system.ruby.TCP.miss_mach_latency_hist_coalsr |           0      0.00%      0.00% |          68     95.77%     95.77% |           0      0.00%     95.77% |           0      0.00%     95.77% |           3      4.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.TCP.miss_mach_latency_hist_coalsr::total           71                      
 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size          128                      
 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket         1279                      
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples          164                      
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean   571.804878                      
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean   508.667381                      
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev   267.247131                      
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |          68     41.46%     41.46% |          13      7.93%     49.39% |          16      9.76%     59.15% |          13      7.93%     67.07% |          29     17.68%     84.76% |          22     13.41%     98.17% |           3      1.83%    100.00% |           0      0.00%    100.00%
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total          164                      
+system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples          163                      
+system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean   564.687117                      
+system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean   498.870659                      
+system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev   272.472640                      
+system.ruby.TCCdir.miss_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |          71     43.56%     43.56% |          13      7.98%     51.53% |          12      7.36%     58.90% |          13      7.98%     66.87% |          29     17.79%     84.66% |          22     13.50%     98.16% |           3      1.84%    100.00% |           0      0.00%    100.00%
+system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total          163                      
 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size         1024                      
 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket        10239                      
 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples            1                      
-system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean         5324                      
-system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean  5324.000000                      
+system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean         5256                      
+system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean  5256.000000                      
 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev          nan                      
 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total            1                      
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size          128                      
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket         1279                      
+system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size           64                      
+system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket          639                      
 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples           62                      
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean   107.322581                      
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean   101.146340                      
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev    70.212972                      
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr |          59     95.16%     95.16% |           2      3.23%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           1      1.61%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean   104.322581                      
+system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean   100.218451                      
+system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev    51.260433                      
+system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |          60     96.77%     96.77% |           1      1.61%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           0      0.00%     98.39% |           1      1.61%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total           62                      
 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size            1                      
 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket            9                      
-system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples            4                      
-system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean            1                      
-system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean            1                      
-system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           4    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total            4                      
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size           64                      
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket          639                      
+system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples            7                      
+system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean     1.428571                      
+system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean     1.219014                      
+system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev     1.133893                      
+system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           6     85.71%     85.71% |           0      0.00%     85.71% |           0      0.00%     85.71% |           1     14.29%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total            7                      
+system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size           32                      
+system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket          319                      
 system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples            3                      
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean   340.333333                      
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean   328.169813                      
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev   116.791838                      
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     66.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean   274.333333                      
+system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean   273.844265                      
+system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev    20.256686                      
+system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     66.67%     66.67% |           1     33.33%    100.00%
 system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total            3                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size          512                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket         5119                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples            6                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean  1019.833333                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean   114.673945                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev  1281.644790                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr |           3     50.00%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           2     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean  1017.833333                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean   114.584426                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev  1278.753677                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr |           3     50.00%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     16.67%     83.33% |           1     16.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total            6                      
 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size         1024                      
 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket        10239                      
 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples           40                      
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean  3606.650000                      
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean  2691.718970                      
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev  1792.166924                      
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr |           7     17.50%     17.50% |           3      7.50%     25.00% |           1      2.50%     27.50% |           7     17.50%     45.00% |          18     45.00%     90.00% |           4     10.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean  3566.725000                      
+system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean  2651.630943                      
+system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev  1765.919997                      
+system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr |           7     17.50%     17.50% |           3      7.50%     25.00% |           1      2.50%     27.50% |           7     17.50%     45.00% |          20     50.00%     95.00% |           2      5.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total           40                      
 system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size          128                      
 system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket         1279                      
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples          582                      
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean   160.070447                      
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean   127.496503                      
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev   147.403962                      
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr |         457     78.52%     78.52% |          28      4.81%     83.33% |          42      7.22%     90.55% |          26      4.47%     95.02% |          17      2.92%     97.94% |           6      1.03%     98.97% |           4      0.69%     99.66% |           1      0.17%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total          582                      
+system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples          562                      
+system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean   153.355872                      
+system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean   125.108856                      
+system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev   133.952348                      
+system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr |         442     78.65%     78.65% |          35      6.23%     84.88% |          40      7.12%     91.99% |          23      4.09%     96.09% |          12      2.14%     98.22% |           6      1.07%     99.29% |           3      0.53%     99.82% |           1      0.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total          562                      
 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size            1                      
 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket            9                      
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples           60                      
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean     1.116667                      
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean     1.059463                      
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::stdev     0.555151                      
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |          57     95.00%     95.00% |           1      1.67%     96.67% |           0      0.00%     96.67% |           2      3.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total           60                      
+system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples           64                      
+system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean     1.093750                      
+system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean     1.044274                      
+system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::stdev     0.526104                      
+system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |          62     96.88%     96.88% |           0      0.00%     96.88% |           0      0.00%     96.88% |           2      3.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total           64                      
 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size          128                      
 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket         1279                      
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples          161                      
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean   576.118012                      
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean   512.838367                      
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev   267.518863                      
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |          66     40.99%     40.99% |          12      7.45%     48.45% |          16      9.94%     58.39% |          13      8.07%     66.46% |          29     18.01%     84.47% |          22     13.66%     98.14% |           3      1.86%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total          161                      
+system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples          160                      
+system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean   570.131250                      
+system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean   504.512629                      
+system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev   272.059675                      
+system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr |           0      0.00%      0.00% |           0      0.00%      0.00% |          68     42.50%     42.50% |          13      8.12%     50.62% |          12      7.50%     58.12% |          13      8.12%     66.25% |          29     18.12%     84.38% |          22     13.75%     98.12% |           3      1.88%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total          160                      
 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size         1024                      
 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket        10239                      
 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples            1                      
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean         5156                      
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean  5156.000000                      
+system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean         5129                      
+system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean         5129                      
 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev          nan                      
 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total            1                      
-system.ruby.SQC_Controller.Fetch         |          12     44.44%     44.44% |          15     55.56%    100.00%
-system.ruby.SQC_Controller.Fetch::total            27                      
-system.ruby.SQC_Controller.TCC_AckS      |          12     44.44%     44.44% |          15     55.56%    100.00%
-system.ruby.SQC_Controller.TCC_AckS::total           27                      
-system.ruby.SQC_Controller.PrbInvData    |          10     41.67%     41.67% |          14     58.33%    100.00%
-system.ruby.SQC_Controller.PrbInvData::total           24                      
-system.ruby.SQC_Controller.I.Fetch       |          12     44.44%     44.44% |          15     55.56%    100.00%
-system.ruby.SQC_Controller.I.Fetch::total           27                      
-system.ruby.SQC_Controller.S.PrbInvData  |          10     41.67%     41.67% |          14     58.33%    100.00%
-system.ruby.SQC_Controller.S.PrbInvData::total           24                      
-system.ruby.SQC_Controller.I_S.TCC_AckS  |          12     44.44%     44.44% |          15     55.56%    100.00%
-system.ruby.SQC_Controller.I_S.TCC_AckS::total           27                      
-system.ruby.TCCdir_Controller.RdBlk               174      0.00%      0.00%
-system.ruby.TCCdir_Controller.RdBlkM             2638      0.00%      0.00%
-system.ruby.TCCdir_Controller.RdBlkS              195      0.00%      0.00%
-system.ruby.TCCdir_Controller.CPUPrbResp          811      0.00%      0.00%
-system.ruby.TCCdir_Controller.ProbeAcksComplete          751      0.00%      0.00%
-system.ruby.TCCdir_Controller.CoreUnblock          829      0.00%      0.00%
-system.ruby.TCCdir_Controller.LastCoreUnblock            2      0.00%      0.00%
-system.ruby.TCCdir_Controller.NB_AckS               2      0.00%      0.00%
-system.ruby.TCCdir_Controller.NB_AckE               2      0.00%      0.00%
-system.ruby.TCCdir_Controller.NB_AckM             223      0.00%      0.00%
-system.ruby.TCCdir_Controller.PrbInvData          112      0.00%      0.00%
-system.ruby.TCCdir_Controller.PrbShrData            4      0.00%      0.00%
+system.ruby.SQC_Controller.Fetch         |          12     50.00%     50.00% |          12     50.00%    100.00%
+system.ruby.SQC_Controller.Fetch::total            24                      
+system.ruby.SQC_Controller.TCC_AckS      |          12     50.00%     50.00% |          12     50.00%    100.00%
+system.ruby.SQC_Controller.TCC_AckS::total           24                      
+system.ruby.SQC_Controller.PrbInvData    |          11     50.00%     50.00% |          11     50.00%    100.00%
+system.ruby.SQC_Controller.PrbInvData::total           22                      
+system.ruby.SQC_Controller.I.Fetch       |          12     50.00%     50.00% |          12     50.00%    100.00%
+system.ruby.SQC_Controller.I.Fetch::total           24                      
+system.ruby.SQC_Controller.S.PrbInvData  |          11     50.00%     50.00% |          11     50.00%    100.00%
+system.ruby.SQC_Controller.S.PrbInvData::total           22                      
+system.ruby.SQC_Controller.I_S.TCC_AckS  |          12     50.00%     50.00% |          12     50.00%    100.00%
+system.ruby.SQC_Controller.I_S.TCC_AckS::total           24                      
+system.ruby.TCCdir_Controller.RdBlk               115      0.00%      0.00%
+system.ruby.TCCdir_Controller.RdBlkM             2448      0.00%      0.00%
+system.ruby.TCCdir_Controller.RdBlkS              103      0.00%      0.00%
+system.ruby.TCCdir_Controller.CPUPrbResp          785      0.00%      0.00%
+system.ruby.TCCdir_Controller.ProbeAcksComplete          730      0.00%      0.00%
+system.ruby.TCCdir_Controller.CoreUnblock          807      0.00%      0.00%
+system.ruby.TCCdir_Controller.LastCoreUnblock            3      0.00%      0.00%
+system.ruby.TCCdir_Controller.NB_AckS               1      0.00%      0.00%
+system.ruby.TCCdir_Controller.NB_AckE               3      0.00%      0.00%
+system.ruby.TCCdir_Controller.NB_AckM             212      0.00%      0.00%
+system.ruby.TCCdir_Controller.PrbInvData          119      0.00%      0.00%
+system.ruby.TCCdir_Controller.PrbShrData            6      0.00%      0.00%
 system.ruby.TCCdir_Controller.I.RdBlk               3      0.00%      0.00%
-system.ruby.TCCdir_Controller.I.RdBlkM            156      0.00%      0.00%
+system.ruby.TCCdir_Controller.I.RdBlkM            154      0.00%      0.00%
 system.ruby.TCCdir_Controller.I.RdBlkS              1      0.00%      0.00%
 system.ruby.TCCdir_Controller.I.PrbInvData            9      0.00%      0.00%
-system.ruby.TCCdir_Controller.S.RdBlkM              2      0.00%      0.00%
-system.ruby.TCCdir_Controller.S.RdBlkS              1      0.00%      0.00%
+system.ruby.TCCdir_Controller.S.RdBlkM              1      0.00%      0.00%
 system.ruby.TCCdir_Controller.E.RdBlkM              1      0.00%      0.00%
-system.ruby.TCCdir_Controller.O.RdBlk               1      0.00%      0.00%
-system.ruby.TCCdir_Controller.O.RdBlkM             70      0.00%      0.00%
-system.ruby.TCCdir_Controller.O.PrbInvData            6      0.00%      0.00%
+system.ruby.TCCdir_Controller.E.RdBlkS              1      0.00%      0.00%
+system.ruby.TCCdir_Controller.O.RdBlk               2      0.00%      0.00%
+system.ruby.TCCdir_Controller.O.RdBlkM             61      0.00%      0.00%
+system.ruby.TCCdir_Controller.O.RdBlkS              1      0.00%      0.00%
+system.ruby.TCCdir_Controller.O.PrbInvData            4      0.00%      0.00%
+system.ruby.TCCdir_Controller.O.PrbShrData            1      0.00%      0.00%
 system.ruby.TCCdir_Controller.M.RdBlk              61      0.00%      0.00%
-system.ruby.TCCdir_Controller.M.RdBlkM            521      0.00%      0.00%
-system.ruby.TCCdir_Controller.M.RdBlkS             25      0.00%      0.00%
-system.ruby.TCCdir_Controller.M.PrbInvData           59      0.00%      0.00%
+system.ruby.TCCdir_Controller.M.RdBlkM            512      0.00%      0.00%
+system.ruby.TCCdir_Controller.M.RdBlkS             20      0.00%      0.00%
+system.ruby.TCCdir_Controller.M.PrbInvData           62      0.00%      0.00%
 system.ruby.TCCdir_Controller.M.PrbShrData            4      0.00%      0.00%
-system.ruby.TCCdir_Controller.CP_I.RdBlk            9      0.00%      0.00%
-system.ruby.TCCdir_Controller.CP_I.RdBlkM           15      0.00%      0.00%
-system.ruby.TCCdir_Controller.CP_I.RdBlkS            7      0.00%      0.00%
-system.ruby.TCCdir_Controller.CP_I.CPUPrbResp           71      0.00%      0.00%
-system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete           65      0.00%      0.00%
+system.ruby.TCCdir_Controller.CP_I.RdBlkM           17      0.00%      0.00%
+system.ruby.TCCdir_Controller.CP_I.CPUPrbResp           70      0.00%      0.00%
+system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete           66      0.00%      0.00%
 system.ruby.TCCdir_Controller.CP_O.RdBlkM            4      0.00%      0.00%
-system.ruby.TCCdir_Controller.CP_O.CPUPrbResp            4      0.00%      0.00%
-system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete            4      0.00%      0.00%
+system.ruby.TCCdir_Controller.CP_O.CPUPrbResp            6      0.00%      0.00%
+system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete            5      0.00%      0.00%
+system.ruby.TCCdir_Controller.CP_OM.RdBlkM           14      0.00%      0.00%
+system.ruby.TCCdir_Controller.CP_OM.CPUPrbResp            1      0.00%      0.00%
+system.ruby.TCCdir_Controller.CP_OM.ProbeAcksComplete            1      0.00%      0.00%
 system.ruby.TCCdir_Controller.CP_IOM.RdBlkM            5      0.00%      0.00%
 system.ruby.TCCdir_Controller.CP_IOM.CPUPrbResp            2      0.00%      0.00%
 system.ruby.TCCdir_Controller.CP_IOM.ProbeAcksComplete            2      0.00%      0.00%
-system.ruby.TCCdir_Controller.I_M.RdBlkM          897      0.00%      0.00%
-system.ruby.TCCdir_Controller.I_M.RdBlkS           30      0.00%      0.00%
-system.ruby.TCCdir_Controller.I_M.NB_AckM          156      0.00%      0.00%
+system.ruby.TCCdir_Controller.I_M.RdBlk            26      0.00%      0.00%
+system.ruby.TCCdir_Controller.I_M.RdBlkM          960      0.00%      0.00%
+system.ruby.TCCdir_Controller.I_M.RdBlkS            3      0.00%      0.00%
+system.ruby.TCCdir_Controller.I_M.NB_AckM          154      0.00%      0.00%
 system.ruby.TCCdir_Controller.I_M.PrbInvData            1      0.00%      0.00%
-system.ruby.TCCdir_Controller.I_ES.RdBlkM           24      0.00%      0.00%
-system.ruby.TCCdir_Controller.I_ES.RdBlkS           34      0.00%      0.00%
-system.ruby.TCCdir_Controller.I_ES.NB_AckS            1      0.00%      0.00%
-system.ruby.TCCdir_Controller.I_ES.NB_AckE            2      0.00%      0.00%
-system.ruby.TCCdir_Controller.I_S.RdBlkM           11      0.00%      0.00%
+system.ruby.TCCdir_Controller.I_ES.NB_AckE            3      0.00%      0.00%
 system.ruby.TCCdir_Controller.I_S.NB_AckS            1      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBS_S.RdBlkM            5      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp            1      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete            1      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBO_O.CPUPrbResp            1      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBO_O.ProbeAcksComplete            1      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBM_M.RdBlk           11      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBM_M.RdBlkM          104      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBM_M.RdBlkS           12      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp          520      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete          520      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBM_M.PrbInvData           14      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBM_O.RdBlkM           13      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBM_O.CPUPrbResp           86      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBM_O.ProbeAcksComplete           86      0.00%      0.00%
-system.ruby.TCCdir_Controller.BB_M.RdBlk           20      0.00%      0.00%
-system.ruby.TCCdir_Controller.BB_M.RdBlkM          181      0.00%      0.00%
-system.ruby.TCCdir_Controller.BB_M.RdBlkS           15      0.00%      0.00%
-system.ruby.TCCdir_Controller.BB_M.CoreUnblock          518      0.00%      0.00%
-system.ruby.TCCdir_Controller.BB_M.PrbInvData           19      0.00%      0.00%
-system.ruby.TCCdir_Controller.BB_O.RdBlkM           35      0.00%      0.00%
-system.ruby.TCCdir_Controller.BB_O.CoreUnblock           84      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBO_O.RdBlkM            5      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBO_O.RdBlkS            1      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBO_O.CPUPrbResp            3      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBO_O.ProbeAcksComplete            3      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBM_M.RdBlk            6      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBM_M.RdBlkM           94      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBM_M.RdBlkS            5      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp          510      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete          510      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBM_M.PrbInvData           15      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBM_O.RdBlkM            6      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBM_O.RdBlkS            5      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBM_O.CPUPrbResp           81      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBM_O.ProbeAcksComplete           81      0.00%      0.00%
+system.ruby.TCCdir_Controller.BB_M.RdBlk           13      0.00%      0.00%
+system.ruby.TCCdir_Controller.BB_M.RdBlkM          176      0.00%      0.00%
+system.ruby.TCCdir_Controller.BB_M.RdBlkS            5      0.00%      0.00%
+system.ruby.TCCdir_Controller.BB_M.CoreUnblock          509      0.00%      0.00%
+system.ruby.TCCdir_Controller.BB_M.PrbInvData           24      0.00%      0.00%
+system.ruby.TCCdir_Controller.BB_O.RdBlkM           26      0.00%      0.00%
+system.ruby.TCCdir_Controller.BB_O.RdBlkS            5      0.00%      0.00%
+system.ruby.TCCdir_Controller.BB_O.CoreUnblock           81      0.00%      0.00%
 system.ruby.TCCdir_Controller.BB_O.PrbInvData            2      0.00%      0.00%
-system.ruby.TCCdir_Controller.BB_OO.LastCoreUnblock            1      0.00%      0.00%
-system.ruby.TCCdir_Controller.BB_S.RdBlkM            9      0.00%      0.00%
-system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock            1      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBS_M.RdBlk            9      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBS_M.RdBlkM           18      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBS_M.CPUPrbResp            4      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBS_M.ProbeAcksComplete            3      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBO_M.RdBlkM           20      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBO_M.CPUPrbResp          122      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBO_M.ProbeAcksComplete           69      0.00%      0.00%
-system.ruby.TCCdir_Controller.S_M.RdBlk            28      0.00%      0.00%
-system.ruby.TCCdir_Controller.S_M.RdBlkM           69      0.00%      0.00%
-system.ruby.TCCdir_Controller.S_M.NB_AckM            3      0.00%      0.00%
-system.ruby.TCCdir_Controller.O_M.RdBlk            20      0.00%      0.00%
-system.ruby.TCCdir_Controller.O_M.RdBlkM          249      0.00%      0.00%
-system.ruby.TCCdir_Controller.O_M.RdBlkS           51      0.00%      0.00%
-system.ruby.TCCdir_Controller.O_M.NB_AckM           64      0.00%      0.00%
+system.ruby.TCCdir_Controller.BB_OO.RdBlkM           14      0.00%      0.00%
+system.ruby.TCCdir_Controller.BB_OO.CoreUnblock            1      0.00%      0.00%
+system.ruby.TCCdir_Controller.BB_OO.LastCoreUnblock            3      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBS_M.CPUPrbResp            2      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBS_M.ProbeAcksComplete            2      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBO_M.RdBlkM            4      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBO_M.CPUPrbResp          110      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBO_M.ProbeAcksComplete           60      0.00%      0.00%
+system.ruby.TCCdir_Controller.S_M.NB_AckM            2      0.00%      0.00%
+system.ruby.TCCdir_Controller.O_M.RdBlkM          198      0.00%      0.00%
+system.ruby.TCCdir_Controller.O_M.RdBlkS           48      0.00%      0.00%
+system.ruby.TCCdir_Controller.O_M.NB_AckM           56      0.00%      0.00%
 system.ruby.TCCdir_Controller.O_M.PrbInvData            2      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBB_S.RdBlk            3      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBB_S.RdBlkM           23      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBB_S.RdBlkS            5      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBB_S.CoreUnblock            2      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBB_M.RdBlk            9      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBB_M.RdBlkM          206      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBB_M.RdBlkS           14      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBB_M.CoreUnblock          223      0.00%      0.00%
-system.ruby.TCCdir_Controller.BBB_E.CoreUnblock            2      0.00%      0.00%
-system.ruby.TCP_Controller.Load          |           5      7.04%      7.04% |           6      8.45%     15.49% |          10     14.08%     29.58% |          13     18.31%     47.89% |           6      8.45%     56.34% |           6      8.45%     64.79% |          13     18.31%     83.10% |          12     16.90%    100.00%
-system.ruby.TCP_Controller.Load::total             71                      
-system.ruby.TCP_Controller.Store         |         109     13.39%     13.39% |         104     12.78%     26.17% |          98     12.04%     38.21% |          93     11.43%     49.63% |         109     13.39%     63.02% |         102     12.53%     75.55% |         113     13.88%     89.43% |          86     10.57%    100.00%
-system.ruby.TCP_Controller.Store::total           814                      
-system.ruby.TCP_Controller.TCC_AckS      |           5      7.94%      7.94% |           5      7.94%     15.87% |           9     14.29%     30.16% |          13     20.63%     50.79% |           4      6.35%     57.14% |           6      9.52%     66.67% |          11     17.46%     84.13% |          10     15.87%    100.00%
-system.ruby.TCP_Controller.TCC_AckS::total           63                      
-system.ruby.TCP_Controller.TCC_AckE      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00%
-system.ruby.TCP_Controller.TCC_AckE::total            2                      
-system.ruby.TCP_Controller.TCC_AckM      |         100     13.46%     13.46% |          94     12.65%     26.11% |          90     12.11%     38.22% |          81     10.90%     49.13% |         102     13.73%     62.85% |          92     12.38%     75.24% |         105     14.13%     89.37% |          79     10.63%    100.00%
-system.ruby.TCP_Controller.TCC_AckM::total          743                      
-system.ruby.TCP_Controller.PrbInvData    |          88     12.61%     12.61% |          87     12.46%     25.07% |          88     12.61%     37.68% |          79     11.32%     49.00% |          90     12.89%     61.89% |          86     12.32%     74.21% |         101     14.47%     88.68% |          79     11.32%    100.00%
-system.ruby.TCP_Controller.PrbInvData::total          698                      
-system.ruby.TCP_Controller.PrbShrData    |          14     15.22%     15.22% |           9      9.78%     25.00% |          17     18.48%     43.48% |           7      7.61%     51.09% |          14     15.22%     66.30% |          10     10.87%     77.17% |          12     13.04%     90.22% |           9      9.78%    100.00%
+system.ruby.TCCdir_Controller.O_M.PrbShrData            1      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBB_S.CoreUnblock            1      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBB_M.RdBlk            4      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBB_M.RdBlkM          196      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBB_M.RdBlkS            8      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBB_M.CoreUnblock          212      0.00%      0.00%
+system.ruby.TCCdir_Controller.BBB_E.CoreUnblock            3      0.00%      0.00%
+system.ruby.TCP_Controller.Load          |          10     13.70%     13.70% |          10     13.70%     27.40% |          11     15.07%     42.47% |          12     16.44%     58.90% |           6      8.22%     67.12% |           3      4.11%     71.23% |          10     13.70%     84.93% |          11     15.07%    100.00%
+system.ruby.TCP_Controller.Load::total             73                      
+system.ruby.TCP_Controller.Store         |         106     13.27%     13.27% |         102     12.77%     26.03% |          97     12.14%     38.17% |          86     10.76%     48.94% |         107     13.39%     62.33% |          98     12.27%     74.59% |         111     13.89%     88.49% |          92     11.51%    100.00%
+system.ruby.TCP_Controller.Store::total           799                      
+system.ruby.TCP_Controller.TCC_AckS      |           9     14.52%     14.52% |           8     12.90%     27.42% |           8     12.90%     40.32% |          12     19.35%     59.68% |           5      8.06%     67.74% |           3      4.84%     72.58% |           8     12.90%     85.48% |           9     14.52%    100.00%
+system.ruby.TCP_Controller.TCC_AckS::total           62                      
+system.ruby.TCP_Controller.TCC_AckE      |           1     33.33%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
+system.ruby.TCP_Controller.TCC_AckE::total            3                      
+system.ruby.TCP_Controller.TCC_AckM      |          93     12.88%     12.88% |          89     12.33%     25.21% |          87     12.05%     37.26% |          76     10.53%     47.78% |          98     13.57%     61.36% |          89     12.33%     73.68% |         106     14.68%     88.37% |          84     11.63%    100.00%
+system.ruby.TCP_Controller.TCC_AckM::total          722                      
+system.ruby.TCP_Controller.PrbInvData    |          84     12.44%     12.44% |          87     12.89%     25.33% |          83     12.30%     37.63% |          78     11.56%     49.19% |          89     13.19%     62.37% |          79     11.70%     74.07% |          97     14.37%     88.44% |          78     11.56%    100.00%
+system.ruby.TCP_Controller.PrbInvData::total          675                      
+system.ruby.TCP_Controller.PrbShrData    |          16     17.39%     17.39% |          10     10.87%     28.26% |           9      9.78%     38.04% |           8      8.70%     46.74% |          15     16.30%     63.04% |           9      9.78%     72.83% |          14     15.22%     88.04% |          11     11.96%    100.00%
 system.ruby.TCP_Controller.PrbShrData::total           92                      
-system.ruby.TCP_Controller.I.Load        |           5      7.46%      7.46% |           5      7.46%     14.93% |           9     13.43%     28.36% |          13     19.40%     47.76% |           6      8.96%     56.72% |           6      8.96%     65.67% |          12     17.91%     83.58% |          11     16.42%    100.00%
-system.ruby.TCP_Controller.I.Load::total           67                      
-system.ruby.TCP_Controller.I.Store       |          98     13.26%     13.26% |          95     12.86%     26.12% |          89     12.04%     38.16% |          82     11.10%     49.26% |          99     13.40%     62.65% |          93     12.58%     75.24% |         105     14.21%     89.45% |          78     10.55%    100.00%
-system.ruby.TCP_Controller.I.Store::total          739                      
+system.ruby.TCP_Controller.I.Load        |          10     15.15%     15.15% |           9     13.64%     28.79% |           9     13.64%     42.42% |          12     18.18%     60.61% |           5      7.58%     68.18% |           3      4.55%     72.73% |           9     13.64%     86.36% |           9     13.64%    100.00%
+system.ruby.TCP_Controller.I.Load::total           66                      
+system.ruby.TCP_Controller.I.Store       |          97     13.42%     13.42% |          91     12.59%     26.00% |          87     12.03%     38.04% |          79     10.93%     48.96% |          92     12.72%     61.69% |          89     12.31%     74.00% |         104     14.38%     88.38% |          84     11.62%    100.00%
+system.ruby.TCP_Controller.I.Store::total          723                      
 system.ruby.TCP_Controller.I.PrbInvData  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.TCP_Controller.I.PrbInvData::total            2                      
-system.ruby.TCP_Controller.S.Store       |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     20.00%     20.00% |           1     20.00%     40.00% |           0      0.00%     40.00% |           2     40.00%     80.00% |           1     20.00%    100.00%
-system.ruby.TCP_Controller.S.Store::total            5                      
-system.ruby.TCP_Controller.S.PrbInvData  |           4      8.33%      8.33% |           4      8.33%     16.67% |           8     16.67%     33.33% |           9     18.75%     52.08% |           3      6.25%     58.33% |           4      8.33%     66.67% |           8     16.67%     83.33% |           8     16.67%    100.00%
-system.ruby.TCP_Controller.S.PrbInvData::total           48                      
-system.ruby.TCP_Controller.S.PrbShrData  |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.TCP_Controller.S.Store       |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           2     66.67%    100.00% |           0      0.00%    100.00%
+system.ruby.TCP_Controller.S.Store::total            3                      
+system.ruby.TCP_Controller.S.PrbInvData  |           6     14.29%     14.29% |           7     16.67%     30.95% |           7     16.67%     47.62% |           7     16.67%     64.29% |           2      4.76%     69.05% |           1      2.38%     71.43% |           5     11.90%     83.33% |           7     16.67%    100.00%
+system.ruby.TCP_Controller.S.PrbInvData::total           42                      
+system.ruby.TCP_Controller.S.PrbShrData  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.TCP_Controller.S.PrbShrData::total            1                      
 system.ruby.TCP_Controller.E.PrbInvData  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.TCP_Controller.E.PrbInvData::total            1                      
-system.ruby.TCP_Controller.O.Store       |           2     20.00%     20.00% |           0      0.00%     20.00% |           2     20.00%     40.00% |           0      0.00%     40.00% |           3     30.00%     70.00% |           1     10.00%     80.00% |           1     10.00%     90.00% |           1     10.00%    100.00%
-system.ruby.TCP_Controller.O.Store::total           10                      
-system.ruby.TCP_Controller.O.PrbInvData  |           9     13.64%     13.64% |           7     10.61%     24.24% |          12     18.18%     42.42% |           7     10.61%     53.03% |          10     15.15%     68.18% |           5      7.58%     75.76% |          10     15.15%     90.91% |           6      9.09%    100.00%
-system.ruby.TCP_Controller.O.PrbInvData::total           66                      
-system.ruby.TCP_Controller.O.PrbShrData  |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.TCP_Controller.O.PrbShrData::total            1                      
-system.ruby.TCP_Controller.M.Load        |           0      0.00%      0.00% |           1     25.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     25.00%     75.00% |           1     25.00%    100.00%
-system.ruby.TCP_Controller.M.Load::total            4                      
-system.ruby.TCP_Controller.M.Store       |           9     15.00%     15.00% |           9     15.00%     30.00% |           7     11.67%     41.67% |          10     16.67%     58.33% |           6     10.00%     68.33% |           8     13.33%     81.67% |           5      8.33%     90.00% |           6     10.00%    100.00%
-system.ruby.TCP_Controller.M.Store::total           60                      
-system.ruby.TCP_Controller.M.PrbInvData  |          75     12.93%     12.93% |          76     13.10%     26.03% |          67     11.55%     37.59% |          62     10.69%     48.28% |          76     13.10%     61.38% |          77     13.28%     74.66% |          82     14.14%     88.79% |          65     11.21%    100.00%
-system.ruby.TCP_Controller.M.PrbInvData::total          580                      
-system.ruby.TCP_Controller.M.PrbShrData  |          14     15.56%     15.56% |           8      8.89%     24.44% |          16     17.78%     42.22% |           7      7.78%     50.00% |          14     15.56%     65.56% |          10     11.11%     76.67% |          12     13.33%     90.00% |           9     10.00%    100.00%
-system.ruby.TCP_Controller.M.PrbShrData::total           90                      
-system.ruby.TCP_Controller.I_M.TCC_AckM  |          98     13.42%     13.42% |          94     12.88%     26.30% |          89     12.19%     38.49% |          80     10.96%     49.45% |          98     13.42%     62.88% |          91     12.47%     75.34% |         103     14.11%     89.45% |          77     10.55%    100.00%
-system.ruby.TCP_Controller.I_M.TCC_AckM::total          730                      
-system.ruby.TCP_Controller.I_ES.TCC_AckS |           5      7.94%      7.94% |           5      7.94%     15.87% |           9     14.29%     30.16% |          13     20.63%     50.79% |           4      6.35%     57.14% |           6      9.52%     66.67% |          11     17.46%     84.13% |          10     15.87%    100.00%
-system.ruby.TCP_Controller.I_ES.TCC_AckS::total           63                      
-system.ruby.TCP_Controller.I_ES.TCC_AckE |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00%
-system.ruby.TCP_Controller.I_ES.TCC_AckE::total            2                      
-system.ruby.TCP_Controller.S_M.TCC_AckM  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     25.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           1     25.00%     75.00% |           1     25.00%    100.00%
-system.ruby.TCP_Controller.S_M.TCC_AckM::total            4                      
-system.ruby.TCP_Controller.O_M.TCC_AckM  |           2     22.22%     22.22% |           0      0.00%     22.22% |           1     11.11%     33.33% |           0      0.00%     33.33% |           3     33.33%     66.67% |           1     11.11%     77.78% |           1     11.11%     88.89% |           1     11.11%    100.00%
-system.ruby.TCP_Controller.O_M.TCC_AckM::total            9                      
-system.ruby.TCP_Controller.O_M.PrbInvData |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.TCP_Controller.O_M.PrbInvData::total            1                      
+system.ruby.TCP_Controller.E.PrbShrData  |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.TCP_Controller.E.PrbShrData::total            1                      
+system.ruby.TCP_Controller.O.Store       |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     11.11%     11.11% |           0      0.00%     11.11% |           5     55.56%     66.67% |           1     11.11%     77.78% |           1     11.11%     88.89% |           1     11.11%    100.00%
+system.ruby.TCP_Controller.O.Store::total            9                      
+system.ruby.TCP_Controller.O.PrbInvData  |           9     16.07%     16.07% |           7     12.50%     28.57% |           8     14.29%     42.86% |           8     14.29%     57.14% |           7     12.50%     69.64% |           3      5.36%     75.00% |           9     16.07%     91.07% |           5      8.93%    100.00%
+system.ruby.TCP_Controller.O.PrbInvData::total           56                      
+system.ruby.TCP_Controller.O.PrbShrData  |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
+system.ruby.TCP_Controller.O.PrbShrData::total            3                      
+system.ruby.TCP_Controller.M.Load        |           0      0.00%      0.00% |           1     14.29%     14.29% |           2     28.57%     42.86% |           0      0.00%     42.86% |           1     14.29%     57.14% |           0      0.00%     57.14% |           1     14.29%     71.43% |           2     28.57%    100.00%
+system.ruby.TCP_Controller.M.Load::total            7                      
+system.ruby.TCP_Controller.M.Store       |           9     14.06%     14.06% |          11     17.19%     31.25% |           9     14.06%     45.31% |           7     10.94%     56.25% |           9     14.06%     70.31% |           8     12.50%     82.81% |           4      6.25%     89.06% |           7     10.94%    100.00%
+system.ruby.TCP_Controller.M.Store::total           64                      
+system.ruby.TCP_Controller.M.PrbInvData  |          69     12.02%     12.02% |          73     12.72%     24.74% |          68     11.85%     36.59% |          62     10.80%     47.39% |          79     13.76%     61.15% |          75     13.07%     74.22% |          82     14.29%     88.50% |          66     11.50%    100.00%
+system.ruby.TCP_Controller.M.PrbInvData::total          574                      
+system.ruby.TCP_Controller.M.PrbShrData  |          14     16.47%     16.47% |          10     11.76%     28.24% |           9     10.59%     38.82% |           8      9.41%     48.24% |          14     16.47%     64.71% |           6      7.06%     71.76% |          14     16.47%     88.24% |          10     11.76%    100.00%
+system.ruby.TCP_Controller.M.PrbShrData::total           85                      
+system.ruby.TCP_Controller.I_M.TCC_AckM  |          93     13.06%     13.06% |          89     12.50%     25.56% |          86     12.08%     37.64% |          76     10.67%     48.31% |          92     12.92%     61.24% |          89     12.50%     73.74% |         104     14.61%     88.34% |          83     11.66%    100.00%
+system.ruby.TCP_Controller.I_M.TCC_AckM::total          712                      
+system.ruby.TCP_Controller.I_ES.TCC_AckS |           9     14.52%     14.52% |           8     12.90%     27.42% |           8     12.90%     40.32% |          12     19.35%     59.68% |           5      8.06%     67.74% |           3      4.84%     72.58% |           8     12.90%     85.48% |           9     14.52%    100.00%
+system.ruby.TCP_Controller.I_ES.TCC_AckS::total           62                      
+system.ruby.TCP_Controller.I_ES.TCC_AckE |           1     33.33%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
+system.ruby.TCP_Controller.I_ES.TCC_AckE::total            3                      
+system.ruby.TCP_Controller.S_M.TCC_AckM  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00%
+system.ruby.TCP_Controller.S_M.TCC_AckM::total            2                      
+system.ruby.TCP_Controller.O_M.TCC_AckM  |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     12.50%     12.50% |           0      0.00%     12.50% |           5     62.50%     75.00% |           0      0.00%     75.00% |           1     12.50%     87.50% |           1     12.50%    100.00%
+system.ruby.TCP_Controller.O_M.TCC_AckM::total            8                      
+system.ruby.TCP_Controller.O_M.PrbShrData |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.TCP_Controller.O_M.PrbShrData::total            2                      
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
index 6f23123b5..55d4b5c7c 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -54,8 +59,13 @@ check_flush=false
 checks_to_complete=100
 clk_domain=system.clk_domain
 deadlock_threshold=50000
+default_p_state=UNDEFINED
 eventq_index=0
 num_cpus=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 system=system
 wakeup_frequency=10
 cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
@@ -70,27 +80,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -102,6 +112,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -109,12 +120,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -136,9 +152,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -152,12 +168,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=true
 
 [system.ruby.clk_domain]
@@ -174,10 +195,15 @@ children=directory requestToDir responseFromDir responseFromMemory responseToDir
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=6
 eventq_index=0
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestToDir=system.ruby.dir_cntrl0.requestToDir
 responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -236,6 +262,7 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 enable_prefetch=false
 eventq_index=0
 l1_request_latency=2
@@ -244,6 +271,10 @@ l2_select_num_bits=0
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 number_of_TBEs=256
 optionalQueue=system.ruby.l1_cntrl0.optionalQueue
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 prefetcher=system.ruby.l1_cntrl0.prefetcher
 recycle_latency=10
 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
@@ -372,17 +403,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.L1Dcache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.L1Icache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=0
 slave=system.cpu.cpuInstDataPort[0]
@@ -405,10 +441,15 @@ L2cache=system.ruby.l2_cntrl0.L2cache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 l2_request_latency=2
 l2_response_latency=2
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
 responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
@@ -499,18 +540,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
 netifs=
 number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
 ruby_system=system.ruby
 topology=Crossbar
@@ -673,42 +719,216 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers18]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers19]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
 weight=1
 
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11
+power_model=Null
 router_id=0
 virt_nets=3
 
@@ -800,8 +1020,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11
+power_model=Null
 router_id=1
 virt_nets=3
 
@@ -893,8 +1119,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11
+power_model=Null
 router_id=2
 virt_nets=3
 
@@ -986,8 +1218,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17
+power_model=Null
 router_id=3
 virt_nets=3
 
@@ -1120,9 +1358,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
index c2086c0ba..cee0dfc57 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
@@ -4,7 +4,5 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
index db9c26437..8e5796606 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
+Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:01:33
-gem5 started Jan 21 2016 14:02:10
-gem5 executing on zizzer, pid 44718
-command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level
+gem5 compiled Oct 13 2016 20:28:06
+gem5 started Oct 13 2016 20:28:31
+gem5 executing on e108600-lin, pid 8234
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 43191 because Ruby Tester completed
+Exiting @ tick 44021 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
index da6a7f59a..ed12265fc 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
@@ -1,45 +1,45 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000043                       # Number of seconds simulated
-sim_ticks                                       43191                       # Number of ticks simulated
-final_tick                                      43191                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000044                       # Number of seconds simulated
+sim_ticks                                       44021                       # Number of ticks simulated
+final_tick                                      44021                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 648785                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 451080                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                                 728057                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 409368                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0        57728                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total              57728                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0        51904                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total           51904                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0          902                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total                 902                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0          811                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total                811                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0   1336574749                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            1336574749                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0   1201731842                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total           1201731842                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   2538306592                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           2538306592                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                         902                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                        811                       # Number of write requests accepted
-system.mem_ctrls.readBursts                       902                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                      811                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  47168                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   10560                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   41728                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                   57728                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys                51904                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    165                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   130                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0        55424                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total              55424                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0        49920                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total           49920                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0          866                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total                 866                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0          780                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total                780                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0   1259035460                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total            1259035460                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0   1134004225                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total           1134004225                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   2393039686                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           2393039686                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                         866                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                        780                       # Number of write requests accepted
+system.mem_ctrls.readBursts                       866                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                      780                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM                  45760                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                    9664                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   40640                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                   55424                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys                49920                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                    151                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   116                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0               232                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1               230                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2               227                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3                48                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0               210                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1               228                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2               223                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3                54                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 0                       # Per bank write bursts
@@ -52,10 +52,10 @@ system.mem_ctrls.perBankRdBursts::12                0                       # Pe
 system.mem_ctrls.perBankRdBursts::13                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0               201                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1               202                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0               184                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1               198                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::2               203                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3                46                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3                50                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::5                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
@@ -70,24 +70,24 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         43109                       # Total gap between requests
+system.mem_ctrls.totGap                         44002                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                   902                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                   866                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6                  811                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     456                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                     281                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6                  780                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                     430                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                     284                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2                       1                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
@@ -132,24 +132,24 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     24                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                     41                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     41                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                     41                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     43                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                     50                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     45                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      7                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     29                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     41                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                     41                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                     48                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::28                     41                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     40                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     40                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     40                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     39                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                     39                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     39                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                     39                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
@@ -181,140 +181,146 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples           94                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean           928                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   868.246553                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   227.729324                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127            1      1.06%      1.06% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255            2      2.13%      3.19% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383            3      3.19%      6.38% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511            1      1.06%      7.45% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639            4      4.26%     11.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            3      3.19%     14.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            2      2.13%     17.02% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            3      3.19%     20.21% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           75     79.79%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total           94                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples           40                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      18.125000                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     17.875881                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      3.480256                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15             4     10.00%     10.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            17     42.50%     52.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19            12     30.00%     82.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21             2      5.00%     87.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23             3      7.50%     95.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-25             1      2.50%     97.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35             1      2.50%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total            40                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples           40                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.300000                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.280005                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.853349                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               35     87.50%     87.50% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                1      2.50%     90.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                1      2.50%     92.50% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                3      7.50%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total            40                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         8956                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   22959                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       3685                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        12.15                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples           93                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    915.268817                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   819.587468                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   267.362608                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127            2      2.15%      2.15% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255            5      5.38%      7.53% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383            1      1.08%      8.60% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511            3      3.23%     11.83% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            3      3.23%     15.05% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            4      4.30%     19.35% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           75     80.65%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total           93                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples           39                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      17.897436                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     17.675839                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      3.385689                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15             5     12.82%     12.82% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17            14     35.90%     48.72% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19            15     38.46%     87.18% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21             3      7.69%     94.87% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::22-23             1      2.56%     97.44% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::36-37             1      2.56%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total            39                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples           39                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.282051                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.268709                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.686284                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               33     84.62%     84.62% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                1      2.56%     87.18% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                5     12.82%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total            39                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                        12989                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   26574                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       3575                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        18.17                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   31.15                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                      1092.08                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       966.13                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   1336.57                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                   1201.73                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   37.17                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                      1039.50                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       923.20                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                   1259.04                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                   1134.00                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                        16.08                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     8.53                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    7.55                       # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen                       1.63                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      25.46                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      647                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     644                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 87.79                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                94.57                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         25.17                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    91.04                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   665280                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   369600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 8311680                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                6231168                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              2542800                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             26706780                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy                87000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               44914308                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower           1146.065527                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE           19                       # Time in different power states
+system.mem_ctrls.busUtil                        15.33                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     8.12                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    7.21                       # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen                       1.66                       # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      25.56                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      627                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     627                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 87.69                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                94.43                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         26.73                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    90.94                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   685440                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   359352                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 8168160                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                5303520                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         3073200.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              8952648                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy                72576                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        11032464                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy            1920                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               37649280                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            855.257264                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                24199                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE           49                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          1300                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         37885                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            5                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         18473                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        24194                       # Time in different power states
 system.mem_ctrls_1.actEnergy                        0                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_1.preEnergy                        0                       # Energy for precharge commands per rank (pJ)
 system.mem_ctrls_1.readEnergy                       0                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              2542800                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy               841320                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy             22767600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               26151720                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            667.544415                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE        37890                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          1300                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.refreshEnergy         1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy               224352                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              3002880                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy               0                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy         2889984                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy          6763920                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               14110416                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            320.538289                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                 7526                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE         7786                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF           526                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF        28183                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         7526                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT             0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
 system.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
-system.ruby.delayHist::samples                   6720                       # delay histogram for all message
-system.ruby.delayHist::mean                  2.675000                       # delay histogram for all message
-system.ruby.delayHist::stdev                 5.399947                       # delay histogram for all message
-system.ruby.delayHist                    |        5144     76.55%     76.55% |          51      0.76%     77.31% |        1138     16.93%     94.24% |           8      0.12%     94.36% |         323      4.81%     99.17% |           6      0.09%     99.26% |           0      0.00%     99.26% |          43      0.64%     99.90% |           0      0.00%     99.90% |           7      0.10%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                     6720                       # delay histogram for all message
+system.ruby.delayHist::samples                   6525                       # delay histogram for all message
+system.ruby.delayHist::mean                  2.632031                       # delay histogram for all message
+system.ruby.delayHist::stdev                 5.481611                       # delay histogram for all message
+system.ruby.delayHist                    |        5040     77.24%     77.24% |          61      0.93%     78.18% |        1056     16.18%     94.36% |           7      0.11%     94.47% |         285      4.37%     98.84% |           1      0.02%     98.85% |           1      0.02%     98.87% |          70      1.07%     99.94% |           0      0.00%     99.94% |           4      0.06%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                     6525                       # delay histogram for all message
 system.ruby.outstanding_req_hist_seqr::bucket_size            2                      
 system.ruby.outstanding_req_hist_seqr::max_bucket           19                      
-system.ruby.outstanding_req_hist_seqr::samples         1041                      
-system.ruby.outstanding_req_hist_seqr::mean    15.700288                      
-system.ruby.outstanding_req_hist_seqr::gmean    15.598621                      
-system.ruby.outstanding_req_hist_seqr::stdev     1.186661                      
-system.ruby.outstanding_req_hist_seqr    |           1      0.10%      0.10% |           2      0.19%      0.29% |           2      0.19%      0.48% |           2      0.19%      0.67% |           4      0.38%      1.06% |           2      0.19%      1.25% |           5      0.48%      1.73% |         167     16.04%     17.77% |         856     82.23%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist_seqr::total         1041                      
+system.ruby.outstanding_req_hist_seqr::samples         1019                      
+system.ruby.outstanding_req_hist_seqr::mean    15.664377                      
+system.ruby.outstanding_req_hist_seqr::gmean    15.560778                      
+system.ruby.outstanding_req_hist_seqr::stdev     1.199712                      
+system.ruby.outstanding_req_hist_seqr    |           1      0.10%      0.10% |           2      0.20%      0.29% |           2      0.20%      0.49% |           2      0.20%      0.69% |           4      0.39%      1.08% |           2      0.20%      1.28% |           5      0.49%      1.77% |         199     19.53%     21.30% |         802     78.70%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist_seqr::total         1019                      
 system.ruby.latency_hist_seqr::bucket_size          128                      
 system.ruby.latency_hist_seqr::max_bucket         1279                      
-system.ruby.latency_hist_seqr::samples           1025                      
-system.ruby.latency_hist_seqr::mean        658.597073                      
-system.ruby.latency_hist_seqr::gmean       361.484818                      
-system.ruby.latency_hist_seqr::stdev       297.350955                      
-system.ruby.latency_hist_seqr            |         154     15.02%     15.02% |          24      2.34%     17.37% |           5      0.49%     17.85% |           4      0.39%     18.24% |          32      3.12%     21.37% |         302     29.46%     50.83% |         418     40.78%     91.61% |          49      4.78%     96.39% |          28      2.73%     99.12% |           9      0.88%    100.00%
-system.ruby.latency_hist_seqr::total             1025                      
+system.ruby.latency_hist_seqr::samples           1004                      
+system.ruby.latency_hist_seqr::mean        684.454183                      
+system.ruby.latency_hist_seqr::gmean       346.202279                      
+system.ruby.latency_hist_seqr::stdev       321.934539                      
+system.ruby.latency_hist_seqr            |         155     15.44%     15.44% |          28      2.79%     18.23% |           4      0.40%     18.63% |           3      0.30%     18.92% |           6      0.60%     19.52% |         263     26.20%     45.72% |         367     36.55%     82.27% |         113     11.25%     93.53% |          53      5.28%     98.80% |          12      1.20%    100.00%
+system.ruby.latency_hist_seqr::total             1004                      
 system.ruby.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.hit_latency_hist_seqr::max_bucket            9                      
-system.ruby.hit_latency_hist_seqr::samples           89                      
+system.ruby.hit_latency_hist_seqr::samples          101                      
 system.ruby.hit_latency_hist_seqr::mean             1                      
 system.ruby.hit_latency_hist_seqr::gmean            1                      
-system.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |          89    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist_seqr::total           89                      
+system.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |         101    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist_seqr::total          101                      
 system.ruby.miss_latency_hist_seqr::bucket_size          128                      
 system.ruby.miss_latency_hist_seqr::max_bucket         1279                      
-system.ruby.miss_latency_hist_seqr::samples          936                      
-system.ruby.miss_latency_hist_seqr::mean   721.125000                      
-system.ruby.miss_latency_hist_seqr::gmean   632.888578                      
-system.ruby.miss_latency_hist_seqr::stdev   227.503250                      
-system.ruby.miss_latency_hist_seqr       |          65      6.94%      6.94% |          24      2.56%      9.51% |           5      0.53%     10.04% |           4      0.43%     10.47% |          32      3.42%     13.89% |         302     32.26%     46.15% |         418     44.66%     90.81% |          49      5.24%     96.05% |          28      2.99%     99.04% |           9      0.96%    100.00%
-system.ruby.miss_latency_hist_seqr::total          936                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.L1Dcache.demand_hits           89                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          875                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          964                       # Number of cache demand accesses
+system.ruby.miss_latency_hist_seqr::samples          903                      
+system.ruby.miss_latency_hist_seqr::mean   760.898117                      
+system.ruby.miss_latency_hist_seqr::gmean   665.813242                      
+system.ruby.miss_latency_hist_seqr::stdev   238.941361                      
+system.ruby.miss_latency_hist_seqr       |          54      5.98%      5.98% |          28      3.10%      9.08% |           4      0.44%      9.52% |           3      0.33%      9.86% |           6      0.66%     10.52% |         263     29.13%     39.65% |         367     40.64%     80.29% |         113     12.51%     92.80% |          53      5.87%     98.67% |          12      1.33%    100.00%
+system.ruby.miss_latency_hist_seqr::total          903                      
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.L1Dcache.demand_hits          101                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          855                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          956                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses           64                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses           64                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_misses           50                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses           50                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
 system.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
 system.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
@@ -324,340 +330,346 @@ system.ruby.l1_cntrl0.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
 system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            4                       # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           80                       # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            6                       # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
-system.ruby.l2_cntrl0.L2cache.demand_hits           34                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses          904                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses          938                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           86                       # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            8                       # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.L2cache.demand_hits           39                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses          866                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses          905                       # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized    11.804543                      
-system.ruby.network.routers0.msg_count.Control::0          939                      
-system.ruby.network.routers0.msg_count.Request_Control::2          278                      
-system.ruby.network.routers0.msg_count.Response_Data::1          936                      
-system.ruby.network.routers0.msg_count.Response_Control::1          873                      
-system.ruby.network.routers0.msg_count.Response_Control::2          873                      
-system.ruby.network.routers0.msg_count.Writeback_Data::0          785                      
-system.ruby.network.routers0.msg_count.Writeback_Data::1          213                      
-system.ruby.network.routers0.msg_count.Writeback_Control::0           25                      
-system.ruby.network.routers0.msg_bytes.Control::0         7512                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2         2224                      
-system.ruby.network.routers0.msg_bytes.Response_Data::1        67392                      
-system.ruby.network.routers0.msg_bytes.Response_Control::1         6984                      
-system.ruby.network.routers0.msg_bytes.Response_Control::2         6984                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0        56520                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1        15336                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0          200                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized    21.822255                      
-system.ruby.network.routers1.msg_count.Control::0         1842                      
-system.ruby.network.routers1.msg_count.Request_Control::2          279                      
-system.ruby.network.routers1.msg_count.Response_Data::1         2649                      
-system.ruby.network.routers1.msg_count.Response_Control::1         1859                      
-system.ruby.network.routers1.msg_count.Response_Control::2          873                      
-system.ruby.network.routers1.msg_count.Writeback_Data::0          785                      
-system.ruby.network.routers1.msg_count.Writeback_Data::1          213                      
-system.ruby.network.routers1.msg_count.Writeback_Control::0           25                      
-system.ruby.network.routers1.msg_bytes.Control::0        14736                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         2232                      
-system.ruby.network.routers1.msg_bytes.Response_Data::1       190728                      
-system.ruby.network.routers1.msg_bytes.Response_Control::1        14872                      
-system.ruby.network.routers1.msg_bytes.Response_Control::2         6984                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0        56520                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1        15336                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0          200                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized    10.015976                      
-system.ruby.network.routers2.msg_count.Control::0          902                      
-system.ruby.network.routers2.msg_count.Response_Data::1         1713                      
-system.ruby.network.routers2.msg_count.Response_Control::1          985                      
-system.ruby.network.routers2.msg_bytes.Control::0         7216                      
-system.ruby.network.routers2.msg_bytes.Response_Data::1       123336                      
-system.ruby.network.routers2.msg_bytes.Response_Control::1         7880                      
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized    14.547012                      
-system.ruby.network.routers3.msg_count.Control::0         1841                      
-system.ruby.network.routers3.msg_count.Request_Control::2          278                      
-system.ruby.network.routers3.msg_count.Response_Data::1         2649                      
-system.ruby.network.routers3.msg_count.Response_Control::1         1858                      
-system.ruby.network.routers3.msg_count.Response_Control::2          873                      
-system.ruby.network.routers3.msg_count.Writeback_Data::0          785                      
-system.ruby.network.routers3.msg_count.Writeback_Data::1          213                      
-system.ruby.network.routers3.msg_count.Writeback_Control::0           25                      
-system.ruby.network.routers3.msg_bytes.Control::0        14728                      
-system.ruby.network.routers3.msg_bytes.Request_Control::2         2224                      
-system.ruby.network.routers3.msg_bytes.Response_Data::1       190728                      
-system.ruby.network.routers3.msg_bytes.Response_Control::1        14864                      
-system.ruby.network.routers3.msg_bytes.Response_Control::2         6984                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::0        56520                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::1        15336                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0          200                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Control            5524                      
-system.ruby.network.msg_count.Request_Control          835                      
-system.ruby.network.msg_count.Response_Data         7947                      
-system.ruby.network.msg_count.Response_Control         8194                      
-system.ruby.network.msg_count.Writeback_Data         2994                      
-system.ruby.network.msg_count.Writeback_Control           75                      
-system.ruby.network.msg_byte.Control            44192                      
-system.ruby.network.msg_byte.Request_Control         6680                      
-system.ruby.network.msg_byte.Response_Data       572184                      
-system.ruby.network.msg_byte.Response_Control        65552                      
-system.ruby.network.msg_byte.Writeback_Data       215568                      
-system.ruby.network.msg_byte.Writeback_Control          600                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        43191                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization    11.009238                      
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::2          278                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::1          936                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::1          808                      
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2         2224                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1        67392                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1         6464                      
-system.ruby.network.routers0.throttle1.link_utilization    12.599847                      
-system.ruby.network.routers0.throttle1.msg_count.Control::0          939                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::1           65                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::2          873                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0          785                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1          213                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0           25                      
-system.ruby.network.routers0.throttle1.msg_bytes.Control::0         7512                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1          520                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2         6984                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0        56520                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1        15336                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0          200                      
-system.ruby.network.routers1.throttle0.link_utilization    23.037207                      
-system.ruby.network.routers1.throttle0.msg_count.Control::0          939                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::1          902                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::1          963                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::2          873                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0          785                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1          213                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0           25                      
-system.ruby.network.routers1.throttle0.msg_bytes.Control::0         7512                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1        64944                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1         7704                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2         6984                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0        56520                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1        15336                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0          200                      
-system.ruby.network.routers1.throttle1.link_utilization    20.607302                      
-system.ruby.network.routers1.throttle1.msg_count.Control::0          903                      
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::2          279                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::1         1747                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::1          896                      
-system.ruby.network.routers1.throttle1.msg_bytes.Control::0         7224                      
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2         2232                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1       125784                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1         7168                      
-system.ruby.network.routers2.throttle0.link_utilization     9.594591                      
-system.ruby.network.routers2.throttle0.msg_count.Control::0          902                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::1          811                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::1           87                      
-system.ruby.network.routers2.throttle0.msg_bytes.Control::0         7216                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1        58392                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1          696                      
-system.ruby.network.routers2.throttle1.link_utilization    10.437360                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::1          902                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::1          898                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1        64944                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1         7184                      
-system.ruby.network.routers3.throttle0.link_utilization    11.009238                      
-system.ruby.network.routers3.throttle0.msg_count.Request_Control::2          278                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::1          936                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::1          808                      
-system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2         2224                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1        67392                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1         6464                      
-system.ruby.network.routers3.throttle1.link_utilization    23.037207                      
-system.ruby.network.routers3.throttle1.msg_count.Control::0          939                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::1          902                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::1          963                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::2          873                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0          785                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1          213                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0           25                      
-system.ruby.network.routers3.throttle1.msg_bytes.Control::0         7512                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1        64944                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1         7704                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2         6984                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0        56520                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1        15336                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0          200                      
-system.ruby.network.routers3.throttle2.link_utilization     9.594591                      
-system.ruby.network.routers3.throttle2.msg_count.Control::0          902                      
-system.ruby.network.routers3.throttle2.msg_count.Response_Data::1          811                      
-system.ruby.network.routers3.throttle2.msg_count.Response_Control::1           87                      
-system.ruby.network.routers3.throttle2.msg_bytes.Control::0         7216                      
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1        58392                      
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1          696                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized    11.308239                      
+system.ruby.network.routers0.msg_count.Control::0          905                      
+system.ruby.network.routers0.msg_count.Request_Control::2          268                      
+system.ruby.network.routers0.msg_count.Response_Data::1          902                      
+system.ruby.network.routers0.msg_count.Response_Control::1          853                      
+system.ruby.network.routers0.msg_count.Response_Control::2          852                      
+system.ruby.network.routers0.msg_count.Writeback_Data::0          769                      
+system.ruby.network.routers0.msg_count.Writeback_Data::1          218                      
+system.ruby.network.routers0.msg_count.Writeback_Control::0           33                      
+system.ruby.network.routers0.msg_bytes.Control::0         7240                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2         2144                      
+system.ruby.network.routers0.msg_bytes.Response_Data::1        64944                      
+system.ruby.network.routers0.msg_bytes.Response_Control::1         6824                      
+system.ruby.network.routers0.msg_bytes.Response_Control::2         6816                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0        55368                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1        15696                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0          264                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized    20.738398                      
+system.ruby.network.routers1.msg_count.Control::0         1771                      
+system.ruby.network.routers1.msg_count.Request_Control::2          268                      
+system.ruby.network.routers1.msg_count.Response_Data::1         2546                      
+system.ruby.network.routers1.msg_count.Response_Control::1         1796                      
+system.ruby.network.routers1.msg_count.Response_Control::2          852                      
+system.ruby.network.routers1.msg_count.Writeback_Data::0          769                      
+system.ruby.network.routers1.msg_count.Writeback_Data::1          218                      
+system.ruby.network.routers1.msg_count.Writeback_Control::0           33                      
+system.ruby.network.routers1.msg_bytes.Control::0        14168                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         2144                      
+system.ruby.network.routers1.msg_bytes.Response_Data::1       183312                      
+system.ruby.network.routers1.msg_bytes.Response_Control::1        14368                      
+system.ruby.network.routers1.msg_bytes.Response_Control::2         6816                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0        55368                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1        15696                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0          264                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     9.432430                      
+system.ruby.network.routers2.msg_count.Control::0          866                      
+system.ruby.network.routers2.msg_count.Response_Data::1         1645                      
+system.ruby.network.routers2.msg_count.Response_Control::1          943                      
+system.ruby.network.routers2.msg_bytes.Control::0         6928                      
+system.ruby.network.routers2.msg_bytes.Response_Data::1       118440                      
+system.ruby.network.routers2.msg_bytes.Response_Control::1         7544                      
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized    13.825598                      
+system.ruby.network.routers3.msg_count.Control::0         1771                      
+system.ruby.network.routers3.msg_count.Request_Control::2          268                      
+system.ruby.network.routers3.msg_count.Response_Data::1         2546                      
+system.ruby.network.routers3.msg_count.Response_Control::1         1796                      
+system.ruby.network.routers3.msg_count.Response_Control::2          852                      
+system.ruby.network.routers3.msg_count.Writeback_Data::0          769                      
+system.ruby.network.routers3.msg_count.Writeback_Data::1          218                      
+system.ruby.network.routers3.msg_count.Writeback_Control::0           33                      
+system.ruby.network.routers3.msg_bytes.Control::0        14168                      
+system.ruby.network.routers3.msg_bytes.Request_Control::2         2144                      
+system.ruby.network.routers3.msg_bytes.Response_Data::1       183312                      
+system.ruby.network.routers3.msg_bytes.Response_Control::1        14368                      
+system.ruby.network.routers3.msg_bytes.Response_Control::2         6816                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::0        55368                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::1        15696                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0          264                      
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
+system.ruby.network.msg_count.Control            5313                      
+system.ruby.network.msg_count.Request_Control          804                      
+system.ruby.network.msg_count.Response_Data         7639                      
+system.ruby.network.msg_count.Response_Control         7944                      
+system.ruby.network.msg_count.Writeback_Data         2961                      
+system.ruby.network.msg_count.Writeback_Control           99                      
+system.ruby.network.msg_byte.Control            42504                      
+system.ruby.network.msg_byte.Request_Control         6432                      
+system.ruby.network.msg_byte.Response_Data       550008                      
+system.ruby.network.msg_byte.Response_Control        63552                      
+system.ruby.network.msg_byte.Writeback_Data       213192                      
+system.ruby.network.msg_byte.Writeback_Control          792                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        44021                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization    10.437064                      
+system.ruby.network.routers0.throttle0.msg_count.Request_Control::2          268                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::1          902                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Control::1          803                      
+system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2         2144                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1        64944                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1         6424                      
+system.ruby.network.routers0.throttle1.link_utilization    12.179414                      
+system.ruby.network.routers0.throttle1.msg_count.Control::0          905                      
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::1           50                      
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::2          852                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0          769                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1          218                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0           33                      
+system.ruby.network.routers0.throttle1.msg_bytes.Control::0         7240                      
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1          400                      
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2         6816                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0        55368                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1        15696                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0          264                      
+system.ruby.network.routers1.throttle0.link_utilization    21.989505                      
+system.ruby.network.routers1.throttle0.msg_count.Control::0          905                      
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::1          864                      
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::1          911                      
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::2          852                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0          769                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1          218                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0           33                      
+system.ruby.network.routers1.throttle0.msg_bytes.Control::0         7240                      
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1        62208                      
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1         7288                      
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2         6816                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0        55368                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1        15696                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0          264                      
+system.ruby.network.routers1.throttle1.link_utilization    19.487290                      
+system.ruby.network.routers1.throttle1.msg_count.Control::0          866                      
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::2          268                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::1         1682                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Control::1          885                      
+system.ruby.network.routers1.throttle1.msg_bytes.Control::0         6928                      
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2         2144                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1       121104                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1         7080                      
+system.ruby.network.routers2.throttle0.link_utilization     9.050226                      
+system.ruby.network.routers2.throttle0.msg_count.Control::0          866                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::1          780                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Control::1           82                      
+system.ruby.network.routers2.throttle0.msg_bytes.Control::0         6928                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1        56160                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1          656                      
+system.ruby.network.routers2.throttle1.link_utilization     9.814634                      
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::1          865                      
+system.ruby.network.routers2.throttle1.msg_count.Response_Control::1          861                      
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1        62280                      
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1         6888                      
+system.ruby.network.routers3.throttle0.link_utilization    10.437064                      
+system.ruby.network.routers3.throttle0.msg_count.Request_Control::2          268                      
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::1          902                      
+system.ruby.network.routers3.throttle0.msg_count.Response_Control::1          803                      
+system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2         2144                      
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1        64944                      
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1         6424                      
+system.ruby.network.routers3.throttle1.link_utilization    21.989505                      
+system.ruby.network.routers3.throttle1.msg_count.Control::0          905                      
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::1          864                      
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::1          911                      
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::2          852                      
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0          769                      
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1          218                      
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0           33                      
+system.ruby.network.routers3.throttle1.msg_bytes.Control::0         7240                      
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1        62208                      
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1         7288                      
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2         6816                      
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0        55368                      
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1        15696                      
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0          264                      
+system.ruby.network.routers3.throttle2.link_utilization     9.050226                      
+system.ruby.network.routers3.throttle2.msg_count.Control::0          866                      
+system.ruby.network.routers3.throttle2.msg_count.Response_Data::1          780                      
+system.ruby.network.routers3.throttle2.msg_count.Response_Control::1           82                      
+system.ruby.network.routers3.throttle2.msg_bytes.Control::0         6928                      
+system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1        56160                      
+system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1          656                      
 system.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples          2620                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean         5.712977                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev        7.142048                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0           |        1406     53.66%     53.66% |           9      0.34%     54.01% |         823     31.41%     85.42% |           4      0.15%     85.57% |         323     12.33%     97.90% |           5      0.19%     98.09% |           0      0.00%     98.09% |          43      1.64%     99.73% |           0      0.00%     99.73% |           7      0.27%    100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total            2620                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_1::bucket_size            4                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::max_bucket           39                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples          3822                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         0.787023                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        2.428600                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |        3460     90.53%     90.53% |          42      1.10%     91.63% |         315      8.24%     99.87% |           4      0.10%     99.97% |           0      0.00%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total            3822                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_0::samples          2559                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean         5.696757                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev        7.319490                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0           |        1396     54.55%     54.55% |           8      0.31%     54.87% |         792     30.95%     85.81% |           2      0.08%     85.89% |         285     11.14%     97.03% |           1      0.04%     97.07% |           1      0.04%     97.11% |          70      2.74%     99.84% |           0      0.00%     99.84% |           4      0.16%    100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total            2559                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples          3698                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         0.702001                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        2.286109                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |        3361     90.89%     90.89% |          15      0.41%     91.29% |          10      0.27%     91.56% |          43      1.16%     92.73% |         218      5.90%     98.62% |          46      1.24%     99.86% |           3      0.08%     99.95% |           2      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total            3698                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples           278                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |         278    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total             278                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples           268                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |         268    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total             268                       # delay histogram for vnet_2
 system.ruby.LD.latency_hist_seqr::bucket_size          128                      
 system.ruby.LD.latency_hist_seqr::max_bucket         1279                      
-system.ruby.LD.latency_hist_seqr::samples           37                      
-system.ruby.LD.latency_hist_seqr::mean     621.135135                      
-system.ruby.LD.latency_hist_seqr::gmean    207.168110                      
-system.ruby.LD.latency_hist_seqr::stdev    333.448910                      
-system.ruby.LD.latency_hist_seqr         |           8     21.62%     21.62% |           0      0.00%     21.62% |           0      0.00%     21.62% |           0      0.00%     21.62% |           0      0.00%     21.62% |          13     35.14%     56.76% |          14     37.84%     94.59% |           2      5.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist_seqr::total            37                      
+system.ruby.LD.latency_hist_seqr::samples           50                      
+system.ruby.LD.latency_hist_seqr::mean     631.160000                      
+system.ruby.LD.latency_hist_seqr::gmean    197.121649                      
+system.ruby.LD.latency_hist_seqr::stdev    346.030868                      
+system.ruby.LD.latency_hist_seqr         |          11     22.00%     22.00% |           0      0.00%     22.00% |           0      0.00%     22.00% |           0      0.00%     22.00% |           1      2.00%     24.00% |          12     24.00%     48.00% |          21     42.00%     90.00% |           5     10.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::total            50                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
-system.ruby.LD.hit_latency_hist_seqr::samples            7                      
+system.ruby.LD.hit_latency_hist_seqr::samples           10                      
 system.ruby.LD.hit_latency_hist_seqr::mean            1                      
 system.ruby.LD.hit_latency_hist_seqr::gmean            1                      
-system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |           7    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist_seqr::total            7                      
+system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist_seqr::total           10                      
 system.ruby.LD.miss_latency_hist_seqr::bucket_size          128                      
 system.ruby.LD.miss_latency_hist_seqr::max_bucket         1279                      
-system.ruby.LD.miss_latency_hist_seqr::samples           30                      
-system.ruby.LD.miss_latency_hist_seqr::mean   765.833333                      
-system.ruby.LD.miss_latency_hist_seqr::gmean   719.114834                      
-system.ruby.LD.miss_latency_hist_seqr::stdev   153.429099                      
-system.ruby.LD.miss_latency_hist_seqr    |           1      3.33%      3.33% |           0      0.00%      3.33% |           0      0.00%      3.33% |           0      0.00%      3.33% |           0      0.00%      3.33% |          13     43.33%     46.67% |          14     46.67%     93.33% |           2      6.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist_seqr::total           30                      
+system.ruby.LD.miss_latency_hist_seqr::samples           40                      
+system.ruby.LD.miss_latency_hist_seqr::mean   788.700000                      
+system.ruby.LD.miss_latency_hist_seqr::gmean   738.614626                      
+system.ruby.LD.miss_latency_hist_seqr::stdev   152.194242                      
+system.ruby.LD.miss_latency_hist_seqr    |           1      2.50%      2.50% |           0      0.00%      2.50% |           0      0.00%      2.50% |           0      0.00%      2.50% |           1      2.50%      5.00% |          12     30.00%     35.00% |          21     52.50%     87.50% |           5     12.50%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::total           40                      
 system.ruby.ST.latency_hist_seqr::bucket_size          128                      
 system.ruby.ST.latency_hist_seqr::max_bucket         1279                      
-system.ruby.ST.latency_hist_seqr::samples          925                      
-system.ruby.ST.latency_hist_seqr::mean     697.631351                      
-system.ruby.ST.latency_hist_seqr::gmean    404.802159                      
-system.ruby.ST.latency_hist_seqr::stdev    266.794551                      
-system.ruby.ST.latency_hist_seqr         |         101     10.92%     10.92% |           7      0.76%     11.68% |           4      0.43%     12.11% |           4      0.43%     12.54% |          32      3.46%     16.00% |         289     31.24%     47.24% |         404     43.68%     90.92% |          47      5.08%     96.00% |          28      3.03%     99.03% |           9      0.97%    100.00%
-system.ruby.ST.latency_hist_seqr::total           925                      
+system.ruby.ST.latency_hist_seqr::samples          904                      
+system.ruby.ST.latency_hist_seqr::mean     719.136062                      
+system.ruby.ST.latency_hist_seqr::gmean    383.374715                      
+system.ruby.ST.latency_hist_seqr::stdev    298.133155                      
+system.ruby.ST.latency_hist_seqr         |         114     12.61%     12.61% |           8      0.88%     13.50% |           4      0.44%     13.94% |           3      0.33%     14.27% |           5      0.55%     14.82% |         251     27.77%     42.59% |         346     38.27%     80.86% |         108     11.95%     92.81% |          53      5.86%     98.67% |          12      1.33%    100.00%
+system.ruby.ST.latency_hist_seqr::total           904                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
-system.ruby.ST.hit_latency_hist_seqr::samples           82                      
+system.ruby.ST.hit_latency_hist_seqr::samples           91                      
 system.ruby.ST.hit_latency_hist_seqr::mean            1                      
 system.ruby.ST.hit_latency_hist_seqr::gmean            1                      
-system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |          82    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist_seqr::total           82                      
+system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |          91    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist_seqr::total           91                      
 system.ruby.ST.miss_latency_hist_seqr::bucket_size          128                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket         1279                      
-system.ruby.ST.miss_latency_hist_seqr::samples          843                      
-system.ruby.ST.miss_latency_hist_seqr::mean   765.393832                      
-system.ruby.ST.miss_latency_hist_seqr::gmean   725.861277                      
-system.ruby.ST.miss_latency_hist_seqr::stdev   162.026380                      
-system.ruby.ST.miss_latency_hist_seqr    |          19      2.25%      2.25% |           7      0.83%      3.08% |           4      0.47%      3.56% |           4      0.47%      4.03% |          32      3.80%      7.83% |         289     34.28%     42.11% |         404     47.92%     90.04% |          47      5.58%     95.61% |          28      3.32%     98.93% |           9      1.07%    100.00%
-system.ruby.ST.miss_latency_hist_seqr::total          843                      
-system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
-system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
-system.ruby.IFETCH.latency_hist_seqr::samples           63                      
-system.ruby.IFETCH.latency_hist_seqr::mean   107.476190                      
-system.ruby.IFETCH.latency_hist_seqr::gmean    95.146533                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    52.448702                      
-system.ruby.IFETCH.latency_hist_seqr     |          11     17.46%     17.46% |          34     53.97%     71.43% |          15     23.81%     95.24% |           2      3.17%     98.41% |           0      0.00%     98.41% |           1      1.59%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist_seqr::total           63                      
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
-system.ruby.IFETCH.miss_latency_hist_seqr::samples           63                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean   107.476190                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    95.146533                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    52.448702                      
-system.ruby.IFETCH.miss_latency_hist_seqr |          11     17.46%     17.46% |          34     53.97%     71.43% |          15     23.81%     95.24% |           2      3.17%     98.41% |           0      0.00%     98.41% |           1      1.59%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist_seqr::total           63                      
-system.ruby.Directory_Controller.Fetch            902      0.00%      0.00%
-system.ruby.Directory_Controller.Data             811      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          902      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          811      0.00%      0.00%
-system.ruby.Directory_Controller.CleanReplacement           87      0.00%      0.00%
-system.ruby.Directory_Controller.I.Fetch          902      0.00%      0.00%
-system.ruby.Directory_Controller.M.Data           811      0.00%      0.00%
-system.ruby.Directory_Controller.M.CleanReplacement           87      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data          902      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack          811      0.00%      0.00%
-system.ruby.L1Cache_Controller.Load                37      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch              67      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store              927      0.00%      0.00%
-system.ruby.L1Cache_Controller.Inv                278      0.00%      0.00%
-system.ruby.L1Cache_Controller.L1_Replacement        12331      0.00%      0.00%
-system.ruby.L1Cache_Controller.Data_Exclusive           30      0.00%      0.00%
-system.ruby.L1Cache_Controller.Data_all_Acks          906      0.00%      0.00%
-system.ruby.L1Cache_Controller.WB_Ack             808      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Load             30      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Ifetch           64      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Store           845      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement          121      0.00%      0.00%
-system.ruby.L1Cache_Controller.S.Inv               54      0.00%      0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement            3      0.00%      0.00%
-system.ruby.L1Cache_Controller.E.Inv                5      0.00%      0.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement           25      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Load               7      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Store             82      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Inv               57      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement          785      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Inv               6      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement          386      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive           30      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks           57      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement        11011      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks          843      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks            6      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_I.Ifetch            3      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_I.Inv            156      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack          652      0.00%      0.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack          156      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GET_INSTR           64      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETS             30      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX            844      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX            653      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX_old          267      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement          603      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean          569      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Data           902      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Ack            898      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data            208      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack_all             65      0.00%      0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock          873      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR           61      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS           29      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX          814      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_PUTX_old          134      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean           60      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GET_INSTR            3      0.00%      0.00%
+system.ruby.ST.miss_latency_hist_seqr::samples          813                      
+system.ruby.ST.miss_latency_hist_seqr::mean   799.517835                      
+system.ruby.ST.miss_latency_hist_seqr::gmean   746.124556                      
+system.ruby.ST.miss_latency_hist_seqr::stdev   185.954617                      
+system.ruby.ST.miss_latency_hist_seqr    |          23      2.83%      2.83% |           8      0.98%      3.81% |           4      0.49%      4.31% |           3      0.37%      4.67% |           5      0.62%      5.29% |         251     30.87%     36.16% |         346     42.56%     78.72% |         108     13.28%     92.00% |          53      6.52%     98.52% |          12      1.48%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::total          813                      
+system.ruby.IFETCH.latency_hist_seqr::bucket_size           32                      
+system.ruby.IFETCH.latency_hist_seqr::max_bucket          319                      
+system.ruby.IFETCH.latency_hist_seqr::samples           50                      
+system.ruby.IFETCH.latency_hist_seqr::mean   110.700000                      
+system.ruby.IFETCH.latency_hist_seqr::gmean    96.182985                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    52.466607                      
+system.ruby.IFETCH.latency_hist_seqr     |           1      2.00%      2.00% |           9     18.00%     20.00% |          11     22.00%     42.00% |           9     18.00%     60.00% |          13     26.00%     86.00% |           5     10.00%     96.00% |           0      0.00%     96.00% |           2      4.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::total           50                      
+system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           32                      
+system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          319                      
+system.ruby.IFETCH.miss_latency_hist_seqr::samples           50                      
+system.ruby.IFETCH.miss_latency_hist_seqr::mean   110.700000                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    96.182985                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    52.466607                      
+system.ruby.IFETCH.miss_latency_hist_seqr |           1      2.00%      2.00% |           9     18.00%     20.00% |          11     22.00%     42.00% |           9     18.00%     60.00% |          13     26.00%     86.00% |           5     10.00%     96.00% |           0      0.00%     96.00% |           2      4.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::total           50                      
+system.ruby.Directory_Controller.Fetch            866      0.00%      0.00%
+system.ruby.Directory_Controller.Data             780      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          865      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          779      0.00%      0.00%
+system.ruby.Directory_Controller.CleanReplacement           82      0.00%      0.00%
+system.ruby.Directory_Controller.I.Fetch          866      0.00%      0.00%
+system.ruby.Directory_Controller.M.Data           780      0.00%      0.00%
+system.ruby.Directory_Controller.M.CleanReplacement           82      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data          865      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack          779      0.00%      0.00%
+system.ruby.L1Cache_Controller.Load                51      0.00%      0.00%
+system.ruby.L1Cache_Controller.Ifetch              55      0.00%      0.00%
+system.ruby.L1Cache_Controller.Store              905      0.00%      0.00%
+system.ruby.L1Cache_Controller.Inv                268      0.00%      0.00%
+system.ruby.L1Cache_Controller.L1_Replacement        11918      0.00%      0.00%
+system.ruby.L1Cache_Controller.Data_Exclusive           39      0.00%      0.00%
+system.ruby.L1Cache_Controller.Data_all_Acks          863      0.00%      0.00%
+system.ruby.L1Cache_Controller.Ack_all              1      0.00%      0.00%
+system.ruby.L1Cache_Controller.WB_Ack             802      0.00%      0.00%
+system.ruby.L1Cache_Controller.NP.Load             41      0.00%      0.00%
+system.ruby.L1Cache_Controller.NP.Ifetch           50      0.00%      0.00%
+system.ruby.L1Cache_Controller.NP.Store           813      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement           92      0.00%      0.00%
+system.ruby.L1Cache_Controller.S.Store              1      0.00%      0.00%
+system.ruby.L1Cache_Controller.S.Inv               37      0.00%      0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement            5      0.00%      0.00%
+system.ruby.L1Cache_Controller.E.Inv                6      0.00%      0.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement           33      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Load              10      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Store             91      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Inv               43      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement          769      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Inv               7      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement          452      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive           39      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks           44      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement        10567      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks          812      0.00%      0.00%
+system.ruby.L1Cache_Controller.SM.Ack_all            1      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS_I.Data_all_Acks            7      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_I.Ifetch            5      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_I.Inv            175      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack          627      0.00%      0.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack          175      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GET_INSTR           50      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETS             41      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX            813      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_UPGRADE            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX            627      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX_old          314      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement          568      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean          551      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Data           864      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Ack            861      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data            212      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack_all             50      0.00%      0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock          852      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GET_INSTR           44      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS           39      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX          783      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_PUTX_old          163      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX            4      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_UPGRADE            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean           44      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GET_INSTR            6      0.00%      0.00%
 system.ruby.L2Cache_Controller.M.L1_GETS            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX           27      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement          603      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean           18      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX          653      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean          219      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.L1_PUTX_old           22      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack          898      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old          111      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data          208      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all           60      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data           29      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.L2_Replacement_clean          121      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data           60      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.L2_Replacement_clean          125      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data          813      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean           20      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock          870      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX           26      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement          568      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean           26      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX          627      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean          224      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.L1_PUTX_old           12      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack          861      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old          139      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data          212      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all           44      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean            3      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data           38      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.L2_Replacement_clean           96      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data           44      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.L2_Replacement_clean          132      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data          782      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock            5      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean           26      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock          847      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
index 41e35786f..fd5963bf9 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -54,8 +59,13 @@ check_flush=false
 checks_to_complete=100
 clk_domain=system.clk_domain
 deadlock_threshold=50000
+default_p_state=UNDEFINED
 eventq_index=0
 num_cpus=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 system=system
 wakeup_frequency=10
 cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
@@ -70,27 +80,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -102,6 +112,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -109,12 +120,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -136,9 +152,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -152,12 +168,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=true
 
 [system.ruby.clk_domain]
@@ -174,11 +195,16 @@ children=directory forwardFromDir requestToDir responseFromDir responseFromMemor
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=6
 eventq_index=0
 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestToDir=system.ruby.dir_cntrl0.requestToDir
 responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -245,10 +271,15 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 l2_select_num_bits=0
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
 requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache
@@ -358,17 +389,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.L1Dcache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.L1Icache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=0
 slave=system.cpu.cpuInstDataPort[0]
@@ -391,8 +427,13 @@ L2cache=system.ruby.l2_cntrl0.L2cache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 request_latency=2
 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
@@ -491,18 +532,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
 netifs=
 number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
 ruby_system=system.ruby
 topology=Crossbar
@@ -665,42 +711,216 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers18]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers19]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
 weight=1
 
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11
+power_model=Null
 router_id=0
 virt_nets=3
 
@@ -792,8 +1012,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11
+power_model=Null
 router_id=1
 virt_nets=3
 
@@ -885,8 +1111,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11
+power_model=Null
 router_id=2
 virt_nets=3
 
@@ -978,8 +1210,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17
+power_model=Null
 router_id=3
 virt_nets=3
 
@@ -1112,9 +1350,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
index c2086c0ba..cee0dfc57 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
@@ -4,7 +4,5 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
index bb50cd40f..354aa7d14 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
+Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:06:59
-gem5 started Jan 21 2016 14:07:35
-gem5 executing on zizzer, pid 50073
-command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
+gem5 compiled Oct 13 2016 20:30:58
+gem5 started Oct 13 2016 20:31:25
+gem5 executing on e108600-lin, pid 17788
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 54211 because Ruby Tester completed
+Exiting @ tick 57351 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index ade451317..c3a7f3ee2 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
@@ -1,45 +1,45 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000054                       # Number of seconds simulated
-sim_ticks                                       54211                       # Number of ticks simulated
-final_tick                                      54211                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000057                       # Number of seconds simulated
+sim_ticks                                       57351                       # Number of ticks simulated
+final_tick                                      57351                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 528623                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 452196                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_tick_rate                                 527309                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 410220                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0        54016                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total              54016                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0        48256                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total           48256                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0          844                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total                 844                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0          754                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total                754                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    996402944                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             996402944                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    890151445                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            890151445                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   1886554389                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1886554389                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                         844                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                        754                       # Number of write requests accepted
-system.mem_ctrls.readBursts                       844                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                      754                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  46720                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                    7296                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   42112                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                   54016                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys                48256                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    114                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                    77                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0        56384                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total              56384                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0        50624                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total           50624                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0          881                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total                 881                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0          791                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total                791                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    983138916                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             983138916                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    882704748                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            882704748                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   1865843664                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1865843664                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                         881                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                        791                       # Number of write requests accepted
+system.mem_ctrls.readBursts                       881                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                      791                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM                  48256                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                    8128                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   42816                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                   56384                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys                50624                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                    127                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                    95                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0               210                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1               227                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2               250                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3                43                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0               222                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1               247                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2               228                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3                57                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 0                       # Per bank write bursts
@@ -52,10 +52,10 @@ system.mem_ctrls.perBankRdBursts::12                0                       # Pe
 system.mem_ctrls.perBankRdBursts::13                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0               189                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1               208                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2               219                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3                42                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0               195                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1               221                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2               201                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3                52                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::5                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
@@ -70,23 +70,23 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         54170                       # Total gap between requests
+system.mem_ctrls.totGap                         57270                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                   844                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                   881                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6                  754                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     587                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                     140                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6                  791                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                     553                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                     198                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       3                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
@@ -132,26 +132,26 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                     21                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                     23                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     37                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                     40                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     41                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     38                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                     25                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                     26                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     31                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                     45                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                     43                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     39                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     39                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                     39                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                     39                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::28                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     38                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     39                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::30                     38                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::31                     38                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::32                     38                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::33                      2                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
@@ -181,360 +181,370 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples           97                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    888.742268                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   795.135498                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   283.200947                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255            8      8.25%      8.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383            2      2.06%     10.31% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511            3      3.09%     13.40% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639            2      2.06%     15.46% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            4      4.12%     19.59% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            1      1.03%     20.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            2      2.06%     22.68% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           75     77.32%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total           97                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples          103                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    877.359223                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   782.793653                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   281.638652                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127            2      1.94%      1.94% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255            4      3.88%      5.83% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383            6      5.83%     11.65% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639            6      5.83%     17.48% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            4      3.88%     21.36% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            3      2.91%     24.27% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            2      1.94%     26.21% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           76     73.79%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          103                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples           38                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      19.052632                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     18.749953                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      3.938359                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15             2      5.26%      5.26% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            13     34.21%     39.47% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             9     23.68%     63.16% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21             8     21.05%     84.21% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23             4     10.53%     94.74% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      19.447368                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     19.196443                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      3.599530                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15             1      2.63%      2.63% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17             9     23.68%     26.32% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19            10     26.32%     52.63% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21            13     34.21%     86.84% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::22-23             3      7.89%     94.74% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::24-25             1      2.63%     97.37% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::38-39             1      2.63%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::36-37             1      2.63%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::total            38                       # Reads before turning the bus around for writes
 system.mem_ctrls.wrPerTurnAround::samples           38                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      17.315789                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     17.271887                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      1.254296                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               16     42.11%     42.11% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                2      5.26%     47.37% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18               13     34.21%     81.58% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                6     15.79%     97.37% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      17.605263                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     17.559134                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      1.284828                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               13     34.21%     34.21% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                1      2.63%     36.84% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18               13     34.21%     71.05% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19               10     26.32%     97.37% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::20                1      2.63%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total            38                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         6080                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   19950                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       3650                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                         8.33                       # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat                        10814                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   25140                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       3770                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        14.34                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   27.33                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       861.82                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       776.82                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    996.40                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    890.15                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   33.34                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       841.42                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       746.56                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    983.14                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    882.70                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                        12.80                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     6.73                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    6.07                       # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen                       1.34                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      24.81                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      637                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     650                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 87.26                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                96.01                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         33.90                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    91.47                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   650160                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   361200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 7725120                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                5723136                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             32013252                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy               103800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               49628028                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower           1056.454956                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE           19                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF          1560                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         45411                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls.busUtil                        12.41                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     6.57                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    5.83                       # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen                       1.47                       # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      24.63                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      656                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     661                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 87.00                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                94.97                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         34.25                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    90.83                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   756840                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   397992                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 8613696                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                5587488                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         4302480.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             11006472                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy                91776                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        15034776                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy            1536                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               45793056                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            798.470053                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                32938                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE           43                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          1820                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            4                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         22513                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        32971                       # Time in different power states
 system.mem_ctrls_1.actEnergy                        0                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_1.preEnergy                        0                       # Energy for precharge commands per rank (pJ)
 system.mem_ctrls_1.readEnergy                       0                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy              1009584                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy             27291600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               31352544                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            667.615178                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE        45416                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          1560                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.refreshEnergy         1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy               224352                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              3002880                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy               0                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy         2889984                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy          9963120                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               17309616                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            301.818905                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                 7526                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE         7786                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF           526                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF        41513                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         7526                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT             0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
 system.ruby.outstanding_req_hist_seqr::bucket_size            2                      
 system.ruby.outstanding_req_hist_seqr::max_bucket           19                      
-system.ruby.outstanding_req_hist_seqr::samples          985                      
-system.ruby.outstanding_req_hist_seqr::mean    15.747208                      
-system.ruby.outstanding_req_hist_seqr::gmean    15.641156                      
-system.ruby.outstanding_req_hist_seqr::stdev     1.199617                      
-system.ruby.outstanding_req_hist_seqr    |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.51% |           2      0.20%      0.71% |           4      0.41%      1.12% |           2      0.20%      1.32% |           3      0.30%      1.62% |         110     11.17%     12.79% |         859     87.21%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist_seqr::total          985                      
+system.ruby.outstanding_req_hist_seqr::samples         1014                      
+system.ruby.outstanding_req_hist_seqr::mean    15.673570                      
+system.ruby.outstanding_req_hist_seqr::gmean    15.569970                      
+system.ruby.outstanding_req_hist_seqr::stdev     1.195975                      
+system.ruby.outstanding_req_hist_seqr    |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.49% |           2      0.20%      0.69% |           4      0.39%      1.08% |           2      0.20%      1.28% |           3      0.30%      1.58% |         194     19.13%     20.71% |         804     79.29%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist_seqr::total         1014                      
 system.ruby.latency_hist_seqr::bucket_size          256                      
 system.ruby.latency_hist_seqr::max_bucket         2559                      
-system.ruby.latency_hist_seqr::samples            970                      
-system.ruby.latency_hist_seqr::mean        876.382474                      
-system.ruby.latency_hist_seqr::gmean       454.463576                      
-system.ruby.latency_hist_seqr::stdev       370.932806                      
-system.ruby.latency_hist_seqr            |         146     15.05%     15.05% |           6      0.62%     15.67% |           4      0.41%     16.08% |         388     40.00%     56.08% |         418     43.09%     99.18% |           8      0.82%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist_seqr::total              970                      
+system.ruby.latency_hist_seqr::samples            999                      
+system.ruby.latency_hist_seqr::mean        900.097097                      
+system.ruby.latency_hist_seqr::gmean       478.512857                      
+system.ruby.latency_hist_seqr::stdev       377.349343                      
+system.ruby.latency_hist_seqr            |         145     14.51%     14.51% |           9      0.90%     15.42% |           4      0.40%     15.82% |         380     38.04%     53.85% |         412     41.24%     95.10% |          49      4.90%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::total              999                      
 system.ruby.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.hit_latency_hist_seqr::max_bucket            9                      
-system.ruby.hit_latency_hist_seqr::samples           92                      
+system.ruby.hit_latency_hist_seqr::samples           90                      
 system.ruby.hit_latency_hist_seqr::mean             1                      
 system.ruby.hit_latency_hist_seqr::gmean            1                      
-system.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |          92    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist_seqr::total           92                      
+system.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |          90    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist_seqr::total           90                      
 system.ruby.miss_latency_hist_seqr::bucket_size          256                      
 system.ruby.miss_latency_hist_seqr::max_bucket         2559                      
-system.ruby.miss_latency_hist_seqr::samples          878                      
-system.ruby.miss_latency_hist_seqr::mean   968.108200                      
-system.ruby.miss_latency_hist_seqr::gmean   862.901849                      
-system.ruby.miss_latency_hist_seqr::stdev   251.425992                      
-system.ruby.miss_latency_hist_seqr       |          54      6.15%      6.15% |           6      0.68%      6.83% |           4      0.46%      7.29% |         388     44.19%     51.48% |         418     47.61%     99.09% |           8      0.91%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist_seqr::total          878                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.L1Dcache.demand_hits           90                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          836                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          926                       # Number of cache demand accesses
+system.ruby.miss_latency_hist_seqr::samples          909                      
+system.ruby.miss_latency_hist_seqr::mean   989.116612                      
+system.ruby.miss_latency_hist_seqr::gmean   881.514808                      
+system.ruby.miss_latency_hist_seqr::stdev   261.625282                      
+system.ruby.miss_latency_hist_seqr       |          55      6.05%      6.05% |           9      0.99%      7.04% |           4      0.44%      7.48% |         380     41.80%     49.28% |         412     45.32%     94.61% |          49      5.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::total          909                      
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.L1Dcache.demand_hits           88                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          859                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          947                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits            2                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses           44                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses           46                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            7                       # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           75                       # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            2                       # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
-system.ruby.l2_cntrl0.L2cache.demand_hits           36                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses          844                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses          880                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.L1Icache.demand_misses           50                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses           52                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            2                       # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           89                       # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            5                       # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.L2cache.demand_hits           28                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses          881                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses          909                       # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     8.888879                      
-system.ruby.network.routers0.msg_count.Request_Control::0          880                      
-system.ruby.network.routers0.msg_count.Response_Data::2          843                      
-system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2           35                      
-system.ruby.network.routers0.msg_count.Writeback_Data::2          874                      
-system.ruby.network.routers0.msg_count.Writeback_Control::0         1749                      
-system.ruby.network.routers0.msg_count.Unblock_Control::2          878                      
-system.ruby.network.routers0.msg_bytes.Request_Control::0         7040                      
-system.ruby.network.routers0.msg_bytes.Response_Data::2        60696                      
-system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2         2520                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::2        62928                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0        13992                      
-system.ruby.network.routers0.msg_bytes.Unblock_Control::2         7024                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized    16.994245                      
-system.ruby.network.routers1.msg_count.Request_Control::0          880                      
-system.ruby.network.routers1.msg_count.Request_Control::1          844                      
-system.ruby.network.routers1.msg_count.Response_Data::2         1686                      
-system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2           36                      
-system.ruby.network.routers1.msg_count.Writeback_Data::2         1628                      
-system.ruby.network.routers1.msg_count.Writeback_Control::0         1749                      
-system.ruby.network.routers1.msg_count.Writeback_Control::1         1509                      
-system.ruby.network.routers1.msg_count.Unblock_Control::2         1720                      
-system.ruby.network.routers1.msg_bytes.Request_Control::0         7040                      
-system.ruby.network.routers1.msg_bytes.Request_Control::1         6752                      
-system.ruby.network.routers1.msg_bytes.Response_Data::2       121392                      
-system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2         2592                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::2       117216                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0        13992                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::1        12072                      
-system.ruby.network.routers1.msg_bytes.Unblock_Control::2        13760                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     8.101677                      
-system.ruby.network.routers2.msg_count.Request_Control::1          844                      
-system.ruby.network.routers2.msg_count.Response_Data::2          843                      
-system.ruby.network.routers2.msg_count.Writeback_Data::2          754                      
-system.ruby.network.routers2.msg_count.Writeback_Control::1         1509                      
-system.ruby.network.routers2.msg_count.Unblock_Control::2          842                      
-system.ruby.network.routers2.msg_bytes.Request_Control::1         6752                      
-system.ruby.network.routers2.msg_bytes.Response_Data::2        60696                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::2        54288                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::1        12072                      
-system.ruby.network.routers2.msg_bytes.Unblock_Control::2         6736                      
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized    11.328267                      
-system.ruby.network.routers3.msg_count.Request_Control::0          880                      
-system.ruby.network.routers3.msg_count.Request_Control::1          844                      
-system.ruby.network.routers3.msg_count.Response_Data::2         1686                      
-system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2           36                      
-system.ruby.network.routers3.msg_count.Writeback_Data::2         1628                      
-system.ruby.network.routers3.msg_count.Writeback_Control::0         1749                      
-system.ruby.network.routers3.msg_count.Writeback_Control::1         1509                      
-system.ruby.network.routers3.msg_count.Unblock_Control::2         1720                      
-system.ruby.network.routers3.msg_bytes.Request_Control::0         7040                      
-system.ruby.network.routers3.msg_bytes.Request_Control::1         6752                      
-system.ruby.network.routers3.msg_bytes.Response_Data::2       121392                      
-system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2         2592                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::2       117216                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0        13992                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::1        12072                      
-system.ruby.network.routers3.msg_bytes.Unblock_Control::2        13760                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Request_Control         5172                      
-system.ruby.network.msg_count.Response_Data         5058                      
-system.ruby.network.msg_count.ResponseL2hit_Data          107                      
-system.ruby.network.msg_count.Writeback_Data         4884                      
-system.ruby.network.msg_count.Writeback_Control         9774                      
-system.ruby.network.msg_count.Unblock_Control         5160                      
-system.ruby.network.msg_byte.Request_Control        41376                      
-system.ruby.network.msg_byte.Response_Data       364176                      
-system.ruby.network.msg_byte.ResponseL2hit_Data         7704                      
-system.ruby.network.msg_byte.Writeback_Data       351648                      
-system.ruby.network.msg_byte.Writeback_Control        78192                      
-system.ruby.network.msg_byte.Unblock_Control        41280                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        54211                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     8.094298                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::2          843                      
-system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2           35                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0          874                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2        60696                      
-system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2         2520                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0         6992                      
-system.ruby.network.routers0.throttle1.link_utilization     9.683459                      
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::0          880                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2          874                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0          875                      
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2          878                      
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0         7040                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2        62928                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0         7000                      
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2         7024                      
-system.ruby.network.routers1.throttle0.link_utilization    17.376547                      
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::0          880                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::2          843                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2          874                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0          875                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1          754                      
-system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2          878                      
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0         7040                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2        60696                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2        62928                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0         7000                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1         6032                      
-system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2         7024                      
-system.ruby.network.routers1.throttle1.link_utilization    16.611942                      
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::1          844                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::2          843                      
-system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2           36                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2          754                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0          874                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1          755                      
-system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2          842                      
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1         6752                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2        60696                      
-system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2         2592                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2        54288                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0         6992                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1         6040                      
-system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2         6736                      
-system.ruby.network.routers2.throttle0.link_utilization     8.510265                      
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::1          844                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2          754                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1          755                      
-system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2          842                      
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1         6752                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2        54288                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1         6040                      
-system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2         6736                      
-system.ruby.network.routers2.throttle1.link_utilization     7.693088                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::2          843                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1          754                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2        60696                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1         6032                      
-system.ruby.network.routers3.throttle0.link_utilization     8.097987                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::2          843                      
-system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2           36                      
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0          874                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2        60696                      
-system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2         2592                      
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0         6992                      
-system.ruby.network.routers3.throttle1.link_utilization    17.376547                      
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::0          880                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::2          843                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2          874                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0          875                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1          754                      
-system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2          878                      
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0         7040                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2        60696                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2        62928                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0         7000                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1         6032                      
-system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2         7024                      
-system.ruby.network.routers3.throttle2.link_utilization     8.510265                      
-system.ruby.network.routers3.throttle2.msg_count.Request_Control::1          844                      
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2          754                      
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1          755                      
-system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2          842                      
-system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1         6752                      
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2        54288                      
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1         6040                      
-system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2         6736                      
-system.ruby.LD.latency_hist_seqr::bucket_size          128                      
-system.ruby.LD.latency_hist_seqr::max_bucket         1279                      
-system.ruby.LD.latency_hist_seqr::samples           54                      
-system.ruby.LD.latency_hist_seqr::mean     874.574074                      
-system.ruby.LD.latency_hist_seqr::gmean    437.265598                      
-system.ruby.LD.latency_hist_seqr::stdev    350.325488                      
-system.ruby.LD.latency_hist_seqr         |           7     12.96%     12.96% |           0      0.00%     12.96% |           0      0.00%     12.96% |           0      0.00%     12.96% |           0      0.00%     12.96% |           0      0.00%     12.96% |           5      9.26%     22.22% |          29     53.70%     75.93% |           9     16.67%     92.59% |           4      7.41%    100.00%
-system.ruby.LD.latency_hist_seqr::total            54                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     8.691653                      
+system.ruby.network.routers0.msg_count.Request_Control::0          909                      
+system.ruby.network.routers0.msg_count.Response_Data::2          881                      
+system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2           28                      
+system.ruby.network.routers0.msg_count.Writeback_Data::2          904                      
+system.ruby.network.routers0.msg_count.Writeback_Control::0         1808                      
+system.ruby.network.routers0.msg_count.Unblock_Control::2          908                      
+system.ruby.network.routers0.msg_bytes.Request_Control::0         7272                      
+system.ruby.network.routers0.msg_bytes.Response_Data::2        63432                      
+system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2         2016                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::2        65088                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0        14464                      
+system.ruby.network.routers0.msg_bytes.Unblock_Control::2         7264                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized    16.709822                      
+system.ruby.network.routers1.msg_count.Request_Control::0          909                      
+system.ruby.network.routers1.msg_count.Request_Control::1          881                      
+system.ruby.network.routers1.msg_count.Response_Data::2         1762                      
+system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2           28                      
+system.ruby.network.routers1.msg_count.Writeback_Data::2         1695                      
+system.ruby.network.routers1.msg_count.Writeback_Control::0         1808                      
+system.ruby.network.routers1.msg_count.Writeback_Control::1         1582                      
+system.ruby.network.routers1.msg_count.Unblock_Control::2         1788                      
+system.ruby.network.routers1.msg_bytes.Request_Control::0         7272                      
+system.ruby.network.routers1.msg_bytes.Request_Control::1         7048                      
+system.ruby.network.routers1.msg_bytes.Response_Data::2       126864                      
+system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2         2016                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::2       122040                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0        14464                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::1        12656                      
+system.ruby.network.routers1.msg_bytes.Unblock_Control::2        14304                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     8.016861                      
+system.ruby.network.routers2.msg_count.Request_Control::1          881                      
+system.ruby.network.routers2.msg_count.Response_Data::2          881                      
+system.ruby.network.routers2.msg_count.Writeback_Data::2          791                      
+system.ruby.network.routers2.msg_count.Writeback_Control::1         1582                      
+system.ruby.network.routers2.msg_count.Unblock_Control::2          880                      
+system.ruby.network.routers2.msg_bytes.Request_Control::1         7048                      
+system.ruby.network.routers2.msg_bytes.Response_Data::2        63432                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::2        56952                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::1        12656                      
+system.ruby.network.routers2.msg_bytes.Unblock_Control::2         7040                      
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized    11.139881                      
+system.ruby.network.routers3.msg_count.Request_Control::0          909                      
+system.ruby.network.routers3.msg_count.Request_Control::1          881                      
+system.ruby.network.routers3.msg_count.Response_Data::2         1762                      
+system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2           28                      
+system.ruby.network.routers3.msg_count.Writeback_Data::2         1695                      
+system.ruby.network.routers3.msg_count.Writeback_Control::0         1808                      
+system.ruby.network.routers3.msg_count.Writeback_Control::1         1582                      
+system.ruby.network.routers3.msg_count.Unblock_Control::2         1788                      
+system.ruby.network.routers3.msg_bytes.Request_Control::0         7272                      
+system.ruby.network.routers3.msg_bytes.Request_Control::1         7048                      
+system.ruby.network.routers3.msg_bytes.Response_Data::2       126864                      
+system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2         2016                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::2       122040                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0        14464                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::1        12656                      
+system.ruby.network.routers3.msg_bytes.Unblock_Control::2        14304                      
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
+system.ruby.network.msg_count.Request_Control         5370                      
+system.ruby.network.msg_count.Response_Data         5286                      
+system.ruby.network.msg_count.ResponseL2hit_Data           84                      
+system.ruby.network.msg_count.Writeback_Data         5085                      
+system.ruby.network.msg_count.Writeback_Control        10170                      
+system.ruby.network.msg_count.Unblock_Control         5364                      
+system.ruby.network.msg_byte.Request_Control        42960                      
+system.ruby.network.msg_byte.Response_Data       380592                      
+system.ruby.network.msg_byte.ResponseL2hit_Data         6048                      
+system.ruby.network.msg_byte.Writeback_Data       366120                      
+system.ruby.network.msg_byte.Writeback_Control        81360                      
+system.ruby.network.msg_byte.Unblock_Control        42912                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        57351                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     7.917909                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::2          881                      
+system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2           28                      
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0          904                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2        63432                      
+system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2         2016                      
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0         7232                      
+system.ruby.network.routers0.throttle1.link_utilization     9.465397                      
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::0          909                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2          904                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0          904                      
+system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2          908                      
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0         7272                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2        65088                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0         7232                      
+system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2         7264                      
+system.ruby.network.routers1.throttle0.link_utilization    17.067706                      
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::0          909                      
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::2          881                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2          904                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0          904                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1          791                      
+system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2          908                      
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0         7272                      
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2        63432                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2        65088                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0         7232                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1         6328                      
+system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2         7264                      
+system.ruby.network.routers1.throttle1.link_utilization    16.351938                      
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::1          881                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::2          881                      
+system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2           28                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2          791                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0          904                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1          791                      
+system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2          880                      
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1         7048                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2        63432                      
+system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2         2016                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2        56952                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0         7232                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1         6328                      
+system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2         7040                      
+system.ruby.network.routers2.throttle0.link_utilization     8.431414                      
+system.ruby.network.routers2.throttle0.msg_count.Request_Control::1          881                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2          791                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1          791                      
+system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2          880                      
+system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1         7048                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2        56952                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1         6328                      
+system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2         7040                      
+system.ruby.network.routers2.throttle1.link_utilization     7.602309                      
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::2          881                      
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1          791                      
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2        63432                      
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1         6328                      
+system.ruby.network.routers3.throttle0.link_utilization     7.920524                      
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::2          881                      
+system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2           28                      
+system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0          904                      
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2        63432                      
+system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2         2016                      
+system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0         7232                      
+system.ruby.network.routers3.throttle1.link_utilization    17.067706                      
+system.ruby.network.routers3.throttle1.msg_count.Request_Control::0          909                      
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::2          881                      
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2          904                      
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0          904                      
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1          791                      
+system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2          908                      
+system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0         7272                      
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2        63432                      
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2        65088                      
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0         7232                      
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1         6328                      
+system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2         7264                      
+system.ruby.network.routers3.throttle2.link_utilization     8.431414                      
+system.ruby.network.routers3.throttle2.msg_count.Request_Control::1          881                      
+system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2          791                      
+system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1          791                      
+system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2          880                      
+system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1         7048                      
+system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2        56952                      
+system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1         6328                      
+system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2         7040                      
+system.ruby.LD.latency_hist_seqr::bucket_size          256                      
+system.ruby.LD.latency_hist_seqr::max_bucket         2559                      
+system.ruby.LD.latency_hist_seqr::samples           48                      
+system.ruby.LD.latency_hist_seqr::mean     885.875000                      
+system.ruby.LD.latency_hist_seqr::gmean    375.211617                      
+system.ruby.LD.latency_hist_seqr::stdev    381.714030                      
+system.ruby.LD.latency_hist_seqr         |           7     14.58%     14.58% |           0      0.00%     14.58% |           0      0.00%     14.58% |          21     43.75%     58.33% |          18     37.50%     95.83% |           2      4.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::total            48                      
 system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
-system.ruby.LD.hit_latency_hist_seqr::samples            6                      
+system.ruby.LD.hit_latency_hist_seqr::samples            7                      
 system.ruby.LD.hit_latency_hist_seqr::mean            1                      
 system.ruby.LD.hit_latency_hist_seqr::gmean            1                      
-system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |           6    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist_seqr::total            6                      
-system.ruby.LD.miss_latency_hist_seqr::bucket_size          128                      
-system.ruby.LD.miss_latency_hist_seqr::max_bucket         1279                      
-system.ruby.LD.miss_latency_hist_seqr::samples           48                      
-system.ruby.LD.miss_latency_hist_seqr::mean   983.770833                      
-system.ruby.LD.miss_latency_hist_seqr::gmean   935.057837                      
-system.ruby.LD.miss_latency_hist_seqr::stdev   169.695753                      
-system.ruby.LD.miss_latency_hist_seqr    |           1      2.08%      2.08% |           0      0.00%      2.08% |           0      0.00%      2.08% |           0      0.00%      2.08% |           0      0.00%      2.08% |           0      0.00%      2.08% |           5     10.42%     12.50% |          29     60.42%     72.92% |           9     18.75%     91.67% |           4      8.33%    100.00%
-system.ruby.LD.miss_latency_hist_seqr::total           48                      
+system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |           7    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist_seqr::total            7                      
+system.ruby.LD.miss_latency_hist_seqr::bucket_size          256                      
+system.ruby.LD.miss_latency_hist_seqr::max_bucket         2559                      
+system.ruby.LD.miss_latency_hist_seqr::samples           41                      
+system.ruby.LD.miss_latency_hist_seqr::mean  1036.951220                      
+system.ruby.LD.miss_latency_hist_seqr::gmean  1032.254678                      
+system.ruby.LD.miss_latency_hist_seqr::stdev   103.845065                      
+system.ruby.LD.miss_latency_hist_seqr    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          21     51.22%     51.22% |          18     43.90%     95.12% |           2      4.88%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::total           41                      
 system.ruby.ST.latency_hist_seqr::bucket_size          256                      
 system.ruby.ST.latency_hist_seqr::max_bucket         2559                      
-system.ruby.ST.latency_hist_seqr::samples          870                      
-system.ruby.ST.latency_hist_seqr::mean     919.120690                      
-system.ruby.ST.latency_hist_seqr::gmean    509.527867                      
-system.ruby.ST.latency_hist_seqr::stdev    331.108106                      
-system.ruby.ST.latency_hist_seqr         |          93     10.69%     10.69% |           6      0.69%     11.38% |           4      0.46%     11.84% |         354     40.69%     52.53% |         405     46.55%     99.08% |           8      0.92%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist_seqr::total           870                      
+system.ruby.ST.latency_hist_seqr::samples          899                      
+system.ruby.ST.latency_hist_seqr::mean     947.919911                      
+system.ruby.ST.latency_hist_seqr::gmean    545.272647                      
+system.ruby.ST.latency_hist_seqr::stdev    331.026961                      
+system.ruby.ST.latency_hist_seqr         |          89      9.90%      9.90% |           6      0.67%     10.57% |           4      0.44%     11.01% |         359     39.93%     50.95% |         394     43.83%     94.77% |          47      5.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::total           899                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
-system.ruby.ST.hit_latency_hist_seqr::samples           84                      
+system.ruby.ST.hit_latency_hist_seqr::samples           81                      
 system.ruby.ST.hit_latency_hist_seqr::mean            1                      
 system.ruby.ST.hit_latency_hist_seqr::gmean            1                      
-system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |          84    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist_seqr::total           84                      
+system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |          81    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist_seqr::total           81                      
 system.ruby.ST.miss_latency_hist_seqr::bucket_size          256                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket         2559                      
-system.ruby.ST.miss_latency_hist_seqr::samples          786                      
-system.ruby.ST.miss_latency_hist_seqr::mean  1017.240458                      
-system.ruby.ST.miss_latency_hist_seqr::gmean   991.935880                      
-system.ruby.ST.miss_latency_hist_seqr::stdev   146.709443                      
-system.ruby.ST.miss_latency_hist_seqr    |           9      1.15%      1.15% |           6      0.76%      1.91% |           4      0.51%      2.42% |         354     45.04%     47.46% |         405     51.53%     98.98% |           8      1.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist_seqr::total          786                      
-system.ruby.IFETCH.latency_hist_seqr::bucket_size           32                      
-system.ruby.IFETCH.latency_hist_seqr::max_bucket          319                      
-system.ruby.IFETCH.latency_hist_seqr::samples           46                      
-system.ruby.IFETCH.latency_hist_seqr::mean    70.195652                      
-system.ruby.IFETCH.latency_hist_seqr::gmean    54.673545                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    37.753363                      
-system.ruby.IFETCH.latency_hist_seqr     |           4      8.70%      8.70% |          14     30.43%     39.13% |          21     45.65%     84.78% |           1      2.17%     86.96% |           4      8.70%     95.65% |           2      4.35%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist_seqr::total           46                      
+system.ruby.ST.miss_latency_hist_seqr::samples          818                      
+system.ruby.ST.miss_latency_hist_seqr::mean  1041.685819                      
+system.ruby.ST.miss_latency_hist_seqr::gmean  1017.650590                      
+system.ruby.ST.miss_latency_hist_seqr::stdev   150.806361                      
+system.ruby.ST.miss_latency_hist_seqr    |           8      0.98%      0.98% |           6      0.73%      1.71% |           4      0.49%      2.20% |         359     43.89%     46.09% |         394     48.17%     94.25% |          47      5.75%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::total          818                      
+system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
+system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
+system.ruby.IFETCH.latency_hist_seqr::samples           52                      
+system.ruby.IFETCH.latency_hist_seqr::mean    86.442308                      
+system.ruby.IFETCH.latency_hist_seqr::gmean    62.630120                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    84.743769                      
+system.ruby.IFETCH.latency_hist_seqr     |          17     32.69%     32.69% |          31     59.62%     92.31% |           1      1.92%     94.23% |           0      0.00%     94.23% |           0      0.00%     94.23% |           2      3.85%     98.08% |           0      0.00%     98.08% |           1      1.92%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::total           52                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
 system.ruby.IFETCH.hit_latency_hist_seqr::samples            2                      
@@ -542,102 +552,98 @@ system.ruby.IFETCH.hit_latency_hist_seqr::mean            1
 system.ruby.IFETCH.hit_latency_hist_seqr::gmean            1                      
 system.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |           2    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.hit_latency_hist_seqr::total            2                      
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           32                      
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          319                      
-system.ruby.IFETCH.miss_latency_hist_seqr::samples           44                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    73.340909                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    65.579350                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    35.479403                      
-system.ruby.IFETCH.miss_latency_hist_seqr |           2      4.55%      4.55% |          14     31.82%     36.36% |          21     47.73%     84.09% |           1      2.27%     86.36% |           4      9.09%     95.45% |           2      4.55%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist_seqr::total           44                      
-system.ruby.Directory_Controller.GETX             761      0.00%      0.00%
-system.ruby.Directory_Controller.GETS              83      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX             755      0.00%      0.00%
-system.ruby.Directory_Controller.Unblock           77      0.00%      0.00%
-system.ruby.Directory_Controller.Last_Unblock            5      0.00%      0.00%
-system.ruby.Directory_Controller.Exclusive_Unblock          760      0.00%      0.00%
-system.ruby.Directory_Controller.Dirty_Writeback          754      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          843      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          754      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETX           691      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETS            78      0.00%      0.00%
-system.ruby.Directory_Controller.I.Memory_Ack          754      0.00%      0.00%
-system.ruby.Directory_Controller.S.GETX            70      0.00%      0.00%
-system.ruby.Directory_Controller.S.GETS             5      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX           755      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Unblock           77      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Memory_Data           78      0.00%      0.00%
-system.ruby.Directory_Controller.SS.Last_Unblock            5      0.00%      0.00%
-system.ruby.Directory_Controller.SS.Memory_Data            5      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Exclusive_Unblock          760      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Memory_Data          760      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Dirty_Writeback          754      0.00%      0.00%
-system.ruby.L1Cache_Controller.Load                56      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch              59      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store              880      0.00%      0.00%
-system.ruby.L1Cache_Controller.L1_Replacement        80012      0.00%      0.00%
-system.ruby.L1Cache_Controller.Data                83      0.00%      0.00%
-system.ruby.L1Cache_Controller.Exclusive_Data          795      0.00%      0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack_Data          874      0.00%      0.00%
-system.ruby.L1Cache_Controller.All_acks           786      0.00%      0.00%
-system.ruby.L1Cache_Controller.Use_Timeout          795      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Load              48      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Ifetch            44      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Store            788      0.00%      0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement           81      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Ifetch             2      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Store              1      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement            7      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement            5      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_W.Use_Timeout            9      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.Load              4      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.Store            68      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement          787      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_W.Load            2      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_W.Store           15      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement        30902      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout          786      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement        45597      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data          786      0.00%      0.00%
-system.ruby.L1Cache_Controller.OM.L1_Replacement           45      0.00%      0.00%
-system.ruby.L1Cache_Controller.OM.All_acks          786      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement         2588      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Data             83      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data            9      0.00%      0.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data           81      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI.Load              2      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI.Ifetch           13      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI.Store             8      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data          793      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETS             92      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX            788      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX            794      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only           81      0.00%      0.00%
-system.ruby.L2Cache_Controller.All_Acks           760      0.00%      0.00%
-system.ruby.L2Cache_Controller.Data               843      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA           81      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA          793      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack          754      0.00%      0.00%
-system.ruby.L2Cache_Controller.Unblock             82      0.00%      0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock          795      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement          836      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS           83      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX          761      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only           81      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX          794      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement           81      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS            9      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX           27      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement          755      0.00%      0.00%
-system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA           81      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA          793      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.Data            83      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.Unblock           82      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGM.Data           760      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMO.All_Acks          760      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock          760      0.00%      0.00%
-system.ruby.L2Cache_Controller.MM.Exclusive_Unblock           26      0.00%      0.00%
-system.ruby.L2Cache_Controller.OO.Exclusive_Unblock            9      0.00%      0.00%
-system.ruby.L2Cache_Controller.MI.Writeback_Ack          754      0.00%      0.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
+system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
+system.ruby.IFETCH.miss_latency_hist_seqr::samples           50                      
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    89.860000                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    73.901725                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    84.644758                      
+system.ruby.IFETCH.miss_latency_hist_seqr |          15     30.00%     30.00% |          31     62.00%     92.00% |           1      2.00%     94.00% |           0      0.00%     94.00% |           0      0.00%     94.00% |           2      4.00%     98.00% |           0      0.00%     98.00% |           1      2.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::total           50                      
+system.ruby.Directory_Controller.GETX             796      0.00%      0.00%
+system.ruby.Directory_Controller.GETS              85      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX             791      0.00%      0.00%
+system.ruby.Directory_Controller.Unblock           81      0.00%      0.00%
+system.ruby.Directory_Controller.Last_Unblock            3      0.00%      0.00%
+system.ruby.Directory_Controller.Exclusive_Unblock          796      0.00%      0.00%
+system.ruby.Directory_Controller.Dirty_Writeback          791      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          881      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          791      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX           735      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETS            82      0.00%      0.00%
+system.ruby.Directory_Controller.I.Memory_Ack          791      0.00%      0.00%
+system.ruby.Directory_Controller.S.GETX            61      0.00%      0.00%
+system.ruby.Directory_Controller.S.GETS             3      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX           791      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Unblock           81      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Memory_Data           82      0.00%      0.00%
+system.ruby.Directory_Controller.SS.Last_Unblock            3      0.00%      0.00%
+system.ruby.Directory_Controller.SS.Memory_Data            3      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock          796      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Memory_Data          796      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback          791      0.00%      0.00%
+system.ruby.L1Cache_Controller.Load                48      0.00%      0.00%
+system.ruby.L1Cache_Controller.Ifetch              64      0.00%      0.00%
+system.ruby.L1Cache_Controller.Store              905      0.00%      0.00%
+system.ruby.L1Cache_Controller.L1_Replacement        84079      0.00%      0.00%
+system.ruby.L1Cache_Controller.Data                85      0.00%      0.00%
+system.ruby.L1Cache_Controller.Exclusive_Data          824      0.00%      0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack_Data          904      0.00%      0.00%
+system.ruby.L1Cache_Controller.All_acks           818      0.00%      0.00%
+system.ruby.L1Cache_Controller.Use_Timeout          823      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Load              41      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Ifetch            50      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Store            818      0.00%      0.00%
+system.ruby.L1Cache_Controller.S.Ifetch             2      0.00%      0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement           82      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement            5      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_W.Use_Timeout            6      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.Load              7      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.Store            70      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement          817      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_W.Store           11      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement        31468      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout          817      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement        48874      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data          818      0.00%      0.00%
+system.ruby.L1Cache_Controller.OM.L1_Replacement          674      0.00%      0.00%
+system.ruby.L1Cache_Controller.OM.All_acks          818      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement         2159      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Data             85      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data            6      0.00%      0.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data           82      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI.Ifetch           12      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI.Store             6      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data          822      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETS             91      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX            818      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX            822      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only           82      0.00%      0.00%
+system.ruby.L2Cache_Controller.All_Acks           796      0.00%      0.00%
+system.ruby.L2Cache_Controller.Data               881      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA           82      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA          822      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack          791      0.00%      0.00%
+system.ruby.L2Cache_Controller.Unblock             84      0.00%      0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock          824      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement          873      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS           85      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX          796      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only           82      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX          822      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement           82      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX           22      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement          791      0.00%      0.00%
+system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA           82      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA          822      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.Data            85      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.Unblock           84      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGM.Data           796      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGMO.All_Acks          796      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock          796      0.00%      0.00%
+system.ruby.L2Cache_Controller.MM.Exclusive_Unblock           22      0.00%      0.00%
+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack          791      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
index 0143ed036..baeaaa8d5 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -54,8 +59,13 @@ check_flush=false
 checks_to_complete=100
 clk_domain=system.clk_domain
 deadlock_threshold=50000
+default_p_state=UNDEFINED
 eventq_index=0
 num_cpus=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 system=system
 wakeup_frequency=10
 cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
@@ -70,27 +80,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -102,6 +112,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -109,12 +120,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -136,9 +152,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -152,12 +168,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=true
 
 [system.ruby.clk_domain]
@@ -174,6 +195,7 @@ children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persiste
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=5
 distributed_persistent=true
@@ -183,8 +205,12 @@ eventq_index=0
 fixed_timeout_latency=100
 l2_select_num_bits=0
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir
 persistentToDir=system.ruby.dir_cntrl0.persistentToDir
+power_model=Null
 recycle_latency=10
 reissue_wakeup_latency=10
 requestFromDir=system.ruby.dir_cntrl0.requestFromDir
@@ -286,6 +312,7 @@ N_tokens=2
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 dynamic_timeout_enabled=true
 eventq_index=0
 fixed_timeout_latency=300
@@ -295,8 +322,12 @@ l2_select_num_bits=0
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 no_mig_atomic=true
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache
 persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache
+power_model=Null
 recycle_latency=10
 reissue_wakeup_latency=10
 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
@@ -422,17 +453,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.L1Dcache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.L1Icache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=0
 slave=system.cpu.cpuInstDataPort[0]
@@ -449,12 +485,17 @@ N_tokens=2
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 filtering_enabled=true
 l2_request_latency=5
 l2_response_latency=5
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache
+power_model=Null
 recycle_latency=10
 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
 responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
@@ -551,18 +592,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
 netifs=
 number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
 ruby_system=system.ruby
 topology=Crossbar
@@ -851,42 +897,342 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers40]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers41]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers42]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers43]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers44]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers45]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers46]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers47]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers48]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers49]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers50]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers51]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers52]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers53]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers54]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers55]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers56]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers57]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers58]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers59]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers60]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers61]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers62]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers63]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers64]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers65]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers66]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers67]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers68]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers69]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers70]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers71]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
 weight=1
 
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
 eventq_index=0
 latency=1
 link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 system.ruby.network.routers0.port_buffers18 system.ruby.network.routers0.port_buffers19 system.ruby.network.routers0.port_buffers20 system.ruby.network.routers0.port_buffers21 system.ruby.network.routers0.port_buffers22 system.ruby.network.routers0.port_buffers23
+power_model=Null
 router_id=0
 virt_nets=6
 
@@ -1062,8 +1408,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 system.ruby.network.routers1.port_buffers18 system.ruby.network.routers1.port_buffers19 system.ruby.network.routers1.port_buffers20 system.ruby.network.routers1.port_buffers21 system.ruby.network.routers1.port_buffers22 system.ruby.network.routers1.port_buffers23
+power_model=Null
 router_id=1
 virt_nets=6
 
@@ -1239,8 +1591,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23
+power_model=Null
 router_id=2
 virt_nets=6
 
@@ -1416,8 +1774,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35
+power_model=Null
 router_id=3
 virt_nets=6
 
@@ -1676,9 +2040,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
index c2086c0ba..cee0dfc57 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
@@ -4,7 +4,5 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
index 583f49075..135163955 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
+Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:12:23
-gem5 started Jan 21 2016 14:12:59
-gem5 executing on zizzer, pid 55402
-command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
+gem5 compiled Oct 13 2016 20:33:48
+gem5 started Oct 13 2016 20:34:17
+gem5 executing on e108600-lin, pid 27528
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 50141 because Ruby Tester completed
+Exiting @ tick 53801 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
index 22bd0b2f6..e0aa11056 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
@@ -1,45 +1,45 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000050                       # Number of seconds simulated
-sim_ticks                                       50141                       # Number of ticks simulated
-final_tick                                      50141                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000054                       # Number of seconds simulated
+sim_ticks                                       53801                       # Number of ticks simulated
+final_tick                                      53801                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 922495                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 453168                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                                 784976                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 409916                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0        50624                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total              50624                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0        46016                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total           46016                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0          791                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total                 791                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0          719                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total                719                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0   1009632835                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            1009632835                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    917731996                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            917731996                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   1927364831                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1927364831                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                         791                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                        719                       # Number of write requests accepted
-system.mem_ctrls.readBursts                       791                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                      719                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  42944                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                    7680                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   39296                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                   50624                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys                46016                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    120                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                    81                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0        52672                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total              52672                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0        47552                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total           47552                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0          823                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total                 823                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0          743                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total                743                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0    979015260                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total             979015260                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0    883849743                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total            883849743                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   1862865003                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           1862865003                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                         824                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                        743                       # Number of write requests accepted
+system.mem_ctrls.readBursts                       824                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                      743                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM                  43776                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                    8960                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   40320                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                   52736                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys                47552                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                    140                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                    90                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0               208                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1               221                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2               189                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3                53                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0               217                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1               193                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2               224                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3                50                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 0                       # Per bank write bursts
@@ -52,10 +52,10 @@ system.mem_ctrls.perBankRdBursts::12                0                       # Pe
 system.mem_ctrls.perBankRdBursts::13                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0               189                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1               195                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2               180                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3                50                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0               196                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1               186                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2               201                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3                47                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::5                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
@@ -70,24 +70,24 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         50084                       # Total gap between requests
+system.mem_ctrls.totGap                         53772                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                   791                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                   824                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6                  719                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     557                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                     111                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2                       3                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6                  743                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                     527                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                     156                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2                       1                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
@@ -132,24 +132,24 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      3                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      4                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::16                      4                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::17                     20                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::18                     40                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     43                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     43                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                     44                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::21                     41                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     40                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     41                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                     40                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     39                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     38                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     38                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     41                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     39                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                     41                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                     40                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                     41                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                     45                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                     39                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     39                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                     39                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     39                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                     39                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
@@ -181,543 +181,531 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples           89                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    910.382022                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   810.808230                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   274.216052                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127            2      2.25%      2.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255            5      5.62%      7.87% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383            2      2.25%     10.11% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511            1      1.12%     11.24% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639            1      1.12%     12.36% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            2      2.25%     14.61% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            1      1.12%     15.73% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            3      3.37%     19.10% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           72     80.90%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total           89                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples           38                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      17.394737                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     17.106045                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      3.831163                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15             8     21.05%     21.05% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            18     47.37%     68.42% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             7     18.42%     86.84% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21             3      7.89%     94.74% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23             1      2.63%     97.37% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-37             1      2.63%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total            38                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples           38                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.157895                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.145372                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.678883                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               36     94.74%     94.74% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                2      5.26%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total            38                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         8848                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   21597                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       3355                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        13.19                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples           90                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    916.622222                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   830.573922                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   254.887972                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127            1      1.11%      1.11% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255            5      5.56%      6.67% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383            1      1.11%      7.78% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511            2      2.22%     10.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            3      3.33%     13.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            4      4.44%     17.78% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            4      4.44%     22.22% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           70     77.78%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total           90                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples           39                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      17.282051                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     16.989006                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      3.886202                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13             1      2.56%      2.56% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15             8     20.51%     23.08% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17            18     46.15%     69.23% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19             8     20.51%     89.74% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21             2      5.13%     94.87% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::22-23             1      2.56%     97.44% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::38-39             1      2.56%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total            39                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples           39                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.153846                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.145622                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.539906                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               36     92.31%     92.31% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                3      7.69%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total            39                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                        11889                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   24885                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       3420                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        17.38                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   32.19                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       856.46                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       783.71                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   1009.63                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    917.73                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   36.38                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                       813.67                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                       749.43                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                    980.20                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                    883.85                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                        12.81                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     6.69                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    6.12                       # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen                       1.30                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      25.17                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      582                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     610                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 86.74                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                95.61                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         33.17                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    91.06                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   642600                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   357000                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 7775040                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                6003072                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             32001624                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy               114000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               49944696                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower           1063.196015                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE           22                       # Time in different power states
+system.mem_ctrls.busUtil                        12.21                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                     6.36                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    5.85                       # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen                       1.38                       # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      25.30                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      599                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     622                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 87.57                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                95.25                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         34.32                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    91.32                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   664020                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   347760                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 7814016                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                5261760                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         3687840.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             10048872                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy                77568                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy        14391360                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy             768                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               42293964                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            786.118548                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                31562                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE           34                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF          1560                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         45408                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            2                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         20645                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        31560                       # Time in different power states
 system.mem_ctrls_1.actEnergy                        0                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_1.preEnergy                        0                       # Energy for precharge commands per rank (pJ)
 system.mem_ctrls_1.readEnergy                       0                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy              1009584                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy             27291600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               31352544                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            667.615178                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE        45416                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          1560                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.refreshEnergy         1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy               224352                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              3002880                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy               0                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy         2889984                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy          9111120                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               16457616                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            305.897957                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                 7526                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE         7786                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF           526                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF        37963                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         7526                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT             0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
 system.ruby.outstanding_req_hist_seqr::bucket_size            2                      
 system.ruby.outstanding_req_hist_seqr::max_bucket           19                      
-system.ruby.outstanding_req_hist_seqr::samples          961                      
-system.ruby.outstanding_req_hist_seqr::mean    15.762747                      
-system.ruby.outstanding_req_hist_seqr::gmean    15.654325                      
-system.ruby.outstanding_req_hist_seqr::stdev     1.209298                      
-system.ruby.outstanding_req_hist_seqr    |           1      0.10%      0.10% |           2      0.21%      0.31% |           2      0.21%      0.52% |           2      0.21%      0.73% |           4      0.42%      1.14% |           2      0.21%      1.35% |           3      0.31%      1.66% |          91      9.47%     11.13% |         854     88.87%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist_seqr::total          961                      
+system.ruby.outstanding_req_hist_seqr::samples          973                      
+system.ruby.outstanding_req_hist_seqr::mean    15.744090                      
+system.ruby.outstanding_req_hist_seqr::gmean    15.636746                      
+system.ruby.outstanding_req_hist_seqr::stdev     1.206668                      
+system.ruby.outstanding_req_hist_seqr    |           1      0.10%      0.10% |           2      0.21%      0.31% |           2      0.21%      0.51% |           2      0.21%      0.72% |           4      0.41%      1.13% |           2      0.21%      1.34% |           3      0.31%      1.64% |         112     11.51%     13.16% |         845     86.84%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist_seqr::total          973                      
 system.ruby.latency_hist_seqr::bucket_size          256                      
 system.ruby.latency_hist_seqr::max_bucket         2559                      
-system.ruby.latency_hist_seqr::samples            946                      
-system.ruby.latency_hist_seqr::mean        831.747357                      
-system.ruby.latency_hist_seqr::gmean       353.331206                      
-system.ruby.latency_hist_seqr::stdev       440.661399                      
-system.ruby.latency_hist_seqr            |         208     21.99%     21.99% |           7      0.74%     22.73% |           5      0.53%     23.26% |         262     27.70%     50.95% |         409     43.23%     94.19% |          55      5.81%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist_seqr::total              946                      
+system.ruby.latency_hist_seqr::samples            958                      
+system.ruby.latency_hist_seqr::mean        879.328810                      
+system.ruby.latency_hist_seqr::gmean       422.320646                      
+system.ruby.latency_hist_seqr::stdev       422.809847                      
+system.ruby.latency_hist_seqr            |         182     19.00%     19.00% |           6      0.63%     19.62% |           4      0.42%     20.04% |         214     22.34%     42.38% |         516     53.86%     96.24% |          36      3.76%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::total              958                      
 system.ruby.hit_latency_hist_seqr::bucket_size          256                      
 system.ruby.hit_latency_hist_seqr::max_bucket         2559                      
-system.ruby.hit_latency_hist_seqr::samples          156                      
-system.ruby.hit_latency_hist_seqr::mean    161.115385                      
-system.ruby.hit_latency_hist_seqr::gmean     5.208817                      
-system.ruby.hit_latency_hist_seqr::stdev   361.858143                      
-system.ruby.hit_latency_hist_seqr        |         132     84.62%     84.62% |           0      0.00%     84.62% |           0      0.00%     84.62% |          17     10.90%     95.51% |           6      3.85%     99.36% |           1      0.64%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist_seqr::total          156                      
+system.ruby.hit_latency_hist_seqr::samples          136                      
+system.ruby.hit_latency_hist_seqr::mean    190.117647                      
+system.ruby.hit_latency_hist_seqr::gmean     5.669159                      
+system.ruby.hit_latency_hist_seqr::stdev   399.173351                      
+system.ruby.hit_latency_hist_seqr        |         112     82.35%     82.35% |           0      0.00%     82.35% |           0      0.00%     82.35% |          10      7.35%     89.71% |          13      9.56%     99.26% |           1      0.74%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist_seqr::total          136                      
 system.ruby.miss_latency_hist_seqr::bucket_size          256                      
 system.ruby.miss_latency_hist_seqr::max_bucket         2559                      
-system.ruby.miss_latency_hist_seqr::samples          790                      
-system.ruby.miss_latency_hist_seqr::mean   964.175949                      
-system.ruby.miss_latency_hist_seqr::gmean   812.519909                      
-system.ruby.miss_latency_hist_seqr::stdev   316.811320                      
-system.ruby.miss_latency_hist_seqr       |          76      9.62%      9.62% |           7      0.89%     10.51% |           5      0.63%     11.14% |         245     31.01%     42.15% |         403     51.01%     93.16% |          54      6.84%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist_seqr::total          790                      
-system.ruby.Directory.incomplete_times_seqr          790                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.L1Dcache.demand_hits          105                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          788                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          893                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits            1                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses           54                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses           55                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            6                       # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           74                       # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            6                       # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
-system.ruby.l2_cntrl0.L2cache.demand_hits           48                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses          793                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses          841                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
+system.ruby.miss_latency_hist_seqr::samples          822                      
+system.ruby.miss_latency_hist_seqr::mean   993.358881                      
+system.ruby.miss_latency_hist_seqr::gmean   861.758158                      
+system.ruby.miss_latency_hist_seqr::stdev   300.791358                      
+system.ruby.miss_latency_hist_seqr       |          70      8.52%      8.52% |           6      0.73%      9.25% |           4      0.49%      9.73% |         204     24.82%     34.55% |         503     61.19%     95.74% |          35      4.26%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::total          822                      
+system.ruby.Directory.incomplete_times_seqr          822                      
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.L1Dcache.demand_hits           92                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          820                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          912                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses           48                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses           48                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            4                       # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           91                       # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            7                       # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.L2cache.demand_hits           43                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses          825                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses          868                       # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     8.090684                      
-system.ruby.network.routers0.msg_count.Request_Control::1          841                      
-system.ruby.network.routers0.msg_count.Response_Data::4          790                      
-system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4           50                      
-system.ruby.network.routers0.msg_count.Response_Control::4            1                      
-system.ruby.network.routers0.msg_count.Writeback_Data::4          862                      
-system.ruby.network.routers0.msg_count.Persistent_Control::3           68                      
-system.ruby.network.routers0.msg_bytes.Request_Control::1         6728                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4        56880                      
-system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4         3600                      
-system.ruby.network.routers0.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::4        62064                      
-system.ruby.network.routers0.msg_bytes.Persistent_Control::3          544                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     8.057777                      
-system.ruby.network.routers1.msg_count.Request_Control::1          841                      
-system.ruby.network.routers1.msg_count.Request_Control::2          793                      
-system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4           50                      
-system.ruby.network.routers1.msg_count.Response_Control::4            1                      
-system.ruby.network.routers1.msg_count.Writeback_Data::4         1553                      
-system.ruby.network.routers1.msg_count.Writeback_Control::4           65                      
-system.ruby.network.routers1.msg_count.Persistent_Control::3           34                      
-system.ruby.network.routers1.msg_bytes.Request_Control::1         6728                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         6344                      
-system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4         3600                      
-system.ruby.network.routers1.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::4       111816                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::4          520                      
-system.ruby.network.routers1.msg_bytes.Persistent_Control::3          272                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     7.216150                      
-system.ruby.network.routers2.msg_count.Request_Control::2          793                      
-system.ruby.network.routers2.msg_count.Response_Data::4          790                      
-system.ruby.network.routers2.msg_count.Writeback_Data::4          719                      
-system.ruby.network.routers2.msg_count.Writeback_Control::4           65                      
-system.ruby.network.routers2.msg_count.Persistent_Control::3           34                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2         6344                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4        56880                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::4        51768                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::4          520                      
-system.ruby.network.routers2.msg_bytes.Persistent_Control::3          272                      
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized     7.788370                      
-system.ruby.network.routers3.msg_count.Request_Control::1          841                      
-system.ruby.network.routers3.msg_count.Request_Control::2          793                      
-system.ruby.network.routers3.msg_count.Response_Data::4          790                      
-system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4           50                      
-system.ruby.network.routers3.msg_count.Response_Control::4            1                      
-system.ruby.network.routers3.msg_count.Writeback_Data::4         1567                      
-system.ruby.network.routers3.msg_count.Writeback_Control::4           65                      
-system.ruby.network.routers3.msg_count.Persistent_Control::3           68                      
-system.ruby.network.routers3.msg_bytes.Request_Control::1         6728                      
-system.ruby.network.routers3.msg_bytes.Request_Control::2         6344                      
-system.ruby.network.routers3.msg_bytes.Response_Data::4        56880                      
-system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4         3600                      
-system.ruby.network.routers3.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::4       112824                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::4          520                      
-system.ruby.network.routers3.msg_bytes.Persistent_Control::3          544                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Request_Control         4902                      
-system.ruby.network.msg_count.Response_Data         2370                      
-system.ruby.network.msg_count.ResponseL2hit_Data          150                      
-system.ruby.network.msg_count.Response_Control            3                      
-system.ruby.network.msg_count.Writeback_Data         4701                      
-system.ruby.network.msg_count.Writeback_Control          195                      
-system.ruby.network.msg_count.Persistent_Control          204                      
-system.ruby.network.msg_byte.Request_Control        39216                      
-system.ruby.network.msg_byte.Response_Data       170640                      
-system.ruby.network.msg_byte.ResponseL2hit_Data        10800                      
-system.ruby.network.msg_byte.Response_Control           24                      
-system.ruby.network.msg_byte.Writeback_Data       338472                      
-system.ruby.network.msg_byte.Writeback_Control         1560                      
-system.ruby.network.msg_byte.Persistent_Control         1632                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        50141                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     7.698291                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          790                      
-system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4           50                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::4            1                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4           14                      
-system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3           34                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        56880                      
-system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4         3600                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4         1008                      
-system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3          272                      
-system.ruby.network.routers0.throttle1.link_utilization     8.483078                      
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::1          841                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4          848                      
-system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3           34                      
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1         6728                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4        61056                      
-system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3          272                      
-system.ruby.network.routers1.throttle0.link_utilization     8.357432                      
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::1          841                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4          834                      
-system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3           34                      
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1         6728                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4        60048                      
-system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3          272                      
-system.ruby.network.routers1.throttle1.link_utilization     7.758122                      
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::2          793                      
-system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4           50                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::4            1                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4          719                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4           65                      
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2         6344                      
-system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4         3600                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4        51768                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4          520                      
-system.ruby.network.routers2.throttle0.link_utilization     7.342295                      
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::2          793                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4          719                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4           65                      
-system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3           34                      
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2         6344                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4        51768                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4          520                      
-system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3          272                      
-system.ruby.network.routers2.throttle1.link_utilization     7.090006                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::4          790                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4        56880                      
-system.ruby.network.routers3.throttle0.link_utilization     7.665384                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::4          790                      
-system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4           50                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::4            1                      
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Data::4           14                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4        56880                      
-system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4         3600                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4         1008                      
-system.ruby.network.routers3.throttle1.link_utilization     8.357432                      
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::1          841                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4          834                      
-system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3           34                      
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1         6728                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4        60048                      
-system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3          272                      
-system.ruby.network.routers3.throttle2.link_utilization     7.342295                      
-system.ruby.network.routers3.throttle2.msg_count.Request_Control::2          793                      
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4          719                      
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4           65                      
-system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3           34                      
-system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2         6344                      
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4        51768                      
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4          520                      
-system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3          272                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized     7.774948                      
+system.ruby.network.routers0.msg_count.Request_Control::1          868                      
+system.ruby.network.routers0.msg_count.Response_Data::4          823                      
+system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4           44                      
+system.ruby.network.routers0.msg_count.Writeback_Data::4          888                      
+system.ruby.network.routers0.msg_count.Persistent_Control::3           76                      
+system.ruby.network.routers0.msg_bytes.Request_Control::1         6944                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4        59256                      
+system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4         3168                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::4        63936                      
+system.ruby.network.routers0.msg_bytes.Persistent_Control::3          608                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized     7.735451                      
+system.ruby.network.routers1.msg_count.Request_Control::1          868                      
+system.ruby.network.routers1.msg_count.Request_Control::2          825                      
+system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4           44                      
+system.ruby.network.routers1.msg_count.Writeback_Data::4         1605                      
+system.ruby.network.routers1.msg_count.Writeback_Control::4           75                      
+system.ruby.network.routers1.msg_count.Persistent_Control::3           38                      
+system.ruby.network.routers1.msg_bytes.Request_Control::1         6944                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         6600                      
+system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4         3168                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::4       115560                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::4          600                      
+system.ruby.network.routers1.msg_bytes.Persistent_Control::3          304                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized     6.985000                      
+system.ruby.network.routers2.msg_count.Request_Control::2          825                      
+system.ruby.network.routers2.msg_count.Response_Data::4          823                      
+system.ruby.network.routers2.msg_count.Writeback_Data::4          743                      
+system.ruby.network.routers2.msg_count.Writeback_Control::4           75                      
+system.ruby.network.routers2.msg_count.Persistent_Control::3           38                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2         6600                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4        59256                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::4        53496                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::4          600                      
+system.ruby.network.routers2.msg_bytes.Persistent_Control::3          304                      
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized     7.498621                      
+system.ruby.network.routers3.msg_count.Request_Control::1          868                      
+system.ruby.network.routers3.msg_count.Request_Control::2          825                      
+system.ruby.network.routers3.msg_count.Response_Data::4          823                      
+system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4           44                      
+system.ruby.network.routers3.msg_count.Writeback_Data::4         1618                      
+system.ruby.network.routers3.msg_count.Writeback_Control::4           75                      
+system.ruby.network.routers3.msg_count.Persistent_Control::3           76                      
+system.ruby.network.routers3.msg_bytes.Request_Control::1         6944                      
+system.ruby.network.routers3.msg_bytes.Request_Control::2         6600                      
+system.ruby.network.routers3.msg_bytes.Response_Data::4        59256                      
+system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4         3168                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::4       116496                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::4          600                      
+system.ruby.network.routers3.msg_bytes.Persistent_Control::3          608                      
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
+system.ruby.network.msg_count.Request_Control         5079                      
+system.ruby.network.msg_count.Response_Data         2469                      
+system.ruby.network.msg_count.ResponseL2hit_Data          132                      
+system.ruby.network.msg_count.Writeback_Data         4854                      
+system.ruby.network.msg_count.Writeback_Control          225                      
+system.ruby.network.msg_count.Persistent_Control          228                      
+system.ruby.network.msg_byte.Request_Control        40632                      
+system.ruby.network.msg_byte.Response_Data       177768                      
+system.ruby.network.msg_byte.ResponseL2hit_Data         9504                      
+system.ruby.network.msg_byte.Writeback_Data       349488                      
+system.ruby.network.msg_byte.Writeback_Control         1800                      
+system.ruby.network.msg_byte.Persistent_Control         1824                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        53801                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization     7.389268                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          823                      
+system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4           44                      
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4           13                      
+system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3           38                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        59256                      
+system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4         3168                      
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4          936                      
+system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3          304                      
+system.ruby.network.routers0.throttle1.link_utilization     8.160629                      
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::1          868                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4          875                      
+system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3           38                      
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1         6944                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4        63000                      
+system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3          304                      
+system.ruby.network.routers1.throttle0.link_utilization     8.051895                      
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::1          868                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4          862                      
+system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3           38                      
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1         6944                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4        62064                      
+system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3          304                      
+system.ruby.network.routers1.throttle1.link_utilization     7.419007                      
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::2          825                      
+system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4           44                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4          743                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4           75                      
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2         6600                      
+system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4         3168                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4        53496                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4          600                      
+system.ruby.network.routers2.throttle0.link_utilization     7.086300                      
+system.ruby.network.routers2.throttle0.msg_count.Request_Control::2          825                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4          743                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4           75                      
+system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3           38                      
+system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2         6600                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4        53496                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4          600                      
+system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3          304                      
+system.ruby.network.routers2.throttle1.link_utilization     6.883701                      
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::4          823                      
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4        59256                      
+system.ruby.network.routers3.throttle0.link_utilization     7.357670                      
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::4          823                      
+system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4           44                      
+system.ruby.network.routers3.throttle0.msg_count.Writeback_Data::4           13                      
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4        59256                      
+system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4         3168                      
+system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4          936                      
+system.ruby.network.routers3.throttle1.link_utilization     8.051895                      
+system.ruby.network.routers3.throttle1.msg_count.Request_Control::1          868                      
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4          862                      
+system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3           38                      
+system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1         6944                      
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4        62064                      
+system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3          304                      
+system.ruby.network.routers3.throttle2.link_utilization     7.086300                      
+system.ruby.network.routers3.throttle2.msg_count.Request_Control::2          825                      
+system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4          743                      
+system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4           75                      
+system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3           38                      
+system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2         6600                      
+system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4        53496                      
+system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4          600                      
+system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3          304                      
 system.ruby.LD.latency_hist_seqr::bucket_size          256                      
 system.ruby.LD.latency_hist_seqr::max_bucket         2559                      
-system.ruby.LD.latency_hist_seqr::samples           46                      
-system.ruby.LD.latency_hist_seqr::mean     817.543478                      
-system.ruby.LD.latency_hist_seqr::gmean    284.544942                      
-system.ruby.LD.latency_hist_seqr::stdev    462.655942                      
-system.ruby.LD.latency_hist_seqr         |          11     23.91%     23.91% |           0      0.00%     23.91% |           0      0.00%     23.91% |          15     32.61%     56.52% |          16     34.78%     91.30% |           4      8.70%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist_seqr::total            46                      
-system.ruby.LD.hit_latency_hist_seqr::bucket_size          128                      
-system.ruby.LD.hit_latency_hist_seqr::max_bucket         1279                      
-system.ruby.LD.hit_latency_hist_seqr::samples           10                      
-system.ruby.LD.hit_latency_hist_seqr::mean          101                      
-system.ruby.LD.hit_latency_hist_seqr::gmean     3.750098                      
-system.ruby.LD.hit_latency_hist_seqr::stdev   300.217329                      
-system.ruby.LD.hit_latency_hist_seqr     |           9     90.00%     90.00% |           0      0.00%     90.00% |           0      0.00%     90.00% |           0      0.00%     90.00% |           0      0.00%     90.00% |           0      0.00%     90.00% |           0      0.00%     90.00% |           1     10.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist_seqr::total           10                      
+system.ruby.LD.latency_hist_seqr::samples           53                      
+system.ruby.LD.latency_hist_seqr::mean     911.113208                      
+system.ruby.LD.latency_hist_seqr::gmean    398.266031                      
+system.ruby.LD.latency_hist_seqr::stdev    447.197842                      
+system.ruby.LD.latency_hist_seqr         |          10     18.87%     18.87% |           0      0.00%     18.87% |           0      0.00%     18.87% |          10     18.87%     37.74% |          28     52.83%     90.57% |           5      9.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::total            53                      
+system.ruby.LD.hit_latency_hist_seqr::bucket_size          256                      
+system.ruby.LD.hit_latency_hist_seqr::max_bucket         2559                      
+system.ruby.LD.hit_latency_hist_seqr::samples            9                      
+system.ruby.LD.hit_latency_hist_seqr::mean          152                      
+system.ruby.LD.hit_latency_hist_seqr::gmean     4.500121                      
+system.ruby.LD.hit_latency_hist_seqr::stdev   435.863798                      
+system.ruby.LD.hit_latency_hist_seqr     |           8     88.89%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           1     11.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist_seqr::total            9                      
 system.ruby.LD.miss_latency_hist_seqr::bucket_size          256                      
 system.ruby.LD.miss_latency_hist_seqr::max_bucket         2559                      
-system.ruby.LD.miss_latency_hist_seqr::samples           36                      
-system.ruby.LD.miss_latency_hist_seqr::mean  1016.583333                      
-system.ruby.LD.miss_latency_hist_seqr::gmean   947.115995                      
-system.ruby.LD.miss_latency_hist_seqr::stdev   254.139824                      
-system.ruby.LD.miss_latency_hist_seqr    |           2      5.56%      5.56% |           0      0.00%      5.56% |           0      0.00%      5.56% |          14     38.89%     44.44% |          16     44.44%     88.89% |           4     11.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist_seqr::total           36                      
+system.ruby.LD.miss_latency_hist_seqr::samples           44                      
+system.ruby.LD.miss_latency_hist_seqr::mean  1066.386364                      
+system.ruby.LD.miss_latency_hist_seqr::gmean   996.352114                      
+system.ruby.LD.miss_latency_hist_seqr::stdev   247.421326                      
+system.ruby.LD.miss_latency_hist_seqr    |           2      4.55%      4.55% |           0      0.00%      4.55% |           0      0.00%      4.55% |          10     22.73%     27.27% |          28     63.64%     90.91% |           4      9.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::total           44                      
 system.ruby.ST.latency_hist_seqr::bucket_size          256                      
 system.ruby.ST.latency_hist_seqr::max_bucket         2559                      
-system.ruby.ST.latency_hist_seqr::samples          846                      
-system.ruby.ST.latency_hist_seqr::mean     881.170213                      
-system.ruby.ST.latency_hist_seqr::gmean    402.465808                      
-system.ruby.ST.latency_hist_seqr::stdev    407.456674                      
-system.ruby.ST.latency_hist_seqr         |         144     17.02%     17.02% |           6      0.71%     17.73% |           5      0.59%     18.32% |         247     29.20%     47.52% |         393     46.45%     93.97% |          51      6.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist_seqr::total           846                      
-system.ruby.ST.hit_latency_hist_seqr::bucket_size          256                      
-system.ruby.ST.hit_latency_hist_seqr::max_bucket         2559                      
-system.ruby.ST.hit_latency_hist_seqr::samples          138                      
-system.ruby.ST.hit_latency_hist_seqr::mean   173.615942                      
-system.ruby.ST.hit_latency_hist_seqr::gmean     5.002563                      
-system.ruby.ST.hit_latency_hist_seqr::stdev   375.029660                      
-system.ruby.ST.hit_latency_hist_seqr     |         115     83.33%     83.33% |           0      0.00%     83.33% |           0      0.00%     83.33% |          16     11.59%     94.93% |           6      4.35%     99.28% |           1      0.72%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist_seqr::total          138                      
+system.ruby.ST.latency_hist_seqr::samples          858                      
+system.ruby.ST.latency_hist_seqr::mean     921.592075                      
+system.ruby.ST.latency_hist_seqr::gmean    471.652464                      
+system.ruby.ST.latency_hist_seqr::stdev    386.984382                      
+system.ruby.ST.latency_hist_seqr         |         126     14.69%     14.69% |           5      0.58%     15.27% |           4      0.47%     15.73% |         204     23.78%     39.51% |         488     56.88%     96.39% |          31      3.61%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::total           858                      
+system.ruby.ST.hit_latency_hist_seqr::bucket_size          128                      
+system.ruby.ST.hit_latency_hist_seqr::max_bucket         1279                      
+system.ruby.ST.hit_latency_hist_seqr::samples          120                      
+system.ruby.ST.hit_latency_hist_seqr::mean   202.641667                      
+system.ruby.ST.hit_latency_hist_seqr::gmean     5.297334                      
+system.ruby.ST.hit_latency_hist_seqr::stdev   407.564189                      
+system.ruby.ST.hit_latency_hist_seqr     |          97     80.83%     80.83% |           0      0.00%     80.83% |           0      0.00%     80.83% |           0      0.00%     80.83% |           0      0.00%     80.83% |           0      0.00%     80.83% |           0      0.00%     80.83% |          10      8.33%     89.17% |          12     10.00%     99.17% |           1      0.83%    100.00%
+system.ruby.ST.hit_latency_hist_seqr::total          120                      
 system.ruby.ST.miss_latency_hist_seqr::bucket_size          256                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket         2559                      
-system.ruby.ST.miss_latency_hist_seqr::samples          708                      
-system.ruby.ST.miss_latency_hist_seqr::mean  1019.083333                      
-system.ruby.ST.miss_latency_hist_seqr::gmean   946.557722                      
-system.ruby.ST.miss_latency_hist_seqr::stdev   233.252272                      
-system.ruby.ST.miss_latency_hist_seqr    |          29      4.10%      4.10% |           6      0.85%      4.94% |           5      0.71%      5.65% |         231     32.63%     38.28% |         387     54.66%     92.94% |          50      7.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist_seqr::total          708                      
+system.ruby.ST.miss_latency_hist_seqr::samples          738                      
+system.ruby.ST.miss_latency_hist_seqr::mean  1038.494580                      
+system.ruby.ST.miss_latency_hist_seqr::gmean   978.643470                      
+system.ruby.ST.miss_latency_hist_seqr::stdev   222.427518                      
+system.ruby.ST.miss_latency_hist_seqr    |          29      3.93%      3.93% |           5      0.68%      4.61% |           4      0.54%      5.15% |         194     26.29%     31.44% |         475     64.36%     95.80% |          31      4.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::total          738                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size           32                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket          319                      
-system.ruby.IFETCH.latency_hist_seqr::samples           54                      
-system.ruby.IFETCH.latency_hist_seqr::mean    69.555556                      
-system.ruby.IFETCH.latency_hist_seqr::gmean    55.256031                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    50.686855                      
-system.ruby.IFETCH.latency_hist_seqr     |           8     14.81%     14.81% |          15     27.78%     42.59% |          25     46.30%     88.89% |           0      0.00%     88.89% |           3      5.56%     94.44% |           0      0.00%     94.44% |           2      3.70%     98.15% |           0      0.00%     98.15% |           0      0.00%     98.15% |           1      1.85%    100.00%
-system.ruby.IFETCH.latency_hist_seqr::total           54                      
+system.ruby.IFETCH.latency_hist_seqr::samples           47                      
+system.ruby.IFETCH.latency_hist_seqr::mean    71.957447                      
+system.ruby.IFETCH.latency_hist_seqr::gmean    60.044920                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    50.481575                      
+system.ruby.IFETCH.latency_hist_seqr     |           7     14.89%     14.89% |          14     29.79%     44.68% |          21     44.68%     89.36% |           0      0.00%     89.36% |           1      2.13%     91.49% |           2      4.26%     95.74% |           1      2.13%     97.87% |           0      0.00%     97.87% |           1      2.13%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::total           47                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            4                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket           39                      
-system.ruby.IFETCH.hit_latency_hist_seqr::samples            8                      
-system.ruby.IFETCH.hit_latency_hist_seqr::mean    20.625000                      
-system.ruby.IFETCH.hit_latency_hist_seqr::gmean    15.768384                      
-system.ruby.IFETCH.hit_latency_hist_seqr::stdev     8.052285                      
-system.ruby.IFETCH.hit_latency_hist_seqr |           1     12.50%     12.50% |           0      0.00%     12.50% |           0      0.00%     12.50% |           0      0.00%     12.50% |           0      0.00%     12.50% |           1     12.50%     25.00% |           6     75.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total            8                      
+system.ruby.IFETCH.hit_latency_hist_seqr::samples            7                      
+system.ruby.IFETCH.hit_latency_hist_seqr::mean    24.428571                      
+system.ruby.IFETCH.hit_latency_hist_seqr::gmean    24.407244                      
+system.ruby.IFETCH.hit_latency_hist_seqr::stdev     1.133893                      
+system.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           7    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist_seqr::total            7                      
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           32                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          319                      
-system.ruby.IFETCH.miss_latency_hist_seqr::samples           46                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    78.065217                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    68.721309                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    50.161252                      
-system.ruby.IFETCH.miss_latency_hist_seqr |           0      0.00%      0.00% |          15     32.61%     32.61% |          25     54.35%     86.96% |           0      0.00%     86.96% |           3      6.52%     93.48% |           0      0.00%     93.48% |           2      4.35%     97.83% |           0      0.00%     97.83% |           0      0.00%     97.83% |           1      2.17%    100.00%
-system.ruby.IFETCH.miss_latency_hist_seqr::total           46                      
+system.ruby.IFETCH.miss_latency_hist_seqr::samples           40                      
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    80.275000                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    70.290048                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    50.290942                      
+system.ruby.IFETCH.miss_latency_hist_seqr |           0      0.00%      0.00% |          14     35.00%     35.00% |          21     52.50%     87.50% |           0      0.00%     87.50% |           1      2.50%     90.00% |           2      5.00%     95.00% |           1      2.50%     97.50% |           0      0.00%     97.50% |           1      2.50%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::total           40                      
 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket            9                      
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples          106                      
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples           92                      
 system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean            1                      
 system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean            1                      
-system.ruby.L1Cache.hit_mach_latency_hist_seqr |           0      0.00%      0.00% |         106    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::total          106                      
+system.ruby.L1Cache.hit_mach_latency_hist_seqr |           0      0.00%      0.00% |          92    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::total           92                      
 system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size          256                      
 system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket         2559                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples           50                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean   500.560000                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean   172.276482                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev   491.089092                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr |          26     52.00%     52.00% |           0      0.00%     52.00% |           0      0.00%     52.00% |          17     34.00%     86.00% |           6     12.00%     98.00% |           1      2.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::total           50                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples           44                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean   585.545455                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean   213.332787                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev   513.546966                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr |          20     45.45%     45.45% |           0      0.00%     45.45% |           0      0.00%     45.45% |          10     22.73%     68.18% |          13     29.55%     97.73% |           1      2.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::total           44                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size          256                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket         2559                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples          790                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean   964.175949                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean   812.519909                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev   316.811320                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |          76      9.62%      9.62% |           7      0.89%     10.51% |           5      0.63%     11.14% |         245     31.01%     42.15% |         403     51.01%     93.16% |          54      6.84%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total          790                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::samples          822                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean   993.358881                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean   861.758158                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev   300.791358                      
+system.ruby.Directory.miss_mach_latency_hist_seqr |          70      8.52%      8.52% |           6      0.73%      9.25% |           4      0.49%      9.73% |         204     24.82%     34.55% |         503     61.19%     95.74% |          35      4.26%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::total          822                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples            7                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples            6                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean            1                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean            1                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           7    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total            7                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size          128                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket         1279                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           6    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total            6                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size          256                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket         2559                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples            3                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean   334.333333                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean    81.936099                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev   537.513101                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr |           2     66.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean          454                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean    91.132360                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev   744.781847                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr |           2     66.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total            3                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size          256                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket         2559                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples           36                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean  1016.583333                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean   947.115995                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev   254.139824                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           2      5.56%      5.56% |           0      0.00%      5.56% |           0      0.00%      5.56% |          14     38.89%     44.44% |          16     44.44%     88.89% |           4     11.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total           36                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples           44                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean  1066.386364                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean   996.352114                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev   247.421326                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           2      4.55%      4.55% |           0      0.00%      4.55% |           0      0.00%      4.55% |          10     22.73%     27.27% |          28     63.64%     90.91% |           4      9.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total           44                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples           98                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples           86                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean            1                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          98    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total           98                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size          256                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket         2559                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples           40                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean   596.525000                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean   258.353536                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev   485.549015                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr |          17     42.50%     42.50% |           0      0.00%     42.50% |           0      0.00%     42.50% |          16     40.00%     82.50% |           6     15.00%     97.50% |           1      2.50%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total           40                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          86    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total           86                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size          128                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket         1279                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples           34                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean   712.676471                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean   359.332613                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev   474.361052                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr |          11     32.35%     32.35% |           0      0.00%     32.35% |           0      0.00%     32.35% |           0      0.00%     32.35% |           0      0.00%     32.35% |           0      0.00%     32.35% |           0      0.00%     32.35% |          10     29.41%     61.76% |          12     35.29%     97.06% |           1      2.94%    100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total           34                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size          256                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket         2559                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          708                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean  1019.083333                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean   946.557722                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev   233.252272                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |          29      4.10%      4.10% |           6      0.85%      4.94% |           5      0.71%      5.65% |         231     32.63%     38.28% |         387     54.66%     92.94% |          50      7.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          708                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples            1                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean            1                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean            1                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::stdev          nan                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total            1                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          738                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean  1038.494580                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean   978.643470                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev   222.427518                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |          29      3.93%      3.93% |           5      0.68%      4.61% |           4      0.54%      5.15% |         194     26.29%     31.44% |         475     64.36%     95.80% |          31      4.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          738                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size            4                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket           39                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples            7                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean    23.428571                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean    23.382968                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev     1.511858                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     14.29%     14.29% |           6     85.71%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean    24.428571                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean    24.407244                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev     1.133893                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           7    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total            7                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples           46                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    78.065217                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    68.721309                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    50.161252                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          15     32.61%     32.61% |          25     54.35%     86.96% |           0      0.00%     86.96% |           3      6.52%     93.48% |           0      0.00%     93.48% |           2      4.35%     97.83% |           0      0.00%     97.83% |           0      0.00%     97.83% |           1      2.17%    100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total           46                      
-system.ruby.Directory_Controller.GETX             710      0.00%      0.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples           40                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    80.275000                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    70.290048                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    50.290942                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          14     35.00%     35.00% |          21     52.50%     87.50% |           0      0.00%     87.50% |           1      2.50%     90.00% |           2      5.00%     95.00% |           1      2.50%     97.50% |           0      0.00%     97.50% |           1      2.50%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total           40                      
+system.ruby.Directory_Controller.GETX             740      0.00%      0.00%
 system.ruby.Directory_Controller.GETS              85      0.00%      0.00%
-system.ruby.Directory_Controller.Lockdown           17      0.00%      0.00%
-system.ruby.Directory_Controller.Unlockdown           17      0.00%      0.00%
-system.ruby.Directory_Controller.Data_Owner            1      0.00%      0.00%
-system.ruby.Directory_Controller.Data_All_Tokens          718      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_Owner_All_Tokens           65      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          790      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          719      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETX           708      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETS            83      0.00%      0.00%
-system.ruby.Directory_Controller.NO.GETX            2      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Lockdown            7      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Data_Owner            1      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Data_All_Tokens          718      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens           65      0.00%      0.00%
-system.ruby.Directory_Controller.L.Unlockdown           17      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.GETS            2      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Memory_Ack          719      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.Memory_Data           10      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown           10      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data          780      0.00%      0.00%
-system.ruby.L1Cache_Controller.Load                46      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch              55      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store              847      0.00%      0.00%
-system.ruby.L1Cache_Controller.L1_Replacement        22253      0.00%      0.00%
+system.ruby.Directory_Controller.Lockdown           19      0.00%      0.00%
+system.ruby.Directory_Controller.Unlockdown           19      0.00%      0.00%
+system.ruby.Directory_Controller.Data_Owner            2      0.00%      0.00%
+system.ruby.Directory_Controller.Data_All_Tokens          741      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_Owner_All_Tokens           73      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_All_Tokens            2      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          823      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          743      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETX           739      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETS            85      0.00%      0.00%
+system.ruby.Directory_Controller.O.Ack_All_Tokens            2      0.00%      0.00%
+system.ruby.Directory_Controller.NO.GETX            1      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Lockdown            4      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Data_Owner            2      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Data_All_Tokens          741      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens           73      0.00%      0.00%
+system.ruby.Directory_Controller.L.Unlockdown           19      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Memory_Ack          743      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.Memory_Data           15      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Lockdown           15      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Memory_Data          808      0.00%      0.00%
+system.ruby.L1Cache_Controller.Load                53      0.00%      0.00%
+system.ruby.L1Cache_Controller.Ifetch              48      0.00%      0.00%
+system.ruby.L1Cache_Controller.Store              859      0.00%      0.00%
+system.ruby.L1Cache_Controller.L1_Replacement        23142      0.00%      0.00%
 system.ruby.L1Cache_Controller.Data_Shared           10      0.00%      0.00%
-system.ruby.L1Cache_Controller.Data_All_Tokens          844      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ack                  1      0.00%      0.00%
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock           34      0.00%      0.00%
-system.ruby.L1Cache_Controller.Request_Timeout           61      0.00%      0.00%
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers          829      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Load             39      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Ifetch           54      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Store           747      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens           14      0.00%      0.00%
+system.ruby.L1Cache_Controller.Data_All_Tokens          869      0.00%      0.00%
+system.ruby.L1Cache_Controller.Own_Lock_or_Unlock           38      0.00%      0.00%
+system.ruby.L1Cache_Controller.Request_Timeout           35      0.00%      0.00%
+system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers          855      0.00%      0.00%
+system.ruby.L1Cache_Controller.NP.Load             47      0.00%      0.00%
+system.ruby.L1Cache_Controller.NP.Ifetch           48      0.00%      0.00%
+system.ruby.L1Cache_Controller.NP.Store           772      0.00%      0.00%
+system.ruby.L1Cache_Controller.NP.Data_All_Tokens           13      0.00%      0.00%
 system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock           14      0.00%      0.00%
-system.ruby.L1Cache_Controller.S.Store              2      0.00%      0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement            8      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Ifetch             1      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement           79      0.00%      0.00%
+system.ruby.L1Cache_Controller.S.Load               1      0.00%      0.00%
+system.ruby.L1Cache_Controller.S.Store              1      0.00%      0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement            9      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement           82      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock            3      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.Load              7      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.Store            79      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement          748      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_W.Store            1      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement          551      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.Load              4      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.Store            69      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement          771      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock            2      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement          624      0.00%      0.00%
 system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock            1      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers           80      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_W.Store           18      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement        10451      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers           83      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_W.Load            1      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_W.Store           17      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement        10842      0.00%      0.00%
 system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock            1      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers          749      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement         9900      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens          746      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Ack               1      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock           10      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Request_Timeout           55      0.00%      0.00%
-system.ruby.L1Cache_Controller.SM.Data_All_Tokens            2      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement          516      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers          772      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement        10272      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Data_All_Tokens          771      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock           12      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Request_Timeout           25      0.00%      0.00%
+system.ruby.L1Cache_Controller.SM.Data_All_Tokens            1      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement          542      0.00%      0.00%
 system.ruby.L1Cache_Controller.IS.Data_Shared           10      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens           82      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Data_All_Tokens           84      0.00%      0.00%
 system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock            5      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Request_Timeout            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETS             93      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX            748      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement          770      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_Shared_Data            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_All_Tokens          833      0.00%      0.00%
-system.ruby.L2Cache_Controller.Persistent_GETX           11      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Request_Timeout           10      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETS             95      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX            773      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement          805      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_Shared_Data            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_All_Tokens          860      0.00%      0.00%
+system.ruby.L2Cache_Controller.Persistent_GETX           13      0.00%      0.00%
 system.ruby.L2Cache_Controller.Persistent_GETS            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.Own_Lock_or_Unlock           17      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS           83      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX          707      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens          773      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock           17      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.Writeback_All_Tokens           39      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.L1_GETX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.L1_GETX            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.L2_Replacement            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.Own_Lock_or_Unlock           19      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS           85      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX          739      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens          807      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock           19      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.Writeback_All_Tokens           33      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.L1_GETX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.L2_Replacement            2      0.00%      0.00%
 system.ruby.L2Cache_Controller.O.Writeback_All_Tokens            7      0.00%      0.00%
 system.ruby.L2Cache_Controller.M.L1_GETS           10      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX           38      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement          769      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens           14      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETX           11      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX           33      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement          801      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens           13      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETX           13      0.00%      0.00%
 system.ruby.L2Cache_Controller.I_L.Persistent_GETS            6      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
index d7e72749d..2dd4fa860 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -54,8 +59,13 @@ check_flush=true
 checks_to_complete=100
 clk_domain=system.clk_domain
 deadlock_threshold=50000
+default_p_state=UNDEFINED
 eventq_index=0
 num_cpus=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 system=system
 wakeup_frequency=10
 cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
@@ -70,27 +80,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -102,6 +112,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -109,12 +120,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -136,9 +152,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -152,12 +168,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=true
 
 [system.ruby.clk_domain]
@@ -174,6 +195,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
 dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
@@ -182,6 +204,10 @@ forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
 from_memory_controller_latency=2
 full_bit_dir_enabled=false
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 probeFilter=system.ruby.dir_cntrl0.probeFilter
 probe_filter_enabled=false
 recycle_latency=10
@@ -309,6 +335,7 @@ buffer_size=0
 cache_response_latency=10
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 forwardToCache=system.ruby.l1_cntrl0.forwardToCache
 issue_latency=2
@@ -316,6 +343,10 @@ l2_cache_hit_latency=10
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 no_mig_atomic=true
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestFromCache=system.ruby.l1_cntrl0.requestFromCache
 responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -447,17 +478,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.L1Dcache
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.L1Icache
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=0
 slave=system.cpu.cpuInstDataPort[0]
@@ -485,18 +521,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
 netifs=
 number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
 ruby_system=system.ruby
 topology=Crossbar
@@ -691,32 +732,234 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers40]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers41]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers42]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers43]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers44]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers45]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers46]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers47]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17
+power_model=Null
 router_id=0
 virt_nets=6
 
@@ -850,8 +1093,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17
+power_model=Null
 router_id=1
 virt_nets=6
 
@@ -985,8 +1234,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23
+power_model=Null
 router_id=2
 virt_nets=6
 
@@ -1161,9 +1416,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
index c2086c0ba..cee0dfc57 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
@@ -4,7 +4,5 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
index cb4dc5a7d..23e165901 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simout
+Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:56:08
-gem5 started Jan 21 2016 13:56:42
-gem5 executing on zizzer, pid 39357
-command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
+gem5 compiled Oct 13 2016 20:24:36
+gem5 started Oct 13 2016 20:24:58
+gem5 executing on e108600-lin, pid 38873
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 29561 because Ruby Tester completed
+Exiting @ tick 31071 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index 7a535a15b..43510f355 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -1,45 +1,45 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000030                       # Number of seconds simulated
-sim_ticks                                       29561                       # Number of ticks simulated
-final_tick                                      29561                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000031                       # Number of seconds simulated
+sim_ticks                                       31071                       # Number of ticks simulated
+final_tick                                      31071                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 585115                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 452068                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                                 307258                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 409592                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        29561                       # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0        56000                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total              56000                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0        50560                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total           50560                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0          875                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total                 875                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0          790                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total                790                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0   1894387876                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            1894387876                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0   1710361625                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total           1710361625                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   3604749501                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           3604749501                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                         876                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                        790                       # Number of write requests accepted
-system.mem_ctrls.readBursts                       876                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                      790                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  46720                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                    9344                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   41728                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                   56064                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys                50560                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    146                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   108                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        31071                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0        55104                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total              55104                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0        50048                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total           50048                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0          861                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total                 861                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0          782                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total                782                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0   1773486531                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total            1773486531                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0   1610762447                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total           1610762447                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   3384248978                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           3384248978                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                         862                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                        782                       # Number of write requests accepted
+system.mem_ctrls.readBursts                       862                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                      782                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM                  45632                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                    9536                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   41024                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                   55168                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys                50048                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                    149                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   111                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0               202                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0               191                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::1               231                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2               235                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3                62                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2               240                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3                51                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 0                       # Per bank write bursts
@@ -52,10 +52,10 @@ system.mem_ctrls.perBankRdBursts::12                0                       # Pe
 system.mem_ctrls.perBankRdBursts::13                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0               184                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1               201                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2               215                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3                52                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0               172                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1               202                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2               220                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3                47                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::5                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
@@ -70,25 +70,25 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         29529                       # Total gap between requests
+system.mem_ctrls.totGap                         31040                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                   876                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                   862                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6                  790                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     418                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                     290                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2                      22                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6                  782                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                     405                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                     288                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2                      19                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::3                       1                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
@@ -132,25 +132,25 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      3                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      6                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      2                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::17                     22                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::18                     40                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     42                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     41                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::20                     41                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::21                     42                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::22                     41                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     41                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     44                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::24                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     42                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                     61                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     41                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                     41                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                     53                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                     44                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::28                     41                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::29                     41                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::30                     40                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::31                     40                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::32                     40                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
@@ -181,363 +181,372 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples           91                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    952.967033                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   882.848619                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   223.022742                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127            2      2.20%      2.20% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255            2      2.20%      4.40% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383            2      2.20%      6.59% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639            1      1.10%      7.69% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            2      2.20%      9.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            1      1.10%     10.99% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           81     89.01%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total           91                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples           90                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    943.644444                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   882.472849                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   228.764454                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255            5      5.56%      5.56% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383            1      1.11%      6.67% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511            1      1.11%      7.78% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639            3      3.33%     11.11% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            2      2.22%     13.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           78     86.67%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total           90                       # Bytes accessed per row activation
 system.mem_ctrls.rdPerTurnAround::samples           40                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      17.800000                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     17.518113                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      3.824348                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15             8     20.00%     20.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            16     40.00%     60.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             8     20.00%     80.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21             6     15.00%     95.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      17.425000                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     17.142863                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      3.754570                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13             1      2.50%      2.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15            10     25.00%     27.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17            16     40.00%     67.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19             6     15.00%     82.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21             5     12.50%     95.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::22-23             1      2.50%     97.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::38-39             1      2.50%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::36-37             1      2.50%    100.00% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::total            40                       # Reads before turning the bus around for writes
 system.mem_ctrls.wrPerTurnAround::samples           40                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.300000                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.268271                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      1.114013                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               36     90.00%     90.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                2      5.00%     95.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21                2      5.00%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.025000                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.024268                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.158114                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               39     97.50%     97.50% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                1      2.50%    100.00% # Writes before turning the bus around for reads
 system.mem_ctrls.wrPerTurnAround::total            40                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                         8835                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   22705                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       3650                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        12.10                       # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat                        12133                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   25680                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       3565                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        17.02                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   31.10                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                      1580.46                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                      1411.59                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   1896.55                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                   1710.36                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   36.02                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                      1468.64                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                      1320.33                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                   1775.55                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                   1610.76                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                        23.38                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                    12.35                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                   11.03                       # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen                       1.74                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      24.79                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      640                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     647                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 87.67                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                94.87                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         17.72                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    91.15                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   567000                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   315000                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 7176000                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                5432832                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              1525680                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             16101360                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy                48600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               31166472                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower           1319.439143                       # Core power per rank (mW)
+system.mem_ctrls.busUtil                        21.79                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                    11.47                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                   10.32                       # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen                       1.76                       # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      25.13                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      625                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     635                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 87.66                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                94.63                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         18.88                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    91.04                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   671160                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   347760                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 8145312                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                5353632                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         1843920.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              8199792                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy                36480                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy         5925264                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy               0                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               30523320                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            982.373274                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                12994                       # Total Idle time Per DRAM Rank
 system.mem_ctrls_0.memoryStateTime::IDLE           11                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::REF           780                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         22844                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         17286                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        12994                       # Time in different power states
 system.mem_ctrls_1.actEnergy                        0                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_1.preEnergy                        0                       # Energy for precharge commands per rank (pJ)
 system.mem_ctrls_1.readEnergy                       0                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              1525680                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy               504792                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy             13719600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               15750072                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            667.262837                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE        22838                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF           780                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.refreshEnergy         1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy               224352                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              3002880                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy               0                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy         2889984                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy          3655920                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               11002416                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            354.105629                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                 7526                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE         7786                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF           526                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF        15233                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         7526                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT             0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        29561                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::UNDEFINED        29561                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED        31071                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED        31071                       # Cumulative time (in ticks) in various power states
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        29561                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        31071                       # Cumulative time (in ticks) in various power states
 system.ruby.outstanding_req_hist_seqr::bucket_size            2                      
 system.ruby.outstanding_req_hist_seqr::max_bucket           19                      
-system.ruby.outstanding_req_hist_seqr::samples         1027                      
-system.ruby.outstanding_req_hist_seqr::mean    15.566699                      
-system.ruby.outstanding_req_hist_seqr::gmean    15.456992                      
-system.ruby.outstanding_req_hist_seqr::stdev     1.265135                      
-system.ruby.outstanding_req_hist_seqr    |           1      0.10%      0.10% |           2      0.19%      0.29% |           2      0.19%      0.49% |           3      0.29%      0.78% |           3      0.29%      1.07% |           6      0.58%      1.66% |           3      0.29%      1.95% |         271     26.39%     28.33% |         736     71.67%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist_seqr::total         1027                      
+system.ruby.outstanding_req_hist_seqr::samples         1010                      
+system.ruby.outstanding_req_hist_seqr::mean    15.556436                      
+system.ruby.outstanding_req_hist_seqr::gmean    15.445317                      
+system.ruby.outstanding_req_hist_seqr::stdev     1.273066                      
+system.ruby.outstanding_req_hist_seqr    |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.50% |           3      0.30%      0.79% |           3      0.30%      1.09% |           6      0.59%      1.68% |           3      0.30%      1.98% |         272     26.93%     28.91% |         718     71.09%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist_seqr::total         1010                      
 system.ruby.latency_hist_seqr::bucket_size          128                      
 system.ruby.latency_hist_seqr::max_bucket         1279                      
-system.ruby.latency_hist_seqr::samples           1012                      
-system.ruby.latency_hist_seqr::mean        452.030632                      
-system.ruby.latency_hist_seqr::gmean       221.913062                      
-system.ruby.latency_hist_seqr::stdev       245.259624                      
-system.ruby.latency_hist_seqr            |         227     22.43%     22.43% |          13      1.28%     23.72% |           6      0.59%     24.31% |         123     12.15%     36.46% |         525     51.88%     88.34% |          73      7.21%     95.55% |          35      3.46%     99.01% |          10      0.99%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist_seqr::total             1012                      
-system.ruby.hit_latency_hist_seqr::bucket_size           64                      
-system.ruby.hit_latency_hist_seqr::max_bucket          639                      
-system.ruby.hit_latency_hist_seqr::samples          140                      
-system.ruby.hit_latency_hist_seqr::mean     75.100000                      
-system.ruby.hit_latency_hist_seqr::gmean     3.808266                      
-system.ruby.hit_latency_hist_seqr::stdev   173.693574                      
-system.ruby.hit_latency_hist_seqr        |         117     83.57%     83.57% |           3      2.14%     85.71% |           1      0.71%     86.43% |           0      0.00%     86.43% |           0      0.00%     86.43% |           0      0.00%     86.43% |           4      2.86%     89.29% |           5      3.57%     92.86% |           8      5.71%     98.57% |           2      1.43%    100.00%
-system.ruby.hit_latency_hist_seqr::total          140                      
+system.ruby.latency_hist_seqr::samples            995                      
+system.ruby.latency_hist_seqr::mean        482.717588                      
+system.ruby.latency_hist_seqr::gmean       245.065735                      
+system.ruby.latency_hist_seqr::stdev       262.743362                      
+system.ruby.latency_hist_seqr            |         233     23.42%     23.42% |           9      0.90%     24.32% |           5      0.50%     24.82% |          58      5.83%     30.65% |         397     39.90%     70.55% |         236     23.72%     94.27% |          55      5.53%     99.80% |           2      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::total              995                      
+system.ruby.hit_latency_hist_seqr::bucket_size          128                      
+system.ruby.hit_latency_hist_seqr::max_bucket         1279                      
+system.ruby.hit_latency_hist_seqr::samples          135                      
+system.ruby.hit_latency_hist_seqr::mean    110.851852                      
+system.ruby.hit_latency_hist_seqr::gmean     6.261385                      
+system.ruby.hit_latency_hist_seqr::stdev   224.829770                      
+system.ruby.hit_latency_hist_seqr        |         111     82.22%     82.22% |           0      0.00%     82.22% |           0      0.00%     82.22% |           3      2.22%     84.44% |          17     12.59%     97.04% |           3      2.22%     99.26% |           0      0.00%     99.26% |           1      0.74%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist_seqr::total          135                      
 system.ruby.miss_latency_hist_seqr::bucket_size          128                      
 system.ruby.miss_latency_hist_seqr::max_bucket         1279                      
-system.ruby.miss_latency_hist_seqr::samples          872                      
-system.ruby.miss_latency_hist_seqr::mean   512.547018                      
-system.ruby.miss_latency_hist_seqr::gmean   426.213857                      
-system.ruby.miss_latency_hist_seqr::stdev   196.222062                      
-system.ruby.miss_latency_hist_seqr       |         107     12.27%     12.27% |          12      1.38%     13.65% |           6      0.69%     14.33% |         114     13.07%     27.41% |         515     59.06%     86.47% |          73      8.37%     94.84% |          35      4.01%     98.85% |          10      1.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist_seqr::total          872                      
-system.ruby.Directory.incomplete_times_seqr          872                      
+system.ruby.miss_latency_hist_seqr::samples          860                      
+system.ruby.miss_latency_hist_seqr::mean   541.091860                      
+system.ruby.miss_latency_hist_seqr::gmean   435.798434                      
+system.ruby.miss_latency_hist_seqr::stdev   216.457686                      
+system.ruby.miss_latency_hist_seqr       |         122     14.19%     14.19% |           9      1.05%     15.23% |           5      0.58%     15.81% |          55      6.40%     22.21% |         380     44.19%     66.40% |         233     27.09%     93.49% |          55      6.40%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::total          860                      
+system.ruby.Directory.incomplete_times_seqr          860                      
 system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
 system.ruby.dir_cntrl0.probeFilter.demand_misses            0                       # Number of cache demand misses
 system.ruby.dir_cntrl0.probeFilter.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        29561                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.L1Dcache.demand_hits           96                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          859                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          955                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits            3                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses           54                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses           57                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L2cache.demand_hits           39                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L2cache.demand_misses          874                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L2cache.demand_accesses          913                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        29561                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            8                       # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           72                       # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            4                       # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_load            3                       # Number of times a load aliased with a pending load
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        29561                       # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        31071                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.L1Dcache.demand_hits           79                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          852                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          931                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses           63                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses           63                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L2cache.demand_hits           54                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L2cache.demand_misses          861                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L2cache.demand_accesses          915                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        31071                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            3                       # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           84                       # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            7                       # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_load            1                       # Number of times a load aliased with a pending load
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        31071                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        29561                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized    15.685362                      
-system.ruby.network.routers0.msg_count.Request_Control::2          876                      
-system.ruby.network.routers0.msg_count.Response_Data::4          874                      
-system.ruby.network.routers0.msg_count.Writeback_Data::5          791                      
-system.ruby.network.routers0.msg_count.Writeback_Control::2          869                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3          869                      
-system.ruby.network.routers0.msg_count.Writeback_Control::5           77                      
-system.ruby.network.routers0.msg_count.Unblock_Control::5          871                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2         7008                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4        62928                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::5        56952                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::2         6952                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3         6952                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::5          616                      
-system.ruby.network.routers0.msg_bytes.Unblock_Control::5         6968                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        29561                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized    15.679443                      
-system.ruby.network.routers1.msg_count.Request_Control::2          876                      
-system.ruby.network.routers1.msg_count.Response_Data::4          874                      
-system.ruby.network.routers1.msg_count.Writeback_Data::5          791                      
-system.ruby.network.routers1.msg_count.Writeback_Control::2          869                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3          869                      
-system.ruby.network.routers1.msg_count.Writeback_Control::5           77                      
-system.ruby.network.routers1.msg_count.Unblock_Control::5          871                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         7008                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4        62928                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::5        56952                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::2         6952                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3         6952                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::5          616                      
-system.ruby.network.routers1.msg_bytes.Unblock_Control::5         6968                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        29561                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized    15.682825                      
-system.ruby.network.routers2.msg_count.Request_Control::2          876                      
-system.ruby.network.routers2.msg_count.Response_Data::4          874                      
-system.ruby.network.routers2.msg_count.Writeback_Data::5          791                      
-system.ruby.network.routers2.msg_count.Writeback_Control::2          869                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3          869                      
-system.ruby.network.routers2.msg_count.Writeback_Control::5           77                      
-system.ruby.network.routers2.msg_count.Unblock_Control::5          871                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2         7008                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4        62928                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::5        56952                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::2         6952                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3         6952                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::5          616                      
-system.ruby.network.routers2.msg_bytes.Unblock_Control::5         6968                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        29561                       # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Request_Control         2628                      
-system.ruby.network.msg_count.Response_Data         2622                      
-system.ruby.network.msg_count.Writeback_Data         2373                      
-system.ruby.network.msg_count.Writeback_Control         5445                      
-system.ruby.network.msg_count.Unblock_Control         2613                      
-system.ruby.network.msg_byte.Request_Control        21024                      
-system.ruby.network.msg_byte.Response_Data       188784                      
-system.ruby.network.msg_byte.Writeback_Data       170856                      
-system.ruby.network.msg_byte.Writeback_Control        43560                      
-system.ruby.network.msg_byte.Unblock_Control        20904                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        29561                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization    14.774534                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          874                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          869                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        62928                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         6952                      
-system.ruby.network.routers0.throttle1.link_utilization    16.596191                      
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::2          876                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5          791                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2          869                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5           77                      
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5          871                      
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2         7008                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5        56952                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2         6952                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5          616                      
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5         6968                      
-system.ruby.network.routers1.throttle0.link_utilization    16.584351                      
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::2          876                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5          791                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2          869                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5           77                      
-system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5          871                      
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2         7008                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5        56952                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2         6952                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5          616                      
-system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5         6968                      
-system.ruby.network.routers1.throttle1.link_utilization    14.774534                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          874                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          869                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        62928                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         6952                      
-system.ruby.network.routers2.throttle0.link_utilization    14.774534                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          874                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          869                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        62928                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         6952                      
-system.ruby.network.routers2.throttle1.link_utilization    16.591117                      
-system.ruby.network.routers2.throttle1.msg_count.Request_Control::2          876                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5          791                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2          869                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5           77                      
-system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5          871                      
-system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2         7008                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5        56952                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2         6952                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5          616                      
-system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5         6968                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        31071                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized    14.722732                      
+system.ruby.network.routers0.msg_count.Request_Control::2          863                      
+system.ruby.network.routers0.msg_count.Response_Data::4          861                      
+system.ruby.network.routers0.msg_count.Writeback_Data::5          783                      
+system.ruby.network.routers0.msg_count.Writeback_Control::2          855                      
+system.ruby.network.routers0.msg_count.Writeback_Control::3          856                      
+system.ruby.network.routers0.msg_count.Writeback_Control::5           71                      
+system.ruby.network.routers0.msg_count.Unblock_Control::5          859                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2         6904                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4        61992                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::5        56376                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::2         6840                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3         6848                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::5          568                      
+system.ruby.network.routers0.msg_bytes.Unblock_Control::5         6872                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        31071                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized    14.717100                      
+system.ruby.network.routers1.msg_count.Request_Control::2          863                      
+system.ruby.network.routers1.msg_count.Response_Data::4          861                      
+system.ruby.network.routers1.msg_count.Writeback_Data::5          782                      
+system.ruby.network.routers1.msg_count.Writeback_Control::2          855                      
+system.ruby.network.routers1.msg_count.Writeback_Control::3          856                      
+system.ruby.network.routers1.msg_count.Writeback_Control::5           71                      
+system.ruby.network.routers1.msg_count.Unblock_Control::5          859                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         6904                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4        61992                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::5        56304                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::2         6840                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3         6848                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::5          568                      
+system.ruby.network.routers1.msg_bytes.Unblock_Control::5         6872                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        31071                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized    14.720318                      
+system.ruby.network.routers2.msg_count.Request_Control::2          863                      
+system.ruby.network.routers2.msg_count.Response_Data::4          861                      
+system.ruby.network.routers2.msg_count.Writeback_Data::5          783                      
+system.ruby.network.routers2.msg_count.Writeback_Control::2          855                      
+system.ruby.network.routers2.msg_count.Writeback_Control::3          856                      
+system.ruby.network.routers2.msg_count.Writeback_Control::5           71                      
+system.ruby.network.routers2.msg_count.Unblock_Control::5          859                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2         6904                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4        61992                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::5        56376                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::2         6840                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3         6848                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::5          568                      
+system.ruby.network.routers2.msg_bytes.Unblock_Control::5         6872                      
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        31071                       # Cumulative time (in ticks) in various power states
+system.ruby.network.msg_count.Request_Control         2589                      
+system.ruby.network.msg_count.Response_Data         2583                      
+system.ruby.network.msg_count.Writeback_Data         2348                      
+system.ruby.network.msg_count.Writeback_Control         5346                      
+system.ruby.network.msg_count.Unblock_Control         2577                      
+system.ruby.network.msg_byte.Request_Control        20712                      
+system.ruby.network.msg_byte.Response_Data       185976                      
+system.ruby.network.msg_byte.Writeback_Data       169056                      
+system.ruby.network.msg_byte.Writeback_Control        42768                      
+system.ruby.network.msg_byte.Unblock_Control        20616                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        31071                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization    13.845708                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          861                      
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          856                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        61992                      
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         6848                      
+system.ruby.network.routers0.throttle1.link_utilization    15.599755                      
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::2          863                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5          783                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2          855                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5           71                      
+system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5          859                      
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2         6904                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5        56376                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2         6840                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5          568                      
+system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5         6872                      
+system.ruby.network.routers1.throttle0.link_utilization    15.586882                      
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::2          863                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5          782                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2          855                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5           71                      
+system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5          859                      
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2         6904                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5        56304                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2         6840                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5          568                      
+system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5         6872                      
+system.ruby.network.routers1.throttle1.link_utilization    13.847317                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          861                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          856                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        61992                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         6848                      
+system.ruby.network.routers2.throttle0.link_utilization    13.847317                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          861                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          856                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        61992                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         6848                      
+system.ruby.network.routers2.throttle1.link_utilization    15.593319                      
+system.ruby.network.routers2.throttle1.msg_count.Request_Control::2          863                      
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5          783                      
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2          855                      
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5           71                      
+system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5          859                      
+system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2         6904                      
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5        56376                      
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2         6840                      
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5          568                      
+system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5         6872                      
 system.ruby.LD.latency_hist_seqr::bucket_size          128                      
 system.ruby.LD.latency_hist_seqr::max_bucket         1279                      
-system.ruby.LD.latency_hist_seqr::samples           43                      
-system.ruby.LD.latency_hist_seqr::mean     511.511628                      
-system.ruby.LD.latency_hist_seqr::gmean    293.373548                      
-system.ruby.LD.latency_hist_seqr::stdev    216.139767                      
-system.ruby.LD.latency_hist_seqr         |           6     13.95%     13.95% |           0      0.00%     13.95% |           0      0.00%     13.95% |           7     16.28%     30.23% |          23     53.49%     83.72% |           5     11.63%     95.35% |           1      2.33%     97.67% |           1      2.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist_seqr::total            43                      
-system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
-system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
-system.ruby.LD.hit_latency_hist_seqr::samples            4                      
-system.ruby.LD.hit_latency_hist_seqr::mean            1                      
-system.ruby.LD.hit_latency_hist_seqr::gmean            1                      
-system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |           4    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist_seqr::total            4                      
+system.ruby.LD.latency_hist_seqr::samples           37                      
+system.ruby.LD.latency_hist_seqr::mean     484.027027                      
+system.ruby.LD.latency_hist_seqr::gmean    206.042037                      
+system.ruby.LD.latency_hist_seqr::stdev    286.676016                      
+system.ruby.LD.latency_hist_seqr         |          10     27.03%     27.03% |           0      0.00%     27.03% |           0      0.00%     27.03% |           0      0.00%     27.03% |          12     32.43%     59.46% |          13     35.14%     94.59% |           2      5.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::total            37                      
+system.ruby.LD.hit_latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.hit_latency_hist_seqr::max_bucket          639                      
+system.ruby.LD.hit_latency_hist_seqr::samples            6                      
+system.ruby.LD.hit_latency_hist_seqr::mean          104                      
+system.ruby.LD.hit_latency_hist_seqr::gmean     4.461922                      
+system.ruby.LD.hit_latency_hist_seqr::stdev   246.465413                      
+system.ruby.LD.hit_latency_hist_seqr     |           5     83.33%     83.33% |           0      0.00%     83.33% |           0      0.00%     83.33% |           0      0.00%     83.33% |           0      0.00%     83.33% |           0      0.00%     83.33% |           0      0.00%     83.33% |           0      0.00%     83.33% |           0      0.00%     83.33% |           1     16.67%    100.00%
+system.ruby.LD.hit_latency_hist_seqr::total            6                      
 system.ruby.LD.miss_latency_hist_seqr::bucket_size          128                      
 system.ruby.LD.miss_latency_hist_seqr::max_bucket         1279                      
-system.ruby.LD.miss_latency_hist_seqr::samples           39                      
-system.ruby.LD.miss_latency_hist_seqr::mean   563.871795                      
-system.ruby.LD.miss_latency_hist_seqr::gmean   525.399638                      
-system.ruby.LD.miss_latency_hist_seqr::stdev   146.240462                      
-system.ruby.LD.miss_latency_hist_seqr    |           2      5.13%      5.13% |           0      0.00%      5.13% |           0      0.00%      5.13% |           7     17.95%     23.08% |          23     58.97%     82.05% |           5     12.82%     94.87% |           1      2.56%     97.44% |           1      2.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist_seqr::total           39                      
+system.ruby.LD.miss_latency_hist_seqr::samples           31                      
+system.ruby.LD.miss_latency_hist_seqr::mean   557.580645                      
+system.ruby.LD.miss_latency_hist_seqr::gmean   432.617733                      
+system.ruby.LD.miss_latency_hist_seqr::stdev   232.424149                      
+system.ruby.LD.miss_latency_hist_seqr    |           5     16.13%     16.13% |           0      0.00%     16.13% |           0      0.00%     16.13% |           0      0.00%     16.13% |          11     35.48%     51.61% |          13     41.94%     93.55% |           2      6.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::total           31                      
 system.ruby.ST.latency_hist_seqr::bucket_size          128                      
 system.ruby.ST.latency_hist_seqr::max_bucket         1279                      
-system.ruby.ST.latency_hist_seqr::samples          910                      
-system.ruby.ST.latency_hist_seqr::mean     473.924176                      
-system.ruby.ST.latency_hist_seqr::gmean    243.035413                      
-system.ruby.ST.latency_hist_seqr::stdev    232.681347                      
-system.ruby.ST.latency_hist_seqr         |         166     18.24%     18.24% |          11      1.21%     19.45% |           6      0.66%     20.11% |         116     12.75%     32.86% |         500     54.95%     87.80% |          68      7.47%     95.27% |          34      3.74%     99.01% |           9      0.99%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist_seqr::total           910                      
-system.ruby.ST.hit_latency_hist_seqr::bucket_size           64                      
-system.ruby.ST.hit_latency_hist_seqr::max_bucket          639                      
-system.ruby.ST.hit_latency_hist_seqr::samples          126                      
-system.ruby.ST.hit_latency_hist_seqr::mean    74.587302                      
-system.ruby.ST.hit_latency_hist_seqr::gmean     3.636852                      
-system.ruby.ST.hit_latency_hist_seqr::stdev   172.646982                      
-system.ruby.ST.hit_latency_hist_seqr     |         105     83.33%     83.33% |           3      2.38%     85.71% |           1      0.79%     86.51% |           0      0.00%     86.51% |           0      0.00%     86.51% |           0      0.00%     86.51% |           4      3.17%     89.68% |           5      3.97%     93.65% |           6      4.76%     98.41% |           2      1.59%    100.00%
-system.ruby.ST.hit_latency_hist_seqr::total          126                      
+system.ruby.ST.latency_hist_seqr::samples          893                      
+system.ruby.ST.latency_hist_seqr::mean     513.324748                      
+system.ruby.ST.latency_hist_seqr::gmean    281.060775                      
+system.ruby.ST.latency_hist_seqr::stdev    242.626948                      
+system.ruby.ST.latency_hist_seqr         |         160     17.92%     17.92% |           8      0.90%     18.81% |           5      0.56%     19.37% |          58      6.49%     25.87% |         385     43.11%     68.98% |         223     24.97%     93.95% |          53      5.94%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::total           893                      
+system.ruby.ST.hit_latency_hist_seqr::bucket_size          128                      
+system.ruby.ST.hit_latency_hist_seqr::max_bucket         1279                      
+system.ruby.ST.hit_latency_hist_seqr::samples          116                      
+system.ruby.ST.hit_latency_hist_seqr::mean   114.353448                      
+system.ruby.ST.hit_latency_hist_seqr::gmean     5.688161                      
+system.ruby.ST.hit_latency_hist_seqr::stdev   222.966921                      
+system.ruby.ST.hit_latency_hist_seqr     |          94     81.03%     81.03% |           0      0.00%     81.03% |           0      0.00%     81.03% |           3      2.59%     83.62% |          16     13.79%     97.41% |           3      2.59%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist_seqr::total          116                      
 system.ruby.ST.miss_latency_hist_seqr::bucket_size          128                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket         1279                      
-system.ruby.ST.miss_latency_hist_seqr::samples          784                      
-system.ruby.ST.miss_latency_hist_seqr::mean   538.103316                      
-system.ruby.ST.miss_latency_hist_seqr::gmean   477.489826                      
-system.ruby.ST.miss_latency_hist_seqr::stdev   168.250948                      
-system.ruby.ST.miss_latency_hist_seqr    |          58      7.40%      7.40% |          10      1.28%      8.67% |           6      0.77%      9.44% |         107     13.65%     23.09% |         492     62.76%     85.84% |          68      8.67%     94.52% |          34      4.34%     98.85% |           9      1.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist_seqr::total          784                      
-system.ruby.IFETCH.latency_hist_seqr::bucket_size           16                      
-system.ruby.IFETCH.latency_hist_seqr::max_bucket          159                      
-system.ruby.IFETCH.latency_hist_seqr::samples           57                      
-system.ruby.IFETCH.latency_hist_seqr::mean           55                      
-system.ruby.IFETCH.latency_hist_seqr::gmean    40.845512                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    30.808162                      
-system.ruby.IFETCH.latency_hist_seqr     |           8     14.04%     14.04% |           6     10.53%     24.56% |           1      1.75%     26.32% |          27     47.37%     73.68% |           9     15.79%     89.47% |           3      5.26%     94.74% |           1      1.75%     96.49% |           0      0.00%     96.49% |           0      0.00%     96.49% |           2      3.51%    100.00%
-system.ruby.IFETCH.latency_hist_seqr::total           57                      
+system.ruby.ST.miss_latency_hist_seqr::samples          777                      
+system.ruby.ST.miss_latency_hist_seqr::mean   572.888031                      
+system.ruby.ST.miss_latency_hist_seqr::gmean   503.124564                      
+system.ruby.ST.miss_latency_hist_seqr::stdev   181.530163                      
+system.ruby.ST.miss_latency_hist_seqr    |          66      8.49%      8.49% |           8      1.03%      9.52% |           5      0.64%     10.17% |          55      7.08%     17.25% |         369     47.49%     64.74% |         220     28.31%     93.05% |          53      6.82%     99.87% |           1      0.13%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::total          777                      
+system.ruby.IFETCH.latency_hist_seqr::bucket_size           32                      
+system.ruby.IFETCH.latency_hist_seqr::max_bucket          319                      
+system.ruby.IFETCH.latency_hist_seqr::samples           63                      
+system.ruby.IFETCH.latency_hist_seqr::mean    48.269841                      
+system.ruby.IFETCH.latency_hist_seqr::gmean    39.118214                      
+system.ruby.IFETCH.latency_hist_seqr::stdev    28.730790                      
+system.ruby.IFETCH.latency_hist_seqr     |          25     39.68%     39.68% |          19     30.16%     69.84% |          18     28.57%     98.41% |           0      0.00%     98.41% |           0      0.00%     98.41% |           1      1.59%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::total           63                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            2                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket           19                      
-system.ruby.IFETCH.hit_latency_hist_seqr::samples            8                      
-system.ruby.IFETCH.hit_latency_hist_seqr::mean     7.250000                      
-system.ruby.IFETCH.hit_latency_hist_seqr::gmean     4.475797                      
-system.ruby.IFETCH.hit_latency_hist_seqr::stdev     5.175492                      
-system.ruby.IFETCH.hit_latency_hist_seqr |           3     37.50%     37.50% |           0      0.00%     37.50% |           0      0.00%     37.50% |           0      0.00%     37.50% |           0      0.00%     37.50% |           5     62.50%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total            8                      
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           16                      
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          159                      
-system.ruby.IFETCH.miss_latency_hist_seqr::samples           49                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    62.795918                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    58.603527                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    25.717196                      
-system.ruby.IFETCH.miss_latency_hist_seqr |           0      0.00%      0.00% |           6     12.24%     12.24% |           1      2.04%     14.29% |          27     55.10%     69.39% |           9     18.37%     87.76% |           3      6.12%     93.88% |           1      2.04%     95.92% |           0      0.00%     95.92% |           0      0.00%     95.92% |           2      4.08%    100.00%
-system.ruby.IFETCH.miss_latency_hist_seqr::total           49                      
-system.ruby.FLUSH.latency_hist_seqr::bucket_size           64                      
-system.ruby.FLUSH.latency_hist_seqr::max_bucket          639                      
+system.ruby.IFETCH.hit_latency_hist_seqr::samples           11                      
+system.ruby.IFETCH.hit_latency_hist_seqr::mean           11                      
+system.ruby.IFETCH.hit_latency_hist_seqr::gmean    11.000000                      
+system.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          11    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist_seqr::total           11                      
+system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           32                      
+system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          319                      
+system.ruby.IFETCH.miss_latency_hist_seqr::samples           52                      
+system.ruby.IFETCH.miss_latency_hist_seqr::mean    56.153846                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean    51.160387                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev    25.308593                      
+system.ruby.IFETCH.miss_latency_hist_seqr |          14     26.92%     26.92% |          19     36.54%     63.46% |          18     34.62%     98.08% |           0      0.00%     98.08% |           0      0.00%     98.08% |           1      1.92%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::total           52                      
+system.ruby.FLUSH.latency_hist_seqr::bucket_size          128                      
+system.ruby.FLUSH.latency_hist_seqr::max_bucket         1279                      
 system.ruby.FLUSH.latency_hist_seqr::samples            2                      
-system.ruby.FLUSH.latency_hist_seqr::mean          527                      
-system.ruby.FLUSH.latency_hist_seqr::gmean   526.885187                      
-system.ruby.FLUSH.latency_hist_seqr::stdev    15.556349                      
-system.ruby.FLUSH.latency_hist_seqr      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.FLUSH.latency_hist_seqr::mean   477.500000                      
+system.ruby.FLUSH.latency_hist_seqr::gmean   204.484718                      
+system.ruby.FLUSH.latency_hist_seqr::stdev   610.233152                      
+system.ruby.FLUSH.latency_hist_seqr      |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.FLUSH.latency_hist_seqr::total            2                      
-system.ruby.FLUSH.hit_latency_hist_seqr::bucket_size           64                      
-system.ruby.FLUSH.hit_latency_hist_seqr::max_bucket          639                      
+system.ruby.FLUSH.hit_latency_hist_seqr::bucket_size          128                      
+system.ruby.FLUSH.hit_latency_hist_seqr::max_bucket         1279                      
 system.ruby.FLUSH.hit_latency_hist_seqr::samples            2                      
-system.ruby.FLUSH.hit_latency_hist_seqr::mean          527                      
-system.ruby.FLUSH.hit_latency_hist_seqr::gmean   526.885187                      
-system.ruby.FLUSH.hit_latency_hist_seqr::stdev    15.556349                      
-system.ruby.FLUSH.hit_latency_hist_seqr  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.FLUSH.hit_latency_hist_seqr::mean   477.500000                      
+system.ruby.FLUSH.hit_latency_hist_seqr::gmean   204.484718                      
+system.ruby.FLUSH.hit_latency_hist_seqr::stdev   610.233152                      
+system.ruby.FLUSH.hit_latency_hist_seqr  |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.FLUSH.hit_latency_hist_seqr::total            2                      
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size           64                      
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket          639                      
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples          101                      
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean    11.415842                      
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean     1.132128                      
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::stdev    73.663867                      
-system.ruby.L1Cache.hit_mach_latency_hist_seqr |          99     98.02%     98.02% |           0      0.00%     98.02% |           0      0.00%     98.02% |           0      0.00%     98.02% |           0      0.00%     98.02% |           0      0.00%     98.02% |           0      0.00%     98.02% |           0      0.00%     98.02% |           2      1.98%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::total          101                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size           64                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket          639                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples           39                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean   240.025641                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean    88.122529                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev   239.543259                      
-system.ruby.L2Cache.hit_mach_latency_hist_seqr |          18     46.15%     46.15% |           3      7.69%     53.85% |           1      2.56%     56.41% |           0      0.00%     56.41% |           0      0.00%     56.41% |           0      0.00%     56.41% |           4     10.26%     66.67% |           5     12.82%     79.49% |           6     15.38%     94.87% |           2      5.13%    100.00%
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::total           39                      
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size          128                      
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket         1279                      
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples           81                      
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean    12.765432                      
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean     1.140390                      
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::stdev   100.950269                      
+system.ruby.L1Cache.hit_mach_latency_hist_seqr |          80     98.77%     98.77% |           0      0.00%     98.77% |           0      0.00%     98.77% |           0      0.00%     98.77% |           0      0.00%     98.77% |           0      0.00%     98.77% |           0      0.00%     98.77% |           1      1.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::total           81                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size          128                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket         1279                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples           54                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean   257.981481                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean    80.555654                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev   275.063320                      
+system.ruby.L2Cache.hit_mach_latency_hist_seqr |          31     57.41%     57.41% |           0      0.00%     57.41% |           0      0.00%     57.41% |           3      5.56%     62.96% |          17     31.48%     94.44% |           3      5.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::total           54                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size          128                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket         1279                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples          872                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean   512.547018                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean   426.213857                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev   196.222062                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |         107     12.27%     12.27% |          12      1.38%     13.65% |           6      0.69%     14.33% |         114     13.07%     27.41% |         515     59.06%     86.47% |          73      8.37%     94.84% |          35      4.01%     98.85% |          10      1.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total          872                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::samples          860                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean   541.091860                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean   435.798434                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev   216.457686                      
+system.ruby.Directory.miss_mach_latency_hist_seqr |         122     14.19%     14.19% |           9      1.05%     15.23% |           5      0.58%     15.81% |          55      6.40%     22.21% |         380     44.19%     66.40% |         233     27.09%     93.49% |          55      6.40%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::total          860                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples            4                      
@@ -545,142 +554,146 @@ system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean            1
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean            1                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           4    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total            4                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket          639                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples            2                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean          310                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean    88.831301                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev   420.021428                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00%
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total            2                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size          128                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket         1279                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples           39                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean   563.871795                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean   525.399638                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev   146.240462                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           2      5.13%      5.13% |           0      0.00%      5.13% |           0      0.00%      5.13% |           7     17.95%     23.08% |          23     58.97%     82.05% |           5     12.82%     94.87% |           1      2.56%     97.44% |           1      2.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total           39                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples           31                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean   557.580645                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean   432.617733                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev   232.424149                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           5     16.13%     16.13% |           0      0.00%     16.13% |           0      0.00%     16.13% |           0      0.00%     16.13% |          11     35.48%     51.61% |          13     41.94%     93.55% |           2      6.45%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total           31                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples           92                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples           75                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean            1                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          92    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total           92                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size           64                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket          639                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples           34                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean   273.705882                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean   119.669415                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev   238.660724                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr |          13     38.24%     38.24% |           3      8.82%     47.06% |           1      2.94%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           4     11.76%     61.76% |           5     14.71%     76.47% |           6     17.65%     94.12% |           2      5.88%    100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total           34                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |          75    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total           75                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size          128                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket         1279                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples           41                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean   321.707317                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean   136.778519                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev   273.433835                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr |          19     46.34%     46.34% |           0      0.00%     46.34% |           0      0.00%     46.34% |           3      7.32%     53.66% |          16     39.02%     92.68% |           3      7.32%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total           41                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size          128                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket         1279                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          784                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean   538.103316                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean   477.489826                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev   168.250948                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |          58      7.40%      7.40% |          10      1.28%      8.67% |           6      0.77%      9.44% |         107     13.65%     23.09% |         492     62.76%     85.84% |          68      8.67%     94.52% |          34      4.34%     98.85% |           9      1.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          784                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size            1                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket            9                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples            3                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean            1                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean            1                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           3    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total            3                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          777                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean   572.888031                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean   503.124564                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev   181.530163                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |          66      8.49%      8.49% |           8      1.03%      9.52% |           5      0.64%     10.17% |          55      7.08%     17.25% |         369     47.49%     64.74% |         220     28.31%     93.05% |          53      6.82%     99.87% |           1      0.13%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          777                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size            2                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket           19                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples            5                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples           11                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean           11                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean    11.000000                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total            5                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           16                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          159                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples           49                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    62.795918                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    58.603527                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    25.717196                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           6     12.24%     12.24% |           1      2.04%     14.29% |          27     55.10%     69.39% |           9     18.37%     87.76% |           3      6.12%     93.88% |           1      2.04%     95.92% |           0      0.00%     95.92% |           0      0.00%     95.92% |           2      4.08%    100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total           49                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size           64                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket          639                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          11    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total           11                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples           52                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    56.153846                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    51.160387                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    25.308593                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |          14     26.92%     26.92% |          19     36.54%     63.46% |          18     34.62%     98.08% |           0      0.00%     98.08% |           0      0.00%     98.08% |           1      1.92%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total           52                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size          128                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket         1279                      
 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::samples            2                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::mean          527                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::gmean   526.885187                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::stdev    15.556349                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::mean   477.500000                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::gmean   204.484718                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::stdev   610.233152                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::total            2                      
-system.ruby.Directory_Controller.GETX             785      0.00%      0.00%
-system.ruby.Directory_Controller.GETS              90      0.00%      0.00%
-system.ruby.Directory_Controller.PUT             1118      0.00%      0.00%
-system.ruby.Directory_Controller.UnblockM          871      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Clean           77      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Dirty          790      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          874      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          790      0.00%      0.00%
+system.ruby.Directory_Controller.GETX             778      0.00%      0.00%
+system.ruby.Directory_Controller.GETS              84      0.00%      0.00%
+system.ruby.Directory_Controller.PUT             1099      0.00%      0.00%
+system.ruby.Directory_Controller.UnblockM          859      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Clean           71      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Dirty          782      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          861      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          782      0.00%      0.00%
 system.ruby.Directory_Controller.GETF               2      0.00%      0.00%
 system.ruby.Directory_Controller.PUTF               2      0.00%      0.00%
-system.ruby.Directory_Controller.NO.PUT           867      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETX           785      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETS            89      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETF             2      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.PUT          251      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.UnblockM          871      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_W.Memory_Data          872      0.00%      0.00%
+system.ruby.Directory_Controller.NO.PUT           853      0.00%      0.00%
+system.ruby.Directory_Controller.NO.GETF            1      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETX           778      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETS            83      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETF             1      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.PUT          246      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.UnblockM          859      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_W.Memory_Data          860      0.00%      0.00%
 system.ruby.Directory_Controller.WB.GETS            1      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean           77      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty          790      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.Memory_Ack          790      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean           71      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty          782      0.00%      0.00%
+system.ruby.Directory_Controller.WB_E_W.Memory_Ack          782      0.00%      0.00%
 system.ruby.Directory_Controller.NO_F.PUTF            2      0.00%      0.00%
-system.ruby.Directory_Controller.NO_F_W.Memory_Data            2      0.00%      0.00%
-system.ruby.L1Cache_Controller.Load                44      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch              59      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store              942      0.00%      0.00%
-system.ruby.L1Cache_Controller.L2_Replacement          867      0.00%      0.00%
-system.ruby.L1Cache_Controller.L1_to_L2         18224      0.00%      0.00%
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1D           34      0.00%      0.00%
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1I            5      0.00%      0.00%
-system.ruby.L1Cache_Controller.Complete_L2_to_L1           39      0.00%      0.00%
-system.ruby.L1Cache_Controller.Exclusive_Data          874      0.00%      0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack          869      0.00%      0.00%
-system.ruby.L1Cache_Controller.All_acks_no_sharers          874      0.00%      0.00%
+system.ruby.Directory_Controller.NO_F_W.Memory_Data            1      0.00%      0.00%
+system.ruby.L1Cache_Controller.Load                39      0.00%      0.00%
+system.ruby.L1Cache_Controller.Ifetch              64      0.00%      0.00%
+system.ruby.L1Cache_Controller.Store              934      0.00%      0.00%
+system.ruby.L1Cache_Controller.L2_Replacement          853      0.00%      0.00%
+system.ruby.L1Cache_Controller.L1_to_L2         18403      0.00%      0.00%
+system.ruby.L1Cache_Controller.Trigger_L2_to_L1D           44      0.00%      0.00%
+system.ruby.L1Cache_Controller.Trigger_L2_to_L1I           11      0.00%      0.00%
+system.ruby.L1Cache_Controller.Complete_L2_to_L1           55      0.00%      0.00%
+system.ruby.L1Cache_Controller.Exclusive_Data          861      0.00%      0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack          855      0.00%      0.00%
+system.ruby.L1Cache_Controller.All_acks_no_sharers          861      0.00%      0.00%
 system.ruby.L1Cache_Controller.Flush_line            2      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Load              40      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Ifetch            49      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Store            785      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Flush_line            2      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Ifetch             2      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Store              1      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.L2_Replacement           76      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.L1_to_L2           85      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D            9      0.00%      0.00%
+system.ruby.L1Cache_Controller.Block_Ack            1      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Load              31      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Ifetch            52      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Store            778      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Flush_line            1      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.L2_Replacement           71      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.L1_to_L2           81      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D           10      0.00%      0.00%
 system.ruby.L1Cache_Controller.MM.Load              4      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.Ifetch            1      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.Store            91      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.L2_Replacement          791      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.L1_to_L2          823      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D           25      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I            5      0.00%      0.00%
-system.ruby.L1Cache_Controller.MR.Store             9      0.00%      0.00%
-system.ruby.L1Cache_Controller.MR.L1_to_L2          116      0.00%      0.00%
-system.ruby.L1Cache_Controller.MMR.Ifetch            5      0.00%      0.00%
-system.ruby.L1Cache_Controller.MMR.Store           25      0.00%      0.00%
-system.ruby.L1Cache_Controller.MMR.L1_to_L2            2      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.L1_to_L2        10757      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data          784      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_W.L1_to_L2          187      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers           88      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_W.L1_to_L2         5531      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers          784      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.L1_to_L2          475      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data           88      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.Store            75      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.L2_Replacement          782      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.L1_to_L2          829      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D           34      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I           11      0.00%      0.00%
+system.ruby.L1Cache_Controller.MR.Store            10      0.00%      0.00%
+system.ruby.L1Cache_Controller.MR.L1_to_L2          114      0.00%      0.00%
+system.ruby.L1Cache_Controller.MMR.Load             2      0.00%      0.00%
+system.ruby.L1Cache_Controller.MMR.Ifetch           11      0.00%      0.00%
+system.ruby.L1Cache_Controller.MMR.Store           31      0.00%      0.00%
+system.ruby.L1Cache_Controller.MMR.L1_to_L2           14      0.00%      0.00%
+system.ruby.L1Cache_Controller.MMR.Flush_line            1      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.L1_to_L2        10904      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data          777      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_W.L1_to_L2          223      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers           83      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_W.L1_to_L2         5430      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers          777      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.L1_to_L2          455      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data           83      0.00%      0.00%
 system.ruby.L1Cache_Controller.MI.Ifetch            1      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack          867      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI.Store             1      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack          853      0.00%      0.00%
 system.ruby.L1Cache_Controller.MT.Store             9      0.00%      0.00%
-system.ruby.L1Cache_Controller.MT.L1_to_L2          118      0.00%      0.00%
-system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1            9      0.00%      0.00%
-system.ruby.L1Cache_Controller.MMT.Ifetch            1      0.00%      0.00%
-system.ruby.L1Cache_Controller.MMT.Store           22      0.00%      0.00%
-system.ruby.L1Cache_Controller.MMT.L1_to_L2          130      0.00%      0.00%
-system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1           30      0.00%      0.00%
+system.ruby.L1Cache_Controller.MT.L1_to_L2          130      0.00%      0.00%
+system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1           10      0.00%      0.00%
+system.ruby.L1Cache_Controller.MMT.Load             2      0.00%      0.00%
+system.ruby.L1Cache_Controller.MMT.Store           30      0.00%      0.00%
+system.ruby.L1Cache_Controller.MMT.L1_to_L2          223      0.00%      0.00%
+system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1           45      0.00%      0.00%
 system.ruby.L1Cache_Controller.MI_F.Writeback_Ack            2      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM_F.Exclusive_Data            2      0.00%      0.00%
-system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers            2      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_F.Block_Ack            1      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM_F.Exclusive_Data            1      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers            1      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
index ffe5cd6c7..9f41aca8f 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
 memories=system.mem_ctrls
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -54,8 +59,13 @@ check_flush=false
 checks_to_complete=100
 clk_domain=system.clk_domain
 deadlock_threshold=50000
+default_p_state=UNDEFINED
 eventq_index=0
 num_cpus=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 system=system
 wakeup_frequency=10
 cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
@@ -70,27 +80,27 @@ transition_latency=100000
 
 [system.mem_ctrls]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -102,6 +112,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -109,12 +120,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10
@@ -136,9 +152,9 @@ tRTW=3
 tWR=15
 tWTR=8
 tXAW=30
-tXP=0
+tXP=6
 tXPDLL=0
-tXS=0
+tXS=270
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -152,12 +168,17 @@ access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 phys_mem=Null
+power_model=Null
 randomization=true
 
 [system.ruby.clk_domain]
@@ -174,6 +195,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
@@ -181,6 +203,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
 eventq_index=0
 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestToDir=system.ruby.dir_cntrl0.requestToDir
 responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -254,11 +280,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
 cluster_id=0
+default_p_state=UNDEFINED
 eventq_index=0
 forwardToCache=system.ruby.l1_cntrl0.forwardToCache
 issue_latency=2
 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
 number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 recycle_latency=10
 requestFromCache=system.ruby.l1_cntrl0.requestFromCache
 responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -340,17 +371,22 @@ coreid=99
 dcache=system.ruby.l1_cntrl0.cacheMemory
 dcache_hit_latency=1
 deadlock_threshold=500000
+default_p_state=UNDEFINED
 eventq_index=0
+garnet_standalone=false
 icache=system.ruby.l1_cntrl0.cacheMemory
 icache_hit_latency=1
 is_cpu_sequencer=true
 max_outstanding_requests=16
 no_retry_on_stall=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
 system=system
-using_network_tester=false
 using_ruby_tester=true
 version=0
 slave=system.cpu.cpuInstDataPort[0]
@@ -363,18 +399,23 @@ eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
 adaptive_routing=false
 buffer_size=0
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
+default_p_state=UNDEFINED
 endpoint_bandwidth=1000
 eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
 netifs=
 number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
 ruby_system=system.ruby
 topology=Crossbar
@@ -541,32 +582,206 @@ eventq_index=0
 ordered=true
 randomization=false
 
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
 weight=1
 
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
 eventq_index=0
 latency=1
 link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
 weight=1
 
 [system.ruby.network.routers0]
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14
+power_model=Null
 router_id=0
 virt_nets=5
 
@@ -679,8 +894,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14
+power_model=Null
 router_id=1
 virt_nets=5
 
@@ -793,8 +1014,14 @@ randomization=false
 type=Switch
 children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19
 clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19
+power_model=Null
 router_id=2
 virt_nets=5
 
@@ -941,9 +1168,14 @@ randomization=false
 [system.sys_port_proxy]
 type=RubyPortProxy
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_cpu_sequencer=true
 no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
index c2086c0ba..cee0dfc57 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
@@ -4,7 +4,5 @@ warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: rounding error > tolerance
     1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
index e720ac2ac..cd24395f8 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:27
-gem5 executing on zizzer, pid 34085
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:45
+gem5 executing on e108600-lin, pid 28072
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby
 
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 37741 because Ruby Tester completed
+Exiting @ tick 39431 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index 4e47c8bcd..0fabd5bae 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -1,45 +1,45 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000038                       # Number of seconds simulated
-sim_ticks                                       37741                       # Number of ticks simulated
-final_tick                                      37741                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000039                       # Number of seconds simulated
+sim_ticks                                       39431                       # Number of ticks simulated
+final_tick                                      39431                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 891959                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 449872                       # Number of bytes of host memory used
+host_tick_rate                                 979592                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 407616                       # Number of bytes of host memory used
 host_seconds                                     0.04                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        37741                       # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0        60992                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total              60992                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0        60800                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total           60800                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0          953                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total                 953                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0          950                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total                950                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0   1616067407                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total            1616067407                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0   1610980101                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total           1610980101                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   3227047508                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           3227047508                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                         953                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                        950                       # Number of write requests accepted
-system.mem_ctrls.readBursts                       953                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                      950                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  52800                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                    8192                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   51456                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                   60992                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys                60800                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    128                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   117                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED        39431                       # Cumulative time (in ticks) in various power states
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0        60224                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total              60224                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0        60032                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total           60032                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0          941                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total                 941                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0          938                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total                938                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0   1527326215                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total            1527326215                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0   1522456950                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total           1522456950                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0   3049783166                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total           3049783166                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                         941                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                        938                       # Number of write requests accepted
+system.mem_ctrls.readBursts                       941                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                      938                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM                  50560                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                    9664                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                   49728                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                   60224                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys                60032                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                    151                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   134                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
 system.mem_ctrls.perBankRdBursts::0               259                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1               251                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2               261                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3                54                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1               247                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2               238                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3                46                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::5                 0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::6                 0                       # Per bank write bursts
@@ -52,10 +52,10 @@ system.mem_ctrls.perBankRdBursts::12                0                       # Pe
 system.mem_ctrls.perBankRdBursts::13                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::14                0                       # Per bank write bursts
 system.mem_ctrls.perBankRdBursts::15                0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0               255                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1               246                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2               250                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3                53                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0               258                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1               243                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2               232                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3                44                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::4                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::5                 0                       # Per bank write bursts
 system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
@@ -70,23 +70,23 @@ system.mem_ctrls.perBankWrBursts::14                0                       # Pe
 system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                         37680                       # Total gap between requests
+system.mem_ctrls.totGap                         39357                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                   953                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                   941                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6                  950                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     469                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                     355                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6                  938                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                     461                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                     328                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       1                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
@@ -133,24 +133,24 @@ system.mem_ctrls.wrQLenPdf::12                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::15                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     33                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                     51                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     51                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     51                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                     53                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     51                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     51                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                     51                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     51                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                     70                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     51                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                     51                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     50                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     50                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     50                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     50                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                     36                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                     47                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                     48                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                     49                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                     49                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                     52                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                     49                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                     49                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                     49                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                     51                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                     67                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                     48                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                     48                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                     48                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                     48                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                     48                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
@@ -181,340 +181,359 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          107                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    956.411215                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   902.763557                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   202.735209                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127            1      0.93%      0.93% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255            3      2.80%      3.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383            1      0.93%      4.67% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639            2      1.87%      6.54% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            4      3.74%     10.28% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895            2      1.87%     12.15% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023            1      0.93%     13.08% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           93     86.92%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          107                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples           50                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      16.240000                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     16.100110                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      2.766859                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15            11     22.00%     22.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            37     74.00%     96.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             1      2.00%     98.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35             1      2.00%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total            50                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples           50                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.080000                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.077788                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.274048                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               46     92.00%     92.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                4      8.00%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total            50                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                        10350                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   26025                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       4125                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        12.55                       # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples          108                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    925.629630                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   827.187599                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   260.509945                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127            4      3.70%      3.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255            3      2.78%      6.48% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383            2      1.85%      8.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511            2      1.85%     10.19% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639            1      0.93%     11.11% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767            1      0.93%     12.04% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895            1      0.93%     12.96% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023            3      2.78%     15.74% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151           91     84.26%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total          108                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples           48                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      16.229167                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean     16.080832                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev      2.837736                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15            10     20.83%     20.83% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17            37     77.08%     97.92% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35             1      2.08%    100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total            48                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples           48                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      16.187500                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     16.181743                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      0.445127                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16               40     83.33%     83.33% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17                7     14.58%     97.92% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18                1      2.08%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total            48                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                        14435                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat                   29445                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                       3950                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                        18.27                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   31.55                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                      1399.01                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                      1363.40                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                   1616.07                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                   1610.98                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                   37.27                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                      1282.24                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                      1261.14                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                   1527.33                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                   1522.46                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                        21.58                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                    10.93                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                   10.65                       # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen                       1.73                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      26.18                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      719                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     799                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 87.15                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                95.92                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         19.80                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    91.56                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   687960                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   382200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 8548800                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                6822144                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy              2034240                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             21405780                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy                65400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy               39946524                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower           1272.020252                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE           11                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF          1040                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         30367                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls.busUtil                        19.87                       # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead                    10.02                       # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite                    9.85                       # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen                       1.68                       # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      25.86                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                      690                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                     766                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 87.34                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                95.27                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                         20.95                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    91.34                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                   792540                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   417312                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 9024960                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                6489504                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         3073200.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy              9767064                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy                64896                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy         8135040                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy            1152                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy               37765668                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            957.765920                       # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime                17819                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE           29                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          1300                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            3                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         20259                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN        17840                       # Time in different power states
 system.mem_ctrls_1.actEnergy                        0                       # Energy for activate commands per rank (pJ)
 system.mem_ctrls_1.preEnergy                        0                       # Energy for precharge commands per rank (pJ)
 system.mem_ctrls_1.readEnergy                       0                       # Energy for read commands per rank (pJ)
 system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy              2034240                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy               673056                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy             18243600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy               20950896                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            667.438547                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE        30364                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          1040                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.refreshEnergy         1229280.000000                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy               224352                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              3002880                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy               0                       # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy         2889984                       # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy          5662320                       # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy               13008816                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            329.913418                       # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime                 7526                       # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE         7786                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF           526                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF        23593                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN         7526                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT             0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED        37741                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::UNDEFINED        37741                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED        39431                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED        39431                       # Cumulative time (in ticks) in various power states
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED        37741                       # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED        39431                       # Cumulative time (in ticks) in various power states
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
-system.ruby.delayHist::samples                   1903                       # delay histogram for all message
-system.ruby.delayHist::mean                  0.196532                       # delay histogram for all message
-system.ruby.delayHist::stdev                 1.062331                       # delay histogram for all message
-system.ruby.delayHist                    |        1839     96.64%     96.64% |           0      0.00%     96.64% |           2      0.11%     96.74% |           0      0.00%     96.74% |           1      0.05%     96.79% |           0      0.00%     96.79% |          61      3.21%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                     1903                       # delay histogram for all message
+system.ruby.delayHist::samples                   1878                       # delay histogram for all message
+system.ruby.delayHist::mean                  0.221512                       # delay histogram for all message
+system.ruby.delayHist::stdev                 1.129790                       # delay histogram for all message
+system.ruby.delayHist                    |        1808     96.27%     96.27% |           0      0.00%     96.27% |           1      0.05%     96.33% |           0      0.00%     96.33% |           0      0.00%     96.33% |           0      0.00%     96.33% |          69      3.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                     1878                       # delay histogram for all message
 system.ruby.outstanding_req_hist_seqr::bucket_size            2                      
 system.ruby.outstanding_req_hist_seqr::max_bucket           19                      
-system.ruby.outstanding_req_hist_seqr::samples         1005                      
-system.ruby.outstanding_req_hist_seqr::mean    15.609950                      
-system.ruby.outstanding_req_hist_seqr::gmean    15.502410                      
-system.ruby.outstanding_req_hist_seqr::stdev     1.236521                      
-system.ruby.outstanding_req_hist_seqr    |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.50% |           2      0.20%      0.70% |           4      0.40%      1.09% |           3      0.30%      1.39% |           4      0.40%      1.79% |         233     23.18%     24.98% |         754     75.02%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist_seqr::total         1005                      
+system.ruby.outstanding_req_hist_seqr::samples          997                      
+system.ruby.outstanding_req_hist_seqr::mean    15.607823                      
+system.ruby.outstanding_req_hist_seqr::gmean    15.499600                      
+system.ruby.outstanding_req_hist_seqr::stdev     1.240894                      
+system.ruby.outstanding_req_hist_seqr    |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.50% |           2      0.20%      0.70% |           4      0.40%      1.10% |           2      0.20%      1.30% |           4      0.40%      1.71% |         227     22.77%     24.47% |         753     75.53%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist_seqr::total          997                      
 system.ruby.latency_hist_seqr::bucket_size          128                      
 system.ruby.latency_hist_seqr::max_bucket         1279                      
-system.ruby.latency_hist_seqr::samples            992                      
-system.ruby.latency_hist_seqr::mean        594.351815                      
-system.ruby.latency_hist_seqr::gmean       584.578373                      
-system.ruby.latency_hist_seqr::stdev        96.099439                      
-system.ruby.latency_hist_seqr            |           2      0.20%      0.20% |           9      0.91%      1.11% |           6      0.60%      1.71% |         111     11.19%     12.90% |         654     65.93%     78.83% |         154     15.52%     94.35% |          49      4.94%     99.29% |           7      0.71%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist_seqr::total              992                      
+system.ruby.latency_hist_seqr::samples            982                      
+system.ruby.latency_hist_seqr::mean        622.683299                      
+system.ruby.latency_hist_seqr::gmean       611.609969                      
+system.ruby.latency_hist_seqr::stdev       106.877832                      
+system.ruby.latency_hist_seqr            |           2      0.20%      0.20% |           7      0.71%      0.92% |           6      0.61%      1.53% |          88      8.96%     10.49% |         458     46.64%     57.13% |         355     36.15%     93.28% |          33      3.36%     96.64% |          33      3.36%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist_seqr::total              982                      
 system.ruby.hit_latency_hist_seqr::bucket_size          128                      
 system.ruby.hit_latency_hist_seqr::max_bucket         1279                      
-system.ruby.hit_latency_hist_seqr::samples           39                      
-system.ruby.hit_latency_hist_seqr::mean    492.692308                      
-system.ruby.hit_latency_hist_seqr::gmean   488.844837                      
-system.ruby.hit_latency_hist_seqr::stdev    62.931522                      
-system.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      2.56%      2.56% |          22     56.41%     58.97% |          15     38.46%     97.44% |           1      2.56%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist_seqr::total           39                      
+system.ruby.hit_latency_hist_seqr::samples           42                      
+system.ruby.hit_latency_hist_seqr::mean    524.214286                      
+system.ruby.hit_latency_hist_seqr::gmean   519.360085                      
+system.ruby.hit_latency_hist_seqr::stdev    71.299963                      
+system.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          17     40.48%     40.48% |          24     57.14%     97.62% |           1      2.38%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist_seqr::total           42                      
 system.ruby.miss_latency_hist_seqr::bucket_size          128                      
 system.ruby.miss_latency_hist_seqr::max_bucket         1279                      
-system.ruby.miss_latency_hist_seqr::samples          953                      
-system.ruby.miss_latency_hist_seqr::mean   598.512067                      
-system.ruby.miss_latency_hist_seqr::gmean   588.872583                      
-system.ruby.miss_latency_hist_seqr::stdev    94.945507                      
-system.ruby.miss_latency_hist_seqr       |           2      0.21%      0.21% |           9      0.94%      1.15% |           5      0.52%      1.68% |          89      9.34%     11.02% |         639     67.05%     78.07% |         153     16.05%     94.12% |          49      5.14%     99.27% |           7      0.73%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist_seqr::total          953                      
-system.ruby.Directory.incomplete_times_seqr          953                      
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        37741                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.cacheMemory.demand_hits           39                       # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses          955                       # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses          994                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        37741                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            7                       # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store          129                       # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            6                       # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_load            1                       # Number of times a load aliased with a pending load
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        37741                       # Cumulative time (in ticks) in various power states
+system.ruby.miss_latency_hist_seqr::samples          940                      
+system.ruby.miss_latency_hist_seqr::mean   627.082979                      
+system.ruby.miss_latency_hist_seqr::gmean   616.094261                      
+system.ruby.miss_latency_hist_seqr::stdev   106.107284                      
+system.ruby.miss_latency_hist_seqr       |           2      0.21%      0.21% |           7      0.74%      0.96% |           6      0.64%      1.60% |          71      7.55%      9.15% |         434     46.17%     55.32% |         354     37.66%     92.98% |          33      3.51%     96.49% |          33      3.51%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist_seqr::total          940                      
+system.ruby.Directory.incomplete_times_seqr          940                      
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED        39431                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.cacheMemory.demand_hits           42                       # Number of cache demand hits
+system.ruby.l1_cntrl0.cacheMemory.demand_misses          941                       # Number of cache demand misses
+system.ruby.l1_cntrl0.cacheMemory.demand_accesses          983                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED        39431                       # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load           14                       # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store          141                       # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store           15                       # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED        39431                       # Cumulative time (in ticks) in various power states
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        37741                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized    12.606979                      
-system.ruby.network.routers0.msg_count.Control::2          953                      
-system.ruby.network.routers0.msg_count.Data::2          951                      
-system.ruby.network.routers0.msg_count.Response_Data::4          953                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3          950                      
-system.ruby.network.routers0.msg_bytes.Control::2         7624                      
-system.ruby.network.routers0.msg_bytes.Data::2        68472                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4        68616                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3         7600                      
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        37741                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized    12.605654                      
-system.ruby.network.routers1.msg_count.Control::2          953                      
-system.ruby.network.routers1.msg_count.Data::2          950                      
-system.ruby.network.routers1.msg_count.Response_Data::4          953                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3          950                      
-system.ruby.network.routers1.msg_bytes.Control::2         7624                      
-system.ruby.network.routers1.msg_bytes.Data::2        68400                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4        68616                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3         7600                      
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        37741                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized    12.605654                      
-system.ruby.network.routers2.msg_count.Control::2          953                      
-system.ruby.network.routers2.msg_count.Data::2          950                      
-system.ruby.network.routers2.msg_count.Response_Data::4          953                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3          950                      
-system.ruby.network.routers2.msg_bytes.Control::2         7624                      
-system.ruby.network.routers2.msg_bytes.Data::2        68400                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4        68616                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3         7600                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED        37741                       # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Control            2859                      
-system.ruby.network.msg_count.Data               2851                      
-system.ruby.network.msg_count.Response_Data         2859                      
-system.ruby.network.msg_count.Writeback_Control         2850                      
-system.ruby.network.msg_byte.Control            22872                      
-system.ruby.network.msg_byte.Data              205272                      
-system.ruby.network.msg_byte.Response_Data       205848                      
-system.ruby.network.msg_byte.Writeback_Control        22800                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        37741                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization    12.621552                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          953                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          950                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        68616                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         7600                      
-system.ruby.network.routers0.throttle1.link_utilization    12.592406                      
-system.ruby.network.routers0.throttle1.msg_count.Control::2          953                      
-system.ruby.network.routers0.throttle1.msg_count.Data::2          951                      
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2         7624                      
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2        68472                      
-system.ruby.network.routers1.throttle0.link_utilization    12.589756                      
-system.ruby.network.routers1.throttle0.msg_count.Control::2          953                      
-system.ruby.network.routers1.throttle0.msg_count.Data::2          950                      
-system.ruby.network.routers1.throttle0.msg_bytes.Control::2         7624                      
-system.ruby.network.routers1.throttle0.msg_bytes.Data::2        68400                      
-system.ruby.network.routers1.throttle1.link_utilization    12.621552                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          953                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          950                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        68616                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         7600                      
-system.ruby.network.routers2.throttle0.link_utilization    12.621552                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          953                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          950                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        68616                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         7600                      
-system.ruby.network.routers2.throttle1.link_utilization    12.589756                      
-system.ruby.network.routers2.throttle1.msg_count.Control::2          953                      
-system.ruby.network.routers2.throttle1.msg_count.Data::2          950                      
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2         7624                      
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2        68400                      
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED        39431                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized    11.905607                      
+system.ruby.network.routers0.msg_count.Control::2          941                      
+system.ruby.network.routers0.msg_count.Data::2          938                      
+system.ruby.network.routers0.msg_count.Response_Data::4          940                      
+system.ruby.network.routers0.msg_count.Writeback_Control::3          938                      
+system.ruby.network.routers0.msg_bytes.Control::2         7528                      
+system.ruby.network.routers0.msg_bytes.Data::2        67536                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4        67680                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3         7504                      
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED        39431                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized    11.910045                      
+system.ruby.network.routers1.msg_count.Control::2          941                      
+system.ruby.network.routers1.msg_count.Data::2          938                      
+system.ruby.network.routers1.msg_count.Response_Data::4          941                      
+system.ruby.network.routers1.msg_count.Writeback_Control::3          938                      
+system.ruby.network.routers1.msg_bytes.Control::2         7528                      
+system.ruby.network.routers1.msg_bytes.Data::2        67536                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4        67752                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3         7504                      
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED        39431                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized    11.907509                      
+system.ruby.network.routers2.msg_count.Control::2          941                      
+system.ruby.network.routers2.msg_count.Data::2          938                      
+system.ruby.network.routers2.msg_count.Response_Data::4          940                      
+system.ruby.network.routers2.msg_count.Writeback_Control::3          938                      
+system.ruby.network.routers2.msg_bytes.Control::2         7528                      
+system.ruby.network.routers2.msg_bytes.Data::2        67536                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4        67680                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3         7504                      
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED        39431                       # Cumulative time (in ticks) in various power states
+system.ruby.network.msg_count.Control            2823                      
+system.ruby.network.msg_count.Data               2814                      
+system.ruby.network.msg_count.Response_Data         2821                      
+system.ruby.network.msg_count.Writeback_Control         2814                      
+system.ruby.network.msg_byte.Control            22584                      
+system.ruby.network.msg_byte.Data              202608                      
+system.ruby.network.msg_byte.Response_Data       203112                      
+system.ruby.network.msg_byte.Writeback_Control        22512                      
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED        39431                       # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization    11.913215                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          940                      
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          938                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        67680                      
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         7504                      
+system.ruby.network.routers0.throttle1.link_utilization    11.897999                      
+system.ruby.network.routers0.throttle1.msg_count.Control::2          941                      
+system.ruby.network.routers0.throttle1.msg_count.Data::2          938                      
+system.ruby.network.routers0.throttle1.msg_bytes.Control::2         7528                      
+system.ruby.network.routers0.throttle1.msg_bytes.Data::2        67536                      
+system.ruby.network.routers1.throttle0.link_utilization    11.897999                      
+system.ruby.network.routers1.throttle0.msg_count.Control::2          941                      
+system.ruby.network.routers1.throttle0.msg_count.Data::2          938                      
+system.ruby.network.routers1.throttle0.msg_bytes.Control::2         7528                      
+system.ruby.network.routers1.throttle0.msg_bytes.Data::2        67536                      
+system.ruby.network.routers1.throttle1.link_utilization    11.922092                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          941                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          938                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        67752                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         7504                      
+system.ruby.network.routers2.throttle0.link_utilization    11.917020                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          940                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          938                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        67680                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         7504                      
+system.ruby.network.routers2.throttle1.link_utilization    11.897999                      
+system.ruby.network.routers2.throttle1.msg_count.Control::2          941                      
+system.ruby.network.routers2.throttle1.msg_count.Data::2          938                      
+system.ruby.network.routers2.throttle1.msg_bytes.Control::2         7528                      
+system.ruby.network.routers2.throttle1.msg_bytes.Data::2        67536                      
 system.ruby.delayVCHist.vnet_1::bucket_size            1                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket            9                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples           953                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |         953    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total             953                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples           940                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |         940    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total             940                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples           950                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean         0.393684                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev        1.477888                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |         886     93.26%     93.26% |           0      0.00%     93.26% |           2      0.21%     93.47% |           0      0.00%     93.47% |           1      0.11%     93.58% |           0      0.00%     93.58% |          61      6.42%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total             950                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples           938                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean         0.443497                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev        1.567923                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |         868     92.54%     92.54% |           0      0.00%     92.54% |           1      0.11%     92.64% |           0      0.00%     92.64% |           0      0.00%     92.64% |           0      0.00%     92.64% |          69      7.36%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total             938                       # delay histogram for vnet_2
 system.ruby.LD.latency_hist_seqr::bucket_size          128                      
 system.ruby.LD.latency_hist_seqr::max_bucket         1279                      
-system.ruby.LD.latency_hist_seqr::samples           50                      
-system.ruby.LD.latency_hist_seqr::mean     620.660000                      
-system.ruby.LD.latency_hist_seqr::gmean    616.355454                      
-system.ruby.LD.latency_hist_seqr::stdev     75.297399                      
-system.ruby.LD.latency_hist_seqr         |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3      6.00%      6.00% |          33     66.00%     72.00% |          10     20.00%     92.00% |           4      8.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist_seqr::total            50                      
+system.ruby.LD.latency_hist_seqr::samples           51                      
+system.ruby.LD.latency_hist_seqr::mean     632.509804                      
+system.ruby.LD.latency_hist_seqr::gmean    625.135320                      
+system.ruby.LD.latency_hist_seqr::stdev     99.959466                      
+system.ruby.LD.latency_hist_seqr         |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           6     11.76%     11.76% |          20     39.22%     50.98% |          21     41.18%     92.16% |           2      3.92%     96.08% |           2      3.92%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist_seqr::total            51                      
+system.ruby.LD.hit_latency_hist_seqr::bucket_size           64                      
+system.ruby.LD.hit_latency_hist_seqr::max_bucket          639                      
+system.ruby.LD.hit_latency_hist_seqr::samples            2                      
+system.ruby.LD.hit_latency_hist_seqr::mean          576                      
+system.ruby.LD.hit_latency_hist_seqr::gmean   575.579708                      
+system.ruby.LD.hit_latency_hist_seqr::stdev    31.112698                      
+system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00%
+system.ruby.LD.hit_latency_hist_seqr::total            2                      
 system.ruby.LD.miss_latency_hist_seqr::bucket_size          128                      
 system.ruby.LD.miss_latency_hist_seqr::max_bucket         1279                      
-system.ruby.LD.miss_latency_hist_seqr::samples           50                      
-system.ruby.LD.miss_latency_hist_seqr::mean   620.660000                      
-system.ruby.LD.miss_latency_hist_seqr::gmean   616.355454                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    75.297399                      
-system.ruby.LD.miss_latency_hist_seqr    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3      6.00%      6.00% |          33     66.00%     72.00% |          10     20.00%     92.00% |           4      8.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist_seqr::total           50                      
+system.ruby.LD.miss_latency_hist_seqr::samples           49                      
+system.ruby.LD.miss_latency_hist_seqr::mean   634.816327                      
+system.ruby.LD.miss_latency_hist_seqr::gmean   627.246231                      
+system.ruby.LD.miss_latency_hist_seqr::stdev   101.240159                      
+system.ruby.LD.miss_latency_hist_seqr    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           6     12.24%     12.24% |          18     36.73%     48.98% |          21     42.86%     91.84% |           2      4.08%     95.92% |           2      4.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist_seqr::total           49                      
 system.ruby.ST.latency_hist_seqr::bucket_size          128                      
 system.ruby.ST.latency_hist_seqr::max_bucket         1279                      
-system.ruby.ST.latency_hist_seqr::samples          892                      
-system.ruby.ST.latency_hist_seqr::mean     591.263453                      
-system.ruby.ST.latency_hist_seqr::gmean    581.152835                      
-system.ruby.ST.latency_hist_seqr::stdev     96.524225                      
-system.ruby.ST.latency_hist_seqr         |           2      0.22%      0.22% |           9      1.01%      1.23% |           6      0.67%      1.91% |         103     11.55%     13.45% |         591     66.26%     79.71% |         135     15.13%     94.84% |          39      4.37%     99.22% |           7      0.78%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist_seqr::total           892                      
+system.ruby.ST.latency_hist_seqr::samples          882                      
+system.ruby.ST.latency_hist_seqr::mean     621.007937                      
+system.ruby.ST.latency_hist_seqr::gmean    609.588661                      
+system.ruby.ST.latency_hist_seqr::stdev    107.265659                      
+system.ruby.ST.latency_hist_seqr         |           2      0.23%      0.23% |           7      0.79%      1.02% |           6      0.68%      1.70% |          78      8.84%     10.54% |         414     46.94%     57.48% |         318     36.05%     93.54% |          29      3.29%     96.83% |          28      3.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist_seqr::total           882                      
 system.ruby.ST.hit_latency_hist_seqr::bucket_size          128                      
 system.ruby.ST.hit_latency_hist_seqr::max_bucket         1279                      
 system.ruby.ST.hit_latency_hist_seqr::samples           38                      
-system.ruby.ST.hit_latency_hist_seqr::mean   491.526316                      
-system.ruby.ST.hit_latency_hist_seqr::gmean   487.637688                      
-system.ruby.ST.hit_latency_hist_seqr::stdev    63.347918                      
-system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      2.63%      2.63% |          22     57.89%     60.53% |          14     36.84%     97.37% |           1      2.63%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist_seqr::mean   517.263158                      
+system.ruby.ST.hit_latency_hist_seqr::gmean   512.460135                      
+system.ruby.ST.hit_latency_hist_seqr::stdev    71.032419                      
+system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          17     44.74%     44.74% |          20     52.63%     97.37% |           1      2.63%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.hit_latency_hist_seqr::total           38                      
 system.ruby.ST.miss_latency_hist_seqr::bucket_size          128                      
 system.ruby.ST.miss_latency_hist_seqr::max_bucket         1279                      
-system.ruby.ST.miss_latency_hist_seqr::samples          854                      
-system.ruby.ST.miss_latency_hist_seqr::mean   595.701405                      
-system.ruby.ST.miss_latency_hist_seqr::gmean   585.707367                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    95.367967                      
-system.ruby.ST.miss_latency_hist_seqr    |           2      0.23%      0.23% |           9      1.05%      1.29% |           5      0.59%      1.87% |          81      9.48%     11.36% |         577     67.56%     78.92% |         134     15.69%     94.61% |          39      4.57%     99.18% |           7      0.82%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist_seqr::total          854                      
+system.ruby.ST.miss_latency_hist_seqr::samples          844                      
+system.ruby.ST.miss_latency_hist_seqr::mean   625.678910                      
+system.ruby.ST.miss_latency_hist_seqr::gmean   614.370879                      
+system.ruby.ST.miss_latency_hist_seqr::stdev   106.283167                      
+system.ruby.ST.miss_latency_hist_seqr    |           2      0.24%      0.24% |           7      0.83%      1.07% |           6      0.71%      1.78% |          61      7.23%      9.00% |         394     46.68%     55.69% |         317     37.56%     93.25% |          29      3.44%     96.68% |          28      3.32%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist_seqr::total          844                      
 system.ruby.IFETCH.latency_hist_seqr::bucket_size          128                      
 system.ruby.IFETCH.latency_hist_seqr::max_bucket         1279                      
-system.ruby.IFETCH.latency_hist_seqr::samples           50                      
-system.ruby.IFETCH.latency_hist_seqr::mean   623.140000                      
-system.ruby.IFETCH.latency_hist_seqr::gmean   615.727796                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    99.820044                      
-system.ruby.IFETCH.latency_hist_seqr     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5     10.00%     10.00% |          30     60.00%     70.00% |           9     18.00%     88.00% |           6     12.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist_seqr::total           50                      
+system.ruby.IFETCH.latency_hist_seqr::samples           49                      
+system.ruby.IFETCH.latency_hist_seqr::mean   642.612245                      
+system.ruby.IFETCH.latency_hist_seqr::gmean   634.549482                      
+system.ruby.IFETCH.latency_hist_seqr::stdev   106.327289                      
+system.ruby.IFETCH.latency_hist_seqr     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           4      8.16%      8.16% |          24     48.98%     57.14% |          16     32.65%     89.80% |           2      4.08%     93.88% |           3      6.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist_seqr::total           49                      
 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size           64                      
 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket          639                      
-system.ruby.IFETCH.hit_latency_hist_seqr::samples            1                      
-system.ruby.IFETCH.hit_latency_hist_seqr::mean          537                      
-system.ruby.IFETCH.hit_latency_hist_seqr::gmean   537.000000                      
-system.ruby.IFETCH.hit_latency_hist_seqr::stdev          nan                      
-system.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total            1                      
+system.ruby.IFETCH.hit_latency_hist_seqr::samples            2                      
+system.ruby.IFETCH.hit_latency_hist_seqr::mean   604.500000                      
+system.ruby.IFETCH.hit_latency_hist_seqr::gmean   604.216848                      
+system.ruby.IFETCH.hit_latency_hist_seqr::stdev    26.162951                      
+system.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist_seqr::total            2                      
 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size          128                      
 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket         1279                      
-system.ruby.IFETCH.miss_latency_hist_seqr::samples           49                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean   624.897959                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean   617.449297                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev   100.069402                      
-system.ruby.IFETCH.miss_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5     10.20%     10.20% |          29     59.18%     69.39% |           9     18.37%     87.76% |           6     12.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist_seqr::total           49                      
+system.ruby.IFETCH.miss_latency_hist_seqr::samples           47                      
+system.ruby.IFETCH.miss_latency_hist_seqr::mean   644.234043                      
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean   635.873481                      
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev   108.241922                      
+system.ruby.IFETCH.miss_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           4      8.51%      8.51% |          22     46.81%     55.32% |          16     34.04%     89.36% |           2      4.26%     93.62% |           3      6.38%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::total           47                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size          128                      
 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket         1279                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples          953                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean   598.512067                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean   588.872583                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    94.945507                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |           2      0.21%      0.21% |           9      0.94%      1.15% |           5      0.52%      1.68% |          89      9.34%     11.02% |         639     67.05%     78.07% |         153     16.05%     94.12% |          49      5.14%     99.27% |           7      0.73%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total          953                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::samples          940                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean   627.082979                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean   616.094261                      
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev   106.107284                      
+system.ruby.Directory.miss_mach_latency_hist_seqr |           2      0.21%      0.21% |           7      0.74%      0.96% |           6      0.64%      1.60% |          71      7.55%      9.15% |         434     46.17%     55.32% |         354     37.66%     92.98% |          33      3.51%     96.49% |          33      3.51%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::total          940                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size          128                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket         1279                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples           50                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean   620.660000                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean   616.355454                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    75.297399                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3      6.00%      6.00% |          33     66.00%     72.00% |          10     20.00%     92.00% |           4      8.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total           50                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples           49                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean   634.816327                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean   627.246231                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev   101.240159                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           6     12.24%     12.24% |          18     36.73%     48.98% |          21     42.86%     91.84% |           2      4.08%     95.92% |           2      4.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total           49                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size          128                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket         1279                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          854                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean   595.701405                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean   585.707367                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    95.367967                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           2      0.23%      0.23% |           9      1.05%      1.29% |           5      0.59%      1.87% |          81      9.48%     11.36% |         577     67.56%     78.92% |         134     15.69%     94.61% |          39      4.57%     99.18% |           7      0.82%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          854                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          844                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean   625.678910                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean   614.370879                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev   106.283167                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           2      0.24%      0.24% |           7      0.83%      1.07% |           6      0.71%      1.78% |          61      7.23%      9.00% |         394     46.68%     55.69% |         317     37.56%     93.25% |          29      3.44%     96.68% |          28      3.32%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          844                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size          128                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket         1279                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples           49                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean   624.897959                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean   617.449297                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev   100.069402                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5     10.20%     10.20% |          29     59.18%     69.39% |           9     18.37%     87.76% |           6     12.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total           49                      
-system.ruby.Directory_Controller.GETX             953      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX             950      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          953      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          950      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETX           953      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX           950      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data          953      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack          950      0.00%      0.00%
-system.ruby.L1Cache_Controller.Load                50      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch              51      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store              893      0.00%      0.00%
-system.ruby.L1Cache_Controller.Data               953      0.00%      0.00%
-system.ruby.L1Cache_Controller.Replacement          952      0.00%      0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack          950      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Load              50      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Ifetch            50      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Store            855      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Ifetch             1      0.00%      0.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples           47                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean   644.234043                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean   635.873481                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev   108.241922                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           4      8.51%      8.51% |          22     46.81%     55.32% |          16     34.04%     89.36% |           2      4.26%     93.62% |           3      6.38%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total           47                      
+system.ruby.Directory_Controller.GETX             941      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX             938      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          941      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          938      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX           941      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX           938      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data          941      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack          938      0.00%      0.00%
+system.ruby.L1Cache_Controller.Load                51      0.00%      0.00%
+system.ruby.L1Cache_Controller.Ifetch              49      0.00%      0.00%
+system.ruby.L1Cache_Controller.Store              883      0.00%      0.00%
+system.ruby.L1Cache_Controller.Data               940      0.00%      0.00%
+system.ruby.L1Cache_Controller.Replacement          938      0.00%      0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack          938      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Load              49      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Ifetch            47      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Store            845      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Load               2      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Ifetch             2      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.Store             38      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Replacement          952      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack          950      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Data             99      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Data            854      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Replacement          938      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack          938      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Data             96      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Data            844      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
index 07db75ab6..52ae02408 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler membus monitor physmem
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 readfile=
 symbolfile=
 thermal_components=
@@ -57,9 +62,15 @@ voltage=1.000000
 [system.cpu]
 type=TrafficGen
 clk_domain=system.clk_domain
-config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
+config_file=/work/curdun01/gem5-external.hg/tests/testing/../../tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
+default_p_state=UNDEFINED
 elastic_req=false
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+progress_check=1000000000
 system=system
 port=system.monitor.slave
 
@@ -74,9 +85,14 @@ transition_latency=100000000
 [system.membus]
 type=NoncoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=1
 frontend_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 response_latency=2
 use_default_range=false
 width=16
@@ -88,6 +104,7 @@ type=CommMonitor
 bandwidth_bins=20
 burst_length_bins=20
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 disable_addr_dists=true
 disable_bandwidth_hists=false
 disable_burst_length_hists=false
@@ -100,6 +117,10 @@ itt_bins=20
 itt_max_bin=100000
 latency_bins=20
 outstanding_bins=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 read_addr_mask=18446744073709551615
 sample_period=1000000000
 system=system
@@ -110,27 +131,27 @@ slave=system.cpu.port
 
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -142,6 +163,7 @@ burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -149,12 +171,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
-range=0:134217727
+power_model=Null
+range=0:134217727:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -176,9 +203,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout
index cf720d597..160888b39 100755
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl/simout
+Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 21 2016 14:20:17
-gem5 started Jan 21 2016 14:20:32
-gem5 executing on zizzer, pid 63117
-command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl -re /z/atgutier/gem5/gem5-commit/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl
+gem5 compiled Oct 13 2016 20:37:50
+gem5 started Oct 13 2016 20:38:05
+gem5 executing on e108600-lin, pid 342
+command line: /work/curdun01/gem5-external.hg/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.tgen/null/none/tgen-dram-ctrl
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
index c0bb5bc83..5d77460fc 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.100000                       # Nu
 sim_ticks                                100000000000                       # Number of ticks simulated
 final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                            10668065661                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 263968                       # Number of bytes of host memory used
-host_seconds                                     9.37                       # Real time elapsed on the host
+host_tick_rate                             5948382023                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222508                       # Number of bytes of host memory used
+host_seconds                                    16.81                       # Real time elapsed on the host
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.pwrStateResidencyTicks::UNDEFINED 100000000000                       # Cumulative time (in ticks) in various power states
@@ -28,45 +28,45 @@ system.physmem.readReqs                       1666397                       # Nu
 system.physmem.writeReqs                      1666879                       # Number of write requests accepted
 system.physmem.readBursts                     1666397                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                    1666879                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                106648000                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      1408                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 106676992                       # Total number of bytes written to DRAM
+system.physmem.bytesReadDRAM                106647808                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      1600                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 106676416                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                 106649408                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys              106680256                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       22                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      30                       # Number of DRAM write bursts merged with an existing one
+system.physmem.servicedByWrQ                       25                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      31                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              104030                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              104029                       # Per bank write bursts
 system.physmem.perBankRdBursts::1              103995                       # Per bank write bursts
 system.physmem.perBankRdBursts::2              104918                       # Per bank write bursts
 system.physmem.perBankRdBursts::3              104597                       # Per bank write bursts
 system.physmem.perBankRdBursts::4              103869                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              103934                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              103933                       # Per bank write bursts
 system.physmem.perBankRdBursts::6              103649                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              104312                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              104313                       # Per bank write bursts
 system.physmem.perBankRdBursts::8              103869                       # Per bank write bursts
 system.physmem.perBankRdBursts::9              104354                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             103835                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             104273                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             104076                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             103834                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             104271                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             104077                       # Per bank write bursts
 system.physmem.perBankRdBursts::13             104035                       # Per bank write bursts
 system.physmem.perBankRdBursts::14             104583                       # Per bank write bursts
 system.physmem.perBankRdBursts::15             104046                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              104357                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              104091                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              104356                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              104090                       # Per bank write bursts
 system.physmem.perBankWrBursts::2              104175                       # Per bank write bursts
 system.physmem.perBankWrBursts::3              103885                       # Per bank write bursts
 system.physmem.perBankWrBursts::4              104730                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              104509                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              104084                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              104226                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              104319                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              104507                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              104083                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              104224                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              104317                       # Per bank write bursts
 system.physmem.perBankWrBursts::9              104219                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             104227                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             104226                       # Per bank write bursts
 system.physmem.perBankWrBursts::11             103701                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             104102                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             104104                       # Per bank write bursts
 system.physmem.perBankWrBursts::13             103984                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             104296                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             104295                       # Per bank write bursts
 system.physmem.perBankWrBursts::15             103923                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
@@ -85,25 +85,25 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                1666879                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    753402                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    771059                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     83025                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     32311                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     12865                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6959                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3834                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1736                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       711                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       362                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       94                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       14                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    733345                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    766437                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    105881                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     41900                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     12740                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      3643                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      1163                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       473                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       265                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       141                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       64                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       64                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                       32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                       32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       64                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       32                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
@@ -132,32 +132,32 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    12106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    15091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    39564                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    91518                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   104735                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   104786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   114835                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   116330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   106236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   102201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   124996                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   116244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   105513                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   101800                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   100156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   100074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    99950                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    99852                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     3792                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     2888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      621                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    10965                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    13956                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    32108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    80984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                   108644                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   106582                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   109181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   116667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   116376                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   107705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   108162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   128453                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   112926                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   102716                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   100795                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   100305                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   100289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   100289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     4132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2753                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1624                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      822                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      299                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
@@ -181,98 +181,106 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      3296341                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean       64.715538                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      64.191659                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev      23.992392                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        3288436     99.76%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         5750      0.17%     99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples      3296279                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean       64.716502                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      64.191055                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev      24.099997                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        3288385     99.76%     99.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         5777      0.18%     99.94% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383           32      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           32      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           32      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           32      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           32      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           32      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         1963      0.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        3296341                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         99183                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        16.800984                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       15.462609                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      106.039262                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          99182    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::384-511            2      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            1      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           64      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           31      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         1986      0.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        3296279                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         99671                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        16.718725                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       15.378386                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      105.780207                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047          99670    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::32768-34815            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           99183                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         99183                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.805582                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.725629                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.745457                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              77723     78.36%     78.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               3827      3.86%     82.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               3399      3.43%     85.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1646      1.66%     87.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                640      0.65%     87.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21              10486     10.57%     98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22               1261      1.27%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 65      0.07%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 41      0.04%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 31      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 25      0.03%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 19      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  6      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  9      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  4      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           99183                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    59888739257                       # Total ticks spent queuing
-system.physmem.totMemAccLat               91133270507                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   8331875000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       35939.53                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           99671                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         99670                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.723337                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.645091                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.734543                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              81521     81.79%     81.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               3623      3.63%     85.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               1868      1.87%     87.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                729      0.73%     88.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                852      0.85%     88.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21               7918      7.94%     96.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22               2886      2.90%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                125      0.13%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 64      0.06%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 33      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 22      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 19      0.02%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  8      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           99670                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    67244030509                       # Total ticks spent queuing
+system.physmem.totMemAccLat               98488505509                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   8331860000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       40353.55                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  54689.53                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  59103.55                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                        1066.48                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                        1066.77                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                        1066.76                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                     1066.49                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                     1066.80                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                          16.67                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       8.33                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      8.33                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.70                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.41                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      32158                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                      4696                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         1.72                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.49                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      32189                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                      4714                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                    1.93                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                   0.28                       # Row buffer hit rate for writes
 system.physmem.avgGap                        30000.50                       # Average gap between requests
 system.physmem.pageHitRate                       1.11                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                12463748640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 6800656500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6499693200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5404585680                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             6531436080                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            67774130595                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy              548449500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             106022700195                       # Total energy per rank (pJ)
-system.physmem_0.averagePower             1060.236875                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE      533126864                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      3339180000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     96126775636                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                12456264240                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 6796572750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                6497883600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5396252400                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             6531436080                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            67770272835                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy              551833500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             106000515405                       # Total energy per rank (pJ)
-system.physmem_1.averagePower             1060.015025                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE      539825532                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      3339180000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     96120321460                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_0.actEnergy                11770732680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 6256266225                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5949783420                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4353725340                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           7874767680.000002                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            23951915280                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy              170961120                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       21181523760                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy          86810400                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy           93287040                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy              81689772945                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              816.897729                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime            47012409463                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE       55286905                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      3331216000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF      351864100                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN    225022822                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     49601087632                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  46435522541                       # Time in different power states
+system.physmem_1.actEnergy                11764756500                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 6253097400                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5948112660                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4347048960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           7875382320.000002                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            23997343140                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy              173667360                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       21132301410                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy          86542080                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy           94312680                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy              81672564510                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              816.725645                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime            46910670248                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE       62942667                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      3331488000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF      353836348                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN    224863707                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     49694899085                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  46331970193                       # Time in different power states
 system.pwrStateResidencyTicks::UNDEFINED 100000000000                       # Cumulative time (in ticks) in various power states
 system.cpu.pwrStateResidencyTicks::UNDEFINED 100000000000                       # Cumulative time (in ticks) in various power states
 system.cpu.numPackets                         3333276                       # Number of packets generated
@@ -289,7 +297,7 @@ system.membus.pkt_size_system.monitor-master::system.physmem.port    213329664
 system.membus.pkt_size::total               213329664                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.reqLayer0.occupancy         11679751447                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization              11.7                       # Layer utilization (%)
-system.membus.respLayer0.occupancy        11025969759                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy        11024098980                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization             11.0                       # Layer utilization (%)
 system.monitor.pwrStateResidencyTicks::UNDEFINED 100000000000                       # Cumulative time (in ticks) in various power states
 system.monitor.readBurstLengthHist::samples      1666397                       # Histogram of burst lengths of transmitted packets
@@ -344,8 +352,8 @@ system.monitor.writeBurstLengthHist::76-79            0      0.00%    100.00% #
 system.monitor.writeBurstLengthHist::total      1666879                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBandwidthHist::samples          100                       # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::mean     1066494080                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::gmean  1063154807.297242                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::stdev  107909912.518316                       # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::gmean  1063154829.648824                       # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::stdev  107909695.124640                       # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::0-1.34218e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
@@ -397,34 +405,34 @@ system.monitor.writeBandwidthHist::total          100                       # Hi
 system.monitor.averageWriteBandwidth       1066802560      0.00%      0.00% # Average write bandwidth (bytes/s)
 system.monitor.totalWrittenBytes            106680256                       # Number of bytes written
 system.monitor.readLatencyHist::samples       1666397                       # Read request-response latency
-system.monitor.readLatencyHist::mean     80828.757102                       # Read request-response latency
-system.monitor.readLatencyHist::gmean    75647.211665                       # Read request-response latency
-system.monitor.readLatencyHist::stdev    40158.670662                       # Read request-response latency
-system.monitor.readLatencyHist::0-32767            22      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::32768-65535       453126     27.19%     27.19% # Read request-response latency
-system.monitor.readLatencyHist::65536-98303      1001111     60.08%     87.27% # Read request-response latency
-system.monitor.readLatencyHist::98304-131071        83302      5.00%     92.27% # Read request-response latency
-system.monitor.readLatencyHist::131072-163839        62543      3.75%     96.02% # Read request-response latency
-system.monitor.readLatencyHist::163840-196607        26583      1.60%     97.62% # Read request-response latency
-system.monitor.readLatencyHist::196608-229375         8788      0.53%     98.14% # Read request-response latency
-system.monitor.readLatencyHist::229376-262143         7677      0.46%     98.61% # Read request-response latency
-system.monitor.readLatencyHist::262144-294911         7849      0.47%     99.08% # Read request-response latency
-system.monitor.readLatencyHist::294912-327679         7874      0.47%     99.55% # Read request-response latency
-system.monitor.readLatencyHist::327680-360447         4044      0.24%     99.79% # Read request-response latency
-system.monitor.readLatencyHist::360448-393215         1555      0.09%     99.88% # Read request-response latency
-system.monitor.readLatencyHist::393216-425983          891      0.05%     99.94% # Read request-response latency
-system.monitor.readLatencyHist::425984-458751          671      0.04%     99.98% # Read request-response latency
-system.monitor.readLatencyHist::458752-491519          316      0.02%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::491520-524287           44      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::524288-557055            1      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::557056-589823            0      0.00%    100.00% # Read request-response latency
+system.monitor.readLatencyHist::mean     85241.043010                       # Read request-response latency
+system.monitor.readLatencyHist::gmean    80106.557141                       # Read request-response latency
+system.monitor.readLatencyHist::stdev    40394.991557                       # Read request-response latency
+system.monitor.readLatencyHist::0-32767            25      0.00%      0.00% # Read request-response latency
+system.monitor.readLatencyHist::32768-65535       443615     26.62%     26.62% # Read request-response latency
+system.monitor.readLatencyHist::65536-98303       995882     59.76%     86.39% # Read request-response latency
+system.monitor.readLatencyHist::98304-131071        85391      5.12%     91.51% # Read request-response latency
+system.monitor.readLatencyHist::131072-163839        63740      3.83%     95.33% # Read request-response latency
+system.monitor.readLatencyHist::163840-196607        33175      1.99%     97.33% # Read request-response latency
+system.monitor.readLatencyHist::196608-229375        11329      0.68%     98.01% # Read request-response latency
+system.monitor.readLatencyHist::229376-262143         8224      0.49%     98.50% # Read request-response latency
+system.monitor.readLatencyHist::262144-294911         8145      0.49%     98.99% # Read request-response latency
+system.monitor.readLatencyHist::294912-327679         8447      0.51%     99.49% # Read request-response latency
+system.monitor.readLatencyHist::327680-360447         5871      0.35%     99.85% # Read request-response latency
+system.monitor.readLatencyHist::360448-393215         1313      0.08%     99.93% # Read request-response latency
+system.monitor.readLatencyHist::393216-425983          659      0.04%     99.97% # Read request-response latency
+system.monitor.readLatencyHist::425984-458751          321      0.02%     99.98% # Read request-response latency
+system.monitor.readLatencyHist::458752-491519          128      0.01%     99.99% # Read request-response latency
+system.monitor.readLatencyHist::491520-524287           34      0.00%     99.99% # Read request-response latency
+system.monitor.readLatencyHist::524288-557055           33      0.00%    100.00% # Read request-response latency
+system.monitor.readLatencyHist::557056-589823           65      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::589824-622591            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::622592-655359            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::total         1666397                       # Read request-response latency
 system.monitor.writeLatencyHist::samples      1666878                       # Write request-response latency
-system.monitor.writeLatencyHist::mean    19652.383883                       # Write request-response latency
-system.monitor.writeLatencyHist::gmean   19632.845881                       # Write request-response latency
-system.monitor.writeLatencyHist::stdev     964.266043                       # Write request-response latency
+system.monitor.writeLatencyHist::mean    20414.077900                       # Write request-response latency
+system.monitor.writeLatencyHist::gmean   20330.210031                       # Write request-response latency
+system.monitor.writeLatencyHist::stdev    1962.397109                       # Write request-response latency
 system.monitor.writeLatencyHist::0-2047             0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::2048-4095            0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::4096-6143            0      0.00%      0.00% # Write request-response latency
@@ -434,13 +442,13 @@ system.monitor.writeLatencyHist::10240-12287            0      0.00%      0.00%
 system.monitor.writeLatencyHist::12288-14335            0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::14336-16383            0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::16384-18431            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::18432-20479      1607382     96.43%     96.43% # Write request-response latency
-system.monitor.writeLatencyHist::20480-22527        29447      1.77%     98.20% # Write request-response latency
-system.monitor.writeLatencyHist::22528-24575        12825      0.77%     98.97% # Write request-response latency
-system.monitor.writeLatencyHist::24576-26623         7107      0.43%     99.39% # Write request-response latency
-system.monitor.writeLatencyHist::26624-28671         4858      0.29%     99.68% # Write request-response latency
-system.monitor.writeLatencyHist::28672-30719         4531      0.27%     99.96% # Write request-response latency
-system.monitor.writeLatencyHist::30720-32767          728      0.04%    100.00% # Write request-response latency
+system.monitor.writeLatencyHist::18432-20479      1311621     78.69%     78.69% # Write request-response latency
+system.monitor.writeLatencyHist::20480-22527        97272      5.84%     84.52% # Write request-response latency
+system.monitor.writeLatencyHist::22528-24575       151281      9.08%     93.60% # Write request-response latency
+system.monitor.writeLatencyHist::24576-26623        83768      5.03%     98.62% # Write request-response latency
+system.monitor.writeLatencyHist::26624-28671        15604      0.94%     99.56% # Write request-response latency
+system.monitor.writeLatencyHist::28672-30719         6292      0.38%     99.94% # Write request-response latency
+system.monitor.writeLatencyHist::30720-32767         1040      0.06%    100.00% # Write request-response latency
 system.monitor.writeLatencyHist::32768-34815            0      0.00%    100.00% # Write request-response latency
 system.monitor.writeLatencyHist::34816-36863            0      0.00%    100.00% # Write request-response latency
 system.monitor.writeLatencyHist::36864-38911            0      0.00%    100.00% # Write request-response latency
@@ -531,18 +539,18 @@ system.monitor.ittReqReq::min_value             28000                       # Re
 system.monitor.ittReqReq::max_value           1041309                       # Request-to-request inter transaction time
 system.monitor.ittReqReq::total               3333275                       # Request-to-request inter transaction time
 system.monitor.outstandingReadsHist::samples          100                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::mean     1.290000                       # Outstanding read transactions
+system.monitor.outstandingReadsHist::mean     1.310000                       # Outstanding read transactions
 system.monitor.outstandingReadsHist::gmean            0                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::stdev     1.216843                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::0             22     22.00%     22.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::1             46     46.00%     68.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::2             23     23.00%     91.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::3              5      5.00%     96.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::4              1      1.00%     97.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::5              2      2.00%     99.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::6              0      0.00%     99.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::7              0      0.00%     99.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::8              1      1.00%    100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::stdev     0.991835                       # Outstanding read transactions
+system.monitor.outstandingReadsHist::0             20     20.00%     20.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::1             44     44.00%     64.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::2             24     24.00%     88.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::3              9      9.00%     97.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::4              3      3.00%    100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::5              0      0.00%    100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::6              0      0.00%    100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::7              0      0.00%    100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::8              0      0.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::9              0      0.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::10             0      0.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::11             0      0.00%    100.00% # Outstanding read transactions
@@ -556,11 +564,11 @@ system.monitor.outstandingReadsHist::18             0      0.00%    100.00% # Ou
 system.monitor.outstandingReadsHist::19             0      0.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::total          100                       # Outstanding read transactions
 system.monitor.outstandingWritesHist::samples          100                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::mean     0.340000                       # Outstanding write transactions
+system.monitor.outstandingWritesHist::mean     0.380000                       # Outstanding write transactions
 system.monitor.outstandingWritesHist::gmean            0                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::stdev     0.476095                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::0            66     66.00%     66.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::1            34     34.00%    100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::stdev     0.487832                       # Outstanding write transactions
+system.monitor.outstandingWritesHist::0            62     62.00%     62.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::1            38     38.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::2             0      0.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::3             0      0.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::4             0      0.00%    100.00% # Outstanding write transactions
-- 
2.30.2